ANDN, BEXTR, BLSI, BLSMSK, BLSR, LZCNT, TZCNT Instructions

Author: andrusza2

.gitignore

@@ -234,3 +234,4 @@ _Pvt_Extensions
 
 # FAKE - F# Make
 .fake/
+/UDEmulator.VC.db

ANDN.c

@@ -8,5 +8,33 @@ int __stdcall ANDNInstructionEmulator(
 	UNREFERENCED_PARAMETER(instruction);
 	UNREFERENCED_PARAMETER(context);
 
+	unsigned int src1 = getRegValue(instruction.src1, context);
+	unsigned int src2;
+	if (instruction.src2 == MEM_32)
+	{
+		src2 = *(unsigned int*)getEffectiveVA(instruction.mem, context);
+	}
+	else
+	{
+		src2 = getRegValue(instruction.src2, context);
+	}
+
+	unsigned int dest = (~src1) & src2;
+	unsigned int SF = dest >> 31;
+
+	// Set flags
+	context->flags &= (~FLAG_SF) & (~FLAG_ZF) & (~FLAG_OF) & (~FLAG_CF);
+	if (SF)
+	{
+		context->flags |= FLAG_SF;
+	}
+
+	if (dest == 0)
+	{
+		context->flags |= FLAG_ZF;
+	}
+
+	setRegValue(instruction.dest, dest, context);
+
 	return TRUE;
 }

BEXTR.c

@@ -8,5 +8,32 @@ int __stdcall BEXTRInstructionEmulator(
 	UNREFERENCED_PARAMETER(instruction);
 	UNREFERENCED_PARAMETER(context);
 
+	unsigned int src1;
+	if (instruction.src1 == MEM_32)
+	{
+		src1 = *(unsigned int*)getEffectiveVA(instruction.mem, context);
+	}
+	else
+	{
+		src1 = getRegValue(instruction.src1, context);
+	}
+	unsigned int src2 = getRegValue(instruction.src2, context);
+
+	
+	unsigned int start = src2 & 0xFF;
+	unsigned int len = (src2 & 0xFF00) >> 8;
+
+	unsigned int dest = (src1 >> start) & ((1 << len) - 1);
+
+	// Set flags
+	context->flags &= (~FLAG_ZF) & (~FLAG_CF) & (~FLAG_OF);
+
+	if (dest == 0)
+	{
+		context->flags |= FLAG_ZF;
+	}
+
+	setRegValue(instruction.dest, dest, context);
+
 	return TRUE;
 }

BLSI.c

@@ -8,5 +8,38 @@ int __stdcall BLSIInstructionEmulator(
 	UNREFERENCED_PARAMETER(instruction);
 	UNREFERENCED_PARAMETER(context);
 
+	unsigned int src;
+	if (instruction.src1 == MEM_32)
+	{
+		src = *(unsigned int*)getEffectiveVA(instruction.mem, context);
+	}
+	else
+	{
+		src = getRegValue(instruction.src1, context);
+	}
+
+	unsigned int operand_size = 32;
+
+	unsigned int dest = (-src) & src;
+
+	// Set flags
+	context->flags &= (~FLAG_ZF) & (~FLAG_SF) & (~FLAG_CF) & (~FLAG_OF);
+	if (src == 0)
+	{
+		context->flags |= FLAG_CF;
+	}
+
+	if (dest == 0)
+	{
+		context->flags |= FLAG_ZF;
+	}
+
+	if (dest >> (operand_size - 1))
+	{
+		context->flags |= FLAG_SF;
+	}
+
+	setRegValue(instruction.dest, dest, context);
+
 	return TRUE;
 }

BLSMSK.c

@@ -8,5 +8,33 @@ int __stdcall BLSMSKInstructionEmulator(
 	UNREFERENCED_PARAMETER(instruction);
 	UNREFERENCED_PARAMETER(context);
 
+	unsigned int src;
+	if (instruction.src1 == MEM_32)
+	{
+		src = *(unsigned int*)getEffectiveVA(instruction.mem, context);
+	}
+	else
+	{
+		src = getRegValue(instruction.src1, context);
+	}
+
+	unsigned int operand_size = 32;
+
+	unsigned int dest = (src-1) ^ src;
+
+	// Set flags
+	context->flags &= (~FLAG_ZF) & (~FLAG_SF) & (~FLAG_CF) & (~FLAG_OF);
+	if (src == 0)
+	{
+		context->flags |= FLAG_CF;
+	}
+
+	if (dest >> (operand_size - 1))
+	{
+		context->flags |= FLAG_SF;
+	}
+
+	setRegValue(instruction.dest, dest, context);
+
 	return TRUE;
 }

BLSR.c

@@ -8,5 +8,38 @@ int __stdcall BLSRInstructionEmulator(
 	UNREFERENCED_PARAMETER(instruction);
 	UNREFERENCED_PARAMETER(context);
 
+	unsigned int src;
+	if (instruction.src1 == MEM_32)
+	{
+		src = *(unsigned int*)getEffectiveVA(instruction.mem, context);
+	}
+	else
+	{
+		src = getRegValue(instruction.src1, context);
+	}
+
+	unsigned int operand_size = 32;
+
+	unsigned int dest = (src-1) & src;
+
+	// Set flags
+	context->flags &= (~FLAG_ZF) & (~FLAG_SF) & (~FLAG_CF) & (~FLAG_OF);
+	if (src == 0)
+	{
+		context->flags |= FLAG_CF;
+	}
+
+	if (dest == 0)
+	{
+		context->flags |= FLAG_ZF;
+	}
+
+	if (dest >> (operand_size - 1))
+	{
+		context->flags |= FLAG_SF;
+	}
+
+	setRegValue(instruction.dest, dest, context);
+
 	return TRUE;
 }

LZCNT.c

@@ -8,5 +8,45 @@ int __stdcall LZCNTInstructionEmulator(
 	UNREFERENCED_PARAMETER(instruction);
 	UNREFERENCED_PARAMETER(context);
 
+	unsigned int src;
+	if (instruction.src1 == MEM_32 || instruction.src1 == MEM_16 )
+	{
+		src = *(unsigned int*)getEffectiveVA(instruction.mem, context);
+	}
+	else
+	{
+		src = getRegValue(instruction.src1, context);
+	}
+
+	unsigned int operand_size = 32;
+
+	if (instruction.dest & 0x10) // 16-bit instruction
+	{
+		operand_size = 16;
+	}
+
+	unsigned int temp = operand_size - 1;
+	unsigned int dest = 0;
+
+	while ((temp >= 0) && (src >> temp == 0))
+	{
+		--temp;
+		++dest;
+	}
+
+	// Set flags
+	context->flags &= (~FLAG_ZF) & (~FLAG_CF);
+	if (dest == operand_size)
+	{
+		context->flags |= FLAG_CF;
+	}
+
+	if (dest == 0)
+	{
+		context->flags |= FLAG_ZF;
+	}
+
+	setRegValue(instruction.dest, dest, context);
+
 	return TRUE;
 }

TZCNT.c

@@ -8,5 +8,45 @@ int __stdcall TZCNTInstructionEmulator(
 	UNREFERENCED_PARAMETER(instruction);
 	UNREFERENCED_PARAMETER(context);
 
+	unsigned int src;
+	if (instruction.src1 == MEM_32 || instruction.src1 == MEM_16)
+	{
+		src = *(unsigned int*)getEffectiveVA(instruction.mem, context);
+	}
+	else
+	{
+		src = getRegValue(instruction.src1, context);
+	}
+
+	unsigned int operand_size = 32;
+
+	if (instruction.dest & 0x10) // 16-bit instruction
+	{
+		operand_size = 16;
+	}
+
+	unsigned int temp = 0;
+	unsigned int dest = 0;
+
+	while ((temp < operand_size) && (((src >> temp) & 0x1) == 0))
+	{
+		--temp;
+		++dest;
+	}
+
+	// Set flags
+	context->flags &= (~FLAG_ZF) & (~FLAG_CF);
+	if (dest == operand_size)
+	{
+		context->flags |= FLAG_CF;
+	}
+
+	if (dest == 0)
+	{
+		context->flags |= FLAG_ZF;
+	}
+
+	setRegValue(instruction.dest, dest, context);
+
 	return TRUE;
 }