Merge branch 'pound-emu:main' into feature-wasm-backend

Author: Proxy-alt

CMakeLists.txt

@@ -159,7 +159,7 @@ if (BALLISTIC_BUILD_TESTS)
     gtest_discover_tests(${DECODER_TEST})
     gtest_discover_tests(${MEMORY_TEST})
 
-    set(TRANSLATION_TESTS movk movn movz ret)
+    set(TRANSLATION_TESTS movk movn movz ret sub)
     foreach (test_name ${TRANSLATION_TESTS})
         set(target_name "test_${test_name}")
         add_executable(${target_name} "tests/translation/${target_name}.cpp")

include/bal_assembler.h

@@ -93,6 +93,30 @@ extern "C"
                                 uint16_t             imm12,
                                 uint8_t              shift);
 
+    /// Emit a `SUB` (Immediate) instruction.
+    ///
+    /// Subtracts a 12 bit immediate value `imm12` with the optional left shift `sh` from register
+    /// value `rn`, and writes the result to the destination register `rd`.
+    ///
+    /// # Safety
+    ///
+    /// * `rn` will be truncated if it exceeds 5 bits.
+    /// * `imm12` will be truncated if it exceeds 12 bits.
+    /// * `sh` must have the value `0`, or `1`
+    /// * Function does not emit instructions if `assembler->status != BAL_SUCCESS`.
+    ///
+    /// # Errors
+    ///
+    /// Modifies `assembler->status` to the following if an error occurs:
+    ///
+    /// * [`BAL_ERROR_INSTRUCTION_OVERFLOW`] if `assembler->offset >= assembler->capacity`.
+    /// * [`BAL_ERROR_INVALID_ARGUMENT`] if function arguments are invalid.
+    void bal_emit_sub_immediate(bal_assembler_t     *assembler,
+                                bal_register_index_t rd,
+                                uint8_t              rn,
+                                uint16_t             imm12,
+                                uint8_t              shift);
+
     /// Emit a `MOVZ` (Move Wide with Zero) instruction.
     ///
     /// Moves a 16-bit immediate into a register, shifting it left by 0, 16, 32, or 48 bits, and

include/bal_engine.h

@@ -145,7 +145,7 @@ extern "C"
     ///
     /// # Safety
     ///
-    /// If `guest_address_staart` is `NULL`, we assume the entry point is 0x0.
+    /// `guest_address_start` must be non-NULL.
     ///
     /// # Errors
     ///

include/bal_types.h

@@ -32,7 +32,7 @@ extern "C"
         OPCODE_DIV,
         OPCODE_AND,
         OPCODE_XOR,
-        OPCODE_NOR,
+        OPCODE_OR_NOT,
         OPCODE_SHIFT,
         OPCODE_LOAD,
         OPCODE_STORE,

src/bal_assembler.c

@@ -16,11 +16,12 @@ bal_assembler_init(bal_assembler_t *assembler, void *buffer, const size_t size,
     if (NULL == buffer)
     {
         BAL_LOG_ERROR(&logger, "Buffer is NULL.");
+        return BAL_ERROR_INVALID_ARGUMENT;
     }
 
     if ((uintptr_t)buffer % 4 != 0)
     {
-        BAL_LOG_ERROR(&logger, "Buffer %p is not 4-byte aligned.");
+        BAL_LOG_ERROR(&logger, "Buffer %p is not 4-byte aligned.", buffer);
         return BAL_ERROR_MEMORY_ALIGNMENT;
     }
 
@@ -103,6 +104,74 @@ bal_emit_add_immediate(bal_assembler_t           *assembler,
     assembler->buffer[assembler->offset++] = instruction;
 }
 
+void
+bal_emit_sub_immediate(bal_assembler_t           *assembler,
+                       const bal_register_index_t rd,
+                       const uint8_t              rn,
+                       const uint16_t             imm12,
+                       const uint8_t              shift)
+{
+    if (NULL == assembler)
+    {
+        return;
+    }
+
+    if (assembler->status != BAL_SUCCESS)
+    {
+        return;
+    }
+
+    const bool can_emit_return_value = can_emit(assembler);
+
+    if (false == can_emit_return_value)
+    {
+        return;
+    }
+
+    if (rd > 31)
+    {
+        BAL_LOG_ERROR(&assembler->logger, "X%u out of range (0-31).", rd);
+        assembler->status = BAL_ERROR_INVALID_ARGUMENT;
+        return;
+    }
+
+    if (shift != 0 && shift != 1)
+    {
+        BAL_LOG_ERROR(&assembler->logger, "%u is not a valid shift amount (0-1).", shift);
+        assembler->status = BAL_ERROR_INVALID_ARGUMENT;
+        return;
+    }
+
+    const uint32_t imm12_mask      = 0xFFF;
+    const uint32_t rn_mask         = 0x1F;
+    const uint32_t imm12_uint32    = imm12 & imm12_mask;
+    const uint32_t rn_uint32       = rn & rn_mask;
+    const uint32_t hard_coded_bits = 0xA2U;
+    const uint32_t shift_uint32    = shift;
+    const uint32_t sf              = 1U;
+
+    uint32_t instruction = 0;
+    instruction |= sf << 31;
+    instruction |= hard_coded_bits << 23;
+    instruction |= shift_uint32 << 22;
+    instruction |= imm12_uint32 << 10;
+    instruction |= rn_uint32 << 5;
+    instruction |= rd;
+
+    const char *mnemonic = "SUB (Imm)";
+    BAL_LOG_TRACE(&assembler->logger,
+                  "[+0x%04zx] %08x %s X%u, #0x%04x, LSL #%u",
+                  assembler->offset * sizeof(uint32_t),
+                  instruction,
+                  mnemonic,
+                  rd,
+                  imm12_uint32,
+                  shift_uint32);
+
+    (void)mnemonic;
+    assembler->buffer[assembler->offset++] = instruction;
+}
+
 void
 bal_emit_movz(bal_assembler_t           *assembler,
               const bal_register_index_t rd,

src/bal_engine.c

@@ -36,7 +36,11 @@ static uint32_t intern_constant(bal_translation_context_t *, bal_constant_t);
 static void     translate_const(bal_translation_context_t *,
                                 const bal_decoder_instruction_metadata_t *,
                                 const uint32_t *);
+static void     translate_sub(bal_translation_context_t *,
+                              const bal_decoder_instruction_metadata_t *,
+                              const uint32_t *);
 static void     translate_return(bal_translation_context_t *, const uint32_t *);
+
 BAL_COLD bal_error_t
 bal_engine_init(const bal_allocator_t *allocator, bal_engine_t *engine, bal_logger_t logger)
 {
@@ -146,9 +150,11 @@ bal_engine_translate(bal_engine_t *BAL_RESTRICT                 engine,
         return engine->status;
     }
 
-    if (BAL_UNLIKELY(NULL == &guest_address_start))
+    if (BAL_UNLIKELY(NULL == guest_address_start))
     {
-        BAL_LOG_INFO(&engine->logger, "Guest Address is NULL, assuming entry point is 0x0");
+        BAL_LOG_ERROR(&engine->logger, "Guest Address is NULL, aborting translation");
+        engine->status = BAL_ERROR_INVALID_ARGUMENT;
+        return engine->status;
     }
 
     const size_t max_instructions_size_bytes = max_instructions * ARM_INSTRUCTION_SIZE_BYTES;
@@ -262,6 +268,9 @@ bal_engine_translate(bal_engine_t *BAL_RESTRICT                 engine,
                 case OPCODE_CONST:
                     translate_const(&context, metadata, arm_instruction_operands);
                     break;
+                case OPCODE_SUB:
+                    translate_sub(&context, metadata, arm_instruction_operands);
+                    break;
                 case OPCODE_RETURN:
                     translate_return(&context, arm_instruction_operands);
                     is_block_terminated = true;
@@ -574,4 +583,74 @@ translate_return(bal_translation_context_t *context, const uint32_t *arm_registe
     BAL_LOG_DEBUG(
         context->logger, "   EMIT: v%u = RET v%u", context->instruction_count, rn_ssa_index);
     context->instruction_count++;
+}
+
+BAL_HOT static void
+translate_sub(bal_translation_context_t                *context,
+              const bal_decoder_instruction_metadata_t *metadata,
+              const uint32_t                           *arm_registers)
+{
+    if (BAL_UNLIKELY(BAL_OPERAND_TYPE_IMMEDIATE != metadata->operands[2].type))
+    {
+        BAL_LOG_DEBUG(context->logger,
+                      "  SKIPPED: SUB variant '%s' not yet implemented in IR layer.",
+                      metadata->name);
+        return;
+    }
+
+    const uint64_t rd    = arm_registers[0];
+    const uint64_t rn    = arm_registers[1];
+    const uint64_t imm12 = arm_registers[2];
+    const uint64_t sh    = arm_registers[3];
+    const uint64_t shift = (1 == sh) ? 12 : 0;
+    const uint64_t value = imm12 << shift;
+
+    BAL_LOG_TRACE(context->logger,
+                  "  Variant='Imm' Rd=%lu Rn=%lu Imm12=0x%lX Shift=%lu Value=0x%llX",
+                  rd,
+                  rn,
+                  imm12,
+                  shift,
+                  (unsigned long long)value);
+
+    const uint64_t rn_ssa_index      = get_or_create_ssa_index(context, rn);
+    const uint64_t value_const_index = intern_constant(context, value);
+
+    if (BAL_UNLIKELY(context->status != BAL_SUCCESS))
+    {
+        return;
+    }
+
+    bal_bit_width_t bit_width;
+
+    switch (metadata->operands[0].type)
+    {
+        case BAL_OPERAND_TYPE_REGISTER_32:
+            bit_width = 32;
+            break;
+        case BAL_OPERAND_TYPE_REGISTER_64:
+            bit_width = 64;
+            break;
+        default:
+            BAL_LOG_ERROR(context->logger, "Unknown register type for SUB (Imm) Rd register");
+            context->status = BAL_ERROR_INCORRECT_REGISTER_TYPE;
+            return;
+    }
+
+    *context->ir_instruction_cursor = (bal_instruction_t)OPCODE_SUB << BAL_OPCODE_SHIFT_POSITION
+                                      | rn_ssa_index << BAL_SOURCE1_SHIFT_POSITION
+                                      | value_const_index << BAL_SOURCE2_SHIFT_POSITION;
+    *context->bit_width_cursor = bit_width;
+
+    BAL_LOG_DEBUG(context->logger,
+                  "  EMIT: v%u = SUB v%u, c%u (%u-bit)",
+                  context->instruction_count,
+                  (uint32_t)rn_ssa_index,
+                  (uint32_t)(value_const_index & ~BAL_IS_CONSTANT_BIT_POSITION),
+                  bit_width);
+
+    context->source_variables[rd].current_ssa_index = context->instruction_count;
+    BAL_LOG_TRACE(context->logger, "  SSA UPDATE: X%lu -> v%u", rd, context->instruction_count);
+
+    context->instruction_count++;
 }

tests/translation/test_sub.cpp

@@ -0,0 +1,132 @@
+#include "setup.h"
+#include <cinttypes>
+#include <cstdio>
+#include <cstdlib>
+#include <gtest/gtest.h>
+
+TEST(Translation, SubImmediate)
+{
+    test_context_t context;
+    test_setup(&context);
+    constexpr bal_register_index_t rds[] = {
+        BAL_REGISTER_X0,
+        BAL_REGISTER_X1,
+        BAL_REGISTER_X15,
+        BAL_REGISTER_X30,
+    };
+
+    constexpr uint8_t  rn           = BAL_REGISTER_X5;
+    constexpr uint16_t immediates[] = { 0U, 1U, 0xAAAU, 0xFFFU };
+    constexpr uint8_t  shifts[]     = { 0U, 1U };
+
+    constexpr size_t rds_count = std::size(rds);
+
+    for (const bal_register_index_t rd : rds)
+    {
+        for (const unsigned short immediate : immediates)
+        {
+            for (const unsigned char shift : shifts)
+            {
+                bal_emit_sub_immediate(&context.assembler, rd, rn, immediate, shift);
+            }
+        }
+    }
+
+    bal_emit_ret(&context.assembler, BAL_REGISTER_X0);
+
+    bal_guest_address_t entry_point = 0x0;
+    bal_engine_translate(&context.engine,
+                         &context.interface,
+                         &entry_point,
+                         context.assembler.offset * sizeof(uint32_t));
+
+    const bal_instruction_t *BAL_RESTRICT ir       = context.engine.instructions;
+    size_t                                ir_index = 0;
+
+    // First IR instruction: GET_REGISTER v0 = X5 (lazy load of Rn on its
+    // first read by the first SUB).
+    //
+    {
+        const auto opcode = static_cast<bal_opcode_t>(ir[ir_index] >> BAL_OPCODE_SHIFT_POSITION);
+
+        if (opcode != OPCODE_GET_REGISTER)
+        {
+            fprintf(
+                stderr, "FAIL: IR Inst %zu is not GET_REGISTER (opcode=%d)\n", ir_index, opcode);
+            GTEST_FAIL();
+        }
+
+        ++ir_index;
+    }
+
+    constexpr uint32_t rn_ssa_expected = 0U;
+
+    for (size_t r = 0; r < rds_count; ++r)
+    {
+        for (const unsigned short immediate : immediates)
+        {
+            for (const unsigned char shift : shifts)
+            {
+                const bal_instruction_t inst = ir[ir_index];
+                const auto opcode = static_cast<bal_opcode_t>(inst >> BAL_OPCODE_SHIFT_POSITION);
+
+                if (opcode != OPCODE_SUB)
+                {
+                    fprintf(stderr, "FAIL: IR Inst %zu is not SUB (opcode=%d)\n", ir_index, opcode);
+                    GTEST_FAIL();
+                }
+
+                const uint32_t src1
+                    = inst >> BAL_SOURCE1_SHIFT_POSITION & BAL_SOURCE_MASK_WITH_FLAG;
+
+                if (src1 & BAL_IS_CONSTANT_BIT_POSITION)
+                {
+                    fprintf(stderr,
+                            "FAIL: IR Inst %zu src1 flagged as constant (expected SSA)\n",
+                            ir_index);
+                    GTEST_FAIL();
+                }
+
+                if (src1 != rn_ssa_expected)
+                {
+                    fprintf(stderr,
+                            "FAIL: IR Inst %zu src1 mismatch. Expected v%u, got v%u\n",
+                            ir_index,
+                            rn_ssa_expected,
+                            src1);
+                    GTEST_FAIL();
+                }
+
+                const uint32_t src2_with_flag
+                    = inst >> BAL_SOURCE2_SHIFT_POSITION & BAL_SOURCE_MASK_WITH_FLAG;
+
+                if (!(src2_with_flag & BAL_IS_CONSTANT_BIT_POSITION))
+                {
+                    fprintf(stderr, "FAIL: IR Inst %zu src2 not flagged as constant\n", ir_index);
+                    GTEST_FAIL();
+                }
+
+                const uint32_t pool_index   = src2_with_flag & BAL_SOURCE_MASK;
+                const uint64_t expected_val = static_cast<uint64_t>(immediate) << (shift * 12U);
+                const uint64_t actual_val   = context.engine.constants[pool_index];
+
+                if (actual_val != expected_val)
+                {
+                    fprintf(stderr,
+                            "FAIL: IR Inst %zu constant c%u mismatch. Expected 0x%" PRIX64
+                            ", Got 0x%" PRIX64 "\n",
+                            ir_index,
+                            pool_index,
+                            expected_val,
+                            actual_val);
+                    GTEST_FAIL();
+                }
+                ++ir_index;
+            }
+        }
+    }
+
+    test_teardown(&context);
+}
+
+/*** end of file ***/