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Add previously approved ECRs
Add the following ECRs which have already been approved as of ACPI-6.4: - Add an ACPI0017 root object - Add a 'Generic Port' Object Signed-off-by: Vishal Verma <[email protected]>
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‎acpi_generic_port_ECN.md‎

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# Title: Introduce a Generic Port for hotplug memory buses like CXL
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# Status: Draft v2
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# Document: ACPI Specification 6.4
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# License
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SPDX-License Identifier: CC-BY-4.0
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# Submitter:
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* Sponsor: Dan Williams, Intel
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* Creators/Contributors:
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* Mahesh Natu, Intel
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* Chet Douglas, Intel
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* Deepak Shivakumar, Intel
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* Jonathan Cameron, Huawei
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# Changes since v1
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* Rename Generic Target to Generic Port and make a new distinct SRAT
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type independent of Generic Initiator (Jonathan)
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* Clarify that this new "Port" concept is not limited to CXL. It is a
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generic way to describe the performance of static paths to
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dynamically added system memory (Mahesh)
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# Summary of the Change
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Introduce a new "Generic Port" type to the SRAT to describe the
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performance from CPU and other initiator domains to the root of a CXL
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topology, or any other topology that might dynamically add system memory
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behind the "Port". This is in support of, but not limited to, the OS
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being able to enumerate the performance topology for dynamically added /
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discovered CXL Memory Device endpoints.
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# Benefits of the Change
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Consider the case of a system with a set of CXL Host Bridges (ACPI0016),
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and some endpoints attached at boot. In that scenario the platform
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firmware is able to enumerate those devices, enumerate and map CXL
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memory into the system physical memory address space, and generate the
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typical static SRAT/SLIT/HMAT set of tables describing CXL attached
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memory. Now, consider the case where devices are dynamically added and
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enumerated post boot, i.e. post generation of the static memory tables.
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In this scenario platform firmware is unable to perform the end-to-end
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enumeration necessary to populate SRAT and HMAT for the endpoints that
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may be hot-inserted behind those bridges post power-on. The
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address-range is unknown so SRAT can not be pre-populated in the typical
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way that hotplug system memory is enumerated. Even if a static address
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range was set aside for future hotplug the performance is unknown (no
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CDAT nor interleave configuration) so HMAT can not be pre-populated.
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However, what is known to platform firmware that generates the
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SRAT/SLIT/HMAT and is the performance characteristics of the path
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between CPU and Generic Initiators to the Generic Port (e.g. CXL Host
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Bridge). With the addition of a Generic Port proximity domain to the
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SRAT then the SLIT and HMAT can enumerate the platform-static component
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of a given edge in the platform-performance topology graph. It enables
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the OS to build out a performance mapping for system memory address
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ranges dynamically discovered, or provisioned, behind a Generic Port.
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The OS mapping takes into account the Generic Port performance (as
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either an initiator or a target), the interleave configuration, and the
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bus enumerable performance characteristics (link latency, bandwidth,
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switch traversals) to supplement the static HMAT data enumerated at
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boot.
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# Impact of the Change
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A new SRAT type requires non-conforming system software to ignore the
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new type in the SRAT, ignore any coordinate in the SLIT that includes
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the associated port's proximity domain, and ignore any coordinate in the
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HMAT that includes the port's proximity domain as either an initiator or
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a target.
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In contrast, conforming system software need only consult the Generic
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Port data to optionally extend the enumeration and distinguish Port
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attached initiators and memory targets from the existing set of
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enumerated proximity domains.
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A conforming implementation also has the option to ignore the Generic Port
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contribution to the performance, in either a row, or col to be considered
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by system software that parses SRAT, SLIT, and HMAT. Given that the OS
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still needs to dynamically enumerate and instantiate the memory ranges and
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initiators behind the Generic Port. The assumption is that operating systems
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that do not support native CXL enumeration will ignore this data in the HMAT,
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while CXL native enumeration aware environments will use this fragment of the
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performance path to calculate the performance characteristics.
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# References
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* Compute Express Link Specification v2.0,
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<https://www.computeexpresslink.org/>
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# Detailed Description of the Change
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* Section 5.2.16 System Resource Affinity Table (SRAT) add another
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bullet for Generic Ports:
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* generic ports (e.g. host bridges that can dynamically discover
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new initiators and instantiate new memory range targets)
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* Add new section 5.2.16.7 Generic Port Affinity Structure:
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The Generic Port Affinity Structure provides an association between a
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proximity domain number and a device handle representing a Generic
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Port (e.g. CXL Host Bridge, or similar device that hosts a dynamic
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topology of memory ranges and/or initiators).
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Support of Generic Port Affinity Structures by an OSPM is optional.
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* Add a table describing the Generic Port Affinity Structure (Table
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5.xx):
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| Field | Byte Length | Byte Offset | Description |
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| :----- | :--- | :--- | :--------------------------- |
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| Type | 1 | 0 | 6 Generic Port Structure |
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| Length | 1 | 1 | 32 |
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| Reserved | 1 | 2 | Reserved and must be zero |
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| Device Handle Type | 1 | 3 | Device Handle Type: See 5.2.16.6 Generic Initiator Affinity Structure for the possible device handle types and their format. |
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| Proximity Domain | 4 | 4 | The proximity domain to identify the performance of this port in the HMAT. |
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| Device Handle | 16 | 8 | Device Handle of the Generic Port, see Table 5.57 and 5.58 for a description of this field. |
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| Flags | 4 | 24 | See table 5.59 for a description of this field. |
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| Reserved | 4 | 28 | Reserved and must be zero. |
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* Replace all instances of "Initiator" with "Initiator / Port" in "Table
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5.59 Flags - Generic Initiator Affinity Structure", including the
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table name.

‎add-cxl-acpi0017.md‎

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# Title: Add CXL Root Object _HID
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# Status: Draft
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# Document: ACPI Specification 6.4
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# License
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SPDX-License Identifier: CC-BY-4.0
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# Submitter:
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* Sponsor: Vishal Verma, Intel
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* Creators/Contributors:
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* Chet Douglas, Intel
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* Ben Widawsky, Intel
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* Dan Williams, Intel
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* Vishal Verma, Intel
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# Summary of the Change
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Add “Compute Express Link Root Object” enumeration value to the ACPI Device IDs Table (5.160).
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# Benefits of the Change
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Compute Express Link (CXL) is a new high-speed CPU-to-Device and CPU-to-
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Memory interconnect. The new ACPI Device ID represents a singleton
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device that allows the OSPM to trigger the enumeration of the CXL.mem
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address space, and indicates the presence of cross Host Bridge
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(ACPI0016) interleaved CXL.mem resources.
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# Impact of the Change
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One new row added to the ACPI Device IDs table (5.160).
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# References
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* Compute Express Link Specification v2.0,
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<https://www.computeexpresslink.org/>
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# Detailed Description of the Change
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Add “Compute Express Link Root Object” enumeration device
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### 5.6.7 Device Class-Specific Objects
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Most device objects are controlled through generic objects and ...
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Table 5.160 ACPI Device IDs
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| Value | Description |
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| :--- | :--------------------------- |
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| .. | .. |
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| ACPI0017 | **Compute Express Link Root Object:** This device represents the root of a CXL capable device hierarchy. It shall be present whenever the platform allows OSPM to dynamically assign CXL endpoints to a platform address space. |
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## Special Instructions

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