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TODO

Tracked tasks and known gaps for the Board-Taxonomies repository.

Near-term

  • Verify GitHub anchor links render correctly after emoji-heading ToC fix (%EF%B8%8F- prefix for headings using 🖥️, 🛠️, 🗺️) — manual check required on GitHub after push
  • Tag v1.1.0 release on GitHub after pi-implementation PR is merged
  • Add .gitattributes to normalise line endings across platforms

Content additions

  • Add Milk-V Oasis to SBC examples (Mini-ITX form factor, RISC-V) — reverted. Oasis has never shipped; Milk-V paused development indefinitely (~16 Jan 2025) after Sophgo was added to a US trade-restriction list and TSMC suspended SG2380 fabrication. Pre-order coupons were refunded. Do not re-add unless it ships
  • Add Luckfox Pico Ultra dimensions note (50 × 50 mm cracker, PoE HAT compatibility needs testing)
  • Clarify Raspberry Pi 5 AI Kit classification (SBC + AI/ML Accelerator dual-category edge case)
  • Consider adding a "Peripheral/Accelerator" sub-type for USB/PCIe/M.2 dongles (Coral, Hailo, Intel NCS) that are not standalone boards — deferred pending taxonomy design discussion

Documentation

  • Add a real-world classification walkthrough example (Milk-V Duo S, step-by-step through Decision Tree)
  • Cross-reference CLAUDE.md decision tree with README Classification Guide — CLAUDE.md updated to match 5-step README tree

Housekeeping

  • Review whether Board-Taxonomies.code-workspace should be tracked or added to .gitignore — deliberate choice: keep tracked (shared workspace config)
  • Create a GitHub Discussions category for community classification questions (complement to issue templates)

Review findings to confirm (2026-07)

From a full document review. Each item survived an adversarial verification pass, but the hardware claims below rest on vendor pages and technical press rather than first-hand testing — confirm against hardware or datasheets before acting.

Hardware claims needing confirmation

  • Luckfox Lyra part number. Document says RV3506G2; Rockchip's part appears to be RK3506G2/RK3506B (no RV3506 in Rockchip's catalogue). Affects eSBC examples and the SBC-vs-eSBC edge case
  • Luckfox Lyra display interface. Document uses it as the flagship "HDMI driven by a VPU, no 3D GPU" example. Research indicates the Lyra has no HDMI (2-lane MIPI DSI only) and the RK3506 has no VPU — a triple Cortex-A7 + Cortex-M0 HMI part with neither GPU nor video codec. If correct, the classification stays eSBC but the stated reasoning is wrong, and a different board is needed to illustrate "HDMI without a 3D GPU"
  • Milk-V Duo S display interface. The worked example's premise says "MIPI CSI" (a camera input) while step 5 says "MIPI DSI". Research says the Duo S has 4-lane MIPI DSI, no HDMI, no 3D GPU. Pick one and make premise and conclusion agree
  • Jetson Nano tensor cores. AI/ML examples say "Jetson Nano/Xavier/Orin (GPU + tensor core AI acceleration)". The Nano's 128-core Maxwell GPU has no tensor cores — those start with Xavier (Volta + NVDLA)
  • Set-top box classification. Consumer Electronics says STBs "typically use eSBC designs", but mainstream STB SoCs (Amlogic S905X/S905X4, Realtek RTD1395) pair a 3D-capable Mali GPU with HDMI output. The document already lists Le Potato (S905X) and BPi-M4 (RTD1395) as SBCs, so this looks self-contradictory
  • Smart TV mainboard example. "Smart TV mainboard with HDMI and Android → SBC" — a TV mainboard's HDMI ports are inputs; the panel is driven over LVDS/eDP/V-by-One. Classification is probably still SBC, but on GPU grounds rather than connector grounds
  • IP camera example. "IP camera board with MIPI DSI and Linux → eSBC" — IP cameras carry MIPI CSI (input), not DSI (output)
  • youyeetoo K1 module outline. Confirmed 260-pin SO-DIMM edge (260 gold fingers) with an 82 × 71 mm module — larger than the 69.6 × 45 mm Jetson outline. Worth confirming against the board in hand, and confirming the 12 V input figure
  • SpacemiT K3 CoM260 input voltage. Not published anywhere reachable; only the developer kit's carrier DC jack rating (19 V/2.37 A or 12 V/5 A) is documented. Deliberately omitted from the README — add if a module-level figure surfaces

Internal contradictions to resolve

  • eSBC intro sentence is stale relative to the criteria four lines below it. It says the differentiator is "the lack of GPU capabilities for general computing", but the refined rule is "no 3D-capable GPU" — and "general computing" reads as GPGPU/OpenCL, which is the opposite of the intended meaning
  • Technical Differentiators table, CM/SoM 3D GPU cell is marked ✓. A module's GPU follows its SoC, and many industrial SoMs have none (Toradex Colibri iMX6ULL, Variscite VAR-SOM-MX6UL, phyCORE-AM335x). It also contradicts the Edge Cases text, which says a CM on a headless carrier is an eSBC. Suggested: Varies (SoC-dependent) plus a footnote that the row describes the concept, not a specific module
  • Technical Differentiators table, eSBC Display Out cell reads ✗/Embedded, which forbids standard display output — contradicting the eSBC definition, the Luckfox Lyra entry, and the SBC-vs-eSBC edge case, all of which allow non-3D-driven HDMI
  • Technical Differentiators table, AI/ML column asserts MMU ✓, Full OS ✓, Standalone ✓, contradicting the category's own "may be standalone boards or companion accelerators" and the M.2/PCIe/USB guidance. A Hailo-8L or Coral USB Accelerator has no MMU, no OS and is not standalone
  • Recycling and Repurposing list disagrees with the canonical Decision Tree: AI/ML is the last rule there and the first step in the tree, and the CM/SoM and Dev/Eval branches are missing entirely. Two procedures that give different answers for the same board
  • CLAUDE.md line 118 tells assistants to classify using the abbreviated Recycling list rather than the canonical 5-step Decision Tree — inherits the above precedence problem
  • CLAUDE.md Repository Structure diagram claims the repo holds only README.md and .github/FUNDING.yml, and that "all meaningful content lives in README.md". It now also holds CHANGELOG, CONTRIBUTING, CODE_OF_CONDUCT, LICENSE, TODO, .gitattributes, .gitignore, the workspace file and the issue templates
  • CLAUDE.md branching rules give three mutually exclusive instructions (feature/-fix/ branches, claude/<session-id> branches, direct pushes to main acceptable for the maintainer)
  • CLAUDE.md emoji inventory omits four emoji the README actually uses: 🔧 (title), 📑 (ToC), 🤖 (AI/ML), 🗺️ (Classification Guide)
  • CLAUDE.md eSBC key trait reads "Full OS, headless or no 3D GPU" — an either/or where the taxonomy has one criterion. A headless board with a 3D GPU is still an SBC by the README's own rule
  • CHANGELOG [Unreleased] is empty while several commits since v1.1.0 changed definitions (SBC/eSBC GPU boundary, FPGA demoted to a note, this review's changes). Notes item 5 points readers there for definition changes

Decision tree gaps

  • Headless-board bug in step 5. "Does it have a 3D-capable GPU for desktop graphics? Yes → SBC" misclassifies a board with a 3D GPU but no display output at all. The NanoPi Zero2 just added is exactly this case: RK3528A with a Mali-450, but no HDMI, no DSI, no video out of any kind. It resolves to eSBC only via the SBC definition's conjunctive "display output backed by a 3D GPU". Step 5 should require the GPU actually drive a user-facing display output
  • Step 1 is a subjective intent gate ahead of every objective hardware question. A Jetson Orin NX module exits at step 1 as AI/ML Accelerator and never reaches step 4, which would have said CM/SoM — while the Edge Cases section says the module is a CM/SoM. Consider whether AI/ML should be an orthogonal tag rather than a mutually exclusive branch
  • SoC FPGAs vs pure FPGAs. Note 6 says classify the FPGA board as Dev/Eval because the silicon has no fixed function — sound for iCE40/Artix/Cyclone, but Zynq-7000, Zynq UltraScale+, PolarFire SoC and Agilex SoC have a hard, non-reconfigurable ARM processing system that does have a fixed function
  • Missing multi-vendor SoM standards. The CM/SoM section says it is organised by connector standard but omits every ratified one: PICMG COM Express and COM-HPC, SGET SMARC 2.x (82 × 50 / 82 × 80 mm), Qseven (70 × 70 / 40 × 70 mm) and OSM. These are the dominant industrial standards, and unlike CM4/CM5 they have published, compliance-tested pinouts
  • Missing form factors: Pi Zero (65 × 30 mm, genuine multi-vendor de facto standard — RPi Zero/Zero 2 W, Radxa Zero/Zero 3W, Orange Pi Zero 2W, Geniatech XPI-3566-Zero); Pico-ITX (100 × 72 mm); 3.5-inch SBC (146 × 102 mm); Nano-ITX (120 × 120 mm); PC/104 (90 × 96 mm); M.2 module lengths (2242/2280/22110) for AI accelerators

Minor / style

  • CODE_OF_CONDUCT.md uses * bullets against the repo - convention, and "toward" at line 20 — previously decided to leave as-is to stay close to the upstream Contributor Covenant text. Revisit only if consistency is preferred over fidelity
  • Spaced hyphens used as dashes (-) in the Form Factor Associations lists, where the rest of the document uses an em dash
  • ToC label for the Dev/Eval entry omits the parenthesised abbreviation that its five sibling entries all carry
  • Milk-V Mars is 85 × 56 mm (the Pi 3B footprint), not the ISO/IEC 7810 ID-1 85.6 × 53.98 mm the credit-card entry cites — check whether "credit card sized" should be stated as approximate
  • Cracker origin claim. "Emerged around 2019 (based on market research and Google Trends data)" could not be corroborated, and FriendlyELEC's NanoPi NEO shipped at 40 × 40 mm in 2016. The term itself appears to originate with this document — kept as-is by choice, but the 2019 date may be worth softening
  • PoE HAT pin positioning claim. No source corroborates that the Milk-V Duo S "established a common PoE HAT header pin positioning" across vendors