Created a Systolic Array and its controller which utilises it in a weight stationary fashion. Combined activation and data FIFOs to a single unit (represented as L0 in diagram) for ease of implementation
System Description
- Corelet : It which has the controller, systolic array, SFUs (Special Function Units) & auxilliary FIFO based interfaces connected within it
- Core : Tying to corelet module to the input and output SRAMs as well as the testbench
- core_tb.sv (Testbench) : Reading data from text files; triggering the start of execution; comparing output to golden vectors
Directory Guide
- src : Contains all the RTL files for the entire design
- sim : Contains the Testbench, filelist, waveforms along with the input/output text vectors