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taichi-ishitanitaichi-ishitani
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rewrite with Veryl
1 parent 985e714 commit feb172f

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‎.gitignore‎

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*.f
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Gemfile.lock
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# Veryl
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Veryl.lock
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/.build
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/dependencies
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/generated
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/map

‎Veryl.toml‎

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[project]
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name = "pzbcm"
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version = "0.1.0"
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authors = ["Taichi Ishitani <ishitani@pezy.co.jp>"]
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license = "Apache-2.0"
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repository = "https://github.com/pezy-computing/pzbcm"
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[build]
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clock_type = "posedge"
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reset_type = "async_low"
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filelist_type = "flgen"
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target = {type = "directory", path = "generated"}
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sourcemap_target = {type = "directory", path = "map"}
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omit_project_prefix = true
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reset_low_suffix = "_n"
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hashed_mangled_name = true
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[format]
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indent_width = 2

‎rtl/pzbcm_sram/pzbcm_sram.veryl‎

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//========================================
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//
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// Copyright (c) 2025 PEZY Computing, K.K.
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//
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//========================================
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pub module pzbcm_sram::<PKG: pzbcm_sram_proto_pkg>#(
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param OUTPUT_FIFO : bool = true,
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param WRITE_FIRST : bool = true,
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param RESET_DATA_PATH: bool = true,
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)(
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i_clk : input clock ,
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i_rst : input reset ,
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i_clear : input logic ,
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i_sram_config: input PKG::SRAM_CONFIG_TYPE ,
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port_if : modport pzbcm_sram_if::<PKG>::sram,
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) {
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import PKG::*;
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var write_ready : logic<BANKS>;
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var write_enable : logic<BANKS>;
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var read_ready : logic<BANKS>;
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var read_enable : logic<BANKS>;
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var read_enable_delay: logic<READ_LATENCY, BANKS>;
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var read_data : logic<BANKS, DATA_WIDTH>;
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var read_data_valid : logic<BANKS>;
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var read_info : READ_INFO_TYPE;
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var read_busy : logic;
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var ram_read_data : logic<DATA_WIDTH>;
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var fifo_ready : logic;
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//--------------------------------------------------------------
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// SRAM instance
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//--------------------------------------------------------------
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always_comb {
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port_if.write_ready = write_ready != '0;
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port_if.read_ready = read_ready != '0;
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}
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for i in 0..BANKS :g_bank {
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var match_write : bool;
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var write_pointer: logic<RAM_POINTER_WIDTH>;
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var match_read : bool;
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var read_pointer : logic<RAM_POINTER_WIDTH>;
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always_comb {
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match_write = match_bank(i, port_if.write_pointer);
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write_pointer = get_ram_pointer(port_if.write_pointer);
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match_read = match_bank(i, port_if.read_pointer);
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read_pointer = get_ram_pointer(port_if.read_pointer);
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if !SINGLE_PORT {
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write_ready[i] = match_write;
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write_enable[i] = port_if.write_valid && write_ready[i];
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read_ready[i] = match_read && fifo_ready;
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read_enable[i] = port_if.read_valid && read_ready[i];
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} else if WRITE_FIRST {
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write_ready[i] = match_write;
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write_enable[i] = port_if.write_valid && write_ready[i];
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read_ready[i] = match_read && fifo_ready && (!write_enable[i]);
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read_enable[i] = port_if.read_valid && read_ready[i];
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} else {
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read_ready[i] = match_read && fifo_ready;
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read_enable[i] = port_if.read_valid && read_ready[i];
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write_ready[i] = match_write && (!read_enable[i]);
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write_enable[i] = port_if.write_valid && write_ready[i];
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}
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}
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if SINGLE_PORT :g {
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var enable : logic<1>;
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var write : logic;
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var ram_pointer: logic<1, RAM_POINTER_WIDTH>;
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always_comb {
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enable[0] = write_enable[i] || read_enable[i];
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if write_enable[i] {
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write = '1;
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ram_pointer[0] = write_pointer;
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} else {
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write = '0;
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ram_pointer[0] = read_pointer;
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}
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}
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inst u_sram_wrapper: SRAM_WRAPPER #(
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WORDS : RAM_WORDS ,
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DATA_WIDTH : DATA_WIDTH ,
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POINTER_WIDTH : RAM_POINTER_WIDTH,
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N_PORT : 1 ,
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SRAM_CONFIG_TYPE: SRAM_CONFIG_TYPE ,
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)(
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i_clk : i_clk ,
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i_enable : enable ,
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i_pointer: ram_pointer ,
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i_write : write ,
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i_data : port_if.write_data,
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o_data : read_data[i] ,
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i_config : i_sram_config ,
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);
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} else {
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var enable : logic<2> ;
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var ram_pointer: logic<2, RAM_POINTER_WIDTH>;
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always_comb {
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enable[0] = write_enable[i];
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ram_pointer[0] = write_pointer;
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enable[1] = read_enable[i];
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ram_pointer[1] = read_pointer;
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}
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inst u_sram_wrapper: SRAM_WRAPPER #(
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DATA_WIDTH : DATA_WIDTH ,
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POINTER_WIDTH : RAM_POINTER_WIDTH,
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N_PORT : 2 ,
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SRAM_CONFIG_TYPE: SRAM_CONFIG_TYPE ,
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)(
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i_clk : i_clk ,
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i_enable : enable ,
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i_pointer: ram_pointer ,
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i_write : '0 ,
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i_data : port_if.write_data,
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o_data : read_data[i] ,
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i_config : i_sram_config ,
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);
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}
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}
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function get_ram_pointer_map() -> bit<RAM_POINTER_WIDTH, 16> {
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var map : bit<RAM_POINTER_WIDTH, 16>;
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var bank_lsb : u16;
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var bank_msb : u16;
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var ram_pointer_pos: u16;
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if BANKS >= 2 {
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bank_lsb = BANK_LSB;
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bank_msb = bank_lsb - BANK_WIDTH - 1;
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} else {
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bank_lsb = 0;
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bank_msb = 0;
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}
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ram_pointer_pos = 0;
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for i: u16 in 0..POINTER_WIDTH {
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if (BANKS == 1) || ((i <: bank_lsb) || (i >: bank_msb)) {
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map[ram_pointer_pos] = i;
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ram_pointer_pos += 1;
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}
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}
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return map;
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}
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const POINTER_MAP: bit<RAM_POINTER_WIDTH, 16> = get_ram_pointer_map();
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function get_ram_pointer(
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pointer: input logic<POINTER_WIDTH>
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) -> logic<RAM_POINTER_WIDTH> {
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if BANKS == 1 {
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return pointer;
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} else if BANK_LSB == 0 {
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return (pointer >> BANK_WIDTH) as RAM_POINTER_WIDTH;
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} else {
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var ram_pointer: logic<RAM_POINTER_WIDTH>;
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for i: u16 in 0..RAM_POINTER_WIDTH {
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ram_pointer[i] = pointer[POINTER_MAP[i]];
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}
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return ram_pointer;
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}
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}
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function match_bank(
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bank_index: input u16 ,
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pointer : input logic<POINTER_WIDTH>,
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) -> bool {
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if BANKS == 1 {
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return true;
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} else {
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let bank: logic<BANK_WIDTH> = pointer[BANK_LSB+:BANK_WIDTH];
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return bank == (bank_index as BANK_WIDTH);
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}
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}
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//--------------------------------------------------------------
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// Read Data
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//--------------------------------------------------------------
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always_comb {
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port_if.read_busy = read_busy;
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}
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always_comb {
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read_busy = read_enable_delay != '0;
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read_data_valid = read_enable_delay[READ_LATENCY - 1];
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}
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always_ff {
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if_reset {
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read_enable_delay = '0;
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} else if i_clear {
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read_enable_delay = '0;
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} else {
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for i: u16 in 0..READ_LATENCY {
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if i == 0 {
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read_enable_delay[i] = read_enable;
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} else {
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read_enable_delay[i] = read_enable_delay[i - 1];
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}
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}
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}
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}
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if READ_INFO :g_read_info {
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inst u_read_info_delay: $std::delay #(
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DELAY: READ_LATENCY ,
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TYPE : READ_INFO_TYPE,
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) (
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i_clk: i_clk ,
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i_rst: i_rst ,
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i_d : port_if.read_info,
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o_d : read_info ,
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);
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} else {
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always_comb {
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read_info = 0 as READ_INFO_TYPE;
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}
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}
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if BANKS == 1 :g_ram_read_data {
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always_comb {
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ram_read_data = read_data[0];
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}
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} else {
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inst u_read_data_mux: $std::mux #(
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WIDTH : DATA_WIDTH ,
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ENTRIES: BANKS ,
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KIND : $std::selector_pkg::selector_kind::ONEHOT,
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)(
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i_select: read_data_valid,
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i_data : read_data ,
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o_data : ram_read_data ,
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);
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}
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//--------------------------------------------------------------
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// Output FIFO
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//--------------------------------------------------------------
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if OUTPUT_FIFO :g_output_fifo {
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const FIFO_DATA_WIDTH: u16 = DATA_WIDTH + (if READ_INFO ? $bits(READ_INFO_TYPE) : 0);
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const FIFO_DEPTH : u16 = READ_LATENCY + 2;
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var empty : logic;
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var almost_full: logic;
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var full : logic;
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var push : logic;
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var push_data : logic<FIFO_DATA_WIDTH>;
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var pop : logic;
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var pop_data : logic<FIFO_DATA_WIDTH>;
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always_comb {
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port_if.fifo_empty = empty;
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port_if.fifo_almost_full = almost_full;
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port_if.fifo_full = full;
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}
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always_comb {
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fifo_ready = (!almost_full) || ((!read_busy) && (!full));
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}
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always_comb {
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push = read_data_valid != '0;
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push_data = {read_info, ram_read_data} as FIFO_DATA_WIDTH;
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}
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always_comb {
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pop = port_if.read_data_ready;
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port_if.read_data_valid = !empty;
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port_if.read_data = pop_data as pzbcm_sram_read_data;
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}
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inst u_read_data_fifo: $std::fifo #(
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WIDTH : FIFO_DATA_WIDTH,
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DEPTH : FIFO_DEPTH ,
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THRESHOLD : 2 ,
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RESET_DATA_FF : RESET_DATA_PATH,
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)(
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i_clk : i_clk ,
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i_rst : i_rst ,
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i_clear : i_clear ,
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o_empty : empty ,
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o_almost_full: almost_full,
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o_full : full ,
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o_word_count : _ ,
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i_push : push ,
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i_data : push_data ,
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i_pop : pop ,
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o_data : pop_data ,
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);
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} else {
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always_comb {
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fifo_ready = '1;
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}
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always_comb {
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port_if.fifo_empty = '1;
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port_if.fifo_almost_full = '0;
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port_if.fifo_full = '0;
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port_if.read_data_valid = read_data_valid;
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port_if.read_data = pzbcm_sram_read_data'{ data: ram_read_data, info: read_info };
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}
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}
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}

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