Fix incorrect negative integer literals (#186)

Author: VonTum

src/codegen/system_verilog.rs

@@ -433,7 +433,13 @@ fn display_constant(typ: &ConcreteType, cst: &Value) -> impl Display {
                     Value::Integer(v) => {
                         if bounds.from < &IBig::from(0) {
                             if v < &IBig::from(0) {
-                                write!(f, "-{bitwidth}'sd{}", -v)
+                                let mut higher_pow2 = ibig::ubig!(0);
+                                higher_pow2.set_bit(bitwidth as usize);
+                                let unsigned_equivalent = IBig::from(higher_pow2) + v;
+                                let unsigned_equivalent: UBig =
+                                    UBig::try_from(unsigned_equivalent).unwrap();
+                                assert!(unsigned_equivalent.bit((bitwidth - 1) as usize), "Sign bit must be \"true\", of course, because it's negative.");
+                                write!(f, "{bitwidth}'sh{unsigned_equivalent:x} /* {v} */")
                             } else {
                                 write!(f, "{bitwidth}'sd{v}")
                             }

src/typing/concrete_type.rs

@@ -337,14 +337,13 @@ impl IntBounds<&'_ IBig> {
     pub fn bitwidth(self) -> u64 {
         assert!(!self.is_empty(), "{self}");
         let min = self.from;
-        let max = self.to - IBig::from(1);
         if min < &IBig::from(0) {
             let min_abs: UBig = UBig::try_from(-min).unwrap() - 1;
 
             let bits_for_min = min_abs.bit_len();
 
-            let bits_for_max = if max > IBig::from(0) {
-                let max = UBig::try_from(max).unwrap();
+            let bits_for_max = if *self.to > IBig::from(0) {
+                let max: UBig = UBig::try_from(self.to).unwrap() - 1;
 
                 max.bit_len()
             } else {
@@ -353,7 +352,7 @@ impl IntBounds<&'_ IBig> {
 
             (usize::max(bits_for_min, bits_for_max) + 1) as u64
         } else {
-            let max = UBig::try_from(max).unwrap();
+            let max: UBig = UBig::try_from(self.to).unwrap() - 1;
 
             max.bit_len() as u64
         }
@@ -429,16 +428,41 @@ mod tests {
     #[test]
     #[rustfmt::skip]
     fn test_bound_to_bits() {
+        for unsigned_bitwidth in 0..5 {
+            let to = IBig::from(2_i64.pow(unsigned_bitwidth));
+            assert_eq!(IntBounds{from: &IBig::from(0), to: &to}.bitwidth(), unsigned_bitwidth as u64);
+            assert_eq!(IntBounds{from: &IBig::from(0), to: &(&to+1)}.bitwidth(), (unsigned_bitwidth+1) as u64);
+        }
+        for signed_bitwidth in 1..5 {
+            let from = -IBig::from(2_i64.pow(signed_bitwidth - 1));
+            let to = IBig::from(2_i64.pow(signed_bitwidth - 1));
+            assert_eq!(IntBounds{from: &from, to: &to}.bitwidth(), signed_bitwidth as u64);
+            assert_eq!(IntBounds{from: &(&from-1), to: &to}.bitwidth(), (signed_bitwidth+1) as u64);
+            assert_eq!(IntBounds{from: &from, to: &(&to+1)}.bitwidth(), (signed_bitwidth+1) as u64);
+        }
+        // Try one-sided negative numbers
+        assert_eq!(IntBounds{from: &IBig::from(-1), to: &IBig::from(0)}.bitwidth(), 1);
+        assert_eq!(IntBounds{from: &IBig::from(-2), to: &IBig::from(0)}.bitwidth(), 2);
+        assert_eq!(IntBounds{from: &IBig::from(-3), to: &IBig::from(0)}.bitwidth(), 3);
+        assert_eq!(IntBounds{from: &IBig::from(-4), to: &IBig::from(0)}.bitwidth(), 3);
+        assert_eq!(IntBounds{from: &IBig::from(-5), to: &IBig::from(0)}.bitwidth(), 4);
+        assert_eq!(IntBounds{from: &IBig::from(-6), to: &IBig::from(0)}.bitwidth(), 4);
+        assert_eq!(IntBounds{from: &IBig::from(-7), to: &IBig::from(0)}.bitwidth(), 4);
+        assert_eq!(IntBounds{from: &IBig::from(-8), to: &IBig::from(0)}.bitwidth(), 4);
+
+        assert_eq!(IntBounds{from: &IBig::from(0), to: &IBig::from(1)}.bitwidth(), 0); // Zero sized wires are now possible
+        assert_eq!(IntBounds{from: &IBig::from(0), to: &IBig::from(256)}.bitwidth(), 8);
+        assert_eq!(IntBounds{from: &IBig::from(20), to: &IBig::from(257)}.bitwidth(), 9);
+        assert_eq!(IntBounds{from: &IBig::from(-256), to: &IBig::from(256)}.bitwidth(), 9);
         assert_eq!(IntBounds{from: &IBig::from(-1), to: &IBig::from(1)}.bitwidth(), 1);
         assert_eq!(IntBounds{from: &IBig::from(-2), to: &IBig::from(1)}.bitwidth(), 2);
+        assert_eq!(IntBounds{from: &IBig::from(-2), to: &IBig::from(2)}.bitwidth(), 2);
+        assert_eq!(IntBounds{from: &IBig::from(-3), to: &IBig::from(2)}.bitwidth(), 3);
+        assert_eq!(IntBounds{from: &IBig::from(-2), to: &IBig::from(3)}.bitwidth(), 3);
         assert_eq!(IntBounds{from: &IBig::from(-1), to: &IBig::from(2)}.bitwidth(), 2);
         assert_eq!(IntBounds{from: &IBig::from(-2), to: &IBig::from(3)}.bitwidth(), 3);
         assert_eq!(IntBounds{from: &IBig::from(2), to: &IBig::from(9)}.bitwidth(), 4);
         assert_eq!(IntBounds{from: &IBig::from(-1000), to: &IBig::from(1)}.bitwidth(), 11);
         assert_eq!(IntBounds{from: &IBig::from(-2000), to: &IBig::from(-999)}.bitwidth(), 12);
-        assert_eq!(IntBounds{from: &IBig::from(-256), to: &IBig::from(256)}.bitwidth(), 9);
-        assert_eq!(IntBounds{from: &IBig::from(0), to: &IBig::from(256)}.bitwidth(), 8);
-        assert_eq!(IntBounds{from: &IBig::from(20), to: &IBig::from(257)}.bitwidth(), 9);
-        assert_eq!(IntBounds{from: &IBig::from(0), to: &IBig::from(1)}.bitwidth(), 0); // Zero sized wires are now possible
     }
 }

test.sus

@@ -1852,3 +1852,9 @@ module IntNarrowToZero {
 	int x = IntNarrow#(FROM: 0, TO: 1)(5)
 	int y = IntNarrow#(FROM: -3, TO: 6)(0)
 }
+
+module NegativeIntLiterals {
+	for int I in -10..10 {
+		int j = I
+	}
+}

test.sus_codegen.sv

@@ -1,3 +1,5 @@
-cargo run signed_int_tests.sus -o codegen.sv --top AllTests
+set -e
 
+cargo run signed_int_tests.sus -o codegen.sv --top AllTests
 
+vivado -mode batch -source sim.tcl

test.sus_errors.txt

@@ -181,6 +181,24 @@ module TestSpecificModulos {
     assert_eq#(ID: "Modulo specific case")(l_wide, r_wide, found_wide, 5 mod 6)
 }
 
+module TestNegate#(int FROM, int TO) {
+    for int V in FROM..TO {
+        int v = V
+        int found = -v
+        gen int EXPECTED = -V
+
+        assert_eq#(ID: "- narrow")(v, v, found, EXPECTED)
+
+        int found_from_zero = 0-v
+        assert_eq#(ID: "0-narrow")(v, v, found_from_zero, EXPECTED)
+
+        int#(FROM, TO) v_wide = v
+
+        int found_wide = -v_wide
+        assert_eq#(ID: "- wide  ")(v_wide, v_wide, found_wide, EXPECTED)
+    }
+}
+
 module AllTests {
     TestAdd#(FROM_L: -8, TO_L: 7, FROM_R: -8, TO_R: 7) add_both_signed
     TestAdd#(FROM_L: -8, TO_L: 7, FROM_R: 0, TO_R: 7)  add_l_signed
@@ -216,5 +234,16 @@ module AllTests {
     TestShr#(FROM_L: -8, TO_L: 7, FROM_R: 0, TO_R: 7)  shr_l_signed
     TestShr#(FROM_L: 0, TO_L: 7, FROM_R: 0, TO_R: 7)   shr_unsigned
 
+    TestNegate#(FROM:  0, TO: 6)   neg_unsigned6
+    TestNegate#(FROM:  0, TO: 7)   neg_unsigned7
+    TestNegate#(FROM:  0, TO: 8)   neg_unsigned8
+    TestNegate#(FROM:  0, TO: 9)   neg_unsigned9
+    TestNegate#(FROM: -8, TO: 7)   neg_signed
+
+    int vvv1 = -1
+    int vvv2 = -2
+    int vvv3 = -3
+    int vvv4 = -4
+
     TestSpecificModulos test_specific_modulos
 }

tests/signed_integers/run.sh

@@ -1,6 +1,6 @@
 # Simulate with Vivado
 
-create_project test_signed_ints /tmp/test_signed_ints -part xc7vx485tffg1157-1
+create_project test_signed_ints /tmp/test_signed_ints -part xc7vx485tffg1157-1 -force
 
 add_files harness.sv
 add_files codegen.sv