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Description
DDR5 RDIMMs have the PCAMP port that is connected up to the FPGA. The CAMP port is used to describe things like the Fail_n
and PWR_GOOD
configuration. The default at startup for our PMICs is that this is configured to operate and that if there is a failure, the VRs will be disabled and we will be notified by the pin driving low.
When this occurs, we should treat this as a MAPO event. This represents a failure of one of the rails which means that we're not going to be able operating and this should be acted upon as a similar way to other power failures in this space. The host cannot continue operating in this world. There's no way we will be able to recover losing 1/12th of memory.
As the number of DIMMs that we should watch is variable and DDR5 DIMM presence is indicated based upon SPD communication, we'll need a way to tell the sequencer which DIMMs to look at, probably through some mask register. Due to issues in Rev 1 of Cosmo, we can't talk to SPD without the SP5 group B supplies up, so we'll probably want to put an interlock into place so we don't advance until that's been updated.
If a failure occurs, we can safely kill the bulk management power rail. In general the I3C and related bits are supposed to stay powered based on Vin_mgmt
, which should operate without the 12V bulk rail powered.