shared ENUMs generating multiple types in vhdl package.

[nathanaelhuffman]

with RDL like this:

 reg {
        name = "1V8 Header Debug Control";
         
         enum debug_mux_sel {
            NONE = 8'h00 {desc = "No Outputs assigned here";};
            i2c_dimm0_bus = 8'h01 {desc = "FPGA -> DIMM0 i2c bus to pins";};
            i2c_dimm1_bus = 8'h02 {desc = "FPGA -> DIMM1 i2c bus to pins";};
            i2c_sp5_dimm0_bus = 8'h03 {desc = "SP5 -> FPGA DIMM0 i2c bus to pins";};
            i2c_sp5_dimm1_bus = 8'h04 {desc = "SP5 -> FPGA DIMM1 i2c bus to pins";};
            i2c_sp5_hp_bus = 8'h05 {desc = "SP5 -> FPGA Hotplug i2c bus to pins";};
            i2c_sp_mux_bus = 8'h06 {desc = "SP -> FPGA MUX i2c bus to pins";};
            espi_bus = 8'h07 {desc = "SP5 -> eSPI bus to pins";};
            sp_console_bus = 8'h08 {desc = "SP <-> FPGA console UART to pins";};
            sp5_console_bus = 8'h09 {desc = "SP5 <-> FPGA console UART to pins";};
            sp_ipcc_bus = 8'h0a {desc = "SP <-> FPGA IPCC UART to pins";};
        };
        field {
            desc = "Selects which debug output is sent to the 1v8 debug header in sets of two pins.
            For i2c buses the highest bit is the clock, the next bit is the data.
            For UARTs the highest bit is the 'from FPGA' side the next bit is the 'to FPGA' side.
            Espi buses have defined pins (TBD) to match standard debug setup.";
            encode = debug_mux_sel;
        } pins7_6[31:24] = 0;
        field {
            desc = "Selects which debug output is sent to the 1v8 debug header in sets of two pins.
            For i2c buses the highest bit is the clock, the next bit is the data.
            For UARTs the highest bit is the 'from FPGA' side the next bit is the 'to FPGA' side.
            Espi buses have defined pins (TBD) to match standard debug setup.";
            encode = debug_mux_sel;
        } pins5_4[23:16] = 0;
} dbg_1v8_ctrl;

we should really only generate 1 type and set of functions with the enum in it and properly share it but we currently generate multiple identical types with different names:

 -- Register-specific Enums
  type dbg_1v8_ctrl_pins7_6 is (
    NONE, -- 0
    I2C_DIMM0_BUS, -- 1
    I2C_DIMM1_BUS, -- 2
    I2C_SP5_DIMM0_BUS, -- 3
    I2C_SP5_DIMM1_BUS, -- 4
    I2C_SP5_HP_BUS, -- 5
    I2C_SP_MUX_BUS, -- 6
    ESPI_BUS, -- 7
    SP_CONSOLE_BUS, -- 8
    SP5_CONSOLE_BUS, -- 9
    SP_IPCC_BUS); -- 10
  type dbg_1v8_ctrl_pins5_4 is (
    NONE, -- 0
    I2C_DIMM0_BUS, -- 1
    I2C_DIMM1_BUS, -- 2
    I2C_SP5_DIMM0_BUS, -- 3
    I2C_SP5_DIMM1_BUS, -- 4
    I2C_SP5_HP_BUS, -- 5
    I2C_SP_MUX_BUS, -- 6
    ESPI_BUS, -- 7
    SP_CONSOLE_BUS, -- 8
    SP5_CONSOLE_BUS, -- 9
    SP_IPCC_BUS); -- 10

We should fix this