@@ -68,7 +68,7 @@ module mkControllerTargetPresentTest (Empty);
6868 endaction
6969 par
7070 await( bench.controller.presence_summary[ 0 ] ) ;
71- await_set ( bench.target.controller0_present) ;
71+ await ( bench.target.controller0_present) ;
7272 endpar
7373
7474 assert_controller_register_eq(
@@ -92,40 +92,63 @@ module mkTargetRoTFaultTest (Empty);
9292 10 * max( protocol_parameters.hello_interval,
9393 protocol_parameters.status_interval)) ;
9494
95- // let controller_state = bench.controller.registers.controller_state;
96- // let target_system_status = bench.controller.registers.target_system_status;
97- // let target_system_faults = bench.controller.registers.target_system_faults;
95+ Reg # ( SystemFaults) target_system_events < - mkReg( defaultValue) ;
96+
97+ function read_controller_0_register_into( id, d) =
98+ read_controller_register_into( bench.controller, 0 , id, asIfc( d)) ;
99+
100+ function read_controller_0_registers_while( predicate) =
101+ seq
102+ while ( predicate) seq
103+ read_controller_0_register_into(
104+ TargetSystemEvents,
105+ target_system_events) ;
106+ // Avoid a tight loop reading the registers otherwise the
107+ // Controller will not make progress due to this interface
108+ // having the highest priority.
109+ repeat ( 3 ) bench.await_tick() ;
110+ endseq
111+ endseq ;
98112
99113 mkAutoFSM( seq
100- // action
101- // bench.controller_to_target.set_state(Connected);
102- // bench.target_to_controller.set_state(Connected);
103- // endaction
104- // par
105- // await_set(controller_state.target_present);
106- // await_set(target_system_status.controller0_detected);
107- // endpar
108-
109- // // Assert no target system faults and set an RoT fault.
110- // assert_eq(
111- // target_system_faults,
112- // defaultValue,
113- // "expected no target system faults");
114- // bench.set_target_system_faults(system_faults_rot);
115-
116- // // Assert the fault is observed by the Controller.
117- // await_set(target_system_faults.rot_fault);
118- // assert_set(target_system_faults.rot_fault, "expected RoT fault");
119-
120- // // Resolve the RoT fault.
121- // bench.set_target_system_faults(system_faults_none);
122-
123- // // Assert the RoT fault cleared.
124- // await_not_set(target_system_faults.rot_fault);
125- // assert_eq(
126- // target_system_faults,
127- // defaultValue,
128- // "expected no target system faults");
114+ action
115+ bench.controller_to_target.set_state( Connected) ;
116+ bench.target_to_controller.set_state( Connected) ;
117+ bench.controller.registers.request.put(
118+ RegisterRequest {
119+ id : 0 ,
120+ register : TransceiverState,
121+ op : tagged Write extend(
122+ { pack( EnabledWhenReceiverAligned) , 4'h0 } ) } ) ;
123+ endaction
124+ par
125+ await( bench.controller.presence_summary[ 0 ] ) ;
126+ await( bench.target.controller0_present) ;
127+ endpar
128+
129+ // Assert no Target system faults and set an RoT fault.
130+ assert_controller_register_eq(
131+ bench.controller, 0 , TargetSystemEvents,
132+ system_faults_none,
133+ " expected no target system faults" ) ;
134+ bench.set_target_system_faults( system_faults_rot) ;
135+
136+ // Assert the fault is observed by the Controller.
137+ read_controller_0_registers_while( ! target_system_events.rot) ;
138+ assert_controller_register_eq(
139+ bench.controller, 0 , TargetSystemEvents,
140+ system_faults_rot,
141+ " expected an RoT faults" ) ;
142+
143+ // Resolve the RoT fault.
144+ bench.set_target_system_faults( system_faults_none) ;
145+
146+ // Assert the RoT fault cleared.
147+ read_controller_0_registers_while( target_system_events.rot) ;
148+ assert_controller_register_eq(
149+ bench.controller, 0 , TargetSystemEvents,
150+ system_faults_none,
151+ " expected no target system faults" ) ;
129152 endseq ) ;
130153endmodule
131154
@@ -369,31 +392,20 @@ module mkReceiversLockedTimeoutTest (Empty);
369392 mkIgnitionControllerAndTargetBench( parameters, 1000 ) ;
370393
371394 mkAutoFSM( seq
395+ clear_controller_counter( bench.controller, 0 , ControllerReceiverReset) ;
396+
372397 // The link between Controller and Target is not connected, causing both
373398 // receivers never to reach locked state.
374-
375- // Reset the controller link status register, clearing any events.
376- // action
377- // let _ <- bench.controller.registers.controller_link_status;
378- // endaction
379-
380399 par
381- // repeat(4) seq
382- // await(bench.controller_receiver_locked_timeout);
383-
384- // // Wait for the receiver reset event bit to be set in the link
385- // // status register.
386- // // action
387- // // let link_status <-
388- // // bench.controller.registers.controller_link_status;
389-
390- // // await_set(link_status.receiver_reset_event);
391- // // endaction
392- // endseq
393-
394400 repeat ( 4 ) await( bench.target_receiver_locked_timeout[ 0 ] ) ;
395401 repeat ( 4 ) await( bench.target_receiver_locked_timeout[ 1 ] ) ;
396402 endpar
403+
404+ assert_controller_counter_eq(
405+ bench.controller,
406+ 0 , ControllerReceiverReset,
407+ 3 ,
408+ " expected Controller reset events" ) ;
397409 endseq ) ;
398410endmodule
399411
@@ -417,9 +429,12 @@ module mkNoLockedTimeoutIfReceiversLockedTest (Empty);
417429 ! bench.controller_receiver_locked_timeout,
418430 " expected no Controller receiver locked timeout" ) ;
419431
420- continuousAssert(
421- ! bench.target_receiver_locked_timeout[ 0 ] ,
422- " expected no receiver locked timeout for Target link 0" ) ;
432+ (* fire_when_enabled *)
433+ rule do_assert_target_receiver_locked_timeout
434+ ( bench.controller_transmitter_output_enabled) ;
435+ assert_true( ! bench.target_receiver_locked_timeout[ 0 ] ,
436+ " expected no receiver locked timeout for Target link 0" ) ;
437+ endrule
423438
424439 mkAutoFSM( seq
425440 action
@@ -429,7 +444,7 @@ module mkNoLockedTimeoutIfReceiversLockedTest (Empty);
429444 RegisterRequest {
430445 id : 0 ,
431446 register : TransceiverState,
432- op : tagged Write 'h20 } ) ;
447+ op : tagged Write ( { 2'h0 , pack ( AlwaysEnabled ) , 4'h0 } ) } ) ;
433448 endaction
434449
435450 par
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