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    223 repositories

    • panamax

      Public
      The Panamax 130-pin padframe for SkyWater sky130
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 14, 2025Feb 14, 2025

    • frigate_analog

      Public
      The analog signal processing and timing frontend subsystems for the Frigate harness chip
      Apache License 2.0
      •0•0•0•0•Updated Feb 14, 2025Feb 14, 2025

    • IHP-Open-PDK

      Public
      130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
      HTML
      •
      Apache License 2.0
      •70•0•1•0•Updated Feb 14, 2025Feb 14, 2025

    • openlane-metrics

      Public
      Repository to store metric results for OpenLane 2.0.0+
      0•0•0•0•Updated Feb 13, 2025Feb 13, 2025

    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      flowasicedaverilogvlsipnrsiliconlvsflowssta
      Python
      •
      Apache License 2.0
      •45•265•82•8•Updated Feb 13, 2025Feb 13, 2025

    • EF_UART

      Public
      Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
      Verilog
      •
      Apache License 2.0
      •3•8•8•1•Updated Feb 13, 2025Feb 13, 2025

    • sky130_ef_ip__template

      Public template
      A template repository for analog designs to ensure consistency and interoperability between IP blocks.
      Apache License 2.0
      •0•0•0•0•Updated Feb 13, 2025Feb 13, 2025

    • caravel

      Public
      Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
      magicyosyscaravelpicorv32openroadvexriscvopenramsky130
      Verilog
      •
      Apache License 2.0
      •69•308•96•5•Updated Feb 12, 2025Feb 12, 2025

    • caravel-sim-infrastructure

      Public
      HTML
      •
      Apache License 2.0
      •4•1•3•1•Updated Feb 12, 2025Feb 12, 2025

    • frigate-os

      Public
      Verilog
      •0•0•0•0•Updated Feb 11, 2025Feb 11, 2025

    • openlane2-ci-designs

      Public
      Continuous Integration Designs for OpenLane 2.0.0 or higher
      Verilog
      •1•0•0•1•Updated Feb 11, 2025Feb 11, 2025

    • nix-eda

      Public
      Nix derivations for EDA tools
      nixedaelectronic-design-automationnix-flake
      Nix
      •
      Apache License 2.0
      •3•9•2•0•Updated Feb 11, 2025Feb 11, 2025

    • EF_SRAM_1024x32

      Public
      Verilog
      •0•3•7•0•Updated Feb 10, 2025Feb 10, 2025

    • nldiff

      Public
      Simple netlist comparison utility
      Python
      •
      Apache License 2.0
      •0•3•0•0•Updated Feb 10, 2025Feb 10, 2025

    • openlane2-step-unit-tests

      Public
      Step-specific Unit Tests for OpenLane 2.0.0+
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 10, 2025Feb 10, 2025

    • ipm

      Public
      Open-source IPs Package Manager (IPM)
      Python
      •
      Apache License 2.0
      •2•14•7•3•Updated Feb 10, 2025Feb 10, 2025

    • caravel_SI_testing

      Public
      C
      •1•2•3•4•Updated Feb 9, 2025Feb 9, 2025

    • BusWrap

      Public
      Python
      •0•5•6•0•Updated Feb 9, 2025Feb 9, 2025

    • cace

      Public
      Circuit Automatic Characterization Engine
      Python
      •
      Apache License 2.0
      •7•47•25•3•Updated Feb 7, 2025Feb 7, 2025

    • openframe_user_project

      Public template
      Example digital project for the Efabless Caravel "openframe" harness
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 7, 2025Feb 7, 2025

    • mpw_precheck

      Public
      Python
      •
      Apache License 2.0
      •24•36•40•6•Updated Feb 7, 2025Feb 7, 2025

    • caravel_user_mini

      Public template
      Verilog
      •
      Apache License 2.0
      •1•3•2•2•Updated Feb 7, 2025Feb 7, 2025

    • caravel_user_project_analog

      Public template
      Verilog
      •
      Apache License 2.0
      •89•45•6•2•Updated Feb 7, 2025Feb 7, 2025

    • caravel_user_project

      Public template
      https://caravel-user-project.readthedocs.io
      Verilog
      •
      Apache License 2.0
      •335•190•85•23•Updated Feb 7, 2025Feb 7, 2025

    • EF_WDT32

      Public
      A simple WatchDog Timer (WDT)
      Verilog
      •
      Apache License 2.0
      •1•0•0•0•Updated Feb 6, 2025Feb 6, 2025

    • caravel_user_UART

      Public
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 6, 2025Feb 6, 2025

    • caravel_user_sram

      Public
      Verilog
      •
      Apache License 2.0
      •0•4•7•1•Updated Feb 6, 2025Feb 6, 2025

    • EF_SHA256

      Public
      Verilog
      •0•0•2•0•Updated Feb 6, 2025Feb 6, 2025

    • EF_AES

      Public
      Verilog
      •0•0•1•0•Updated Feb 6, 2025Feb 6, 2025

    • EF_GPIO8

      Public
      A generic 8-bit General Purpose I/O (GPIO) Peripheral
      Verilog
      •
      Apache License 2.0
      •1•1•1•0•Updated Feb 6, 2025Feb 6, 2025