diff --git a/src/hotspot/cpu/x86/assembler_x86.cpp b/src/hotspot/cpu/x86/assembler_x86.cpp
index 29e4fcee2f63a..473a1856b25fa 100644
--- a/src/hotspot/cpu/x86/assembler_x86.cpp
+++ b/src/hotspot/cpu/x86/assembler_x86.cpp
@@ -1549,7 +1549,6 @@ void Assembler::addr_nop_8() {
 }
 
 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
@@ -1557,7 +1556,6 @@ void Assembler::addsd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::addsd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -1568,14 +1566,12 @@ void Assembler::addsd(XMMRegister dst, Address src) {
 }
 
 void Assembler::addss(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x58, (0xC0 | encode));
 }
 
 void Assembler::addss(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -2032,7 +2028,6 @@ void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
 void Assembler::comisd(XMMRegister dst, Address src) {
   // NOTE: dbx seems to decode this as comiss even though the
   // 0x66 is there. Strangely ucomisd comes out correct
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -2043,7 +2038,6 @@ void Assembler::comisd(XMMRegister dst, Address src) {
 }
 
 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -2051,7 +2045,6 @@ void Assembler::comisd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::comiss(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -2061,7 +2054,6 @@ void Assembler::comiss(XMMRegister dst, Address src) {
 }
 
 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x2F, (0xC0 | encode));
@@ -2163,7 +2155,6 @@ void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
 }
 
 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xE6, (0xC0 | encode));
@@ -2226,7 +2217,6 @@ void Assembler::vcvtph2ps(XMMRegister dst, Address src, int vector_len) {
 }
 
 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x5B, (0xC0 | encode));
@@ -2240,7 +2230,6 @@ void Assembler::vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
 }
 
 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
@@ -2248,7 +2237,6 @@ void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -2259,14 +2247,12 @@ void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
 }
 
 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes, true);
   emit_int16(0x2A, (0xC0 | encode));
 }
 
 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -2276,14 +2262,12 @@ void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
 }
 
 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes, true);
   emit_int16(0x2A, (0xC0 | encode));
 }
 
 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -2293,21 +2277,18 @@ void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
 }
 
 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes, true);
   emit_int16(0x2A, (0xC0 | encode));
 }
 
 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x5A, (0xC0 | encode));
 }
 
 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -2318,28 +2299,24 @@ void Assembler::cvtss2sd(XMMRegister dst, Address src) {
 
 
 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
   emit_int16(0x2C, (0xC0 | encode));
 }
 
 void Assembler::cvtss2sil(Register dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x2D, (0xC0 | encode));
 }
 
 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x2C, (0xC0 | encode));
 }
 
 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -2552,7 +2529,6 @@ void Assembler::edecl(Register dst, Address src, bool no_flags) {
 }
 
 void Assembler::divsd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -2563,7 +2539,6 @@ void Assembler::divsd(XMMRegister dst, Address src) {
 }
 
 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
@@ -2571,7 +2546,6 @@ void Assembler::divsd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::divss(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -2581,7 +2555,6 @@ void Assembler::divss(XMMRegister dst, Address src) {
 }
 
 void Assembler::divss(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x5E, (0xC0 | encode));
@@ -2853,7 +2826,6 @@ void Assembler::ldmxcsr( Address src) {
     emit_int8((unsigned char)0xAE);
     emit_operand(as_Register(2), src, 0);
   } else {
-    NOT_LP64(assert(VM_Version::supports_sse(), ""));
     InstructionMark im(this);
     prefix(src, true /* is_map1 */);
     emit_int8((unsigned char)0xAE);
@@ -2935,13 +2907,11 @@ void Assembler::elzcntl(Register dst, Address src, bool no_flags) {
 
 // Emit mfence instruction
 void Assembler::mfence() {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
   emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF0);
 }
 
 // Emit sfence instruction
 void Assembler::sfence() {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
   emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF8);
 }
 
@@ -2950,7 +2920,6 @@ void Assembler::mov(Register dst, Register src) {
 }
 
 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
@@ -2959,7 +2928,6 @@ void Assembler::movapd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
@@ -2967,7 +2935,6 @@ void Assembler::movaps(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x16, (0xC0 | encode));
@@ -3403,14 +3370,12 @@ void Assembler::movb(Address dst, Register src) {
 }
 
 void Assembler::movdl(XMMRegister dst, Register src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes, true);
   emit_int16(0x6E, (0xC0 | encode));
 }
 
 void Assembler::movdl(Register dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   // swap src/dst to get correct prefix
   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes, true);
@@ -3418,7 +3383,6 @@ void Assembler::movdl(Register dst, XMMRegister src) {
 }
 
 void Assembler::movdl(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -3428,7 +3392,6 @@ void Assembler::movdl(XMMRegister dst, Address src) {
 }
 
 void Assembler::movdl(Address dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -3438,14 +3401,12 @@ void Assembler::movdl(Address dst, XMMRegister src) {
 }
 
 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x6F, (0xC0 | encode));
 }
 
 void Assembler::movdqa(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
@@ -3455,7 +3416,6 @@ void Assembler::movdqa(XMMRegister dst, Address src) {
 }
 
 void Assembler::movdqu(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
@@ -3465,14 +3425,12 @@ void Assembler::movdqu(XMMRegister dst, Address src) {
 }
 
 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x6F, (0xC0 | encode));
 }
 
 void Assembler::movdqu(Address dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
@@ -3917,7 +3875,6 @@ void Assembler::movl(Address dst, Register src) {
 // when loading from memory. But for old Opteron use movlpd instead of movsd.
 // The selection is done in MacroAssembler::movdbl() and movflt().
 void Assembler::movlpd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -3928,7 +3885,6 @@ void Assembler::movlpd(XMMRegister dst, Address src) {
 }
 
 void Assembler::movq(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -3939,7 +3895,6 @@ void Assembler::movq(XMMRegister dst, Address src) {
 }
 
 void Assembler::movq(Address dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -3950,7 +3905,6 @@ void Assembler::movq(Address dst, XMMRegister src) {
 }
 
 void Assembler::movq(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -3958,7 +3912,6 @@ void Assembler::movq(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::movq(Register dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   // swap src/dst to get correct prefix
   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes, true);
@@ -3966,7 +3919,6 @@ void Assembler::movq(Register dst, XMMRegister src) {
 }
 
 void Assembler::movq(XMMRegister dst, Register src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes, true);
   emit_int16(0x6E, (0xC0 | encode));
@@ -3986,7 +3938,6 @@ void Assembler::movsbl(Register dst, Register src) { // movsxb
 }
 
 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
@@ -3994,7 +3945,6 @@ void Assembler::movsd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::movsd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -4005,7 +3955,6 @@ void Assembler::movsd(XMMRegister dst, Address src) {
 }
 
 void Assembler::movsd(Address dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -4025,14 +3974,12 @@ void Assembler::vmovsd(XMMRegister dst, XMMRegister src, XMMRegister src2) {
 }
 
 void Assembler::movss(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x10, (0xC0 | encode));
 }
 
 void Assembler::movss(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -4042,7 +3989,6 @@ void Assembler::movss(XMMRegister dst, Address src) {
 }
 
 void Assembler::movss(Address dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -4065,7 +4011,6 @@ void Assembler::movswl(Register dst, Register src) { // movsxw
 }
 
 void Assembler::movups(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
@@ -4085,7 +4030,6 @@ void Assembler::vmovups(XMMRegister dst, Address src, int vector_len) {
 }
 
 void Assembler::movups(Address dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
@@ -4183,7 +4127,6 @@ void Assembler::emull(Register src, bool no_flags) {
 }
 
 void Assembler::mulsd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -4194,7 +4137,6 @@ void Assembler::mulsd(XMMRegister dst, Address src) {
 }
 
 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
@@ -4202,7 +4144,6 @@ void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::mulss(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -4212,7 +4153,6 @@ void Assembler::mulss(XMMRegister dst, Address src) {
 }
 
 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x59, (0xC0 | encode));
@@ -4675,7 +4615,6 @@ void Assembler::eorb(Register dst, Address src1, Register src2, bool no_flags) {
 }
 
 void Assembler::packsswb(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x63, (0xC0 | encode));
@@ -4689,7 +4628,6 @@ void Assembler::vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int
 }
 
 void Assembler::packssdw(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x6B, (0xC0 | encode));
@@ -4703,7 +4641,6 @@ void Assembler::vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int
 }
 
 void Assembler::packuswb(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
@@ -4714,7 +4651,6 @@ void Assembler::packuswb(XMMRegister dst, Address src) {
 }
 
 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x67, (0xC0 | encode));
@@ -4895,7 +4831,6 @@ void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
 
 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x74, (0xC0 | encode));
@@ -5043,7 +4978,6 @@ void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Addre
 
 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x75, (0xC0 | encode));
@@ -5092,7 +5026,6 @@ void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vect
 
 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x76, (0xC0 | encode));
@@ -5197,7 +5130,6 @@ void Assembler::pcmpgtq(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::pmovmskb(Register dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xD7, (0xC0 | encode));
@@ -5263,7 +5195,6 @@ void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
 }
 
 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int24((unsigned char)0xC5, (0xC0 | encode), imm8);
@@ -5349,14 +5280,12 @@ void Assembler::vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8
 }
 
 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes, true);
   emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8);
 }
 
 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
@@ -5666,7 +5595,6 @@ void Assembler::vpmovzxwq(XMMRegister dst, XMMRegister src, int vector_len) {
 }
 
 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xF5, (0xC0 | encode));
@@ -5893,7 +5821,6 @@ void Assembler::popl(Address dst) {
 #endif
 
 void Assembler::prefetchnta(Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
   InstructionMark im(this);
   prefix(src, true /* is_map1 */);
   emit_int8(0x18);
@@ -5909,7 +5836,6 @@ void Assembler::prefetchr(Address src) {
 }
 
 void Assembler::prefetcht0(Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
   InstructionMark im(this);
   prefix(src, true /* is_map1 */);
   emit_int8(0x18);
@@ -5917,7 +5843,6 @@ void Assembler::prefetcht0(Address src) {
 }
 
 void Assembler::prefetcht1(Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
   InstructionMark im(this);
   prefix(src, true /* is_map1 */);
   emit_int8(0x18);
@@ -5925,7 +5850,6 @@ void Assembler::prefetcht1(Address src) {
 }
 
 void Assembler::prefetcht2(Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
   InstructionMark im(this);
   prefix(src, true /* is_map1 */);
   emit_int8(0x18);
@@ -6002,7 +5926,6 @@ void Assembler::pshufb(XMMRegister dst, Address src) {
 
 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
   assert(isByte(mode), "invalid value");
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -6013,7 +5936,6 @@ void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_l
   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
          (vector_len == AVX_256bit? VM_Version::supports_avx2() :
          (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)), "");
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
@@ -6021,7 +5943,6 @@ void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_l
 
 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
   assert(isByte(mode), "invalid value");
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
@@ -6034,7 +5955,6 @@ void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
 
 void Assembler::pshufhw(XMMRegister dst, XMMRegister src, int mode) {
   assert(isByte(mode), "invalid value");
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
@@ -6044,7 +5964,6 @@ void Assembler::vpshufhw(XMMRegister dst, XMMRegister src, int mode, int vector_
     assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
             (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
             (vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)), "");
-    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
     InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
     int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
     emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
@@ -6052,7 +5971,6 @@ void Assembler::vpshufhw(XMMRegister dst, XMMRegister src, int mode, int vector_
 
 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
   assert(isByte(mode), "invalid value");
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
   emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
@@ -6060,7 +5978,6 @@ void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
 
 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
   assert(isByte(mode), "invalid value");
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
@@ -6075,7 +5992,6 @@ void Assembler::vpshuflw(XMMRegister dst, XMMRegister src, int mode, int vector_
     assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
             (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
             (vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)), "");
-    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
     InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
     int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
     emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
@@ -6092,7 +6008,6 @@ void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, i
 
 void Assembler::shufpd(XMMRegister dst, XMMRegister src, int imm8) {
   assert(isByte(imm8), "invalid value");
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
@@ -6107,7 +6022,6 @@ void Assembler::vshufpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int i
 
 void Assembler::shufps(XMMRegister dst, XMMRegister src, int imm8) {
   assert(isByte(imm8), "invalid value");
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
@@ -6121,7 +6035,6 @@ void Assembler::vshufps(XMMRegister dst, XMMRegister nds, XMMRegister src, int i
 
 void Assembler::psrldq(XMMRegister dst, int shift) {
   // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int24(0x73, (0xC0 | encode), shift);
@@ -6138,7 +6051,6 @@ void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_
 
 void Assembler::pslldq(XMMRegister dst, int shift) {
   // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   // XMM7 is for /7 encoding: 66 0F 73 /7 ib
   int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -6234,7 +6146,6 @@ void Assembler::evptestnmd(KRegister dst, XMMRegister nds, XMMRegister src, int
 }
 
 void Assembler::punpcklbw(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
@@ -6245,14 +6156,12 @@ void Assembler::punpcklbw(XMMRegister dst, Address src) {
 }
 
 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x60, (0xC0 | encode));
 }
 
 void Assembler::punpckldq(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
@@ -6263,14 +6172,12 @@ void Assembler::punpckldq(XMMRegister dst, Address src) {
 }
 
 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x62, (0xC0 | encode));
 }
 
 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -6426,14 +6333,12 @@ void Assembler::ercll(Register dst, Register src, int imm8) {
 }
 
 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x53, (0xC0 | encode));
 }
 
 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x53, (0xC0 | encode));
@@ -7134,7 +7039,6 @@ void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) {
 }
 
 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
@@ -7142,7 +7046,6 @@ void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::sqrtsd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -7153,7 +7056,6 @@ void Assembler::sqrtsd(XMMRegister dst, Address src) {
 }
 
 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x51, (0xC0 | encode));
@@ -7164,7 +7066,6 @@ void Assembler::std() {
 }
 
 void Assembler::sqrtss(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -7185,7 +7086,6 @@ void Assembler::stmxcsr(Address dst) {
     emit_int8((unsigned char)0xAE);
     emit_operand(as_Register(3), dst, 0);
   } else {
-    NOT_LP64(assert(VM_Version::supports_sse(), ""));
     InstructionMark im(this);
     prefix(dst, true /* is_map1 */);
     emit_int8((unsigned char)0xAE);
@@ -7276,7 +7176,6 @@ void Assembler::esubl(Register dst, Register src1, Register src2, bool no_flags)
 }
 
 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
@@ -7284,7 +7183,6 @@ void Assembler::subsd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::subsd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -7295,14 +7193,12 @@ void Assembler::subsd(XMMRegister dst, Address src) {
 }
 
 void Assembler::subss(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x5C, (0xC0 | encode));
 }
 
 void Assembler::subss(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -7438,7 +7334,6 @@ void Assembler::etzcntq(Register dst, Address src, bool no_flags) {
 }
 
 void Assembler::ucomisd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -7449,7 +7344,6 @@ void Assembler::ucomisd(XMMRegister dst, Address src) {
 }
 
 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -7457,7 +7351,6 @@ void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::ucomiss(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
@@ -7467,7 +7360,6 @@ void Assembler::ucomiss(XMMRegister dst, Address src) {
 }
 
 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x2E, (0xC0 | encode));
@@ -7859,7 +7751,6 @@ void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 // Float-point vector arithmetic
 
 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -7867,7 +7758,6 @@ void Assembler::addpd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::addpd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
@@ -7879,7 +7769,6 @@ void Assembler::addpd(XMMRegister dst, Address src) {
 
 
 void Assembler::addps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x58, (0xC0 | encode));
@@ -7922,7 +7811,6 @@ void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector
 }
 
 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -7930,7 +7818,6 @@ void Assembler::subpd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::subps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x5C, (0xC0 | encode));
@@ -7973,7 +7860,6 @@ void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector
 }
 
 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -7981,7 +7867,6 @@ void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::mulpd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
@@ -7992,7 +7877,6 @@ void Assembler::mulpd(XMMRegister dst, Address src) {
 }
 
 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x59, (0xC0 | encode));
@@ -8069,7 +7953,6 @@ void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int
 }
 
 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -8077,7 +7960,6 @@ void Assembler::divpd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::divps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x5E, (0xC0 | encode));
@@ -8211,7 +8093,6 @@ void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
 }
 
 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -8219,7 +8100,6 @@ void Assembler::andpd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::andnpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -8227,14 +8107,12 @@ void Assembler::andnpd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::andps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x54, (0xC0 | encode));
 }
 
 void Assembler::andps(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
@@ -8244,7 +8122,6 @@ void Assembler::andps(XMMRegister dst, Address src) {
 }
 
 void Assembler::andpd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
@@ -8291,7 +8168,6 @@ void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector
 }
 
 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -8300,7 +8176,6 @@ void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -8308,7 +8183,6 @@ void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -8316,14 +8190,12 @@ void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x57, (0xC0 | encode));
 }
 
 void Assembler::xorpd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
@@ -8334,7 +8206,6 @@ void Assembler::xorpd(XMMRegister dst, Address src) {
 }
 
 void Assembler::xorps(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
@@ -8397,28 +8268,24 @@ void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int v
 }
 
 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xFC, (0xC0 | encode));
 }
 
 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xFD, (0xC0 | encode));
 }
 
 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xFE, (0xC0 | encode));
 }
 
 void Assembler::paddd(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -8427,7 +8294,6 @@ void Assembler::paddd(XMMRegister dst, Address src) {
 }
 
 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -8738,14 +8604,12 @@ void Assembler::vpsubusw(XMMRegister dst, XMMRegister nds, Address src, int vect
 
 
 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xF8, (0xC0 | encode));
 }
 
 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xF9, (0xC0 | encode));
@@ -8758,7 +8622,6 @@ void Assembler::psubd(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -8837,7 +8700,6 @@ void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector
 }
 
 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xD5, (0xC0 | encode));
@@ -8851,7 +8713,6 @@ void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
 }
 
 void Assembler::pmuludq(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xF4, (0xC0 | encode));
@@ -8952,7 +8813,6 @@ void Assembler::vpminsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int v
 }
 
 void Assembler::pminsw(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xEA, (0xC0 | encode));
@@ -8990,7 +8850,6 @@ void Assembler::vpminsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int v
 }
 
 void Assembler::minps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x5D, (0xC0 | encode));
@@ -9003,7 +8862,6 @@ void Assembler::vminps(XMMRegister dst, XMMRegister nds, XMMRegister src, int ve
 }
 
 void Assembler::minpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x5D, (0xC0 | encode));
@@ -9031,7 +8889,6 @@ void Assembler::vpmaxsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int v
 }
 
 void Assembler::pmaxsw(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xEE, (0xC0 | encode));
@@ -9069,7 +8926,6 @@ void Assembler::vpmaxsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int v
 }
 
 void Assembler::maxps(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
   emit_int16(0x5F, (0xC0 | encode));
@@ -9083,7 +8939,6 @@ void Assembler::vmaxps(XMMRegister dst, XMMRegister nds, XMMRegister src, int ve
 }
 
 void Assembler::maxpd(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16(0x5F, (0xC0 | encode));
@@ -9438,7 +9293,6 @@ void Assembler::evpmaxuq(XMMRegister dst, KRegister mask, XMMRegister nds, Addre
 
 // Shift packed integers left by specified number of bits.
 void Assembler::psllw(XMMRegister dst, int shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   // XMM6 is for /6 encoding: 66 0F 71 /6 ib
   int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9446,7 +9300,6 @@ void Assembler::psllw(XMMRegister dst, int shift) {
 }
 
 void Assembler::pslld(XMMRegister dst, int shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   // XMM6 is for /6 encoding: 66 0F 72 /6 ib
   int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9454,7 +9307,6 @@ void Assembler::pslld(XMMRegister dst, int shift) {
 }
 
 void Assembler::psllq(XMMRegister dst, int shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   // XMM6 is for /6 encoding: 66 0F 73 /6 ib
   int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9462,21 +9314,18 @@ void Assembler::psllq(XMMRegister dst, int shift) {
 }
 
 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xF1, (0xC0 | encode));
 }
 
 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xF2, (0xC0 | encode));
 }
 
 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9493,7 +9342,6 @@ void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_l
 
 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
   assert(UseAVX > 0, "requires some form of AVX");
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   // XMM6 is for /6 encoding: 66 0F 72 /6 ib
   int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9533,7 +9381,6 @@ void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int
 
 // Shift packed integers logically right by specified number of bits.
 void Assembler::psrlw(XMMRegister dst, int shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   // XMM2 is for /2 encoding: 66 0F 71 /2 ib
   int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9541,7 +9388,6 @@ void Assembler::psrlw(XMMRegister dst, int shift) {
 }
 
 void Assembler::psrld(XMMRegister dst, int shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   // XMM2 is for /2 encoding: 66 0F 72 /2 ib
   int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9551,7 +9397,6 @@ void Assembler::psrld(XMMRegister dst, int shift) {
 void Assembler::psrlq(XMMRegister dst, int shift) {
   // Do not confuse it with psrldq SSE2 instruction which
   // shifts 128 bit value in xmm register by number of bytes.
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   // XMM2 is for /2 encoding: 66 0F 73 /2 ib
@@ -9560,21 +9405,18 @@ void Assembler::psrlq(XMMRegister dst, int shift) {
 }
 
 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xD1, (0xC0 | encode));
 }
 
 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xD2, (0xC0 | encode));
 }
 
 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9646,7 +9488,6 @@ void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int
 
 // Shift packed integers arithmetically right by specified number of bits.
 void Assembler::psraw(XMMRegister dst, int shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   // XMM4 is for /4 encoding: 66 0F 71 /4 ib
   int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9654,7 +9495,6 @@ void Assembler::psraw(XMMRegister dst, int shift) {
 }
 
 void Assembler::psrad(XMMRegister dst, int shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   // XMM4 is for /4 encoding: 66 0F 72 /4 ib
   int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9664,14 +9504,12 @@ void Assembler::psrad(XMMRegister dst, int shift) {
 }
 
 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xE1, (0xC0 | encode));
 }
 
 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xE2, (0xC0 | encode));
@@ -9727,7 +9565,6 @@ void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int
 
 // logical operations packed integers
 void Assembler::pand(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xDB, (0xC0 | encode));
@@ -9830,7 +9667,6 @@ void Assembler::vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, in
 }
 
 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   attributes.set_rex_vex_w_reverted();
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
@@ -9845,7 +9681,6 @@ void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int ve
 }
 
 void Assembler::por(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xEB, (0xC0 | encode));
@@ -9906,7 +9741,6 @@ void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address
 }
 
 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
   emit_int16((unsigned char)0xEF, (0xC0 | encode));
@@ -12540,7 +12374,6 @@ void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegist
 
 void Assembler::gf2p8affineqb(XMMRegister dst, XMMRegister src, int imm8) {
   assert(VM_Version::supports_gfni(), "");
-  NOT_LP64(assert(VM_Version::supports_sse(), "");)
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
   emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
@@ -12548,7 +12381,6 @@ void Assembler::gf2p8affineqb(XMMRegister dst, XMMRegister src, int imm8) {
 
 void Assembler::vgf2p8affineqb(XMMRegister dst, XMMRegister src2, XMMRegister src3, int imm8, int vector_len) {
   assert(VM_Version::supports_gfni(), "requires GFNI support");
-  NOT_LP64(assert(VM_Version::supports_sse(), "");)
   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
   emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
@@ -15562,14 +15394,12 @@ void Assembler::cmpxchgq(Register reg, Address adr) {
 }
 
 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes, true);
   emit_int16(0x2A, (0xC0 | encode));
 }
 
 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -15579,7 +15409,6 @@ void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
 }
 
 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionMark im(this);
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
@@ -15589,7 +15418,6 @@ void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
 }
 
 void Assembler::cvttsd2siq(Register dst, Address src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   // F2 REX.W 0F 2C /r
   // CVTTSD2SI r64, xmm1/m64
   InstructionMark im(this);
@@ -15600,21 +15428,18 @@ void Assembler::cvttsd2siq(Register dst, Address src) {
 }
 
 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
   emit_int16(0x2C, (0xC0 | encode));
 }
 
 void Assembler::cvtsd2siq(Register dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
   emit_int16(0x2D, (0xC0 | encode));
 }
 
 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
-  NOT_LP64(assert(VM_Version::supports_sse(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
   emit_int16(0x2C, (0xC0 | encode));
@@ -15960,16 +15785,12 @@ void Assembler::elzcntq(Register dst, Address src, bool no_flags) {
 }
 
 void Assembler::movdq(XMMRegister dst, Register src) {
-  // table D-1 says MMX/SSE2
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes, true);
   emit_int16(0x6E, (0xC0 | encode));
 }
 
 void Assembler::movdq(Register dst, XMMRegister src) {
-  // table D-1 says MMX/SSE2
-  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
   // swap src/dst to get correct prefix
   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes, true);
diff --git a/src/hotspot/cpu/x86/c1_LinearScan_x86.hpp b/src/hotspot/cpu/x86/c1_LinearScan_x86.hpp
index 62a1bd6510e41..dcc9a77765a8f 100644
--- a/src/hotspot/cpu/x86/c1_LinearScan_x86.hpp
+++ b/src/hotspot/cpu/x86/c1_LinearScan_x86.hpp
@@ -67,7 +67,7 @@ inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
     _first_reg = pd_first_byte_reg;
     _last_reg = FrameMap::last_byte_reg();
     return true;
-  } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) {
+  } else if (cur->type() == T_FLOAT || cur->type() == T_DOUBLE) {
     _first_reg = pd_first_xmm_reg;
     _last_reg = last_xmm_reg;
     return true;
diff --git a/src/hotspot/cpu/x86/c1_Runtime1_x86.cpp b/src/hotspot/cpu/x86/c1_Runtime1_x86.cpp
index f42032bb27535..db6614686a2a1 100644
--- a/src/hotspot/cpu/x86/c1_Runtime1_x86.cpp
+++ b/src/hotspot/cpu/x86/c1_Runtime1_x86.cpp
@@ -334,21 +334,19 @@ static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
   int xmm_bypass_limit = FrameMap::get_num_caller_save_xmms();
 
   if (save_fpu_registers) {
-    if (UseSSE >= 2) {
-      int xmm_off = xmm_regs_as_doubles_off;
-      for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
-        if (n < xmm_bypass_limit) {
-          VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
-          map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
-          // %%% This is really a waste but we'll keep things as they were for now
-          if (true) {
-            map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next());
-          }
+    int xmm_off = xmm_regs_as_doubles_off;
+    for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
+      if (n < xmm_bypass_limit) {
+        VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
+        map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
+        // %%% This is really a waste but we'll keep things as they were for now
+        if (true) {
+          map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next());
         }
-        xmm_off += 2;
       }
-      assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
+      xmm_off += 2;
     }
+    assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
   }
 
   return map;
@@ -369,19 +367,17 @@ void C1_MacroAssembler::save_live_registers_no_oop_map(bool save_fpu_registers)
 #endif
 
   if (save_fpu_registers) {
-    if (UseSSE >= 2) {
-      // save XMM registers
-      // XMM registers can contain float or double values, but this is not known here,
-      // so always save them as doubles.
-      // note that float values are _not_ converted automatically, so for float values
-      // the second word contains only garbage data.
-      int xmm_bypass_limit = FrameMap::get_num_caller_save_xmms();
-      int offset = 0;
-      for (int n = 0; n < xmm_bypass_limit; n++) {
-        XMMRegister xmm_name = as_XMMRegister(n);
-        __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name);
-        offset += 8;
-      }
+    // save XMM registers
+    // XMM registers can contain float or double values, but this is not known here,
+    // so always save them as doubles.
+    // note that float values are _not_ converted automatically, so for float values
+    // the second word contains only garbage data.
+    int xmm_bypass_limit = FrameMap::get_num_caller_save_xmms();
+    int offset = 0;
+    for (int n = 0; n < xmm_bypass_limit; n++) {
+      XMMRegister xmm_name = as_XMMRegister(n);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name);
+      offset += 8;
     }
   }
 }
diff --git a/src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp b/src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
index 9ca463336681e..7ab5f80b9a326 100644
--- a/src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
+++ b/src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
@@ -1132,7 +1132,6 @@ void C2_MacroAssembler::signum_fp(int opcode, XMMRegister dst, XMMRegister zero,
   Label DONE_LABEL;
 
   if (opcode == Op_SignumF) {
-    assert(UseSSE > 0, "required");
     ucomiss(dst, zero);
     jcc(Assembler::equal, DONE_LABEL);    // handle special case +0.0/-0.0, if argument is +0.0/-0.0, return argument
     jcc(Assembler::parity, DONE_LABEL);   // handle special case NaN, if argument NaN, return NaN
@@ -1140,7 +1139,6 @@ void C2_MacroAssembler::signum_fp(int opcode, XMMRegister dst, XMMRegister zero,
     jcc(Assembler::above, DONE_LABEL);
     xorps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), noreg);
   } else if (opcode == Op_SignumD) {
-    assert(UseSSE > 1, "required");
     ucomisd(dst, zero);
     jcc(Assembler::equal, DONE_LABEL);    // handle special case +0.0/-0.0, if argument is +0.0/-0.0, return argument
     jcc(Assembler::parity, DONE_LABEL);   // handle special case NaN, if argument NaN, return NaN
@@ -4108,7 +4106,7 @@ void C2_MacroAssembler::count_positives(Register ary1, Register len,
     // Fallthru to tail compare
   } else {
 
-    if (UseAVX >= 2 && UseSSE >= 2) {
+    if (UseAVX >= 2) {
       // With AVX2, use 32-byte vector compare
       Label COMPARE_WIDE_VECTORS, BREAK_LOOP;
 
@@ -4255,7 +4253,7 @@ void C2_MacroAssembler::count_positives(Register ary1, Register len,
 
   // That's it
   bind(DONE);
-  if (UseAVX >= 2 && UseSSE >= 2) {
+  if (UseAVX >= 2) {
     // clean upper bits of YMM registers
     vpxor(vec1, vec1);
     vpxor(vec2, vec2);
diff --git a/src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.cpp
index be25326d68262..925444792caac 100644
--- a/src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.cpp
+++ b/src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.cpp
@@ -74,11 +74,11 @@ void BarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorators,
   case T_ADDRESS: __ movptr(dst, src);              break;
   case T_FLOAT:
     assert(dst == noreg, "only to ftos");
-    __ load_float(src);
+    __ movflt(xmm0, src);
     break;
   case T_DOUBLE:
     assert(dst == noreg, "only to dtos");
-    __ load_double(src);
+    __ movdbl(xmm0, src);
     break;
   case T_LONG:
     assert(dst == noreg, "only to ltos");
@@ -148,11 +148,11 @@ void BarrierSetAssembler::store_at(MacroAssembler* masm, DecoratorSet decorators
     break;
   case T_FLOAT:
     assert(val == noreg, "only tos");
-    __ store_float(dst);
+    __ movflt(dst, xmm0);
     break;
   case T_DOUBLE:
     assert(val == noreg, "only tos");
-    __ store_double(dst);
+    __ movdbl(dst, xmm0);
     break;
   case T_ADDRESS:
     __ movptr(dst, val);
diff --git a/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp
index 6e1596a0e4b1a..45e4c46161ff1 100644
--- a/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp
+++ b/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp
@@ -53,61 +53,31 @@ static void save_machine_state(MacroAssembler* masm, bool handle_gpr, bool handl
     // Some paths can be reached from the c2i adapter with live fp arguments in registers.
     assert(Argument::n_float_register_parameters_j == 8, "8 fp registers to save at java call");
 
-    if (UseSSE >= 2) {
-      const int xmm_size = wordSize * 2;
-      __ subptr(rsp, xmm_size * 8);
-      __ movdbl(Address(rsp, xmm_size * 0), xmm0);
-      __ movdbl(Address(rsp, xmm_size * 1), xmm1);
-      __ movdbl(Address(rsp, xmm_size * 2), xmm2);
-      __ movdbl(Address(rsp, xmm_size * 3), xmm3);
-      __ movdbl(Address(rsp, xmm_size * 4), xmm4);
-      __ movdbl(Address(rsp, xmm_size * 5), xmm5);
-      __ movdbl(Address(rsp, xmm_size * 6), xmm6);
-      __ movdbl(Address(rsp, xmm_size * 7), xmm7);
-    } else if (UseSSE >= 1) {
-      const int xmm_size = wordSize * 1;
-      __ subptr(rsp, xmm_size * 8);
-      __ movflt(Address(rsp, xmm_size * 0), xmm0);
-      __ movflt(Address(rsp, xmm_size * 1), xmm1);
-      __ movflt(Address(rsp, xmm_size * 2), xmm2);
-      __ movflt(Address(rsp, xmm_size * 3), xmm3);
-      __ movflt(Address(rsp, xmm_size * 4), xmm4);
-      __ movflt(Address(rsp, xmm_size * 5), xmm5);
-      __ movflt(Address(rsp, xmm_size * 6), xmm6);
-      __ movflt(Address(rsp, xmm_size * 7), xmm7);
-    } else {
-      __ push_FPU_state();
-    }
+    const int xmm_size = wordSize * 2;
+    __ subptr(rsp, xmm_size * 8);
+    __ movdbl(Address(rsp, xmm_size * 0), xmm0);
+    __ movdbl(Address(rsp, xmm_size * 1), xmm1);
+    __ movdbl(Address(rsp, xmm_size * 2), xmm2);
+    __ movdbl(Address(rsp, xmm_size * 3), xmm3);
+    __ movdbl(Address(rsp, xmm_size * 4), xmm4);
+    __ movdbl(Address(rsp, xmm_size * 5), xmm5);
+    __ movdbl(Address(rsp, xmm_size * 6), xmm6);
+    __ movdbl(Address(rsp, xmm_size * 7), xmm7);
   }
 }
 
 static void restore_machine_state(MacroAssembler* masm, bool handle_gpr, bool handle_fp) {
   if (handle_fp) {
-    if (UseSSE >= 2) {
-      const int xmm_size = wordSize * 2;
-      __ movdbl(xmm0, Address(rsp, xmm_size * 0));
-      __ movdbl(xmm1, Address(rsp, xmm_size * 1));
-      __ movdbl(xmm2, Address(rsp, xmm_size * 2));
-      __ movdbl(xmm3, Address(rsp, xmm_size * 3));
-      __ movdbl(xmm4, Address(rsp, xmm_size * 4));
-      __ movdbl(xmm5, Address(rsp, xmm_size * 5));
-      __ movdbl(xmm6, Address(rsp, xmm_size * 6));
-      __ movdbl(xmm7, Address(rsp, xmm_size * 7));
-      __ addptr(rsp, xmm_size * 8);
-    } else if (UseSSE >= 1) {
-      const int xmm_size = wordSize * 1;
-      __ movflt(xmm0, Address(rsp, xmm_size * 0));
-      __ movflt(xmm1, Address(rsp, xmm_size * 1));
-      __ movflt(xmm2, Address(rsp, xmm_size * 2));
-      __ movflt(xmm3, Address(rsp, xmm_size * 3));
-      __ movflt(xmm4, Address(rsp, xmm_size * 4));
-      __ movflt(xmm5, Address(rsp, xmm_size * 5));
-      __ movflt(xmm6, Address(rsp, xmm_size * 6));
-      __ movflt(xmm7, Address(rsp, xmm_size * 7));
-      __ addptr(rsp, xmm_size * 8);
-    } else {
-      __ pop_FPU_state();
-    }
+    const int xmm_size = wordSize * 2;
+    __ movdbl(xmm0, Address(rsp, xmm_size * 0));
+    __ movdbl(xmm1, Address(rsp, xmm_size * 1));
+    __ movdbl(xmm2, Address(rsp, xmm_size * 2));
+    __ movdbl(xmm3, Address(rsp, xmm_size * 3));
+    __ movdbl(xmm4, Address(rsp, xmm_size * 4));
+    __ movdbl(xmm5, Address(rsp, xmm_size * 5));
+    __ movdbl(xmm6, Address(rsp, xmm_size * 6));
+    __ movdbl(xmm7, Address(rsp, xmm_size * 7));
+    __ addptr(rsp, xmm_size * 8);
   }
 
   if (handle_gpr) {
diff --git a/src/hotspot/cpu/x86/interp_masm_x86.cpp b/src/hotspot/cpu/x86/interp_masm_x86.cpp
index 93117ff8b7d47..bd029f2e4ac41 100644
--- a/src/hotspot/cpu/x86/interp_masm_x86.cpp
+++ b/src/hotspot/cpu/x86/interp_masm_x86.cpp
@@ -417,8 +417,8 @@ void InterpreterMacroAssembler::load_earlyret_value(TosState state) {
     case ctos:                                   // fall through
     case stos:                                   // fall through
     case itos: movl(rax, val_addr);                 break;
-    case ftos: load_float(val_addr);                break;
-    case dtos: load_double(val_addr);               break;
+    case ftos: movflt(xmm0, val_addr);              break;
+    case dtos: movdbl(xmm0, val_addr);              break;
     case vtos: /* nothing to do */                  break;
     default  : ShouldNotReachHere();
   }
diff --git a/src/hotspot/cpu/x86/macroAssembler_x86.cpp b/src/hotspot/cpu/x86/macroAssembler_x86.cpp
index 0f7651b9de2e8..64d46c87fb9c5 100644
--- a/src/hotspot/cpu/x86/macroAssembler_x86.cpp
+++ b/src/hotspot/cpu/x86/macroAssembler_x86.cpp
@@ -2173,54 +2173,6 @@ void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratc
   }
 }
 
-void MacroAssembler::load_float(Address src) {
-#ifdef _LP64
-  movflt(xmm0, src);
-#else
-  if (UseSSE >= 1) {
-    movflt(xmm0, src);
-  } else {
-    fld_s(src);
-  }
-#endif // LP64
-}
-
-void MacroAssembler::store_float(Address dst) {
-#ifdef _LP64
-  movflt(dst, xmm0);
-#else
-  if (UseSSE >= 1) {
-    movflt(dst, xmm0);
-  } else {
-    fstp_s(dst);
-  }
-#endif // LP64
-}
-
-void MacroAssembler::load_double(Address src) {
-#ifdef _LP64
-  movdbl(xmm0, src);
-#else
-  if (UseSSE >= 2) {
-    movdbl(xmm0, src);
-  } else {
-    fld_d(src);
-  }
-#endif // LP64
-}
-
-void MacroAssembler::store_double(Address dst) {
-#ifdef _LP64
-  movdbl(dst, xmm0);
-#else
-  if (UseSSE >= 2) {
-    movdbl(dst, xmm0);
-  } else {
-    fstp_d(dst);
-  }
-#endif // LP64
-}
-
 // dst = c = a * b + c
 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
   Assembler::vfmadd231sd(c, a, b);
@@ -4186,46 +4138,25 @@ XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
 #endif
 }
 
-static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
-
-#ifndef _LP64
-static bool use_x87_registers() { return UseSSE < 2; }
-#endif
-static bool use_xmm_registers() { return UseSSE >= 1; }
-
 // C1 only ever uses the first double/float of the XMM register.
-static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
+static int xmm_save_size() { return sizeof(double); }
 
 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
-  if (UseSSE == 1) {
-    masm->movflt(Address(rsp, offset), reg);
-  } else {
-    masm->movdbl(Address(rsp, offset), reg);
-  }
+  masm->movdbl(Address(rsp, offset), reg);
 }
 
 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
-  if (UseSSE == 1) {
-    masm->movflt(reg, Address(rsp, offset));
-  } else {
-    masm->movdbl(reg, Address(rsp, offset));
-  }
+  masm->movdbl(reg, Address(rsp, offset));
 }
 
 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
-                                  bool save_fpu, int& gp_area_size,
-                                  int& fp_area_size, int& xmm_area_size) {
+                                  bool save_fpu, int& gp_area_size, int& xmm_area_size) {
 
   gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
                          StackAlignmentInBytes);
-#ifdef _LP64
-  fp_area_size = 0;
-#else
-  fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
-#endif
-  xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
+  xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
 
-  return gp_area_size + fp_area_size + xmm_area_size;
+  return gp_area_size + xmm_area_size;
 }
 
 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
@@ -4234,22 +4165,15 @@ void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool s
   RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
 
   int gp_area_size;
-  int fp_area_size;
   int xmm_area_size;
   int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
-                                               gp_area_size, fp_area_size, xmm_area_size);
+                                               gp_area_size, xmm_area_size);
   subptr(rsp, total_save_size);
 
   push_set(gp_registers_to_push, 0);
 
-#ifndef _LP64
-  if (save_fpu && use_x87_registers()) {
-    fnsave(Address(rsp, gp_area_size));
-    fwait();
-  }
-#endif
-  if (save_fpu && use_xmm_registers()) {
-    push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
+  if (save_fpu) {
+    push_set(call_clobbered_xmm_registers(), gp_area_size);
   }
 
   block_comment("push_call_clobbered_registers end");
@@ -4261,19 +4185,13 @@ void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool re
   RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
 
   int gp_area_size;
-  int fp_area_size;
   int xmm_area_size;
   int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
-                                               gp_area_size, fp_area_size, xmm_area_size);
+                                               gp_area_size, xmm_area_size);
 
-  if (restore_fpu && use_xmm_registers()) {
-    pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
+  if (restore_fpu) {
+    pop_set(call_clobbered_xmm_registers(), gp_area_size);
   }
-#ifndef _LP64
-  if (restore_fpu && use_x87_registers()) {
-    frstor(Address(rsp, gp_area_size));
-  }
-#endif
 
   pop_set(gp_registers_to_pop, 0);
 
@@ -6737,39 +6655,7 @@ void MacroAssembler::generate_fill(BasicType t, bool aligned,
     subptr(count, 1<<(shift-1));
     BIND(L_skip_align2);
   }
-  if (UseSSE < 2) {
-    Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
-    // Fill 32-byte chunks
-    subptr(count, 8 << shift);
-    jcc(Assembler::less, L_check_fill_8_bytes);
-    align(16);
-
-    BIND(L_fill_32_bytes_loop);
-
-    for (int i = 0; i < 32; i += 4) {
-      movl(Address(to, i), value);
-    }
-
-    addptr(to, 32);
-    subptr(count, 8 << shift);
-    jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
-    BIND(L_check_fill_8_bytes);
-    addptr(count, 8 << shift);
-    jccb(Assembler::zero, L_exit);
-    jmpb(L_fill_8_bytes);
-
-    //
-    // length is too short, just fill qwords
-    //
-    BIND(L_fill_8_bytes_loop);
-    movl(Address(to, 0), value);
-    movl(Address(to, 4), value);
-    addptr(to, 8);
-    BIND(L_fill_8_bytes);
-    subptr(count, 1 << (shift + 1));
-    jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
-    // fall through to fill 4 bytes
-  } else {
+  {
     Label L_fill_32_bytes;
     if (!UseUnalignedLoadStores) {
       // align to 8 bytes, we know we are 4 byte aligned to start
@@ -6781,7 +6667,6 @@ void MacroAssembler::generate_fill(BasicType t, bool aligned,
     }
     BIND(L_fill_32_bytes);
     {
-      assert( UseSSE >= 2, "supported cpu only" );
       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
       movdl(xtmp, value);
       if (UseAVX >= 2 && UseUnalignedLoadStores) {
diff --git a/src/hotspot/cpu/x86/macroAssembler_x86.hpp b/src/hotspot/cpu/x86/macroAssembler_x86.hpp
index 27c90fb866e05..36f898df2ca2b 100644
--- a/src/hotspot/cpu/x86/macroAssembler_x86.hpp
+++ b/src/hotspot/cpu/x86/macroAssembler_x86.hpp
@@ -512,22 +512,6 @@ class MacroAssembler: public Assembler {
   void jC2 (Register tmp, Label& L);
   void jnC2(Register tmp, Label& L);
 
-  // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
-  // register xmm0. Otherwise, the value is loaded onto the FPU stack.
-  void load_float(Address src);
-
-  // Store float value to 'address'. If UseSSE >= 1, the value is stored
-  // from register xmm0. Otherwise, the value is stored from the FPU stack.
-  void store_float(Address dst);
-
-  // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
-  // register xmm0. Otherwise, the value is loaded onto the FPU stack.
-  void load_double(Address src);
-
-  // Store double value to 'address'. If UseSSE >= 2, the value is stored
-  // from register xmm0. Otherwise, the value is stored from the FPU stack.
-  void store_double(Address dst);
-
 #ifndef _LP64
   // Pop ST (ffree & fincstp combined)
   void fpop();
diff --git a/src/hotspot/cpu/x86/methodHandles_x86.cpp b/src/hotspot/cpu/x86/methodHandles_x86.cpp
index ed19daff37ddf..92993dcbf640d 100644
--- a/src/hotspot/cpu/x86/methodHandles_x86.cpp
+++ b/src/hotspot/cpu/x86/methodHandles_x86.cpp
@@ -651,17 +651,7 @@ void MethodHandles::trace_method_handle(MacroAssembler* _masm, const char* adapt
 
   // save FP result, valid at some call sites (adapter_opt_return_float, ...)
   __ decrement(rsp, 2 * wordSize);
-#ifdef _LP64
   __ movdbl(Address(rsp, 0), xmm0);
-#else
-  if  (UseSSE >= 2) {
-    __ movdbl(Address(rsp, 0), xmm0);
-  } else if (UseSSE == 1) {
-    __ movflt(Address(rsp, 0), xmm0);
-  } else {
-    __ fst_d(Address(rsp, 0));
-  }
-#endif // LP64
 
   // Incoming state:
   // rcx: method handle
@@ -676,17 +666,7 @@ void MethodHandles::trace_method_handle(MacroAssembler* _masm, const char* adapt
   __ super_call_VM_leaf(CAST_FROM_FN_PTR(address, trace_method_handle_stub_wrapper), rsp);
   __ increment(rsp, sizeof(MethodHandleStubArguments));
 
-#ifdef _LP64
   __ movdbl(xmm0, Address(rsp, 0));
-#else
-  if  (UseSSE >= 2) {
-    __ movdbl(xmm0, Address(rsp, 0));
-  } else if (UseSSE == 1) {
-    __ movflt(xmm0, Address(rsp, 0));
-  } else {
-    __ fld_d(Address(rsp, 0));
-  }
-#endif // LP64
   __ increment(rsp, 2 * wordSize);
 
   __ popa();
diff --git a/src/hotspot/cpu/x86/templateTable_x86.cpp b/src/hotspot/cpu/x86/templateTable_x86.cpp
index b9637e1d7c49c..226b8b1c65597 100644
--- a/src/hotspot/cpu/x86/templateTable_x86.cpp
+++ b/src/hotspot/cpu/x86/templateTable_x86.cpp
@@ -276,44 +276,36 @@ void TemplateTable::lconst(int value) {
 
 void TemplateTable::fconst(int value) {
   transition(vtos, ftos);
-  if (UseSSE >= 1) {
-    static float one = 1.0f, two = 2.0f;
-    switch (value) {
-    case 0:
-      __ xorps(xmm0, xmm0);
-      break;
-    case 1:
-      __ movflt(xmm0, ExternalAddress((address) &one), rscratch1);
-      break;
-    case 2:
-      __ movflt(xmm0, ExternalAddress((address) &two), rscratch1);
-      break;
-    default:
-      ShouldNotReachHere();
-      break;
-    }
-  } else {
+  static float one = 1.0f, two = 2.0f;
+  switch (value) {
+  case 0:
+    __ xorps(xmm0, xmm0);
+    break;
+  case 1:
+    __ movflt(xmm0, ExternalAddress((address) &one), rscratch1);
+    break;
+  case 2:
+    __ movflt(xmm0, ExternalAddress((address) &two), rscratch1);
+    break;
+  default:
     ShouldNotReachHere();
+    break;
   }
 }
 
 void TemplateTable::dconst(int value) {
   transition(vtos, dtos);
-  if (UseSSE >= 2) {
-    static double one = 1.0;
-    switch (value) {
-    case 0:
-      __ xorpd(xmm0, xmm0);
-      break;
-    case 1:
-      __ movdbl(xmm0, ExternalAddress((address) &one), rscratch1);
-      break;
-    default:
-      ShouldNotReachHere();
-      break;
-    }
-  } else {
+  static double one = 1.0;
+  switch (value) {
+  case 0:
+    __ xorpd(xmm0, xmm0);
+    break;
+  case 1:
+    __ movdbl(xmm0, ExternalAddress((address) &one), rscratch1);
+    break;
+  default:
     ShouldNotReachHere();
+    break;
   }
 }
 
@@ -373,7 +365,7 @@ void TemplateTable::ldc(LdcType type) {
   __ jccb(Assembler::notEqual, notFloat);
 
   // ftos
-  __ load_float(Address(rcx, rbx, Address::times_ptr, base_offset));
+  __ movflt(xmm0, Address(rcx, rbx, Address::times_ptr, base_offset));
   __ push(ftos);
   __ jmp(Done);
 
@@ -452,7 +444,7 @@ void TemplateTable::ldc2_w() {
   __ jccb(Assembler::notEqual, notDouble);
 
   // dtos
-  __ load_double(Address(rcx, rbx, Address::times_ptr, base_offset));
+  __ movdbl(xmm0, Address(rcx, rbx, Address::times_ptr, base_offset));
   __ push(dtos);
 
   __ jmp(Done);
@@ -506,7 +498,7 @@ void TemplateTable::condy_helper(Label& Done) {
       __ cmpl(flags, ftos);
       __ jccb(Assembler::notEqual, notFloat);
       // ftos
-      __ load_float(field);
+      __ movflt(xmm0, field);
       __ push(ftos);
       __ jmp(Done);
 
@@ -561,7 +553,7 @@ void TemplateTable::condy_helper(Label& Done) {
       __ cmpl(flags, dtos);
       __ jccb(Assembler::notEqual, notDouble);
       // dtos
-      __ load_double(field);
+      __ movdbl(xmm0, field);
       __ push(dtos);
       __ jmp(Done);
 
@@ -655,13 +647,13 @@ void TemplateTable::lload() {
 void TemplateTable::fload() {
   transition(vtos, ftos);
   locals_index(rbx);
-  __ load_float(faddress(rbx));
+  __ movflt(xmm0, faddress(rbx));
 }
 
 void TemplateTable::dload() {
   transition(vtos, dtos);
   locals_index(rbx);
-  __ load_double(daddress(rbx));
+  __ movdbl(xmm0, daddress(rbx));
 }
 
 void TemplateTable::aload() {
@@ -692,13 +684,13 @@ void TemplateTable::wide_lload() {
 void TemplateTable::wide_fload() {
   transition(vtos, ftos);
   locals_index_wide(rbx);
-  __ load_float(faddress(rbx));
+  __ movflt(xmm0, faddress(rbx));
 }
 
 void TemplateTable::wide_dload() {
   transition(vtos, dtos);
   locals_index_wide(rbx);
-  __ load_double(daddress(rbx));
+  __ movdbl(xmm0, daddress(rbx));
 }
 
 void TemplateTable::wide_aload() {
@@ -852,12 +844,12 @@ void TemplateTable::lload(int n) {
 
 void TemplateTable::fload(int n) {
   transition(vtos, ftos);
-  __ load_float(faddress(n));
+  __ movflt(xmm0, faddress(n));
 }
 
 void TemplateTable::dload(int n) {
   transition(vtos, dtos);
-  __ load_double(daddress(n));
+  __ movdbl(xmm0, daddress(n));
 }
 
 void TemplateTable::aload(int n) {
@@ -959,13 +951,13 @@ void TemplateTable::lstore() {
 void TemplateTable::fstore() {
   transition(ftos, vtos);
   locals_index(rbx);
-  __ store_float(faddress(rbx));
+  __ movflt(faddress(rbx), xmm0);
 }
 
 void TemplateTable::dstore() {
   transition(dtos, vtos);
   locals_index(rbx);
-  __ store_double(daddress(rbx));
+  __ movdbl(daddress(rbx), xmm0);
 }
 
 void TemplateTable::astore() {
@@ -1041,7 +1033,7 @@ void TemplateTable::lastore() {
 void TemplateTable::fastore() {
   transition(ftos, vtos);
   __ pop_i(rbx);
-  // value is in UseSSE >= 1 ? xmm0 : ST(0)
+  // value is in xmm0
   // rbx:  index
   // rdx:  array
   index_check(rdx, rbx); // prefer index in rbx
@@ -1054,7 +1046,7 @@ void TemplateTable::fastore() {
 void TemplateTable::dastore() {
   transition(dtos, vtos);
   __ pop_i(rbx);
-  // value is in UseSSE >= 2 ? xmm0 : ST(0)
+  // value is in xmm0
   // rbx:  index
   // rdx:  array
   index_check(rdx, rbx); // prefer index in rbx
@@ -1170,12 +1162,12 @@ void TemplateTable::lstore(int n) {
 
 void TemplateTable::fstore(int n) {
   transition(ftos, vtos);
-  __ store_float(faddress(n));
+  __ movflt(faddress(n), xmm0);
 }
 
 void TemplateTable::dstore(int n) {
   transition(dtos, vtos);
-  __ store_double(daddress(n));
+  __ movdbl(daddress(n), xmm0);
 }
 
 
@@ -1397,81 +1389,73 @@ void TemplateTable::lushr() {
 void TemplateTable::fop2(Operation op) {
   transition(ftos, ftos);
 
-  if (UseSSE >= 1) {
-    switch (op) {
-    case add:
-      __ addss(xmm0, at_rsp());
-      __ addptr(rsp, Interpreter::stackElementSize);
-      break;
-    case sub:
-      __ movflt(xmm1, xmm0);
-      __ pop_f(xmm0);
-      __ subss(xmm0, xmm1);
-      break;
-    case mul:
-      __ mulss(xmm0, at_rsp());
-      __ addptr(rsp, Interpreter::stackElementSize);
-      break;
-    case div:
-      __ movflt(xmm1, xmm0);
-      __ pop_f(xmm0);
-      __ divss(xmm0, xmm1);
-      break;
-    case rem:
-      // On x86_64 platforms the SharedRuntime::frem method is called to perform the
-      // modulo operation. The frem method calls the function
-      // double fmod(double x, double y) in math.h. The documentation of fmod states:
-      // "If x or y is a NaN, a NaN is returned." without specifying what type of NaN
-      // (signalling or quiet) is returned.
-      __ movflt(xmm1, xmm0);
-      __ pop_f(xmm0);
-      __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::frem), 2);
-      break;
-    default:
-      ShouldNotReachHere();
-      break;
-    }
-  } else {
+  switch (op) {
+  case add:
+    __ addss(xmm0, at_rsp());
+    __ addptr(rsp, Interpreter::stackElementSize);
+    break;
+  case sub:
+    __ movflt(xmm1, xmm0);
+    __ pop_f(xmm0);
+    __ subss(xmm0, xmm1);
+    break;
+  case mul:
+    __ mulss(xmm0, at_rsp());
+    __ addptr(rsp, Interpreter::stackElementSize);
+    break;
+  case div:
+    __ movflt(xmm1, xmm0);
+    __ pop_f(xmm0);
+    __ divss(xmm0, xmm1);
+    break;
+  case rem:
+    // On x86_64 platforms the SharedRuntime::frem method is called to perform the
+    // modulo operation. The frem method calls the function
+    // double fmod(double x, double y) in math.h. The documentation of fmod states:
+    // "If x or y is a NaN, a NaN is returned." without specifying what type of NaN
+    // (signalling or quiet) is returned.
+    __ movflt(xmm1, xmm0);
+    __ pop_f(xmm0);
+    __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::frem), 2);
+    break;
+  default:
     ShouldNotReachHere();
+    break;
   }
 }
 
 void TemplateTable::dop2(Operation op) {
   transition(dtos, dtos);
-  if (UseSSE >= 2) {
-    switch (op) {
-    case add:
-      __ addsd(xmm0, at_rsp());
-      __ addptr(rsp, 2 * Interpreter::stackElementSize);
-      break;
-    case sub:
-      __ movdbl(xmm1, xmm0);
-      __ pop_d(xmm0);
-      __ subsd(xmm0, xmm1);
-      break;
-    case mul:
-      __ mulsd(xmm0, at_rsp());
-      __ addptr(rsp, 2 * Interpreter::stackElementSize);
-      break;
-    case div:
-      __ movdbl(xmm1, xmm0);
-      __ pop_d(xmm0);
-      __ divsd(xmm0, xmm1);
-      break;
-    case rem:
-      // Similar to fop2(), the modulo operation is performed using the
-      // SharedRuntime::drem method on x86_64 platforms for the same reasons
-      // as mentioned in fop2().
-      __ movdbl(xmm1, xmm0);
-      __ pop_d(xmm0);
-      __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::drem), 2);
-      break;
-    default:
-      ShouldNotReachHere();
-      break;
-    }
-  } else {
+  switch (op) {
+  case add:
+    __ addsd(xmm0, at_rsp());
+    __ addptr(rsp, 2 * Interpreter::stackElementSize);
+    break;
+  case sub:
+    __ movdbl(xmm1, xmm0);
+    __ pop_d(xmm0);
+    __ subsd(xmm0, xmm1);
+    break;
+  case mul:
+    __ mulsd(xmm0, at_rsp());
+    __ addptr(rsp, 2 * Interpreter::stackElementSize);
+    break;
+  case div:
+    __ movdbl(xmm1, xmm0);
+    __ pop_d(xmm0);
+    __ divsd(xmm0, xmm1);
+    break;
+  case rem:
+    // Similar to fop2(), the modulo operation is performed using the
+    // SharedRuntime::drem method on x86_64 platforms for the same reasons
+    // as mentioned in fop2().
+    __ movdbl(xmm1, xmm0);
+    __ pop_d(xmm0);
+    __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::drem), 2);
+    break;
+  default:
     ShouldNotReachHere();
+    break;
   }
 }
 
@@ -1502,23 +1486,15 @@ static jlong double_signflip_pool[2*2];
 
 void TemplateTable::fneg() {
   transition(ftos, ftos);
-  if (UseSSE >= 1) {
-    static jlong *float_signflip  = double_quadword(&float_signflip_pool[1],  CONST64(0x8000000080000000),  CONST64(0x8000000080000000));
-    __ xorps(xmm0, ExternalAddress((address) float_signflip), rscratch1);
-  } else {
-    ShouldNotReachHere();
-  }
+  static jlong *float_signflip  = double_quadword(&float_signflip_pool[1],  CONST64(0x8000000080000000),  CONST64(0x8000000080000000));
+  __ xorps(xmm0, ExternalAddress((address) float_signflip), rscratch1);
 }
 
 void TemplateTable::dneg() {
   transition(dtos, dtos);
-  if (UseSSE >= 2) {
-    static jlong *double_signflip =
-      double_quadword(&double_signflip_pool[1], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
-    __ xorpd(xmm0, ExternalAddress((address) double_signflip), rscratch1);
-  } else {
-    ShouldNotReachHere();
-  }
+  static jlong *double_signflip =
+    double_quadword(&double_signflip_pool[1], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
+  __ xorpd(xmm0, ExternalAddress((address) double_signflip), rscratch1);
 }
 
 void TemplateTable::iinc() {
@@ -1682,36 +1658,31 @@ void TemplateTable::lcmp() {
 }
 
 void TemplateTable::float_cmp(bool is_float, int unordered_result) {
-  if ((is_float && UseSSE >= 1) ||
-      (!is_float && UseSSE >= 2)) {
-    Label done;
-    if (is_float) {
-      // XXX get rid of pop here, use ... reg, mem32
-      __ pop_f(xmm1);
-      __ ucomiss(xmm1, xmm0);
-    } else {
-      // XXX get rid of pop here, use ... reg, mem64
-      __ pop_d(xmm1);
-      __ ucomisd(xmm1, xmm0);
-    }
-    if (unordered_result < 0) {
-      __ movl(rax, -1);
-      __ jccb(Assembler::parity, done);
-      __ jccb(Assembler::below, done);
-      __ setb(Assembler::notEqual, rdx);
-      __ movzbl(rax, rdx);
-    } else {
-      __ movl(rax, 1);
-      __ jccb(Assembler::parity, done);
-      __ jccb(Assembler::above, done);
-      __ movl(rax, 0);
-      __ jccb(Assembler::equal, done);
-      __ decrementl(rax);
-    }
-    __ bind(done);
+  Label done;
+  if (is_float) {
+    // XXX get rid of pop here, use ... reg, mem32
+    __ pop_f(xmm1);
+    __ ucomiss(xmm1, xmm0);
   } else {
-    ShouldNotReachHere();
+    // XXX get rid of pop here, use ... reg, mem64
+    __ pop_d(xmm1);
+    __ ucomisd(xmm1, xmm0);
+  }
+  if (unordered_result < 0) {
+    __ movl(rax, -1);
+    __ jccb(Assembler::parity, done);
+    __ jccb(Assembler::below, done);
+    __ setb(Assembler::notEqual, rdx);
+    __ movzbl(rax, rdx);
+  } else {
+    __ movl(rax, 1);
+    __ jccb(Assembler::parity, done);
+    __ jccb(Assembler::above, done);
+    __ movl(rax, 0);
+    __ jccb(Assembler::equal, done);
+    __ decrementl(rax);
   }
+  __ bind(done);
 }
 
 void TemplateTable::branch(bool is_jsr, bool is_wide) {
diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp
index c320d4e8a0d0d..f7c9ebef3efe6 100644
--- a/src/hotspot/cpu/x86/vm_version_x86.cpp
+++ b/src/hotspot/cpu/x86/vm_version_x86.cpp
@@ -1271,7 +1271,7 @@ void VM_Version::get_processor_features() {
     FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
   }
 
-  if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
+  if (supports_fma()) {
     if (FLAG_IS_DEFAULT(UseFMA)) {
       UseFMA = true;
     }
@@ -1340,22 +1340,9 @@ void VM_Version::get_processor_features() {
     FLAG_SET_DEFAULT(UseSHA, false);
   }
 
-#ifdef COMPILER2
-  if (UseFPUForSpilling) {
-    if (UseSSE < 2) {
-      // Only supported with SSE2+
-      FLAG_SET_DEFAULT(UseFPUForSpilling, false);
-    }
-  }
-#endif
-
 #if COMPILER2_OR_JVMCI
   int max_vector_size = 0;
-  if (UseSSE < 2) {
-    // Vectors (in XMM) are only supported with SSE2+
-    // SSE is always 2 on x64.
-    max_vector_size = 0;
-  } else if (UseAVX == 0 || !os_supports_avx_vectors()) {
+  if (UseAVX == 0 || !os_supports_avx_vectors()) {
     // 16 byte vectors (in XMM) are supported with SSE2+
     max_vector_size = 16;
   } else if (UseAVX == 1 || UseAVX == 2) {
@@ -1870,7 +1857,7 @@ void VM_Version::get_processor_features() {
 #endif
 
   // Use XMM/YMM MOVDQU instruction for Object Initialization
-  if (!UseFastStosb && UseSSE >= 2 && UseUnalignedLoadStores) {
+  if (!UseFastStosb && UseUnalignedLoadStores) {
     if (FLAG_IS_DEFAULT(UseXMMForObjInit)) {
       UseXMMForObjInit = true;
     }
@@ -1985,22 +1972,18 @@ void VM_Version::get_processor_features() {
 #endif
     log->cr();
     log->print("Allocation");
-    if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
+    if (AllocatePrefetchStyle <= 0) {
       log->print_cr(": no prefetching");
     } else {
       log->print(" prefetching: ");
-      if (UseSSE == 0 && supports_3dnow_prefetch()) {
+      if (AllocatePrefetchInstr == 0) {
+        log->print("PREFETCHNTA");
+      } else if (AllocatePrefetchInstr == 1) {
+        log->print("PREFETCHT0");
+      } else if (AllocatePrefetchInstr == 2) {
+        log->print("PREFETCHT2");
+      } else if (AllocatePrefetchInstr == 3) {
         log->print("PREFETCHW");
-      } else if (UseSSE >= 1) {
-        if (AllocatePrefetchInstr == 0) {
-          log->print("PREFETCHNTA");
-        } else if (AllocatePrefetchInstr == 1) {
-          log->print("PREFETCHT0");
-        } else if (AllocatePrefetchInstr == 2) {
-          log->print("PREFETCHT2");
-        } else if (AllocatePrefetchInstr == 3) {
-          log->print("PREFETCHW");
-        }
       }
       if (AllocatePrefetchLines > 1) {
         log->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
diff --git a/src/hotspot/cpu/x86/x86.ad b/src/hotspot/cpu/x86/x86.ad
index 7bde4ced2ba48..b1fa0bb396ae7 100644
--- a/src/hotspot/cpu/x86/x86.ad
+++ b/src/hotspot/cpu/x86/x86.ad
@@ -1368,11 +1368,6 @@ bool Matcher::match_rule_supported(int opcode) {
         return false;
       }
       break;
-    case Op_AddReductionVL:
-      if (UseSSE < 2) { // requires at least SSE2
-        return false;
-      }
-      break;
     case Op_AbsVB:
     case Op_AbsVS:
     case Op_AbsVI:
@@ -1556,31 +1551,11 @@ bool Matcher::match_rule_supported(int opcode) {
         return false;
       }
       break;
-    case Op_SignumF:
-      if (UseSSE < 1) {
-        return false;
-      }
-      break;
-    case Op_SignumD:
-      if (UseSSE < 2) {
-        return false;
-      }
-      break;
     case Op_CompressM:
       if (!VM_Version::supports_avx512vl() || !VM_Version::supports_bmi2()) {
         return false;
       }
       break;
-    case Op_SqrtF:
-      if (UseSSE < 1) {
-        return false;
-      }
-      break;
-    case Op_SqrtD:
-      if (UseSSE < 2) {
-        return false;
-      }
-      break;
     case Op_ConvF2HF:
     case Op_ConvHF2F:
       if (!VM_Version::supports_float16()) {
@@ -2173,7 +2148,6 @@ const RegMask* Matcher::predicate_reg_mask(void) {
 // Max vector size in bytes. 0 if not supported.
 int Matcher::vector_width_in_bytes(BasicType bt) {
   assert(is_java_primitive(bt), "only primitive type vectors");
-  if (UseSSE < 2) return 0;
   // SSE2 supports 128bit vectors for all types.
   // AVX2 supports 256bit vectors for all types.
   // AVX2/EVEX supports 512bit vectors for all types.
@@ -2884,7 +2858,7 @@ instruct ShouldNotReachHere() %{
 // ============================================================================
 
 instruct addF_reg(regF dst, regF src) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (AddF dst src));
 
   format %{ "addss   $dst, $src" %}
@@ -2896,7 +2870,7 @@ instruct addF_reg(regF dst, regF src) %{
 %}
 
 instruct addF_mem(regF dst, memory src) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (AddF dst (LoadF src)));
 
   format %{ "addss   $dst, $src" %}
@@ -2908,7 +2882,7 @@ instruct addF_mem(regF dst, memory src) %{
 %}
 
 instruct addF_imm(regF dst, immF con) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (AddF dst con));
   format %{ "addss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
   ins_cost(150);
@@ -2955,7 +2929,7 @@ instruct addF_reg_imm(regF dst, regF src, immF con) %{
 %}
 
 instruct addD_reg(regD dst, regD src) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (AddD dst src));
 
   format %{ "addsd   $dst, $src" %}
@@ -2967,7 +2941,7 @@ instruct addD_reg(regD dst, regD src) %{
 %}
 
 instruct addD_mem(regD dst, memory src) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (AddD dst (LoadD src)));
 
   format %{ "addsd   $dst, $src" %}
@@ -2979,7 +2953,7 @@ instruct addD_mem(regD dst, memory src) %{
 %}
 
 instruct addD_imm(regD dst, immD con) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (AddD dst con));
   format %{ "addsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}
   ins_cost(150);
@@ -3026,7 +3000,7 @@ instruct addD_reg_imm(regD dst, regD src, immD con) %{
 %}
 
 instruct subF_reg(regF dst, regF src) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (SubF dst src));
 
   format %{ "subss   $dst, $src" %}
@@ -3038,7 +3012,7 @@ instruct subF_reg(regF dst, regF src) %{
 %}
 
 instruct subF_mem(regF dst, memory src) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (SubF dst (LoadF src)));
 
   format %{ "subss   $dst, $src" %}
@@ -3050,7 +3024,7 @@ instruct subF_mem(regF dst, memory src) %{
 %}
 
 instruct subF_imm(regF dst, immF con) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (SubF dst con));
   format %{ "subss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
   ins_cost(150);
@@ -3097,7 +3071,7 @@ instruct subF_reg_imm(regF dst, regF src, immF con) %{
 %}
 
 instruct subD_reg(regD dst, regD src) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (SubD dst src));
 
   format %{ "subsd   $dst, $src" %}
@@ -3109,7 +3083,7 @@ instruct subD_reg(regD dst, regD src) %{
 %}
 
 instruct subD_mem(regD dst, memory src) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (SubD dst (LoadD src)));
 
   format %{ "subsd   $dst, $src" %}
@@ -3121,7 +3095,7 @@ instruct subD_mem(regD dst, memory src) %{
 %}
 
 instruct subD_imm(regD dst, immD con) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (SubD dst con));
   format %{ "subsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}
   ins_cost(150);
@@ -3168,7 +3142,7 @@ instruct subD_reg_imm(regD dst, regD src, immD con) %{
 %}
 
 instruct mulF_reg(regF dst, regF src) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (MulF dst src));
 
   format %{ "mulss   $dst, $src" %}
@@ -3180,7 +3154,7 @@ instruct mulF_reg(regF dst, regF src) %{
 %}
 
 instruct mulF_mem(regF dst, memory src) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (MulF dst (LoadF src)));
 
   format %{ "mulss   $dst, $src" %}
@@ -3192,7 +3166,7 @@ instruct mulF_mem(regF dst, memory src) %{
 %}
 
 instruct mulF_imm(regF dst, immF con) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (MulF dst con));
   format %{ "mulss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
   ins_cost(150);
@@ -3239,7 +3213,7 @@ instruct mulF_reg_imm(regF dst, regF src, immF con) %{
 %}
 
 instruct mulD_reg(regD dst, regD src) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (MulD dst src));
 
   format %{ "mulsd   $dst, $src" %}
@@ -3251,7 +3225,7 @@ instruct mulD_reg(regD dst, regD src) %{
 %}
 
 instruct mulD_mem(regD dst, memory src) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (MulD dst (LoadD src)));
 
   format %{ "mulsd   $dst, $src" %}
@@ -3263,7 +3237,7 @@ instruct mulD_mem(regD dst, memory src) %{
 %}
 
 instruct mulD_imm(regD dst, immD con) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (MulD dst con));
   format %{ "mulsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}
   ins_cost(150);
@@ -3310,7 +3284,7 @@ instruct mulD_reg_imm(regD dst, regD src, immD con) %{
 %}
 
 instruct divF_reg(regF dst, regF src) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (DivF dst src));
 
   format %{ "divss   $dst, $src" %}
@@ -3322,7 +3296,7 @@ instruct divF_reg(regF dst, regF src) %{
 %}
 
 instruct divF_mem(regF dst, memory src) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (DivF dst (LoadF src)));
 
   format %{ "divss   $dst, $src" %}
@@ -3334,7 +3308,7 @@ instruct divF_mem(regF dst, memory src) %{
 %}
 
 instruct divF_imm(regF dst, immF con) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (DivF dst con));
   format %{ "divss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
   ins_cost(150);
@@ -3381,7 +3355,7 @@ instruct divF_reg_imm(regF dst, regF src, immF con) %{
 %}
 
 instruct divD_reg(regD dst, regD src) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (DivD dst src));
 
   format %{ "divsd   $dst, $src" %}
@@ -3393,7 +3367,7 @@ instruct divD_reg(regD dst, regD src) %{
 %}
 
 instruct divD_mem(regD dst, memory src) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (DivD dst (LoadD src)));
 
   format %{ "divsd   $dst, $src" %}
@@ -3405,7 +3379,7 @@ instruct divD_mem(regD dst, memory src) %{
 %}
 
 instruct divD_imm(regD dst, immD con) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (DivD dst con));
   format %{ "divsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}
   ins_cost(150);
@@ -3452,7 +3426,7 @@ instruct divD_reg_imm(regD dst, regD src, immD con) %{
 %}
 
 instruct absF_reg(regF dst) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (AbsF dst));
   ins_cost(150);
   format %{ "andps   $dst, [0x7fffffff]\t# abs float by sign masking" %}
@@ -3476,7 +3450,7 @@ instruct absF_reg_reg(vlRegF dst, vlRegF src) %{
 %}
 
 instruct absD_reg(regD dst) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (AbsD dst));
   ins_cost(150);
   format %{ "andpd   $dst, [0x7fffffffffffffff]\t"
@@ -3502,7 +3476,7 @@ instruct absD_reg_reg(vlRegD dst, vlRegD src) %{
 %}
 
 instruct negF_reg(regF dst) %{
-  predicate((UseSSE>=1) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (NegF dst));
   ins_cost(150);
   format %{ "xorps   $dst, [0x80000000]\t# neg float by sign flipping" %}
@@ -3525,7 +3499,7 @@ instruct negF_reg_reg(vlRegF dst, vlRegF src) %{
 %}
 
 instruct negD_reg(regD dst) %{
-  predicate((UseSSE>=2) && (UseAVX == 0));
+  predicate(UseAVX == 0);
   match(Set dst (NegD dst));
   ins_cost(150);
   format %{ "xorpd   $dst, [0x8000000000000000]\t"
@@ -3552,7 +3526,6 @@ instruct negD_reg_reg(vlRegD dst, vlRegD src) %{
 // sqrtss instruction needs destination register to be pre initialized for best performance
 // Therefore only the instruct rule where the input is pre-loaded into dst register is defined below
 instruct sqrtF_reg(regF dst) %{
-  predicate(UseSSE>=1);
   match(Set dst (SqrtF dst));
   format %{ "sqrtss  $dst, $dst" %}
   ins_encode %{
@@ -3564,7 +3537,6 @@ instruct sqrtF_reg(regF dst) %{
 // sqrtsd instruction needs destination register to be pre initialized for best performance
 // Therefore only the instruct rule where the input is pre-loaded into dst register is defined below
 instruct sqrtD_reg(regD dst) %{
-  predicate(UseSSE>=2);
   match(Set dst (SqrtD dst));
   format %{ "sqrtsd  $dst, $dst" %}
   ins_encode %{
@@ -4486,7 +4458,7 @@ instruct ReplI_zero(vec dst, immI_0 zero) %{
 %}
 
 instruct ReplI_M1(vec dst, immI_M1 con) %{
-  predicate(UseSSE >= 2 && Matcher::is_non_long_integral_vector(n));
+  predicate(Matcher::is_non_long_integral_vector(n));
   match(Set dst (Replicate con));
   format %{ "vallones $dst" %}
   ins_encode %{
@@ -4566,7 +4538,7 @@ instruct ReplL_zero(vec dst, immL0 zero) %{
 %}
 
 instruct ReplL_M1(vec dst, immL_M1 con) %{
-  predicate(UseSSE >= 2 && Matcher::vector_element_basic_type(n) == T_LONG);
+  predicate(Matcher::vector_element_basic_type(n) == T_LONG);
   match(Set dst (Replicate con));
   format %{ "vallones $dst" %}
   ins_encode %{
@@ -6938,7 +6910,6 @@ instruct vshiftL_arith_reg(vec dst, vec src, vec shift, vec tmp) %{
   ins_encode %{
     uint vlen = Matcher::vector_length(this);
     if (vlen == 2) {
-      assert(UseSSE >= 2, "required");
       __ movdqu($dst$$XMMRegister, $src$$XMMRegister);
       __ psrlq($dst$$XMMRegister, $shift$$XMMRegister);
       __ movdqu($tmp$$XMMRegister, ExternalAddress(vector_long_sign_mask()), noreg);
@@ -8312,7 +8283,6 @@ instruct vabsnegD(vec dst, vec src) %{
     int opcode = this->ideal_Opcode();
     uint vlen = Matcher::vector_length(this);
     if (vlen == 2) {
-      assert(UseSSE >= 2, "required");
       __ vabsnegd(opcode, $dst$$XMMRegister, $src$$XMMRegister);
     } else {
       int vlen_enc = vector_length_encoding(this);
diff --git a/src/hotspot/share/adlc/dfa.cpp b/src/hotspot/share/adlc/dfa.cpp
index 9b3b87e13a90b..9c3d76cba55d5 100644
--- a/src/hotspot/share/adlc/dfa.cpp
+++ b/src/hotspot/share/adlc/dfa.cpp
@@ -461,7 +461,7 @@ void ArchDesc::buildDFA(FILE* fp) {
 
 
 class dfa_shared_preds {
-  enum { count = 3 IA32_ONLY( + 1 ) };
+  enum { count = 3 };
 
   static bool        _found[count];
   static const char* _type [count];
@@ -572,10 +572,10 @@ class dfa_shared_preds {
   }
 };
 // shared predicates, _var and _pred entry should be the same length
-bool         dfa_shared_preds::_found[dfa_shared_preds::count] = { false,          false,           false               IA32_ONLY(COMMA false)  };
-const char*  dfa_shared_preds::_type [dfa_shared_preds::count] = { "int",          "jlong",         "intptr_t"          IA32_ONLY(COMMA "bool") };
-const char*  dfa_shared_preds::_var  [dfa_shared_preds::count] = { "_n_get_int__", "_n_get_long__", "_n_get_intptr_t__" IA32_ONLY(COMMA "Compile__current____select_24_bit_instr__") };
-const char*  dfa_shared_preds::_pred [dfa_shared_preds::count] = { "n->get_int()", "n->get_long()", "n->get_intptr_t()" IA32_ONLY(COMMA "Compile::current()->select_24_bit_instr()") };
+bool         dfa_shared_preds::_found[dfa_shared_preds::count] = { false,          false,           false               };
+const char*  dfa_shared_preds::_type [dfa_shared_preds::count] = { "int",          "jlong",         "intptr_t"          };
+const char*  dfa_shared_preds::_var  [dfa_shared_preds::count] = { "_n_get_int__", "_n_get_long__", "_n_get_intptr_t__" };
+const char*  dfa_shared_preds::_pred [dfa_shared_preds::count] = { "n->get_int()", "n->get_long()", "n->get_intptr_t()" };
 
 // Helper method to check whether a node is vector unary operation.
 static bool is_vector_unary_op_name(const char* op_name) {
diff --git a/src/hotspot/share/c1/c1_LinearScan.cpp b/src/hotspot/share/c1/c1_LinearScan.cpp
index 3736284892fd9..29c2d3d9b9266 100644
--- a/src/hotspot/share/c1/c1_LinearScan.cpp
+++ b/src/hotspot/share/c1/c1_LinearScan.cpp
@@ -1087,43 +1087,23 @@ IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
   // this operand is allowed to be on the stack in some cases
   BasicType opr_type = opr->type_register();
   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
-    if (IA32_ONLY( (UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 ) NOT_IA32( true )) {
-      // SSE float instruction (T_DOUBLE only supported with SSE2)
-      switch (op->code()) {
-        case lir_cmp:
-        case lir_add:
-        case lir_sub:
-        case lir_mul:
-        case lir_div:
-        {
-          assert(op->as_Op2() != nullptr, "must be LIR_Op2");
-          LIR_Op2* op2 = (LIR_Op2*)op;
-          if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
-            assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
-            return shouldHaveRegister;
-          }
-        }
-        default:
-          break;
-      }
-    } else {
-      // FPU stack float instruction
-      switch (op->code()) {
-        case lir_add:
-        case lir_sub:
-        case lir_mul:
-        case lir_div:
-        {
-          assert(op->as_Op2() != nullptr, "must be LIR_Op2");
-          LIR_Op2* op2 = (LIR_Op2*)op;
-          if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
-            assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
-            return shouldHaveRegister;
-          }
+    // SSE float instruction
+    switch (op->code()) {
+      case lir_cmp:
+      case lir_add:
+      case lir_sub:
+      case lir_mul:
+      case lir_div:
+      {
+        assert(op->as_Op2() != nullptr, "must be LIR_Op2");
+        LIR_Op2* op2 = (LIR_Op2*)op;
+        if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
+          assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
+          return shouldHaveRegister;
         }
-        default:
-          break;
       }
+      default:
+        break;
     }
     // We want to sometimes use logical operations on pointers, in particular in GC barriers.
     // Since 64bit logical operations do not current support operands on stack, we have to make sure
@@ -1284,28 +1264,20 @@ void LinearScan::build_intervals() {
   // virtual fpu operands. Otherwise no allocation for fpu registers is
   // performed and so the temp ranges would be useless
   if (has_fpu_registers()) {
-#ifdef X86
-    if (UseSSE < 2) {
-#endif // X86
-      for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
-        LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
-        assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
-        assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
-        caller_save_registers[num_caller_save_registers++] = reg_num(opr);
-      }
-#ifdef X86
+#ifndef X86
+    for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
+      LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
+      assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
+      assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
+      caller_save_registers[num_caller_save_registers++] = reg_num(opr);
     }
-#endif // X86
-
-#ifdef X86
-    if (UseSSE > 0) {
-      int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
-      for (i = 0; i < num_caller_save_xmm_regs; i ++) {
-        LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
-        assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
-        assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
-        caller_save_registers[num_caller_save_registers++] = reg_num(opr);
-      }
+#else
+    int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
+    for (i = 0; i < num_caller_save_xmm_regs; i ++) {
+      LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
+      assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
+      assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
+      caller_save_registers[num_caller_save_registers++] = reg_num(opr);
     }
 #endif // X86
   }
@@ -2152,40 +2124,30 @@ LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
 #ifndef __SOFTFP__
       case T_FLOAT: {
 #ifdef X86
-        if (UseSSE >= 1) {
-          int last_xmm_reg = pd_last_xmm_reg;
-#ifdef _LP64
-          if (UseAVX < 3) {
-            last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
-          }
-#endif // LP64
-          assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
-          assert(interval->assigned_regHi() == any_reg, "must not have hi register");
-          return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
+        int last_xmm_reg = pd_last_xmm_reg;
+        if (UseAVX < 3) {
+          last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
         }
-#endif // X86
-
+        assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
+        assert(interval->assigned_regHi() == any_reg, "must not have hi register");
+        return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
+#else
         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
+#endif // !X86
       }
 
       case T_DOUBLE: {
-#ifdef X86
-        if (UseSSE >= 2) {
-          int last_xmm_reg = pd_last_xmm_reg;
-#ifdef _LP64
-          if (UseAVX < 3) {
-            last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
-          }
-#endif // LP64
-          assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
-          assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
-          return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
+#if defined(X86)
+        int last_xmm_reg = pd_last_xmm_reg;
+        if (UseAVX < 3) {
+          last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
         }
-#endif // X86
-
-#if defined(ARM32)
+        assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
+        assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
+        LIR_Opr result = LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
+#elif defined(ARM32)
         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
diff --git a/src/hotspot/share/opto/compile.cpp b/src/hotspot/share/opto/compile.cpp
index c830d0c854b2a..9e29ecb7616d6 100644
--- a/src/hotspot/share/opto/compile.cpp
+++ b/src/hotspot/share/opto/compile.cpp
@@ -1014,8 +1014,6 @@ void Compile::Init(bool aliasing) {
   _matcher = nullptr;  // filled in later
   _cfg     = nullptr;  // filled in later
 
-  IA32_ONLY( set_24_bit_selection_and_mode(true, false); )
-
   _node_note_array = nullptr;
   _default_node_notes = nullptr;
   DEBUG_ONLY( _modified_nodes = nullptr; ) // Used in Optimize()
@@ -4100,17 +4098,6 @@ bool Compile::final_graph_reshaping() {
     }
   }
 
-#ifdef IA32
-  // If original bytecodes contained a mixture of floats and doubles
-  // check if the optimizer has made it homogeneous, item (3).
-  if (UseSSE == 0 &&
-      frc.get_float_count() > 32 &&
-      frc.get_double_count() == 0 &&
-      (10 * frc.get_call_count() < frc.get_float_count()) ) {
-    set_24_bit_selection_and_mode(false, true);
-  }
-#endif // IA32
-
   set_java_calls(frc.get_java_call_count());
   set_inner_loops(frc.get_inner_loop_count());
 
diff --git a/src/hotspot/share/opto/compile.hpp b/src/hotspot/share/opto/compile.hpp
index bd998194ff790..271013f29c5cc 100644
--- a/src/hotspot/share/opto/compile.hpp
+++ b/src/hotspot/share/opto/compile.hpp
@@ -1300,21 +1300,6 @@ class Compile : public Phase {
   bool needs_clinit_barrier(ciMethod* ik,        ciMethod* accessing_method);
   bool needs_clinit_barrier(ciInstanceKlass* ik, ciMethod* accessing_method);
 
-#ifdef IA32
- private:
-  bool _select_24_bit_instr;   // We selected an instruction with a 24-bit result
-  bool _in_24_bit_fp_mode;     // We are emitting instructions with 24-bit results
-
-  // Remember if this compilation changes hardware mode to 24-bit precision.
-  void set_24_bit_selection_and_mode(bool selection, bool mode) {
-    _select_24_bit_instr = selection;
-    _in_24_bit_fp_mode   = mode;
-  }
-
- public:
-  bool select_24_bit_instr() const { return _select_24_bit_instr; }
-  bool in_24_bit_fp_mode() const   { return _in_24_bit_fp_mode; }
-#endif // IA32
 #ifdef ASSERT
   VerifyMeetResult* _type_verify;
   void set_exception_backedge() { _exception_backedge = true; }