[BUG] SystemVerilog port type compatibility issue: packet_type_o enum port declaration triggers DSim PortTypeMismatch

[AlexChenIC]

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

Summary

Altair DSim 2026.0 simulator elaboration fails due to a type mismatch on the rv_tracer.packet_type_o port connection in ariane_testharness.

Observed Error (DSim)

=E:[PortTypeMismatch]:
  ariane_testharness.sv:727 packet_type_o
  formal: enum logic[3:0]{...}[0:0]
  actual: enum logic[3:0]{...}

Relevant Code

corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv(line 60)
corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv (line 172)
corev_apu/tb/ariane_testharness.sv (line 727)

Root cause (based on code inspection)

In corev_apu/.../rv_tracer.sv (line 60), the port is declared as an unpacked array of an enum type:

output te_pkg::it_packet_type_e [N-1:0] packet_type_o,

The instantiation parameter N is set to 1, while te_pkg::it_packet_type_e (in te_pkg.sv) is defined as an enumerated type with packed bit-width [3:0]. With N=1, the port becomes a single-element unpacked array ([0:0]) of a scalar enum, which is not type-compatible with a scalar enum connection under strict SystemVerilog typing. DSim therefore correctly flags this as a fatal type error.

Per Mike Thompson’s suggestion (based on git blame), could a maintainer please assign this issue to Jean Roch Coulon?

Thanks.