[BUG] mstatus.SD does not reflect VS=Dirty, violating RISC-V Privileged Spec

[oChunCai]

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

Spec Reference

According to the RISC-V Privileged Spec (the SD description of mstatus), SD is a read-only bit that summarizes whether any extension state is dirty:

this is equivalent to: SD == 1 if any of FS==Dirty, VS==Dirty, or XS==Dirty holds

Problem Description

In core/csr_regfile.sv (around lines 1859–1863). The computation of SD only considers XS and FS, and does not include VS:

As a result, there exists a condition where VS=Dirty but SD=0,which contradicts the specification definition of SD.