Fix Vivado property usage for simulation files (#474)

[rbrglez]

Replace used_in_implementation and used_in_synthesis with used_in

Vivado does not support used_in_implementation for all file types (e.g., Verilog and VHDL). Replaced both used_in_implementation and used_in_synthesis with the used_in property, which explicitly defines the allowed design flows and works consistently across all file types.

[olofk]

The fix looks good, but we need to also update the tests because they are failing with this change. Easiest way to see what needs to be done is to run GOLDEN_RUN=1 tox from the edalize root and it will update the reference files with the expected changes. Check and add the changed files and update the PR.