diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..438c411
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,9 @@
+This repository contains some files that are licensed under the Amazon
+Software License, and some files that are licensed under the NVIDIA Open
+NVDLA License and Agreement v1.0. When editing, redistributing, or
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+in this distribution as 'LICENSE.nvdla'.
diff --git a/LICENSE.asl b/LICENSE.asl
new file mode 100644
index 0000000..d217d71
--- /dev/null
+++ b/LICENSE.asl
@@ -0,0 +1,161 @@
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diff --git a/LICENSE.nvdla b/LICENSE.nvdla
new file mode 100644
index 0000000..f9bb874
--- /dev/null
+++ b/LICENSE.nvdla
@@ -0,0 +1,206 @@
+NVIDIA Open NVDLA License and Agreement v1.0
+
+NVIDIA's Deep Learning Accelerator ("NVDLA") is a hardware design that
+accelerates inferencing in System-on-a-Chip designs. Subject to the terms
+and conditions of this Open NVDLA License and Agreement, NVIDIA offers its
+NVDLA design on a royalty-free, open-source basis, promoting the adoption of
+deep learning inferencing in third-party designs and IoT devices, and
+expanding the overall market for AI.
+
+By exercising the rights granted hereunder, You accept and agree to be bound
+by these terms and conditions. You are granted the rights hereunder in
+consideration of Your agreement to these terms and conditions. If You do
+not agree to these terms and conditions, do not download or use the NVDLA
+Specification.
+
+If You are agreeing to these terms and conditions on behalf of a legal
+entity, You represent that You have the legal authority to bind the legal
+entity to these terms and conditions.
+
+In consideration of the mutual covenants contained herein, You agree as
+follows:
+
+1. DEFINITIONS.
+
+"NVDLA Specification" shall mean and include the design information, code,
+and documentation used in designing a deep learning accelerator or creating
+a DLA Product, which may include: HDL, netlists, GDSII files, mask works,
+architectural descriptions, interface specifications, microcode, software
+source code, documentation source, and configuration files.
+
+"Contributor" shall mean NVIDIA and any owner of a NVDLA Contribution that
+NVIDIA has incorporated within the NVDLA Specification.
+
+"Derivative Work" shall mean any work that is based on (or derived from)
+any portion of the NVDLA Specification. For the purposes of this License,
+Derivative Works shall not include works that remain separable from, or
+merely link (or bind by name) to the interfaces of, any portion of the NVDLA
+Specification and Derivative Works thereof.
+
+"DLA Product" shall mean a semiconductor chip product or portions thereof
+designed or manufactured in accordance with a NVDLA Specification or a
+Derivative Work, including any semiconductor chip product embodying a mask
+work included in a NVDLA Specification or a Derivative Work.
+
+"NVDLA" means NVIDIA's Deep Learning Accelerator, a hardware design that
+accelerates inferencing in System-on-a-Chip designs.
+
+"NVDLA Contribution" shall mean any work of authorship, design, or
+inventorship that is intentionally submitted to NVIDIA for inclusion in the
+NVDLA Specification by a person authorized to submit the contribution on
+behalf of the owner.
+
+"NVDLA Patents" shall mean patents that are necessary to practice the NVDLA
+Specification and any Derivative Works.
+
+"NVDLA Patent Rights" shall mean the right to make, have made, use, sell,
+offer for sale, and import patents that are necessary to practice the NVDLA
+Specification and any Derivative Works.
+
+"Other NVDLA Rights" includes copyright, design right (whether registered or
+unregistered), semiconductor topography (mask work) rights, and database
+rights to the NVDLA Specification and any Derivative Work. For the
+avoidance of doubt, Other NVDLA Rights does not include patents or
+trademarks.
+
+"License" and "Agreement" shall mean the terms and conditions for use,
+reproduction, and distribution as set forth in this document.
+
+"You" (or "Your") shall mean an individual or Legal Entity agreeing to the
+terms and conditions of this License.
+
+2. LICENSE TO NVDLA PATENTS.
+
+Subject to the terms and conditions of this License, NVIDIA and each
+Contributor hereby grant to You a perpetual, worldwide, non-exclusive,
+no-charge, royalty-free, irrevocable (except as stated in this section)
+license under the NVDLA Patents to make, have made, use, offer to sell,
+sell, import, and otherwise transfer DLA Products and the NVDLA
+Specification, where such license applies only to those patent claims
+licensable by such Contributor that are necessarily infringed either by (i)
+their Contribution(s) alone or (ii) the combination of their NVDLA
+Contribution(s) with the portion of the NVDLA Specification to which such
+NVDLA Contribution(s) was submitted.
+
+If You institute patent litigation against any entity (including a
+cross-claim or counterclaim in a lawsuit) alleging that any portion of the
+NVDLA Specification, a NVDLA Contribution incorporated within the NVDLA
+Specification, or any portion of a DLA Product directly or contributorily
+infringes any patent, then any patent licenses granted to You under this
+License and Agreement shall terminate as of the date such litigation is
+filed.
+
+3. LICENSE TO OTHER NVDLA RIGHTS.
+
+Subject to the terms and conditions of this License, NVIDIA and each
+Contributor hereby grant to You a perpetual, worldwide, non-exclusive,
+no-charge, royalty-free, irrevocable license under the Other NVDLA Rights to
+reproduce, prepare Derivative Works of, publicly display, publicly perform,
+sublicense, and distribute the NVDLA Specification and such Derivative
+Works, and to commercially exploit any mask works included in the NVDLA
+Specification or such Derivative Works.
+
+4. REDISTRIBUTION.
+
+You may reproduce and distribute copies of the NVDLA Specification or
+Derivative Works thereof in any medium, with or without modifications,
+provided that You meet the following conditions:
+
+ 1. You must give any other recipients of the NVDLA Specification or
+ Derivative Works a copy of this License and Agreement; and
+
+ 2. You must cause any modified files or other portions of the NVDLA
+ Specification to carry prominent notices stating that You changed such
+ files or other portions; and
+
+ 3. You must retain, in any Derivative Works that You distribute, all
+ notices, including copyright, patent, trademark, and attribution
+ notices, from the NVDLA Specification, excluding those notices that do
+ not pertain to any part of the Derivative Works; and
+
+ 4. You may add Your own copyright statement to Your modifications and may
+ provide additional or different license terms and conditions for use,
+ reproduction, or distribution of Your modifications, or for any such
+ Derivative Works as a whole, provided Your use, reproduction, and
+ distribution of the NVDLA Specification otherwise complies with the
+ conditions stated in this License and Agreement.
+
+5. SUBMISSION OF NVDLA CONTRIBUTIONS.
+
+You are not required to submit contributions to the NVDLA Specification, but
+you may do so at your discretion. Unless You explicitly state otherwise,
+any NVDLA Contribution intentionally submitted by you to NVIDIA for
+inclusion in the NVDLA Specification shall be provided under the terms and
+conditions of this License and Agreement, without any additional terms or
+conditions. NVIDIA is under no obligation to consider, review, or
+incorporate any NVDLA Contribution into any version of the NVDLA
+Specification
+
+6. TRADEMARKS.
+
+This License does not grant permission to use the trade names, trademarks,
+service marks, or product names ("Marks") of NVIDIA or any Contributor,
+except as required for reasonable and customary use in describing the origin
+of the NVDLA Specification. For DLA Products that are compatible with NVDLA
+interfaces, NVIDIA and You may mutually agree on certain marketing
+activities and branding involving the use of NVIDIA's Marks under separate
+agreement and/or supplemental terms.
+
+7. NO IMPLIED RIGHTS.
+
+Except for the licenses expressly set forth herein, no other licenses are
+granted hereunder whether by implication, estoppel or otherwise. This
+License and Agreement provides you with no implied rights or licenses to the
+intellectual property of NVIDIA or any Contributor.
+
+8. DISCLAIMER OF WARRANTY.
+
+Unless required by applicable law or agreed to in writing, NVIDIA provides
+the NVDLA Specification (and each Contributor provides its NVDLA
+Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+KIND, either express or implied, including, without limitation, any
+warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or
+FITNESS FOR A PARTICULAR PURPOSE.
+
+You are solely responsible for determining the appropriateness of Your use
+of NVDLA, the NVDLA Specification, or any DLA Product, and You assume all
+associated risks, including but not limited to the risks and costs of damage
+to or loss of data, programs or equipment, and unavailability or
+interruption of operations. You agree to comply with all regulations and
+safety standards applicable to Your use of NVDLA and the NVDLA
+Specification. You acknowledge that the NVDLA and NVDLA Specification
+provided to You under this Agreement are not intended to be used, without
+additional safeguards and/or process technology, to control or operate
+machines that can lead to personal injury, death, or severe physical or
+environmental damage, and if You make, use, or sell such machines, You agree
+to assume all liability therefor and will comply with all applicable
+safety-related laws, regulations, and best industry practices.
+
+9. LIMITATION OF LIABILITY.
+
+In no event and under no legal theory, whether in tort (including
+negligence), contract, or otherwise, shall NVIDIA or any Contributor be
+liable to You for damages, including any direct, indirect, special,
+incidental, or consequential damages of any character arising as a result of
+this License and Agreement, or arising out of the use or inability to use
+any DLA Product (including but not limited to damages for loss of goodwill,
+work stoppage, computer failure or malfunction, or any and all other
+commercial damages or losses).
+
+10. WAIVER AND INDEMNITY.
+
+You agree to waive any and all claims against NVIDIA and each Contributor
+arising from Your use of NVDLA or the NVDLA Specification. If Your use of
+the NVDLA, the NVDLA Specification, or any portion thereof, results in any
+liabilities, demands, damages, expenses or losses arising from such use,
+including any damages from products based on, or resulting from, Your use of
+NVDLA or the NVDLA Specification licensed under this Agreement, You shall
+indemnify and hold harmless NVIDIA and each Contributor to the extent
+permitted by law. In addition, You agree to defend, indemnify, and hold
+NVIDIA and each Contributor harmless from any claim brought by a third party
+alleging any defect in the design, manufacture, or any Product which You
+make, have made, sell, or distribute pursuant to this Agreement. Your sole
+remedy for any such matter shall be the immediate, unilateral termination of
+this Agreement.
+
+END OF OPEN NVDLA LICENSE AND AGREEMENT
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..2ab2e2b
--- /dev/null
+++ b/README.md
@@ -0,0 +1,19 @@
+# Virtual Platform On AWS FPGA
+
+## NVDLA
+
+The NVIDIA Deep Learning Accelerator (NVDLA) is a free and open architecture that promotes a standard way to design deep learning inference accelerators. With its modular architecture, NVDLA is scalable, highly configurable, and designed to simplify integration and portability. Learn more about NVDLA on the project web page.
+
+
+
+## Online Documentation
+
+You can find the latest NVDLA Virtual Platform documentation for AWS FPGA [here](http://nvdla.org/vp_fpga.html).
+
+## NVIDIA Sample AFI
+
+agfi-0ebfbde27cfbc88d2
+
+## EC2 FPGA Hardware and Software Development Kits version
+
+be3d41cb1b6b5db6bc24b577ab1af8d2eb4de102
\ No newline at end of file
diff --git a/cl_memdut/build/README.md b/cl_memdut/build/README.md
new file mode 100644
index 0000000..4a542c6
--- /dev/null
+++ b/cl_memdut/build/README.md
@@ -0,0 +1,181 @@
+# How to build and submit your Custom Logic (CL) to AWS
+
+# Table of Contents
+
+1. [Overview of AFI Build process](#buildoverview)
+2. [Build procedure step by step](#stepbystep)
+3. [Build strategies and parallel builds](#strategies)
+4. [About Encryption during build process](#buildencryption)
+5. [Advanced Notes](#buildadvanced_notes)
+6. [Build Frequently Asked Questions](#buildfaq)
+
+
+
+## Overview
+
+Once the developer has a functional design, the next steps are to: synthesize the design into basic FPGA cells, perform place-and-route, and check that the design meets the timing/frequency constraints. This could be an iterative process. Upon success, the developer will need to pass the output of the flow to AWS for final AFI creation.
+
+The developer needs to transfer to AWS a tar file that includes the encrypted placed-and-routed design checkpoint (referred to as DCP throughout this document) and [manifest](./../../../../docs/AFI_Manifest.md). The DCP includes the complete developer design that meets timing/frequency constraints, placement boundaries within the allocated CL area on the FPGA, and the functional requirements laid out in the [Shell Interface Specification](./../../../../docs/AWS_Shell_Interface_Specification.md#overview). The [manifest.txt](./../../../../docs/AFI_Manifest.md) should include key parameters needed for registering and loading the AFI, such as target frequency.
+
+To assist in this process, AWS provides a reference DCP that includes the shell (SH) logic with a black-boxed CL under: `$HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp`
+
+AWS also provides an out-of-the-box generic script called `aws_build_dcp_from_cl.sh` that is used to test compile a few examples, such as the `cl_hello_world` design, as if they were developer code. These reference examples can serve as starting points for new designs. The output of the AWS-provided scripts will create a tar file, with both the encrypted placed-and-routed DCP and the corresponding `manifest.txt`, which AWS will use to generate the final bitstream.
+
+AWS provides multiple options to generate a DCP that meets placement and timing constraints. The `aws_build_dcp_from_cl.sh` provides multiple choices for implementation strategies, invoked by the `-strategy` option. For more details refer to [Build Strategies](#strategies) below or call `aws_build_dcp_from_cl.sh -help` for the list of supported capabilities.
+
+Advanced developers can use different scripts, tools, and techniques (e.g., regioning), with the condition that they submit both the `manifest.txt` and "encrypted placed-and-routed design checkpoint (DCP)" in a single tar file that passes final checks.
+
+
+## Build Procedure
+
+The following describes the step-by-step procedure to build developer CLs. Some of these steps can be modified or adjusted based on developer experience and design needs.
+
+A developer can execute `$HDK_SHELL_DIR/build/scripts/aws_build_dcp_from_cl.sh` to check the environment, setup the build directory, invoke Xilinx Vivado to create the encrypted placed-and-routed DCP (which include AWS Shell + Developer CL), create the [`manifest.txt`](./../../../../docs/AFI_Manifest.md) that AWS will ingest through the CreateFpgaImage EC2 API. Executing this script also entails encryption of developer-specified RTL files. Further details on invoking the script from Vivado are provided below.
+
+### 1) Pre-requisite: Environment Variables and Tools
+
+ 1. The environment variable `HDK_SHELL_DIR` should have been set. This is usually done by executing `source hdk_setup.sh` from the HDK root directory
+ 2. The environment variable `CL_DIR` should have been set pointing to the root directory where the CL exists. The CL root directory should have the `/build` and `/design` subdirectories. One way to make sure to have the right directory is to execute `source $(HDK_DIR)/cl/developer_designs/prepare_new_cl.sh`
+ 3. Developer have Xilinx Vivado tools installed, with the supported version by the HDK, and with proper license. If the developer is using AWS supplied [FPGA Development AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) from AWS marketplace, it includes the README.md how to setup up the tools and license.
+
+### 2) Encrypt Source Files
+
+CL Encryption is required and AFI creation will fail if your CL source files are not encrypted. As a pre-cursor to the build process, modify the `$CL_DIR/build/scripts/encrypt.tcl` script to include all the CL source files, so the script can encrypt and copy them to the `$CL_DIR/build/src_post_encryption` directory.
+
+### 3) Prepare for the CL Build
+
+Modify the `$CL_DIR/build/scripts/create_dcp_from_cl.tcl` script to include:
+ 1. The list of CL encrypted files in `$CL_DIR/build/src_post_encryption`.
+ 2. The list of CL specific timing and placement constraints in `$CL_DIR/build/constraints`.
+ 3. The specific constraints and design file for IP any included in your CL (e.g., DDR4).
+
+### 4) Build
+
+Run the build script, aws_build_dcp_from_cl.sh, from the `$CL_DIR/build/scripts` directory.
+
+The build script performs:
+ - Synthesis of CL.
+ - Implementation of CL with AWS Shell.
+ - Generation of Design Checkpoint (DCP) for AWS ingestion with the associated logs.
+ - Generation of the corresponding manifest.txt.
+
+
+#### Build Strategies
+In order to help developers close timing goals and successfully build their designs efficiently, the build script provides the means to synthesize with different strategies. The different strategies alter the directives used by the synthesis tool. For example, some directives might specify additional optimizations to close timing, while others may specify less effort to minimize synthesis time for designs that can more easily close timing and area goals. Since every design is different, some strategies may provide better results than another build strategies. If a developer has trouble successfully building their design with one strategy it is encouraged that they try a different strategy, or run a few strategies in parallel using the FPGA Developer AMI. The strategies are described in more detail below.
+
+Build script usage:
+
+ $ ./aws_build_dcp_from_cl.sh [ [-script ] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-uram_option 2 | 3 | 4] [-foreground] [-notify] | [-h] | [-H] | [-help] ]
+Options:
+
+* -script \
+ * Use the specified vivado script. The default script create_dcp_from_cl.tcl will be used if a script is not specified.
+
+* -h, -H, -help
+ * Print a usage message.
+
+* -strategy \
+ * Use the specified strategy to alter the directives used during synthesis. The DEFAULT strategy will be used if a strategy is not specified.
+
+* -clock_recipe_a \
+ * Use the Clock Group A clock frequencies defined for the specified Clock Group A recipe. This is an optional argument and the default value will be A0. Refer to the [Clock Group Recipes Table](./../../../../docs/clock_recipes.csv).
+
+* -clock_recipe_b \
+ * Use the Clock Group B clock frequencies defined for the specified Clock Group B recipe. This is an optional argument and the default value will be B0. Refer to the [Clock Group Recipes Table](./../../../../docs/clock_recipes.csv).
+
+* -clock_recipe_c \
+ * Use the Clock Group C clock frequencies defined for the specified Clock Group C recipe. This is an optional argument and the default value will be C0. Refer to the [Clock Group Recipes Table](./../../../../docs/clock_recipes.csv).
+
+* -uram_option \<2 | 3 | 4>
+ * Use the specified URAM option to define the percentage of URAM sites used for the design. A value of 2 indicates 50%, a value of 3 indicates 75%, and a value of 4 indicates 100%. This is an optional argument and the default value will be 2.
+
+* -foreground
+ * Run the build in the foreground such that all output will go to the terminal and the build may be terminated if the terminal is closed. This option is useful if you want to wait for the build to complete. This option is safe if the terminal is running on the AWS instance, for example on a GUI desktop on the instance.
+
+* -notify
+ * Send e-mail to notify user once the build is complete. Requires setup described in `$HDK_DIR/cl/examples/README.md`.
+
+Strategy descriptions:
+
+* BASIC
+ * This is the basic flow in Vivado and contains the mandatory steps to be able to build a design. It is designed to provide a good balance between runtime and Quality of Results (QOR).
+
+* EXPLORE
+ * This is a high-effort flow which is designed to give improved QOR results at the expense of runtime.
+
+* TIMING
+ * This flow is designed for more aggressive timing optimization at the expense of runtime and congestion.
+
+* CONGESTION
+ * This flow is designed to insert more aggressive whitespace to alleviate routing congestion.
+
+* DEFAULT
+ * This is an additional high-effort flow that results in improved QOR results for the example design at the expense of runtime.
+
+In addition, in order to aid developers with build verification, there is a final step in the build script that emulates the process that AWS uses to generate bitstreams from a developer DCP.
+
+The outputs of the build script are:
+ - `$CL_DIR/build/checkpoints/*`: Various checkpoints generated during the build process.
+ - `$CL_DIR/build/to_aws/SH_CL_routed.dcp`: Encrypted placed-and-routed design checkpoint for AWS ingestion.
+ - `$CL_DIR/build/reports/*`: Various build reports (generally, check_timing/report_timing).
+ - `$CL_DIR/build/src_post_encryption/*`: Encrypted developer source.
+ - `$CL_DIR/build/constraints/*`: Implementation constraints.
+
+A developer may need to iterate multiple times through this process until arriving upon an error-free run.
+
+### 5) Submit the final tar file to AWS to register the AFI
+
+To submit the DCP, create an S3 bucket for submitting the design and upload the tarball file into that bucket.
+You need to prepare the following information:
+
+1. Name of the logic design *(Optional)*.
+2. Generic description of the logic design *(Optional)*.
+3. PCI IDs: Device, Vendor, Subsystem, SubsystemVendor.
+4. Location of the tarball file object in S3.
+5. Location of an S3 directory where AWS would write back logs of the AFI creation.
+6. Version of the AWS Shell.
+
+**NOTE**: *The PCI IDs for the example CLs should be found in the README files in the respective CL example directory.
+If you are building a custom CL, then you need to incorporate these values in your design as shown in the [AWS Shell Interface Specifications](./../../../../docs/AWS_Shell_Interface_Specification.md#pcie-ids).*
+
+[Refer to step 3 for instructions on how to submit the Design Checkpoint to AWS](./../../../../cl/examples/README.md)
+
+
+## Build Strategies and Parallel Builds
+
+Developers may face challenges fitting the CL design into the FPGA due to routing congestion, placement congestion, or not being able to meet timing. These are typical challenges in FPGA and chip development.
+
+AWS script `./aws_build_dcp_from_cl.sh` offers an optional flag to set one of a few useful implementation strategies, which would automatically different directives to various build steps. You can learn about the various strategy options by running `$ ./aws_build_dcp_from_cl.sh -help`.
+
+If you are running on one of the EC2 compute instances with 31GiB DRAM or more, you could run multiple builds concurrently for the same CL, but calling the build script multiple times with different `-strategy` options, taking advantage of the large vCPU count typically available on EC2 instances, as each build would typically consume between 1 to 8 vCPUs throughout the entire run of a given build.
+
+
+## About Encryption
+
+Developer RTL is encrypted using IEEE 1735 V2 encryption. This level of encryption protects both the raw source files and the implemented design.
+
+
+## Advanced Notes
+
+* The included implementation flow is a baseline flow. It is possible to add advanced commands/constraints (e.g, rejoining) to the flow.
+* Developers are free to modify the flow, but the final output must be a tar file with manifest.txt and the combined (AWS Shell + CL), encrypted, placed-and-routed design checkpoint,.
+
+
+# Frequently Asked Questions
+
+
+**Q: What are the different files that a developer needs to provide to AWS?**
+The developer should submit a tar file that contains the placed-and-routed DCP along with the required manifest.txt file.
+
+**Q: What should I do my design is not meeting timing?**
+The developer should evaluate the timing path to identify a solution that may include design changes or additional constraints. Additionally, the developer can try using one of the different build strategies that may help resolve the timing violations.
+
+**Q: My design was meeting timing, but even without changes, subsequent builds are not meeting timing?**
+This may happen due to various reasons. The developer should investigate the timing violation regardless of the lack of design changes. Additionally, the developer can try using one of the different build strategies that may help resolve the timing violations.
+
+**Q: "pr_verify" is complaining that the design checkpoints are incompatible. What should I do?**
+The developer can double-check that the AWS Shell DCP, SH_CL_BB_routed.dcp, was downloaded properly from the S3 bucket to the `hdk/common/shell_stable/build/checkpoints/from_aws` directory during the [hdk_setup.sh](../../../../../hdk_setup.sh) step and that there aren't errors in the build log.
+
+**Q: What version of Vivado do I need to use?**
+The valid version of Vivado is verified during the [hdk_setup.sh](../../../../../hdk_setup.sh) step.
+
diff --git a/cl_memdut/build/constraints/cl_pnr_user.xdc b/cl_memdut/build/constraints/cl_pnr_user.xdc
new file mode 100644
index 0000000..ae81f02
--- /dev/null
+++ b/cl_memdut/build/constraints/cl_pnr_user.xdc
@@ -0,0 +1,6 @@
+# This contains the CL specific constraints for Top level PNR
+
+# False paths between main clock and tck
+set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
+set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
+set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
diff --git a/cl_memdut/build/constraints/cl_synth_user.xdc b/cl_memdut/build/constraints/cl_synth_user.xdc
new file mode 100644
index 0000000..08b4712
--- /dev/null
+++ b/cl_memdut/build/constraints/cl_synth_user.xdc
@@ -0,0 +1,3 @@
+# This contains the CL specific constraints for synthesis at the CL level
+
+
diff --git a/cl_memdut/build/scripts/create_dcp_from_cl.tcl b/cl_memdut/build/scripts/create_dcp_from_cl.tcl
new file mode 100644
index 0000000..4bf22a2
--- /dev/null
+++ b/cl_memdut/build/scripts/create_dcp_from_cl.tcl
@@ -0,0 +1,367 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+package require tar
+
+## Do not edit $TOP
+set TOP top_sp
+
+## Replace with the name of your module
+set CL_MODULE cl_memdut
+
+#################################################
+## Command-line Arguments
+#################################################
+set timestamp [lindex $argv 0]
+set strategy [lindex $argv 1]
+set hdk_version [lindex $argv 2]
+set shell_version [lindex $argv 3]
+set device_id [lindex $argv 4]
+set vendor_id [lindex $argv 5]
+set subsystem_id [lindex $argv 6]
+set subsystem_vendor_id [lindex $argv 7]
+set clock_recipe_a [lindex $argv 8]
+set clock_recipe_b [lindex $argv 9]
+set clock_recipe_c [lindex $argv 10]
+set uram_option [lindex $argv 11]
+set notify_via_sns [lindex $argv 12]
+
+##################################################
+## Flow control variables
+##################################################
+set cl.synth 1
+set implement 1
+
+#################################################
+## Generate CL_routed.dcp (Done by User)
+#################################################
+puts "AWS FPGA Scripts";
+puts "Creating Design Checkpoint from Custom Logic source code";
+puts "HDK Version: $hdk_version";
+puts "Shell Version: $shell_version";
+puts "Vivado Script Name: $argv0";
+puts "Strategy: $strategy";
+puts "PCI Device ID $device_id";
+puts "PCI Vendor ID $vendor_id";
+puts "PCI Subsystem ID $subsystem_id";
+puts "PCI Subsystem Vendor ID $subsystem_vendor_id";
+puts "Clock Recipe A: $clock_recipe_a";
+puts "Clock Recipe B: $clock_recipe_b";
+puts "Clock Recipe C: $clock_recipe_c";
+puts "URAM option: $uram_option";
+puts "Notify when done: $notify_via_sns";
+
+#checking if CL_DIR env variable exists
+if { [info exists ::env(CL_DIR)] } {
+ set CL_DIR $::env(CL_DIR)
+ puts "Using CL directory $CL_DIR";
+} else {
+ puts "Error: CL_DIR environment variable not defined ! ";
+ puts "Use export CL_DIR=Your_Design_Root_Directory"
+ exit 2
+}
+
+#checking if HDK_SHELL_DIR env variable exists
+if { [info exists ::env(HDK_SHELL_DIR)] } {
+ set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
+ puts "Using Shell directory $HDK_SHELL_DIR";
+} else {
+ puts "Error: HDK_SHELL_DIR environment variable not defined ! ";
+ puts "Run the hdk_setup.sh script from the root directory of aws-fpga";
+ exit 2
+}
+
+#checking if HDK_SHELL_DESIGN_DIR env variable exists
+if { [info exists ::env(HDK_SHELL_DESIGN_DIR)] } {
+ set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
+ puts "Using Shell design directory $HDK_SHELL_DESIGN_DIR";
+} else {
+ puts "Error: HDK_SHELL_DESIGN_DIR environment variable not defined ! ";
+ puts "Run the hdk_setup.sh script from the root directory of aws-fpga";
+ exit 2
+}
+
+##################################################
+### Output Directories used by step_user.tcl
+##################################################
+set implDir $CL_DIR/build/checkpoints
+set rptDir $CL_DIR/build/reports
+set cacheDir $HDK_SHELL_DESIGN_DIR/cache/ddr4_phy
+
+puts "All reports and intermediate results will be time stamped with $timestamp";
+
+set_msg_config -id {Chipscope 16-3} -suppress
+set_msg_config -string {AXI_QUAD_SPI} -suppress
+
+# Suppress Warnings
+# These are to avoid warning messages that may not be real issues. A developer
+# may comment them out if they wish to see more information from warning
+# messages.
+set_msg_config -id {Common 17-55} -suppress
+set_msg_config -id {Designutils 20-1567} -suppress
+set_msg_config -id {IP_Flow 19-2162} -suppress
+set_msg_config -id {Project 1-498} -suppress
+set_msg_config -id {Route 35-328} -suppress
+set_msg_config -id {Vivado 12-508} -suppress
+set_msg_config -id {Constraints 18-4866} -suppress
+set_msg_config -id {filemgmt 56-12} -suppress
+set_msg_config -id {Constraints 18-4644} -suppress
+set_msg_config -id {Coretcl 2-64} -suppress
+set_msg_config -id {Vivado 12-4739} -suppress
+set_msg_config -id {Vivado 12-5201} -suppress
+set_msg_config -id {DRC CKLD-1} -suppress
+set_msg_config -id {IP_Flow 19-2248} -suppress
+set_msg_config -id {Opt 31-155} -suppress
+set_msg_config -id {Synth 8-115} -suppress
+set_msg_config -id {Synth 8-3936} -suppress
+set_msg_config -id {Vivado 12-1023} -suppress
+set_msg_config -id {Constraints 18-550} -suppress
+set_msg_config -id {Synth 8-3295} -suppress
+set_msg_config -id {Synth 8-3321} -suppress
+set_msg_config -id {Synth 8-3331} -suppress
+set_msg_config -id {Synth 8-3332} -suppress
+set_msg_config -id {Synth 8-350} -suppress
+set_msg_config -id {Synth 8-3848} -suppress
+set_msg_config -id {Synth 8-3917} -suppress
+set_msg_config -id {Synth 8-6014} -suppress
+set_msg_config -id {Vivado 12-1580} -suppress
+set_msg_config -id {Constraints 18-619} -suppress
+set_msg_config -id {DRC CKLD-2} -suppress
+set_msg_config -id {DRC REQP-1853} -suppress
+set_msg_config -id {Timing 38-436} -suppress
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
+
+# Check that an email address has been set, else unset notify_via_sns
+
+if {[string compare $notify_via_sns "1"] == 0} {
+ if {![info exists env(EMAIL)]} {
+ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL variable empty! Completition notification will *not* be sent!";
+ set notify_via_sns 0;
+ } else {
+ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL address for completion notification set to $env(EMAIL).";
+ }
+}
+
+##################################################
+### Strategy options
+##################################################
+switch $strategy {
+ "BASIC" {
+ puts "BASIC strategy."
+ source $HDK_SHELL_DIR/build/scripts/strategy_BASIC.tcl
+ }
+ "EXPLORE" {
+ puts "EXPLORE strategy."
+ source $HDK_SHELL_DIR/build/scripts/strategy_EXPLORE.tcl
+ }
+ "TIMING" {
+ puts "TIMING strategy."
+ source $HDK_SHELL_DIR/build/scripts/strategy_TIMING.tcl
+ }
+ "CONGESTION" {
+ puts "CONGESTION strategy."
+ source $HDK_SHELL_DIR/build/scripts/strategy_CONGESTION.tcl
+ }
+ "DEFAULT" {
+ puts "DEFAULT strategy."
+ source $HDK_SHELL_DIR/build/scripts/strategy_DEFAULT.tcl
+ }
+ default {
+ puts "$strategy is NOT a valid strategy. Defaulting to strategy DEFAULT."
+ source $HDK_SHELL_DIR/build/scripts/strategy_DEFAULT.tcl
+ }
+}
+
+#Encrypt source code
+source encrypt.tcl
+
+#Set the Device Type
+source $HDK_SHELL_DIR/build/scripts/device_type.tcl
+
+#Procedure for running various implementation steps (impl_step)
+source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
+
+########################################
+## Generate clocks based on Recipe
+########################################
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
+
+source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
+
+##################################################
+### CL XPR OOC Synthesis
+##################################################
+if {${cl.synth}} {
+ source -notrace ./synth_${CL_MODULE}.tcl
+}
+
+##################################################
+### Implementation
+##################################################
+if {$implement} {
+
+ ########################
+ # Link Design
+ ########################
+ if {$link} {
+ ####Create in-memory prjoect and setup IP cache location
+ create_project -part [DEVICE_TYPE] -in_memory
+ set_property IP_REPO_PATHS $cacheDir [current_project]
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Combining Shell and CL design checkpoints";
+ add_files $HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp
+ add_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
+ set_property SCOPED_TO_CELLS {CL} [get_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp]
+
+ #Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)
+ read_xdc [ list \
+ $CL_DIR/build/constraints/cl_pnr_user.xdc
+ ]
+ set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]
+
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running link_design";
+ link_design -top $TOP -part [DEVICE_TYPE] -reconfig_partitions {SH CL}
+
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - PLATFORM.IMPL==[get_property PLATFORM.IMPL [current_design]]";
+ ##################################################
+ # Apply Clock Properties for Clock Table Recipes
+ ##################################################
+ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
+
+ # Apply properties to clocks
+ source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
+
+ # Write post-link checkpoint
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Writing post-link_design checkpoint ${timestamp}.post_link.dcp";
+ write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.post_link.dcp
+ }
+
+ ########################
+ # CL Optimize
+ ########################
+ if {$opt} {
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running optimization";
+ impl_step opt_design $TOP $opt_options $opt_directive $opt_preHookTcl $opt_postHookTcl
+ if {$psip} {
+ impl_step opt_design $TOP "-merge_equivalent_drivers -sweep"
+ }
+ }
+
+ ########################
+ # CL Place
+ ########################
+ if {$place} {
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running placement";
+ if {$psip} {
+ append place_options " -fanout_opt"
+ }
+ impl_step place_design $TOP $place_options $place_directive $place_preHookTcl $place_postHookTcl
+ }
+
+ ##############################
+ # CL Post-Place Optimization
+ ##############################
+ if {$phys_opt} {
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-place optimization";
+ impl_step phys_opt_design $TOP $phys_options $phys_directive $phys_preHookTcl $phys_postHookTcl
+ }
+
+ ########################
+ # CL Route
+ ########################
+ if {$route} {
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Routing design";
+ impl_step route_design $TOP $route_options $route_directive $route_preHookTcl $route_postHookTcl
+ }
+
+ ##############################
+ # CL Post-Route Optimization
+ ##############################
+ set SLACK [get_property SLACK [get_timing_paths]]
+ #Post-route phys_opt will not be run if slack is positive or greater than -200ps.
+ if {$route_phys_opt && $SLACK > -0.400 && $SLACK < 0} {
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-route optimization";
+ impl_step route_phys_opt_design $TOP $post_phys_options $post_phys_directive $post_phys_preHookTcl $post_phys_postHookTcl
+ }
+
+ ##############################
+ # Final Implmentation Steps
+ ##############################
+ # Report final timing
+ report_timing_summary -file $CL_DIR/build/reports/${timestamp}.SH_CL_final_timing_summary.rpt
+
+ # This is what will deliver to AWS
+ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Writing final DCP to to_aws directory.";
+
+ write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
+
+ # Generate debug probes file
+ write_debug_probes -force -no_partial_ltxfile -file $CL_DIR/build/checkpoints/${timestamp}.debug_probes.ltx
+
+ close_project
+}
+
+# ################################################
+# Create Manifest and Tarball for delivery
+# ################################################
+
+# Create a zipped tar file, that would be used for createFpgaImage EC2 API
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Compress files for sending to AWS. "
+
+# Create manifest file
+set manifest_file [open "$CL_DIR/build/checkpoints/to_aws/${timestamp}.manifest.txt" w]
+set hash [lindex [split [exec sha256sum $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp] ] 0]
+
+puts $manifest_file "manifest_format_version=1\n"
+puts $manifest_file "pci_vendor_id=$vendor_id\n"
+puts $manifest_file "pci_device_id=$device_id\n"
+puts $manifest_file "pci_subsystem_id=$subsystem_id\n"
+puts $manifest_file "pci_subsystem_vendor_id=$subsystem_vendor_id\n"
+puts $manifest_file "dcp_hash=$hash\n"
+puts $manifest_file "shell_version=$shell_version\n"
+puts $manifest_file "dcp_file_name=${timestamp}.SH_CL_routed.dcp\n"
+puts $manifest_file "hdk_version=$hdk_version\n"
+puts $manifest_file "date=$timestamp\n"
+puts $manifest_file "clock_recipe_a=$clock_recipe_a\n"
+puts $manifest_file "clock_recipe_b=$clock_recipe_b\n"
+puts $manifest_file "clock_recipe_c=$clock_recipe_c\n"
+
+close $manifest_file
+
+# Delete old tar file with same name
+if { [file exists $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar] } {
+ puts "Deleting old tar file with same name.";
+ file delete -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar
+}
+
+# Tar checkpoint to aws
+cd $CL_DIR/build/checkpoints
+tar::create to_aws/${timestamp}.Developer_CL.tar [glob to_aws/${timestamp}*]
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Finished creating final tar file in to_aws directory.";
+
+if {[string compare $notify_via_sns "1"] == 0} {
+ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Calling notification script to send e-mail to $env(EMAIL)";
+ exec $env(HDK_COMMON_DIR)/scripts/notify_via_sns.py
+}
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
+
+
diff --git a/cl_memdut/build/scripts/encrypt.tcl b/cl_memdut/build/scripts/encrypt.tcl
new file mode 100644
index 0000000..4287fc6
--- /dev/null
+++ b/cl_memdut/build/scripts/encrypt.tcl
@@ -0,0 +1,81 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+# TODO:
+# Add check if CL_DIR and HDK_SHELL_DIR directories exist
+# Add check if /build and /build/src_port_encryption directories exist
+# Add check if the vivado_keyfile exist
+
+set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
+set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
+set CL_DIR $::env(CL_DIR)
+
+set TARGET_DIR $CL_DIR/build/src_post_encryption
+set UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces
+
+
+# Remove any previously encrypted files, that may no longer be used
+exec rm -rf $TARGET_DIR/*
+
+#---- Developr would replace this section with design files ----
+
+## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files.
+file copy -force $CL_DIR/design/cl_memdut_defines.vh $TARGET_DIR
+file copy -force $CL_DIR/design/cl_id_defines.vh $TARGET_DIR
+file copy -force $CL_DIR/design/cl_memdut_pkg.sv $TARGET_DIR
+file copy -force $CL_DIR/design/cl_memdut_wrap.sv $TARGET_DIR
+file copy -force $CL_DIR/design/cl_memdut.sv $TARGET_DIR
+file copy -force $CL_DIR/design/axil_slave.sv $TARGET_DIR
+file copy -force $CL_DIR/design/cl_dma_pcis_slv.sv $TARGET_DIR
+file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut.v $TARGET_DIR
+file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_apb_slave.v $TARGET_DIR
+file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_256_256.v $TARGET_DIR
+file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_256.v $TARGET_DIR
+file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256.v $TARGET_DIR
+file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_resp_256.v $TARGET_DIR
+file copy -force $CL_DIR/design/simple_dut/nv_ram_rws_256x128.v $TARGET_DIR
+file copy -force $CL_DIR/design/simple_dut/nv_ram_rws_256x27.v $TARGET_DIR
+file copy -force $CL_DIR/design/simple_dut/nv_ram_rws_512x256.v $TARGET_DIR
+file copy -force $CL_DIR/design/simple_dut/nv_ram_rws_512x32.v $TARGET_DIR
+file copy -force $CL_DIR/../common/design/transactors/cfg/cl_cfgreg.sv $TARGET_DIR
+file copy -force $CL_DIR/../common/design/transactors/irq/cl_irq_up.v $TARGET_DIR
+file copy -force $CL_DIR/../common/design/transactors/irq/cl_irq_up_bit.v $TARGET_DIR
+file copy -force $CL_DIR/../common/design/transactors/irq/simulate_x_tick.vh $TARGET_DIR
+file copy -force $CL_DIR/../common/design/vlibs/NV_CLK_gate_power.v $TARGET_DIR
+file copy -force $CL_DIR/../common/design/vlibs/p_SSYNC2DO_C_PP.v $TARGET_DIR
+file copy -force $CL_DIR/../common/design/vlibs/p_SSYNC3DO_C_PPP.v $TARGET_DIR
+file copy -force $CL_DIR/../common/design/vlibs/sync2d_c_pp.v $TARGET_DIR
+file copy -force $CL_DIR/../common/design/vlibs/sync3d_c_ppp.v $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_cl_sda_template.inc $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_pcim_template.inc $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_a_b_d_template.inc $TARGET_DIR
+
+#---- End of section replaced by Developr ---
+
+
+
+# Make sure files have write permissions for the encryption
+
+exec chmod +w {*}[glob $TARGET_DIR/*]
+
+# encrypt .v/.sv/.vh/inc as verilog files
+encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
+
+# encrypt *vhdl files
+encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ]
+
diff --git a/cl_memdut/build/scripts/synth_cl_memdut.tcl b/cl_memdut/build/scripts/synth_cl_memdut.tcl
new file mode 100644
index 0000000..d57b431
--- /dev/null
+++ b/cl_memdut/build/scripts/synth_cl_memdut.tcl
@@ -0,0 +1,137 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+#Param needed to avoid clock name collisions
+set_param sta.enableAutoGenClkNamePersistence 0
+set CL_MODULE $CL_MODULE
+
+create_project -in_memory -part [DEVICE_TYPE] -force
+
+########################################
+## Generate clocks based on Recipe
+########################################
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
+
+source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
+
+#############################
+## Read design files
+#############################
+
+#Convenience to set the root of the RTL directory
+set ENC_SRC_DIR $CL_DIR/build/src_post_encryption
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's Custom Logic files post encryption.";
+
+#---- User would replace this section -----
+
+# Reading the .sv and .v files, as proper designs would not require
+# reading .v, .vh, nor .inc files
+
+read_verilog -v [glob $ENC_SRC_DIR/*.v]
+read_verilog -sv [glob $ENC_SRC_DIR/*.?v]
+
+#---- End of section replaced by User ----
+
+puts "AWS FPGA: Reading AWS Shell design";
+
+#Read AWS Design files
+read_verilog [ list \
+ $HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
+ $HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \
+ $HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_acc_axl.sv \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_gen_axl.sv \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sh_ddr.sv \
+ $HDK_SHELL_DESIGN_DIR/interfaces/cl_ports.vh
+]
+
+puts "AWS FPGA: Reading IP blocks";
+
+#Read DDR IP
+read_ip [ list \
+ $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci
+]
+
+#Read IP for axi register slices
+read_ip [ list \
+ $HDK_SHELL_DESIGN_DIR/ip/src_register_slice/src_register_slice.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/dest_register_slice/dest_register_slice.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/axi_clock_converter_0/axi_clock_converter_0.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/axi_register_slice/axi_register_slice.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/axi_register_slice_light/axi_register_slice_light.xci
+]
+
+#Read IP for virtual jtag / ILA/VIO
+read_ip [ list \
+ $HDK_SHELL_DESIGN_DIR/ip/cl_debug_bridge/cl_debug_bridge.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/ila_1/ila_1.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/ila_vio_counter/ila_vio_counter.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/vio_0/vio_0.xci
+]
+
+# Additional IP's that might be needed if using the DDR
+read_ip [ list \
+ $CL_DIR/../common/design/xilinx_ip/axi_interconnect_nvdla_256b/axi_interconnect_nvdla_256b.xci \
+ $CL_DIR/../common/design/xilinx_ip/axi_apb_bridge_0/axi_apb_bridge_0.xci \
+ $CL_DIR/../common/design/xilinx_ip/xilinx_subtracter_0/xilinx_subtracter_0.xci
+]
+
+puts "AWS FPGA: Reading AWS constraints";
+
+#Read all the constraints
+#
+# cl_clocks_aws.xdc - AWS auto-generated clock constraint. ***DO NOT MODIFY***
+# cl_ddr.xdc - AWS provided DDR pin constraints. ***DO NOT MODIFY***
+# cl_synth_user.xdc - Developer synthesis constraints.
+read_xdc [ list \
+ $CL_DIR/build/constraints/cl_clocks_aws.xdc \
+ $HDK_SHELL_DIR/build/constraints/cl_ddr.xdc \
+ $HDK_SHELL_DIR/build/constraints/cl_synth_aws.xdc \
+ $CL_DIR/build/constraints/cl_synth_user.xdc
+]
+
+#Do not propagate local clock constraints for clocks generated in the SH
+set_property USED_IN {synthesis implementation OUT_OF_CONTEXT} [get_files cl_clocks_aws.xdc]
+set_property PROCESSING_ORDER EARLY [get_files cl_clocks_aws.xdc]
+
+########################
+# CL Synthesis
+########################
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthesis.";
+
+update_compile_order -fileset sources_1
+puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
+eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -verilog_define DESIGNWARE_NOEXIST -verilog_define SYNTHESIS -verilog_define FPGA -verilog_define NV_FPGA_FIFOGEN -verilog_define NV_FPGA_RAMS -verilog_define NV_FPGA_LIBS -verilog_define VLIB_BYPASS_POWER_CG -verilog_define DISABLE_VJTAG_DEBUG -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
+
+set failval [catch {exec grep "FAIL" failfast.csv}]
+if { $failval==0 } {
+ puts "AWS FPGA: FATAL ERROR--Resource utilization error; check failfast.csv for details"
+ exit 1
+}
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing post synth checkpoint.";
+write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
+
+close_project
+#Set param back to default value
+set_param sta.enableAutoGenClkNamePersistence 1
diff --git a/cl_memdut/design/axil_slave.sv b/cl_memdut/design/axil_slave.sv
new file mode 100644
index 0000000..b056ff5
--- /dev/null
+++ b/cl_memdut/design/axil_slave.sv
@@ -0,0 +1,153 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+module axil_slave (
+ input clk,
+ input rst_n,
+
+ input awvalid,
+ input[63:0] awaddr,
+ output logic awready,
+
+ //Write data
+ input wvalid,
+ input[31:0] wdata,
+ input[3:0] wstrb,
+ output logic wready,
+
+ //Write response
+ output logic bvalid,
+ output logic[1:0] bresp,
+ input bready,
+
+ //Read address
+ input arvalid,
+ input[63:0] araddr,
+ output logic arready,
+
+ //Read data/response
+ output logic rvalid,
+ output logic[31:0] rdata,
+ output logic[1:0] rresp,
+
+ input rready
+);
+
+logic[63:0] awaddr_q;
+logic arvalid_q;
+
+// Does not work when awvalid and wvalid are asserted at the same time
+//assign awready = !wvalid;
+//assign wready = !arvalid;
+//
+//always_ff @(negedge rst_n or posedge clk)
+// if (!rst_n)
+// awaddr_q <= 0;
+// else if (awvalid && awready)
+// awaddr_q <= awaddr;
+//
+//always_ff @(negedge rst_n or posedge clk)
+// if (!rst_n)
+// begin
+// bvalid <= 0;
+// bresp <= 0;
+// end
+// else
+// begin
+// bvalid <= wvalid && wready;
+// bresp <= 0;
+// end
+
+
+ logic wr_active;
+ logic [63:0] wr_addr;
+
+ always_ff @(negedge rst_n or posedge clk)
+ if (!rst_n) begin
+ wr_active <= 0;
+ wr_addr <= 0;
+ end
+ else begin
+ wr_active <= wr_active && bvalid && bready ? 1'b0 :
+ awvalid && ~wr_active ? 1'b1 :
+ wr_active;
+ wr_addr <= awvalid && ~wr_active ? awaddr : wr_addr;
+ end
+
+ assign awready = ~wr_active;
+ assign wready = wr_active && wvalid;
+
+ always_ff @(negedge rst_n or posedge clk)
+ if (!rst_n)
+ bvalid <= 0;
+ else
+ bvalid <= bvalid && bready ? 1'b0 :
+ ~bvalid && wready ? 1'b1 :
+ bvalid;
+ assign bresp = 0;
+
+assign arready = !arvalid_q && !rvalid;
+
+always_ff @(negedge rst_n or posedge clk)
+ if (!rst_n)
+ arvalid_q <= 0;
+ else
+ arvalid_q <= arvalid;
+
+logic[31:0] ram_rdata;
+
+always_ff @(negedge rst_n or posedge clk)
+ if (!rst_n)
+ begin
+ rvalid <= 0;
+ rdata <= 0;
+ rresp <= 0;
+ end
+ else if (rvalid && rready)
+ begin
+ rvalid <= 0;
+ rdata <= 0;
+ rresp <= 0;
+ end
+ else if (arvalid_q)
+ begin
+ rvalid <= 1;
+ rdata <= ram_rdata;
+ rresp <= 0;
+ end
+
+bram_2rw #(.WIDTH(32), .ADDR_WIDTH(8), .DEPTH(256) ) AXIL_RAM (
+ .clk(clk),
+// .wea(wvalid),
+// .ena(wvalid),
+// .addra(awaddr_q[10:2]),
+// .da(wdata),
+ .wea(wready),
+ .ena(wready),
+ .addra(wr_addr[9:2]),
+ .da(wdata),
+
+ .qa(),
+
+ .web(1'b0),
+ .enb(arvalid),
+ .addrb(araddr[9:2]),
+ .db(32'h0),
+ .qb(ram_rdata)
+ );
+
+endmodule
+
+
diff --git a/cl_memdut/design/cl_dma_pcis_slv.sv b/cl_memdut/design/cl_dma_pcis_slv.sv
new file mode 100644
index 0000000..6064d53
--- /dev/null
+++ b/cl_memdut/design/cl_dma_pcis_slv.sv
@@ -0,0 +1,661 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+module cl_dma_pcis_slv #(parameter SCRB_MAX_ADDR = 64'h3FFFFFFFF, parameter SCRB_BURST_LEN_MINUS1 = 15, parameter NO_SCRB_INST = 1)
+
+(
+ input aclk,
+ input aresetn,
+
+ axi_bus_t.master sh_cl_dma_pcis_bus,
+ axi_bus_t.master nvdla_dbb_axi_bus,
+ axi_bus_t.master nvdla_cvsram_axi_bus,
+
+ axi_bus_t sh_cl_dma_pcis_q,
+
+ axi_bus_t.slave cl_sh_ddr_bus
+
+
+);
+localparam NUM_CFG_STGS_CL_DDR_ATG = 4;
+localparam NUM_CFG_STGS_SH_DDR_ATG = 4;
+
+//----------------------------
+// Internal signals
+//----------------------------
+axi_bus_t cl_sh_ddr_q();
+axi_bus_t cl_sh_ddr_q2();
+axi_bus_t sh_cl_pcis();
+
+//----------------------------
+// End Internal signals
+//----------------------------
+
+
+//reset synchronizers
+(* dont_touch = "true" *) logic slr0_sync_aresetn;
+(* dont_touch = "true" *) logic slr1_sync_aresetn;
+(* dont_touch = "true" *) logic slr2_sync_aresetn;
+lib_pipe #(.WIDTH(1), .STAGES(4)) SLR0_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in_bus(aresetn), .out_bus(slr0_sync_aresetn));
+lib_pipe #(.WIDTH(1), .STAGES(4)) SLR1_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in_bus(aresetn), .out_bus(slr1_sync_aresetn));
+lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in_bus(aresetn), .out_bus(slr2_sync_aresetn));
+
+//----------------------------
+// flop the dma_pcis interface input of CL
+//----------------------------
+
+ // AXI4 Register Slice for dma_pcis interface
+ axi_register_slice PCI_AXL_REG_SLC (
+ .aclk (aclk),
+ .aresetn (slr0_sync_aresetn),
+ .s_axi_awid (sh_cl_dma_pcis_bus.awid),
+ .s_axi_awaddr (sh_cl_dma_pcis_bus.awaddr),
+ .s_axi_awlen (sh_cl_dma_pcis_bus.awlen),
+ .s_axi_awvalid (sh_cl_dma_pcis_bus.awvalid),
+ .s_axi_awsize (sh_cl_dma_pcis_bus.awsize),
+ .s_axi_awready (sh_cl_dma_pcis_bus.awready),
+ .s_axi_wdata (sh_cl_dma_pcis_bus.wdata),
+ .s_axi_wstrb (sh_cl_dma_pcis_bus.wstrb),
+ .s_axi_wlast (sh_cl_dma_pcis_bus.wlast),
+ .s_axi_wvalid (sh_cl_dma_pcis_bus.wvalid),
+ .s_axi_wready (sh_cl_dma_pcis_bus.wready),
+ .s_axi_bid (sh_cl_dma_pcis_bus.bid),
+ .s_axi_bresp (sh_cl_dma_pcis_bus.bresp),
+ .s_axi_bvalid (sh_cl_dma_pcis_bus.bvalid),
+ .s_axi_bready (sh_cl_dma_pcis_bus.bready),
+ .s_axi_arid (sh_cl_dma_pcis_bus.arid),
+ .s_axi_araddr (sh_cl_dma_pcis_bus.araddr),
+ .s_axi_arlen (sh_cl_dma_pcis_bus.arlen),
+ .s_axi_arvalid (sh_cl_dma_pcis_bus.arvalid),
+ .s_axi_arsize (sh_cl_dma_pcis_bus.arsize),
+ .s_axi_arready (sh_cl_dma_pcis_bus.arready),
+ .s_axi_rid (sh_cl_dma_pcis_bus.rid),
+ .s_axi_rdata (sh_cl_dma_pcis_bus.rdata),
+ .s_axi_rresp (sh_cl_dma_pcis_bus.rresp),
+ .s_axi_rlast (sh_cl_dma_pcis_bus.rlast),
+ .s_axi_rvalid (sh_cl_dma_pcis_bus.rvalid),
+ .s_axi_rready (sh_cl_dma_pcis_bus.rready),
+
+ .m_axi_awid (sh_cl_dma_pcis_q.awid),
+ .m_axi_awaddr (sh_cl_dma_pcis_q.awaddr),
+ .m_axi_awlen (sh_cl_dma_pcis_q.awlen),
+ .m_axi_awvalid (sh_cl_dma_pcis_q.awvalid),
+ .m_axi_awsize (sh_cl_dma_pcis_q.awsize),
+ .m_axi_awready (sh_cl_dma_pcis_q.awready),
+ .m_axi_wdata (sh_cl_dma_pcis_q.wdata),
+ .m_axi_wstrb (sh_cl_dma_pcis_q.wstrb),
+ .m_axi_wvalid (sh_cl_dma_pcis_q.wvalid),
+ .m_axi_wlast (sh_cl_dma_pcis_q.wlast),
+ .m_axi_wready (sh_cl_dma_pcis_q.wready),
+ .m_axi_bresp (sh_cl_dma_pcis_q.bresp),
+ .m_axi_bvalid (sh_cl_dma_pcis_q.bvalid),
+ .m_axi_bid (sh_cl_dma_pcis_q.bid),
+ .m_axi_bready (sh_cl_dma_pcis_q.bready),
+ .m_axi_arid (sh_cl_dma_pcis_q.arid),
+ .m_axi_araddr (sh_cl_dma_pcis_q.araddr),
+ .m_axi_arlen (sh_cl_dma_pcis_q.arlen),
+ .m_axi_arsize (sh_cl_dma_pcis_q.arsize),
+ .m_axi_arvalid (sh_cl_dma_pcis_q.arvalid),
+ .m_axi_arready (sh_cl_dma_pcis_q.arready),
+ .m_axi_rid (sh_cl_dma_pcis_q.rid),
+ .m_axi_rdata (sh_cl_dma_pcis_q.rdata),
+ .m_axi_rresp (sh_cl_dma_pcis_q.rresp),
+ .m_axi_rlast (sh_cl_dma_pcis_q.rlast),
+ .m_axi_rvalid (sh_cl_dma_pcis_q.rvalid),
+ .m_axi_rready (sh_cl_dma_pcis_q.rready)
+ );
+
+
+//----------------------------
+// axi interconnect for DDR address decodes
+//----------------------------
+(* dont_touch = "true" *) axi_interconnect_nvdla_256b AXI_INTERCONNECT (
+ .INTERCONNECT_ACLK (aclk)
+ ,.INTERCONNECT_ARESETN (slr1_sync_aresetn)
+ ,.S00_AXI_ARESET_OUT_N ()
+ ,.S00_AXI_ACLK (aclk)
+ ,.S00_AXI_AWID ({2'b0, sh_cl_dma_pcis_q.awid[5:0]})
+ ,.S00_AXI_AWADDR ({sh_cl_dma_pcis_q.awaddr[63:37], 1'b0, sh_cl_dma_pcis_q.awaddr[35:0]})
+ ,.S00_AXI_AWLEN (sh_cl_dma_pcis_q.awlen)
+ ,.S00_AXI_AWSIZE (sh_cl_dma_pcis_q.awsize)
+ ,.S00_AXI_AWBURST (2'b01)
+ ,.S00_AXI_AWLOCK (1'b0)
+ ,.S00_AXI_AWCACHE (4'b11)
+ ,.S00_AXI_AWPROT (3'b010)
+ ,.S00_AXI_AWQOS (4'b0)
+ ,.S00_AXI_AWVALID (sh_cl_dma_pcis_q.awvalid)
+ ,.S00_AXI_AWREADY (sh_cl_dma_pcis_q.awready)
+ ,.S00_AXI_WDATA (sh_cl_dma_pcis_q.wdata)
+ ,.S00_AXI_WSTRB (sh_cl_dma_pcis_q.wstrb)
+ ,.S00_AXI_WLAST (sh_cl_dma_pcis_q.wlast)
+ ,.S00_AXI_WVALID (sh_cl_dma_pcis_q.wvalid)
+ ,.S00_AXI_WREADY (sh_cl_dma_pcis_q.wready)
+ ,.S00_AXI_BID (sh_cl_dma_pcis_q.bid[5:0])
+ ,.S00_AXI_BRESP (sh_cl_dma_pcis_q.bresp)
+ ,.S00_AXI_BVALID (sh_cl_dma_pcis_q.bvalid)
+ ,.S00_AXI_BREADY (sh_cl_dma_pcis_q.bready)
+ ,.S00_AXI_ARID ({2'b0, sh_cl_dma_pcis_q.arid[5:0]})
+ ,.S00_AXI_ARADDR (sh_cl_dma_pcis_q.araddr)
+ ,.S00_AXI_ARLEN (sh_cl_dma_pcis_q.arlen)
+ ,.S00_AXI_ARSIZE (sh_cl_dma_pcis_q.arsize)
+ ,.S00_AXI_ARBURST (2'b01)
+ ,.S00_AXI_ARLOCK (1'b0)
+ ,.S00_AXI_ARCACHE (4'b11)
+ ,.S00_AXI_ARPROT (3'b010)
+ ,.S00_AXI_ARQOS (4'b0)
+ ,.S00_AXI_ARVALID (sh_cl_dma_pcis_q.arvalid)
+ ,.S00_AXI_ARREADY (sh_cl_dma_pcis_q.arready)
+ ,.S00_AXI_RID (sh_cl_dma_pcis_q.rid[5:0])
+ ,.S00_AXI_RDATA (sh_cl_dma_pcis_q.rdata)
+ ,.S00_AXI_RRESP (sh_cl_dma_pcis_q.rresp)
+ ,.S00_AXI_RLAST (sh_cl_dma_pcis_q.rlast)
+ ,.S00_AXI_RVALID (sh_cl_dma_pcis_q.rvalid)
+ ,.S00_AXI_RREADY (sh_cl_dma_pcis_q.rready)
+ ,.S01_AXI_ARESET_OUT_N ()
+ ,.S01_AXI_ACLK (aclk)
+ ,.S01_AXI_AWID (nvdla_dbb_axi_bus.awid)
+ ,.S01_AXI_AWADDR ({24'b0, nvdla_dbb_axi_bus.awaddr})
+ ,.S01_AXI_AWLEN ({4'b0, nvdla_dbb_axi_bus.awlen})
+ ,.S01_AXI_AWSIZE (nvdla_dbb_axi_bus.awsize)
+ ,.S01_AXI_AWBURST (2'b01)
+ ,.S01_AXI_AWLOCK (1'b0)
+ ,.S01_AXI_AWCACHE (4'b11)
+ ,.S01_AXI_AWPROT (3'b010)
+ ,.S01_AXI_AWQOS (4'b0)
+ ,.S01_AXI_AWVALID (nvdla_dbb_axi_bus.awvalid)
+ ,.S01_AXI_AWREADY (nvdla_dbb_axi_bus.awready)
+ ,.S01_AXI_WDATA (nvdla_dbb_axi_bus.wdata)
+ ,.S01_AXI_WSTRB (nvdla_dbb_axi_bus.wstrb)
+ ,.S01_AXI_WLAST (nvdla_dbb_axi_bus.wlast)
+ ,.S01_AXI_WVALID (nvdla_dbb_axi_bus.wvalid)
+ ,.S01_AXI_WREADY (nvdla_dbb_axi_bus.wready)
+ ,.S01_AXI_BID (nvdla_dbb_axi_bus.bid)
+ ,.S01_AXI_BRESP (nvdla_dbb_axi_bus.bresp)
+ ,.S01_AXI_BVALID (nvdla_dbb_axi_bus.bvalid)
+ ,.S01_AXI_BREADY (nvdla_dbb_axi_bus.bready)
+ ,.S01_AXI_ARID (nvdla_dbb_axi_bus.arid)
+ ,.S01_AXI_ARADDR ({24'b0, nvdla_dbb_axi_bus.araddr})
+ ,.S01_AXI_ARLEN ({4'b0, nvdla_dbb_axi_bus.arlen})
+ ,.S01_AXI_ARSIZE (nvdla_dbb_axi_bus.arsize)
+ ,.S01_AXI_ARBURST (2'b01)
+ ,.S01_AXI_ARLOCK (1'b0)
+ ,.S01_AXI_ARCACHE (4'b11)
+ ,.S01_AXI_ARPROT (3'b10)
+ ,.S01_AXI_ARQOS (4'b0)
+ ,.S01_AXI_ARVALID (nvdla_dbb_axi_bus.arvalid)
+ ,.S01_AXI_ARREADY (nvdla_dbb_axi_bus.arready)
+ ,.S01_AXI_RID (nvdla_dbb_axi_bus.rid)
+ ,.S01_AXI_RDATA (nvdla_dbb_axi_bus.rdata)
+ ,.S01_AXI_RRESP (nvdla_dbb_axi_bus.rresp)
+ ,.S01_AXI_RLAST (nvdla_dbb_axi_bus.rlast)
+ ,.S01_AXI_RVALID (nvdla_dbb_axi_bus.rvalid)
+ ,.S01_AXI_RREADY (nvdla_dbb_axi_bus.rready)
+ ,.S02_AXI_ARESET_OUT_N ()
+ ,.S02_AXI_ACLK (aclk)
+ ,.S02_AXI_AWID (nvdla_cvsram_axi_bus.awid)
+ ,.S02_AXI_AWADDR ({24'b0, nvdla_cvsram_axi_bus.awaddr})
+ ,.S02_AXI_AWLEN ({4'b0, nvdla_cvsram_axi_bus.awlen})
+ ,.S02_AXI_AWSIZE (nvdla_cvsram_axi_bus.awsize)
+ ,.S02_AXI_AWBURST (2'b01)
+ ,.S02_AXI_AWLOCK (1'b0)
+ ,.S02_AXI_AWCACHE (4'b11)
+ ,.S02_AXI_AWPROT (3'b10)
+ ,.S02_AXI_AWQOS (4'b0)
+ ,.S02_AXI_AWVALID (nvdla_cvsram_axi_bus.awvalid)
+ ,.S02_AXI_AWREADY (nvdla_cvsram_axi_bus.awready)
+ ,.S02_AXI_WDATA (nvdla_cvsram_axi_bus.wdata)
+ ,.S02_AXI_WSTRB (nvdla_cvsram_axi_bus.wstrb)
+ ,.S02_AXI_WLAST (nvdla_cvsram_axi_bus.wlast)
+ ,.S02_AXI_WVALID (nvdla_cvsram_axi_bus.wvalid)
+ ,.S02_AXI_WREADY (nvdla_cvsram_axi_bus.wready)
+ ,.S02_AXI_BID (nvdla_cvsram_axi_bus.bid)
+ ,.S02_AXI_BRESP (nvdla_cvsram_axi_bus.bresp)
+ ,.S02_AXI_BVALID (nvdla_cvsram_axi_bus.bvalid)
+ ,.S02_AXI_BREADY (nvdla_cvsram_axi_bus.bready)
+ ,.S02_AXI_ARID (nvdla_cvsram_axi_bus.arid)
+ ,.S02_AXI_ARADDR ({24'b0, nvdla_cvsram_axi_bus.araddr})
+ ,.S02_AXI_ARLEN ({4'b0, nvdla_cvsram_axi_bus.arlen})
+ ,.S02_AXI_ARSIZE (nvdla_cvsram_axi_bus.arsize)
+ ,.S02_AXI_ARBURST (2'b01)
+ ,.S02_AXI_ARLOCK (1'b0)
+ ,.S02_AXI_ARCACHE (4'b11)
+ ,.S02_AXI_ARPROT (3'b10)
+ ,.S02_AXI_ARQOS (4'b0)
+ ,.S02_AXI_ARVALID (nvdla_cvsram_axi_bus.arvalid)
+ ,.S02_AXI_ARREADY (nvdla_cvsram_axi_bus.arready)
+ ,.S02_AXI_RID (nvdla_cvsram_axi_bus.rid)
+ ,.S02_AXI_RDATA (nvdla_cvsram_axi_bus.rdata)
+ ,.S02_AXI_RRESP (nvdla_cvsram_axi_bus.rresp)
+ ,.S02_AXI_RLAST (nvdla_cvsram_axi_bus.rlast)
+ ,.S02_AXI_RVALID (nvdla_cvsram_axi_bus.rvalid)
+ ,.S02_AXI_RREADY (nvdla_cvsram_axi_bus.rready)
+ ,.M00_AXI_ARESET_OUT_N ()
+ ,.M00_AXI_ACLK (aclk)
+ ,.M00_AXI_AWID (cl_sh_ddr_q.awid[11:0])
+ ,.M00_AXI_AWADDR (cl_sh_ddr_q.awaddr)
+ ,.M00_AXI_AWLEN (cl_sh_ddr_q.awlen)
+ ,.M00_AXI_AWSIZE (cl_sh_ddr_q.awsize)
+ ,.M00_AXI_AWBURST ()
+ ,.M00_AXI_AWLOCK ()
+ ,.M00_AXI_AWCACHE ()
+ ,.M00_AXI_AWPROT ()
+ ,.M00_AXI_AWQOS ()
+ ,.M00_AXI_AWVALID (cl_sh_ddr_q.awvalid)
+ ,.M00_AXI_AWREADY (cl_sh_ddr_q.awready)
+ ,.M00_AXI_WDATA (cl_sh_ddr_q.wdata)
+ ,.M00_AXI_WSTRB (cl_sh_ddr_q.wstrb)
+ ,.M00_AXI_WLAST (cl_sh_ddr_q.wlast)
+ ,.M00_AXI_WVALID (cl_sh_ddr_q.wvalid)
+ ,.M00_AXI_WREADY (cl_sh_ddr_q.wready)
+ ,.M00_AXI_BID (cl_sh_ddr_q.bid[11:0])
+ ,.M00_AXI_BRESP (cl_sh_ddr_q.bresp)
+ ,.M00_AXI_BVALID (cl_sh_ddr_q.bvalid)
+ ,.M00_AXI_BREADY (cl_sh_ddr_q.bready)
+ ,.M00_AXI_ARID (cl_sh_ddr_q.arid[11:0])
+ ,.M00_AXI_ARADDR (cl_sh_ddr_q.araddr)
+ ,.M00_AXI_ARLEN (cl_sh_ddr_q.arlen)
+ ,.M00_AXI_ARSIZE (cl_sh_ddr_q.arsize)
+ ,.M00_AXI_ARBURST ()
+ ,.M00_AXI_ARLOCK ()
+ ,.M00_AXI_ARCACHE ()
+ ,.M00_AXI_ARPROT ()
+ ,.M00_AXI_ARQOS ()
+ ,.M00_AXI_ARVALID (cl_sh_ddr_q.arvalid)
+ ,.M00_AXI_ARREADY (cl_sh_ddr_q.arready)
+ ,.M00_AXI_RID (cl_sh_ddr_q.rid[11:0])
+ ,.M00_AXI_RDATA (cl_sh_ddr_q.rdata)
+ ,.M00_AXI_RRESP (cl_sh_ddr_q.rresp)
+ ,.M00_AXI_RLAST (cl_sh_ddr_q.rlast)
+ ,.M00_AXI_RVALID (cl_sh_ddr_q.rvalid)
+ ,.M00_AXI_RREADY (cl_sh_ddr_q.rready));
+
+//(* dont_touch = "true" *) axi_interconnect AXI_CROSSBAR
+// (.ACLK(aclk),
+// .ARESETN(slr1_sync_aresetn),
+//
+// .M00_AXI_araddr(),
+// .M00_AXI_arburst(),
+// .M00_AXI_arcache(),
+// .M00_AXI_arid(),
+// .M00_AXI_arlen(),
+// .M00_AXI_arlock(),
+// .M00_AXI_arprot(),
+// .M00_AXI_arqos(),
+// .M00_AXI_arready(1'b0),
+// .M00_AXI_arregion(),
+// .M00_AXI_arsize(),
+// .M00_AXI_arvalid(),
+// .M00_AXI_awaddr(),
+// .M00_AXI_awburst(),
+// .M00_AXI_awcache(),
+// .M00_AXI_awid(),
+// .M00_AXI_awlen(),
+// .M00_AXI_awlock(),
+// .M00_AXI_awprot(),
+// .M00_AXI_awqos(),
+// .M00_AXI_awready(1'b0),
+// .M00_AXI_awregion(),
+// .M00_AXI_awsize(),
+// .M00_AXI_awvalid(),
+// .M00_AXI_bid(),
+// .M00_AXI_bready(),
+// .M00_AXI_bresp(),
+// .M00_AXI_bvalid(1'b0),
+// .M00_AXI_rdata(),
+// .M00_AXI_rid(),
+// .M00_AXI_rlast(),
+// .M00_AXI_rready(),
+// .M00_AXI_rresp(),
+// .M00_AXI_rvalid(1'b0),
+// .M00_AXI_wdata(),
+// .M00_AXI_wlast(),
+// .M00_AXI_wready(1'b0),
+// .M00_AXI_wstrb(),
+// .M00_AXI_wvalid(),
+//
+// .M01_AXI_araddr(),
+// .M01_AXI_arburst(),
+// .M01_AXI_arcache(),
+// .M01_AXI_arid(),
+// .M01_AXI_arlen(),
+// .M01_AXI_arlock(),
+// .M01_AXI_arprot(),
+// .M01_AXI_arqos(),
+// .M01_AXI_arready(1'b0),
+// .M01_AXI_arregion(),
+// .M01_AXI_arsize(),
+// .M01_AXI_arvalid(),
+// .M01_AXI_awaddr(),
+// .M01_AXI_awburst(),
+// .M01_AXI_awcache(),
+// .M01_AXI_awid(),
+// .M01_AXI_awlen(),
+// .M01_AXI_awlock(),
+// .M01_AXI_awprot(),
+// .M01_AXI_awqos(),
+// .M01_AXI_awready(1'b0),
+// .M01_AXI_awregion(),
+// .M01_AXI_awsize(),
+// .M01_AXI_awvalid(),
+// .M01_AXI_bid(),
+// .M01_AXI_bready(),
+// .M01_AXI_bresp(),
+// .M01_AXI_bvalid(1'b0),
+// .M01_AXI_rdata(),
+// .M01_AXI_rid(),
+// .M01_AXI_rlast(),
+// .M01_AXI_rready(),
+// .M01_AXI_rresp(),
+// .M01_AXI_rvalid(1'b0),
+// .M01_AXI_wdata(),
+// .M01_AXI_wlast(),
+// .M01_AXI_wready(1'b0),
+// .M01_AXI_wstrb(),
+// .M01_AXI_wvalid(),
+//
+// .M02_AXI_araddr(cl_sh_ddr_q.araddr),
+// .M02_AXI_arburst(),
+// .M02_AXI_arcache(),
+// .M02_AXI_arid(cl_sh_ddr_q.arid[6:0]),
+// .M02_AXI_arlen(cl_sh_ddr_q.arlen),
+// .M02_AXI_arlock(),
+// .M02_AXI_arprot(),
+// .M02_AXI_arqos(),
+// .M02_AXI_arready(cl_sh_ddr_q.arready),
+// .M02_AXI_arregion(),
+// .M02_AXI_arsize(cl_sh_ddr_q.arsize),
+// .M02_AXI_arvalid(cl_sh_ddr_q.arvalid),
+// .M02_AXI_awaddr(cl_sh_ddr_q.awaddr),
+// .M02_AXI_awburst(),
+// .M02_AXI_awcache(),
+// .M02_AXI_awid(cl_sh_ddr_q.awid[6:0]),
+// .M02_AXI_awlen(cl_sh_ddr_q.awlen),
+// .M02_AXI_awlock(),
+// .M02_AXI_awprot(),
+// .M02_AXI_awqos(),
+// .M02_AXI_awready(cl_sh_ddr_q.awready),
+// .M02_AXI_awregion(),
+// .M02_AXI_awsize(cl_sh_ddr_q.awsize),
+// .M02_AXI_awvalid(cl_sh_ddr_q.awvalid),
+// .M02_AXI_bid(cl_sh_ddr_q.bid[6:0]),
+// .M02_AXI_bready(cl_sh_ddr_q.bready),
+// .M02_AXI_bresp(cl_sh_ddr_q.bresp),
+// .M02_AXI_bvalid(cl_sh_ddr_q.bvalid),
+// .M02_AXI_rdata(cl_sh_ddr_q.rdata),
+// .M02_AXI_rid(cl_sh_ddr_q.rid[6:0]),
+// .M02_AXI_rlast(cl_sh_ddr_q.rlast),
+// .M02_AXI_rready(cl_sh_ddr_q.rready),
+// .M02_AXI_rresp(cl_sh_ddr_q.rresp),
+// .M02_AXI_rvalid(cl_sh_ddr_q.rvalid),
+// .M02_AXI_wdata(cl_sh_ddr_q.wdata),
+// .M02_AXI_wlast(cl_sh_ddr_q.wlast),
+// .M02_AXI_wready(cl_sh_ddr_q.wready),
+// .M02_AXI_wstrb(cl_sh_ddr_q.wstrb),
+// .M02_AXI_wvalid(cl_sh_ddr_q.wvalid),
+//
+// .M03_AXI_araddr(),
+// .M03_AXI_arburst(),
+// .M03_AXI_arcache(),
+// .M03_AXI_arid(),
+// .M03_AXI_arlen(),
+// .M03_AXI_arlock(),
+// .M03_AXI_arprot(),
+// .M03_AXI_arqos(),
+// .M03_AXI_arready(1'b0),
+// .M03_AXI_arregion(),
+// .M03_AXI_arsize(),
+// .M03_AXI_arvalid(),
+// .M03_AXI_awaddr(),
+// .M03_AXI_awburst(),
+// .M03_AXI_awcache(),
+// .M03_AXI_awid(),
+// .M03_AXI_awlen(),
+// .M03_AXI_awlock(),
+// .M03_AXI_awprot(),
+// .M03_AXI_awqos(),
+// .M03_AXI_awready(1'b0),
+// .M03_AXI_awregion(),
+// .M03_AXI_awsize(),
+// .M03_AXI_awvalid(),
+// .M03_AXI_bid(),
+// .M03_AXI_bready(),
+// .M03_AXI_bresp(),
+// .M03_AXI_bvalid(1'b0),
+// .M03_AXI_rdata(),
+// .M03_AXI_rid(),
+// .M03_AXI_rlast(),
+// .M03_AXI_rready(),
+// .M03_AXI_rresp(),
+// .M03_AXI_rvalid(1'b0),
+// .M03_AXI_wdata(),
+// .M03_AXI_wlast(),
+// .M03_AXI_wready(1'b0),
+// .M03_AXI_wstrb(),
+// .M03_AXI_wvalid(),
+//
+// .S00_AXI_araddr({sh_cl_dma_pcis_q.araddr[63:37], 1'b0, sh_cl_dma_pcis_q.araddr[35:0]}),
+// .S00_AXI_arburst(2'b1),
+// .S00_AXI_arcache(4'b11),
+// .S00_AXI_arid(sh_cl_dma_pcis_q.arid[5:0]),
+// .S00_AXI_arlen(sh_cl_dma_pcis_q.arlen),
+// .S00_AXI_arlock(1'b0),
+// .S00_AXI_arprot(3'b10),
+// .S00_AXI_arqos(4'b0),
+// .S00_AXI_arready(sh_cl_dma_pcis_q.arready),
+// .S00_AXI_arregion(4'b0),
+// .S00_AXI_arsize(sh_cl_dma_pcis_q.arsize),
+// .S00_AXI_arvalid(sh_cl_dma_pcis_q.arvalid),
+// .S00_AXI_awaddr({sh_cl_dma_pcis_q.awaddr[63:37], 1'b0, sh_cl_dma_pcis_q.awaddr[35:0]}),
+// .S00_AXI_awburst(2'b1),
+// .S00_AXI_awcache(4'b11),
+// .S00_AXI_awid(sh_cl_dma_pcis_q.awid[5:0]),
+// .S00_AXI_awlen(sh_cl_dma_pcis_q.awlen),
+// .S00_AXI_awlock(1'b0),
+// .S00_AXI_awprot(3'b10),
+// .S00_AXI_awqos(4'b0),
+// .S00_AXI_awready(sh_cl_dma_pcis_q.awready),
+// .S00_AXI_awregion(4'b0),
+// .S00_AXI_awsize(sh_cl_dma_pcis_q.awsize),
+// .S00_AXI_awvalid(sh_cl_dma_pcis_q.awvalid),
+// .S00_AXI_bid(sh_cl_dma_pcis_q.bid[5:0]),
+// .S00_AXI_bready(sh_cl_dma_pcis_q.bready),
+// .S00_AXI_bresp(sh_cl_dma_pcis_q.bresp),
+// .S00_AXI_bvalid(sh_cl_dma_pcis_q.bvalid),
+// .S00_AXI_rdata(sh_cl_dma_pcis_q.rdata),
+// .S00_AXI_rid(sh_cl_dma_pcis_q.rid[5:0]),
+// .S00_AXI_rlast(sh_cl_dma_pcis_q.rlast),
+// .S00_AXI_rready(sh_cl_dma_pcis_q.rready),
+// .S00_AXI_rresp(sh_cl_dma_pcis_q.rresp),
+// .S00_AXI_rvalid(sh_cl_dma_pcis_q.rvalid),
+// .S00_AXI_wdata(sh_cl_dma_pcis_q.wdata),
+// .S00_AXI_wlast(sh_cl_dma_pcis_q.wlast),
+// .S00_AXI_wready(sh_cl_dma_pcis_q.wready),
+// .S00_AXI_wstrb(sh_cl_dma_pcis_q.wstrb),
+// .S00_AXI_wvalid(sh_cl_dma_pcis_q.wvalid),
+//
+// .S01_AXI_araddr(64'h0),
+// .S01_AXI_arburst(2'b1),
+// .S01_AXI_arcache(4'b11),
+// .S01_AXI_arid(6'h0),
+// .S01_AXI_arlen(8'h0),
+// .S01_AXI_arlock(1'b0),
+// .S01_AXI_arprot(3'b10),
+// .S01_AXI_arqos(4'b0),
+// .S01_AXI_arready(),
+// .S01_AXI_arregion(4'b0),
+// .S01_AXI_arsize(3'h0),
+// .S01_AXI_arvalid(1'b0),
+// .S01_AXI_awaddr(64'h0),
+// .S01_AXI_awburst(2'b1),
+// .S01_AXI_awcache(4'b11),
+// .S01_AXI_awid(6'h0),
+// .S01_AXI_awlen(8'h0),
+// .S01_AXI_awlock(1'b0),
+// .S01_AXI_awprot(3'b10),
+// .S01_AXI_awqos(4'b0),
+// .S01_AXI_awready(),
+// .S01_AXI_awregion(4'b0),
+// .S01_AXI_awsize(3'h0),
+// .S01_AXI_awvalid(1'b0),
+// .S01_AXI_bid(),
+// .S01_AXI_bready(1'b0),
+// .S01_AXI_bresp(),
+// .S01_AXI_bvalid(),
+// .S01_AXI_rdata(),
+// .S01_AXI_rid(),
+// .S01_AXI_rlast(),
+// .S01_AXI_rready(1'b0),
+// .S01_AXI_rresp(),
+// .S01_AXI_rvalid(),
+// .S01_AXI_wdata(512'h0),
+// .S01_AXI_wlast(1'b0),
+// .S01_AXI_wready(),
+// .S01_AXI_wstrb(64'h0),
+// .S01_AXI_wvalid(1'b0));
+
+//----------------------------
+// flop the output of interconnect for DDRC
+//----------------------------
+ axi_register_slice DDR_C_TST_AXI4_REG_SLC (
+ .aclk (aclk),
+ .aresetn (slr1_sync_aresetn),
+
+ .s_axi_awid (cl_sh_ddr_q.awid),
+ .s_axi_awaddr ({cl_sh_ddr_q.awaddr[63:36], 2'b0, cl_sh_ddr_q.awaddr[33:0]}),
+ .s_axi_awlen (cl_sh_ddr_q.awlen),
+ .s_axi_awsize (cl_sh_ddr_q.awsize),
+ .s_axi_awvalid (cl_sh_ddr_q.awvalid),
+ .s_axi_awready (cl_sh_ddr_q.awready),
+ .s_axi_wdata (cl_sh_ddr_q.wdata),
+ .s_axi_wstrb (cl_sh_ddr_q.wstrb),
+ .s_axi_wlast (cl_sh_ddr_q.wlast),
+ .s_axi_wvalid (cl_sh_ddr_q.wvalid),
+ .s_axi_wready (cl_sh_ddr_q.wready),
+ .s_axi_bid (cl_sh_ddr_q.bid),
+ .s_axi_bresp (cl_sh_ddr_q.bresp),
+ .s_axi_bvalid (cl_sh_ddr_q.bvalid),
+ .s_axi_bready (cl_sh_ddr_q.bready),
+ .s_axi_arid (cl_sh_ddr_q.arid),
+ .s_axi_araddr ({cl_sh_ddr_q.araddr[63:36], 2'b0, cl_sh_ddr_q.araddr[33:0]}),
+ .s_axi_arlen (cl_sh_ddr_q.arlen),
+ .s_axi_arsize (cl_sh_ddr_q.arsize),
+ .s_axi_arvalid (cl_sh_ddr_q.arvalid),
+ .s_axi_arready (cl_sh_ddr_q.arready),
+ .s_axi_rid (cl_sh_ddr_q.rid),
+ .s_axi_rdata (cl_sh_ddr_q.rdata),
+ .s_axi_rresp (cl_sh_ddr_q.rresp),
+ .s_axi_rlast (cl_sh_ddr_q.rlast),
+ .s_axi_rvalid (cl_sh_ddr_q.rvalid),
+ .s_axi_rready (cl_sh_ddr_q.rready),
+ .m_axi_awid (cl_sh_ddr_q2.awid),
+ .m_axi_awaddr (cl_sh_ddr_q2.awaddr),
+ .m_axi_awlen (cl_sh_ddr_q2.awlen),
+ .m_axi_awsize (cl_sh_ddr_q2.awsize),
+ .m_axi_awvalid (cl_sh_ddr_q2.awvalid),
+ .m_axi_awready (cl_sh_ddr_q2.awready),
+ .m_axi_wdata (cl_sh_ddr_q2.wdata),
+ .m_axi_wstrb (cl_sh_ddr_q2.wstrb),
+ .m_axi_wlast (cl_sh_ddr_q2.wlast),
+ .m_axi_wvalid (cl_sh_ddr_q2.wvalid),
+ .m_axi_wready (cl_sh_ddr_q2.wready),
+ .m_axi_bid (cl_sh_ddr_q2.bid),
+ .m_axi_bresp (cl_sh_ddr_q2.bresp),
+ .m_axi_bvalid (cl_sh_ddr_q2.bvalid),
+ .m_axi_bready (cl_sh_ddr_q2.bready),
+ .m_axi_arid (cl_sh_ddr_q2.arid),
+ .m_axi_araddr (cl_sh_ddr_q2.araddr),
+ .m_axi_arlen (cl_sh_ddr_q2.arlen),
+ .m_axi_arsize (cl_sh_ddr_q2.arsize),
+ .m_axi_arvalid (cl_sh_ddr_q2.arvalid),
+ .m_axi_arready (cl_sh_ddr_q2.arready),
+ .m_axi_rid (cl_sh_ddr_q2.rid),
+ .m_axi_rdata (cl_sh_ddr_q2.rdata),
+ .m_axi_rresp (cl_sh_ddr_q2.rresp),
+ .m_axi_rlast (cl_sh_ddr_q2.rlast),
+ .m_axi_rvalid (cl_sh_ddr_q2.rvalid),
+ .m_axi_rready (cl_sh_ddr_q2.rready)
+ );
+
+
+//----------------------------
+// flop the output of ATG/Scrubber for DDRC
+//----------------------------
+
+ axi_register_slice DDR_C_TST_AXI4_REG_SLC_1 (
+ .aclk (aclk),
+ .aresetn (slr1_sync_aresetn),
+
+ .s_axi_awid (cl_sh_ddr_q2.awid),
+ .s_axi_awaddr ({cl_sh_ddr_q2.awaddr}),
+ .s_axi_awlen (cl_sh_ddr_q2.awlen),
+ .s_axi_awsize (cl_sh_ddr_q2.awsize),
+ .s_axi_awvalid (cl_sh_ddr_q2.awvalid),
+ .s_axi_awready (cl_sh_ddr_q2.awready),
+ .s_axi_wdata (cl_sh_ddr_q2.wdata),
+ .s_axi_wstrb (cl_sh_ddr_q2.wstrb),
+ .s_axi_wlast (cl_sh_ddr_q2.wlast),
+ .s_axi_wvalid (cl_sh_ddr_q2.wvalid),
+ .s_axi_wready (cl_sh_ddr_q2.wready),
+ .s_axi_bid (cl_sh_ddr_q2.bid),
+ .s_axi_bresp (cl_sh_ddr_q2.bresp),
+ .s_axi_bvalid (cl_sh_ddr_q2.bvalid),
+ .s_axi_bready (cl_sh_ddr_q2.bready),
+ .s_axi_arid (cl_sh_ddr_q2.arid),
+ .s_axi_araddr (cl_sh_ddr_q2.araddr),
+ .s_axi_arlen (cl_sh_ddr_q2.arlen),
+ .s_axi_arsize (cl_sh_ddr_q2.arsize),
+ .s_axi_arvalid (cl_sh_ddr_q2.arvalid),
+ .s_axi_arready (cl_sh_ddr_q2.arready),
+ .s_axi_rid (cl_sh_ddr_q2.rid),
+ .s_axi_rdata (cl_sh_ddr_q2.rdata),
+ .s_axi_rresp (cl_sh_ddr_q2.rresp),
+ .s_axi_rlast (cl_sh_ddr_q2.rlast),
+ .s_axi_rvalid (cl_sh_ddr_q2.rvalid),
+ .s_axi_rready (cl_sh_ddr_q2.rready),
+
+ .m_axi_awid (cl_sh_ddr_bus.awid),
+ .m_axi_awaddr (cl_sh_ddr_bus.awaddr),
+ .m_axi_awlen (cl_sh_ddr_bus.awlen),
+ .m_axi_awsize (cl_sh_ddr_bus.awsize),
+ .m_axi_awvalid (cl_sh_ddr_bus.awvalid),
+ .m_axi_awready (cl_sh_ddr_bus.awready),
+ .m_axi_wdata (cl_sh_ddr_bus.wdata),
+ .m_axi_wstrb (cl_sh_ddr_bus.wstrb),
+ .m_axi_wlast (cl_sh_ddr_bus.wlast),
+ .m_axi_wvalid (cl_sh_ddr_bus.wvalid),
+ .m_axi_wready (cl_sh_ddr_bus.wready),
+ .m_axi_bid (cl_sh_ddr_bus.bid),
+ .m_axi_bresp (cl_sh_ddr_bus.bresp),
+ .m_axi_bvalid (cl_sh_ddr_bus.bvalid),
+ .m_axi_bready (cl_sh_ddr_bus.bready),
+ .m_axi_arid (cl_sh_ddr_bus.arid),
+ .m_axi_araddr (cl_sh_ddr_bus.araddr),
+ .m_axi_arlen (cl_sh_ddr_bus.arlen),
+ .m_axi_arsize (cl_sh_ddr_bus.arsize),
+ .m_axi_arvalid (cl_sh_ddr_bus.arvalid),
+ .m_axi_arready (cl_sh_ddr_bus.arready),
+ .m_axi_rid (cl_sh_ddr_bus.rid),
+ .m_axi_rdata (cl_sh_ddr_bus.rdata),
+ .m_axi_rresp (cl_sh_ddr_bus.rresp),
+ .m_axi_rlast (cl_sh_ddr_bus.rlast),
+ .m_axi_rvalid (cl_sh_ddr_bus.rvalid),
+ .m_axi_rready (cl_sh_ddr_bus.rready)
+ );
+
+endmodule
+
diff --git a/cl_memdut/design/cl_id_defines.vh b/cl_memdut/design/cl_id_defines.vh
new file mode 100644
index 0000000..d957c70
--- /dev/null
+++ b/cl_memdut/design/cl_id_defines.vh
@@ -0,0 +1,33 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// CL_SH_ID0
+// - PCIe Vendor/Device ID Values
+// 31:16: PCIe Device ID
+// 15: 0: PCIe Vendor ID
+// - A Vendor ID value of 0x8086 is not valid.
+// - If using a Vendor ID value of 0x1D0F (Amazon) then valid
+// values for Device ID's are in the range of 0xF000 - 0xF0FF.
+// - A Vendor/Device ID of 0 (zero) is not valid.
+`define CL_SH_ID0 32'hF001_1D0F
+
+// CL_SH_ID1
+// - PCIe Subsystem/Subsystem Vendor ID Values
+// 31:16: PCIe Subsystem ID
+// 15: 0: PCIe Subsystem Vendor ID
+// - A PCIe Subsystem/Subsystem Vendor ID of 0 (zero) is not valid
+`define CL_SH_ID1 32'h1D51_FEDC
+
+
diff --git a/cl_memdut/design/cl_ila.sv b/cl_memdut/design/cl_ila.sv
new file mode 100644
index 0000000..df0a565
--- /dev/null
+++ b/cl_memdut/design/cl_ila.sv
@@ -0,0 +1,161 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+module cl_ila (
+
+ input aclk,
+
+ input drck,
+ input shift,
+ input tdi,
+ input update,
+ input sel,
+ output logic tdo,
+ input tms,
+ input tck,
+ input runtest,
+ input reset,
+ input capture,
+ input bscanid_en,
+
+ axi_bus_t sh_cl_dma_pcis_q,
+ axi_bus_t cl_sh_ddr_bus
+
+);
+
+//----------------------------
+// Debug bridge
+//----------------------------
+ cl_debug_bridge CL_DEBUG_BRIDGE (
+ .clk(aclk),
+ .S_BSCAN_drck(drck),
+ .S_BSCAN_shift(shift),
+ .S_BSCAN_tdi(tdi),
+ .S_BSCAN_update(update),
+ .S_BSCAN_sel(sel),
+ .S_BSCAN_tdo(tdo),
+ .S_BSCAN_tms(tms),
+ .S_BSCAN_tck(tck),
+ .S_BSCAN_runtest(runtest),
+ .S_BSCAN_reset(reset),
+ .S_BSCAN_capture(capture),
+ .S_BSCAN_bscanid_en(bscanid_en)
+ );
+
+
+//----------------------------
+// Debug Core ILA for dmm pcis AXI4 interface
+//----------------------------
+ ila_1 CL_DMA_ILA_0 (
+ .clk (aclk),
+ .probe0 (sh_cl_dma_pcis_q.awvalid),
+ .probe1 (sh_cl_dma_pcis_q.awaddr),
+ .probe2 (2'b0),
+ .probe3 (sh_cl_dma_pcis_q.awready),
+ .probe4 (sh_cl_dma_pcis_q.wvalid),
+ .probe5 (sh_cl_dma_pcis_q.wstrb),
+ .probe6 (sh_cl_dma_pcis_q.wlast),
+ .probe7 (sh_cl_dma_pcis_q.wready),
+ .probe8 (1'b0),
+ .probe9 (1'b0),
+ .probe10 (sh_cl_dma_pcis_q.wdata),
+ .probe11 (1'b0),
+ .probe12 (sh_cl_dma_pcis_q.arready),
+ .probe13 (2'b0),
+ .probe14 (sh_cl_dma_pcis_q.rdata),
+ .probe15 (sh_cl_dma_pcis_q.araddr),
+ .probe16 (sh_cl_dma_pcis_q.arvalid),
+ .probe17 (3'b0),
+ .probe18 (3'b0),
+ .probe19 (sh_cl_dma_pcis_q.awid),
+ .probe20 (sh_cl_dma_pcis_q.arid),
+ .probe21 (sh_cl_dma_pcis_q.awlen),
+ .probe22 (sh_cl_dma_pcis_q.rlast),
+ .probe23 (3'b0),
+ .probe24 (sh_cl_dma_pcis_q.rresp),
+ .probe25 (sh_cl_dma_pcis_q.rid),
+ .probe26 (sh_cl_dma_pcis_q.rvalid),
+ .probe27 (sh_cl_dma_pcis_q.arlen),
+ .probe28 (3'b0),
+ .probe29 (sh_cl_dma_pcis_q.bresp),
+ .probe30 (sh_cl_dma_pcis_q.rready),
+ .probe31 (4'b0),
+ .probe32 (4'b0),
+ .probe33 (4'b0),
+ .probe34 (4'b0),
+ .probe35 (sh_cl_dma_pcis_q.bvalid),
+ .probe36 (4'b0),
+ .probe37 (4'b0),
+ .probe38 (sh_cl_dma_pcis_q.bid),
+ .probe39 (sh_cl_dma_pcis_q.bready),
+ .probe40 (1'b0),
+ .probe41 (1'b0),
+ .probe42 (1'b0),
+ .probe43 (1'b0)
+ );
+//----------------------------
+// Debug Core ILA for DDRA AXI4 interface monitoring
+//----------------------------
+ ila_1 CL_DDRA_ILA_0 (
+ .clk (aclk),
+ .probe0 (cl_sh_ddr_bus.awvalid),
+ .probe1 (cl_sh_ddr_bus.awaddr),
+ .probe2 (2'b0),
+ .probe3 (cl_sh_ddr_bus.awready),
+ .probe4 (cl_sh_ddr_bus.wvalid),
+ .probe5 (cl_sh_ddr_bus.wstrb),
+ .probe6 (cl_sh_ddr_bus.wlast),
+ .probe7 (cl_sh_ddr_bus.wready),
+ .probe8 (1'b0),
+ .probe9 (1'b0),
+ .probe10 (cl_sh_ddr_bus.wdata),
+ .probe11 (1'b0),
+ .probe12 (cl_sh_ddr_bus.arready),
+ .probe13 (2'b0),
+ .probe14 (cl_sh_ddr_bus.rdata),
+ .probe15 (cl_sh_ddr_bus.araddr),
+ .probe16 (cl_sh_ddr_bus.arvalid),
+ .probe17 (3'b0),
+ .probe18 (3'b0),
+ .probe19 (cl_sh_ddr_bus.awid[4:0]),
+ .probe20 (cl_sh_ddr_bus.arid[4:0]),
+ .probe21 (cl_sh_ddr_bus.awlen),
+ .probe22 (cl_sh_ddr_bus.rlast),
+ .probe23 (3'b0),
+ .probe24 (cl_sh_ddr_bus.rresp),
+ .probe25 (cl_sh_ddr_bus.rid[4:0]),
+ .probe26 (cl_sh_ddr_bus.rvalid),
+ .probe27 (cl_sh_ddr_bus.arlen),
+ .probe28 (3'b0),
+ .probe29 (cl_sh_ddr_bus.bresp),
+ .probe30 (cl_sh_ddr_bus.rready),
+ .probe31 (4'b0),
+ .probe32 (4'b0),
+ .probe33 (4'b0),
+ .probe34 (4'b0),
+ .probe35 (cl_sh_ddr_bus.bvalid),
+ .probe36 (4'b0),
+ .probe37 (4'b0),
+ .probe38 (cl_sh_ddr_bus.bid[4:0]),
+ .probe39 (cl_sh_ddr_bus.bready),
+ .probe40 (1'b0),
+ .probe41 (1'b0),
+ .probe42 (1'b0),
+ .probe43 (1'b0)
+ );
+
+
+endmodule
+
diff --git a/cl_memdut/design/cl_memdut.sv b/cl_memdut/design/cl_memdut.sv
new file mode 100644
index 0000000..5315d5f
--- /dev/null
+++ b/cl_memdut/design/cl_memdut.sv
@@ -0,0 +1,394 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+module cl_memdut #(parameter NUM_DDR=4)
+
+(
+ `include "cl_ports.vh"
+
+);
+
+//`include "cl_common_defines.vh" // CL Defines for all examples
+`include "cl_id_defines.vh" // Defines for ID0 and ID1 (PCI ID's)
+`include "cl_memdut_defines.vh"
+
+// TIE OFF ALL UNUSED INTERFACES
+// Including all the unused interface to tie off
+// This list is put in the top of the fie to remind
+// developers to remve the specific interfaces
+// that the CL will use
+
+`include "unused_ddr_a_b_d_template.inc"
+`include "unused_pcim_template.inc"
+`include "unused_cl_sda_template.inc"
+
+// Define the addition pipeline stag
+// needed to close timing for the various
+// place where ATG (Automatic Test Generator)
+// is defined
+
+ localparam NUM_CFG_STGS_CL_DDR_ATG = 8;
+ localparam NUM_CFG_STGS_SH_DDR_ATG = 4;
+ localparam NUM_CFG_STGS_PCIE_ATG = 4;
+
+// To reduce RTL simulation time, only 8KiB of
+// each external DRAM is scrubbed in simulations
+
+`ifdef SIM
+ localparam DDR_SCRB_MAX_ADDR = 64'h1FFF;
+`else
+ localparam DDR_SCRB_MAX_ADDR = 64'h3FFFFFFFF; //16GB
+`endif
+ localparam DDR_SCRB_BURST_LEN_MINUS1 = 15;
+
+`ifdef NO_CL_TST_SCRUBBER
+ localparam NO_SCRB_INST = 1;
+`else
+ localparam NO_SCRB_INST = 0;
+`endif
+
+//----------------------------
+// Internal signals
+//----------------------------
+axi_bus_t sh_cl_dma_pcis_bus();
+axi_bus_t sh_cl_dma_pcis_q();
+// keep below memdut_axi_0/1 i/f same as nvdla configuration. Note: nvdla, axi_data_width=512,axi_len_width=4
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(256), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(40), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_dbb_axi_bus();
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(256), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(40), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_cvsram_axi_bus();
+
+axi_bus_t cl_sh_ddr_bus();
+
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(32), .AWS_FPGA_AXI_BUS_ID_WIDTH(1), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(32), .AWS_FPGA_AXI_BUS_LEN_WIDTH(1)) sh_ocl_bus();
+
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(32), .AWS_FPGA_AXI_BUS_ID_WIDTH(1), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(32), .AWS_FPGA_AXI_BUS_LEN_WIDTH(1)) sh_bar1_bus();
+
+logic clk;
+(* dont_touch = "true" *) logic pipe_rst_n;
+logic pre_sync_rst_n;
+(* dont_touch = "true" *) logic sync_rst_n;
+logic sh_cl_flr_assert_q;
+
+//----------------------------
+// End Internal signals
+//----------------------------
+
+assign clk = clk_main_a0;
+
+//reset synchronizer
+lib_pipe #(.WIDTH(1), .STAGES(4)) PIPE_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(rst_main_n), .out_bus(pipe_rst_n));
+
+always_ff @(negedge pipe_rst_n or posedge clk)
+ if (!pipe_rst_n)
+ begin
+ pre_sync_rst_n <= 0;
+ sync_rst_n <= 0;
+ end
+ else
+ begin
+ pre_sync_rst_n <= 1;
+ sync_rst_n <= pre_sync_rst_n;
+ end
+
+//FLR response
+always_ff @(negedge sync_rst_n or posedge clk)
+ if (!sync_rst_n)
+ begin
+ sh_cl_flr_assert_q <= 0;
+ cl_sh_flr_done <= 0;
+ end
+ else
+ begin
+ sh_cl_flr_assert_q <= sh_cl_flr_assert;
+ cl_sh_flr_done <= sh_cl_flr_assert_q && !cl_sh_flr_done;
+ end
+
+//-------------------------------------------
+// Tie-Off Global Signals
+//-------------------------------------------
+`ifndef CL_VERSION
+ `define CL_VERSION 32'hee_ee_ee_00
+`endif
+
+
+ assign cl_sh_status0[31:0] = 32'h0000_0FF0;
+ assign cl_sh_status1[31:0] = `CL_VERSION;
+
+//-------------------------------------------------
+// ID Values
+//-------------------------------------------------
+ assign cl_sh_id0[31:0] = `CL_SH_ID0;
+ assign cl_sh_id1[31:0] = `CL_SH_ID1;
+
+
+///////////////////////////////////////////////////////////////////////
+///////////////// DMA PCIS SLAVE module ///////////////////////////////
+///////////////////////////////////////////////////////////////////////
+
+assign sh_cl_dma_pcis_bus.awvalid = sh_cl_dma_pcis_awvalid;
+assign sh_cl_dma_pcis_bus.awaddr = sh_cl_dma_pcis_awaddr;
+assign sh_cl_dma_pcis_bus.awid[5:0] = sh_cl_dma_pcis_awid;
+assign sh_cl_dma_pcis_bus.awlen = sh_cl_dma_pcis_awlen;
+assign sh_cl_dma_pcis_bus.awsize = sh_cl_dma_pcis_awsize;
+assign cl_sh_dma_pcis_awready = sh_cl_dma_pcis_bus.awready;
+assign sh_cl_dma_pcis_bus.wvalid = sh_cl_dma_pcis_wvalid;
+assign sh_cl_dma_pcis_bus.wdata = sh_cl_dma_pcis_wdata;
+assign sh_cl_dma_pcis_bus.wstrb = sh_cl_dma_pcis_wstrb;
+assign sh_cl_dma_pcis_bus.wlast = sh_cl_dma_pcis_wlast;
+assign cl_sh_dma_pcis_wready = sh_cl_dma_pcis_bus.wready;
+assign cl_sh_dma_pcis_bvalid = sh_cl_dma_pcis_bus.bvalid;
+assign cl_sh_dma_pcis_bresp = sh_cl_dma_pcis_bus.bresp;
+assign sh_cl_dma_pcis_bus.bready = sh_cl_dma_pcis_bready;
+assign cl_sh_dma_pcis_bid = sh_cl_dma_pcis_bus.bid[5:0];
+assign sh_cl_dma_pcis_bus.arvalid = sh_cl_dma_pcis_arvalid;
+assign sh_cl_dma_pcis_bus.araddr = sh_cl_dma_pcis_araddr;
+assign sh_cl_dma_pcis_bus.arid[5:0] = sh_cl_dma_pcis_arid;
+assign sh_cl_dma_pcis_bus.arlen = sh_cl_dma_pcis_arlen;
+assign sh_cl_dma_pcis_bus.arsize = sh_cl_dma_pcis_arsize;
+assign cl_sh_dma_pcis_arready = sh_cl_dma_pcis_bus.arready;
+assign cl_sh_dma_pcis_rvalid = sh_cl_dma_pcis_bus.rvalid;
+assign cl_sh_dma_pcis_rid = sh_cl_dma_pcis_bus.rid[5:0];
+assign cl_sh_dma_pcis_rlast = sh_cl_dma_pcis_bus.rlast;
+assign cl_sh_dma_pcis_rresp = sh_cl_dma_pcis_bus.rresp;
+assign cl_sh_dma_pcis_rdata = sh_cl_dma_pcis_bus.rdata;
+assign sh_cl_dma_pcis_bus.rready = sh_cl_dma_pcis_rready;
+
+assign cl_sh_ddr_awid = cl_sh_ddr_bus.awid;
+assign cl_sh_ddr_awaddr = cl_sh_ddr_bus.awaddr;
+assign cl_sh_ddr_awlen = cl_sh_ddr_bus.awlen;
+assign cl_sh_ddr_awsize = cl_sh_ddr_bus.awsize;
+assign cl_sh_ddr_awvalid = cl_sh_ddr_bus.awvalid;
+assign cl_sh_ddr_bus.awready = sh_cl_ddr_awready;
+assign cl_sh_ddr_wid = 16'b0;
+assign cl_sh_ddr_wdata = cl_sh_ddr_bus.wdata;
+assign cl_sh_ddr_wstrb = cl_sh_ddr_bus.wstrb;
+assign cl_sh_ddr_wlast = cl_sh_ddr_bus.wlast;
+assign cl_sh_ddr_wvalid = cl_sh_ddr_bus.wvalid;
+assign cl_sh_ddr_bus.wready = sh_cl_ddr_wready;
+assign cl_sh_ddr_bus.bid = sh_cl_ddr_bid;
+assign cl_sh_ddr_bus.bresp = sh_cl_ddr_bresp;
+assign cl_sh_ddr_bus.bvalid = sh_cl_ddr_bvalid;
+assign cl_sh_ddr_bready = cl_sh_ddr_bus.bready;
+assign cl_sh_ddr_arid = cl_sh_ddr_bus.arid;
+assign cl_sh_ddr_araddr = cl_sh_ddr_bus.araddr;
+assign cl_sh_ddr_arlen = cl_sh_ddr_bus.arlen;
+assign cl_sh_ddr_arsize = cl_sh_ddr_bus.arsize;
+assign cl_sh_ddr_arvalid = cl_sh_ddr_bus.arvalid;
+assign cl_sh_ddr_bus.arready = sh_cl_ddr_arready;
+assign cl_sh_ddr_bus.rid = sh_cl_ddr_rid;
+assign cl_sh_ddr_bus.rresp = sh_cl_ddr_rresp;
+assign cl_sh_ddr_bus.rvalid = sh_cl_ddr_rvalid;
+assign cl_sh_ddr_bus.rdata = sh_cl_ddr_rdata;
+assign cl_sh_ddr_bus.rlast = sh_cl_ddr_rlast;
+assign cl_sh_ddr_rready = cl_sh_ddr_bus.rready;
+
+(* dont_touch = "true" *) logic dma_pcis_slv_sync_rst_n;
+lib_pipe #(.WIDTH(1), .STAGES(4)) DMA_PCIS_SLV_SLC_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(sync_rst_n), .out_bus(dma_pcis_slv_sync_rst_n));
+cl_dma_pcis_slv #(.SCRB_BURST_LEN_MINUS1(DDR_SCRB_BURST_LEN_MINUS1),
+ .SCRB_MAX_ADDR(DDR_SCRB_MAX_ADDR),
+ .NO_SCRB_INST(NO_SCRB_INST)) CL_DMA_PCIS_SLV (
+ .aclk(clk),
+ .aresetn(dma_pcis_slv_sync_rst_n),
+
+ .sh_cl_dma_pcis_bus(sh_cl_dma_pcis_bus),
+ .nvdla_dbb_axi_bus(nvdla_dbb_axi_bus),
+ .nvdla_cvsram_axi_bus(nvdla_cvsram_axi_bus),
+
+ .sh_cl_dma_pcis_q(sh_cl_dma_pcis_q),
+
+ .cl_sh_ddr_bus (cl_sh_ddr_bus)
+ );
+
+///////////////////////////////////////////////////////////////////////
+///////////////// DMA PCIS SLAVE module ///////////////////////////////
+///////////////////////////////////////////////////////////////////////
+
+
+///////////////////////////////////////////////////////////////////////
+///////////////// OCL SLAVE module ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////
+
+assign sh_ocl_bus.awvalid = sh_ocl_awvalid;
+assign sh_ocl_bus.awaddr[31:0] = sh_ocl_awaddr;
+assign ocl_sh_awready = sh_ocl_bus.awready;
+assign sh_ocl_bus.wvalid = sh_ocl_wvalid;
+assign sh_ocl_bus.wdata[31:0] = sh_ocl_wdata;
+assign sh_ocl_bus.wstrb[3:0] = sh_ocl_wstrb;
+assign ocl_sh_wready = sh_ocl_bus.wready;
+assign ocl_sh_bvalid = sh_ocl_bus.bvalid;
+assign ocl_sh_bresp = sh_ocl_bus.bresp;
+assign sh_ocl_bus.bready = sh_ocl_bready;
+assign sh_ocl_bus.arvalid = sh_ocl_arvalid;
+assign sh_ocl_bus.araddr[31:0] = sh_ocl_araddr;
+assign ocl_sh_arready = sh_ocl_bus.arready;
+assign ocl_sh_rvalid = sh_ocl_bus.rvalid;
+assign ocl_sh_rresp = sh_ocl_bus.rresp;
+assign ocl_sh_rdata = sh_ocl_bus.rdata[31:0];
+assign sh_ocl_bus.rready = sh_ocl_rready;
+
+(* dont_touch = "true" *) logic ocl_slv_sync_rst_n;
+lib_pipe #(.WIDTH(1), .STAGES(4)) OCL_SLV_SLC_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(sync_rst_n), .out_bus(ocl_slv_sync_rst_n));
+
+///////////////////////////////////////////////////////////////////////
+///////////////// OCL SLAVE module ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////
+
+
+//-----------------------------------------
+// Interrrupt example
+//-----------------------------------------
+
+(* dont_touch = "true" *) logic int_slv_sync_rst_n;
+lib_pipe #(.WIDTH(1), .STAGES(4)) INT_SLV_SLC_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(sync_rst_n), .out_bus(int_slv_sync_rst_n));
+
+//-----------------------------------------
+// Interrrupt example
+//-----------------------------------------
+
+//-----------------------------------------
+// BAR1 SLAVE module
+//-----------------------------------------
+
+assign sh_bar1_bus.awvalid = sh_bar1_awvalid;
+assign sh_bar1_bus.awaddr[31:0] = sh_bar1_awaddr;
+assign bar1_sh_awready = sh_bar1_bus.awready;
+assign sh_bar1_bus.wvalid = sh_bar1_wvalid;
+assign sh_bar1_bus.wdata[31:0] = sh_bar1_wdata;
+assign sh_bar1_bus.wstrb[3:0] = sh_bar1_wstrb;
+assign bar1_sh_wready = sh_bar1_bus.wready;
+assign bar1_sh_bvalid = sh_bar1_bus.bvalid;
+assign bar1_sh_bresp = sh_bar1_bus.bresp;
+assign sh_bar1_bus.bready = sh_bar1_bready;
+assign sh_bar1_bus.arvalid = sh_bar1_arvalid;
+assign sh_bar1_bus.araddr[31:0] = sh_bar1_araddr;
+assign bar1_sh_arready = sh_bar1_bus.arready;
+assign bar1_sh_rvalid = sh_bar1_bus.rvalid;
+assign bar1_sh_rresp = sh_bar1_bus.rresp;
+assign bar1_sh_rdata = sh_bar1_bus.rdata[31:0];
+assign sh_bar1_bus.rready = sh_bar1_rready;
+
+(* dont_touch = "true" *) logic bar1_slv_sync_rst_n;
+lib_pipe #(.WIDTH(1), .STAGES(4)) BAR1_SLV_SLC_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(sync_rst_n), .out_bus(bar1_slv_sync_rst_n));
+
+//-----------------------------------------
+// BAR1 SLAVE module
+//-----------------------------------------
+
+//-----------------------------------------
+// Virtual JTAG ILA Debug core example
+//-----------------------------------------
+
+
+`ifndef DISABLE_VJTAG_DEBUG
+
+cl_ila CL_ILA (
+
+ .aclk(clk),
+
+ .drck(drck),
+ .shift(shift),
+ .tdi(tdi),
+ .update(update),
+ .sel(sel),
+ .tdo(tdo),
+ .tms(tms),
+ .tck(tck),
+ .runtest(runtest),
+ .reset(reset),
+ .capture(capture),
+ .bscanid_en(bscanid_en),
+
+ .sh_cl_dma_pcis_q(sh_cl_dma_pcis_q),
+ .cl_sh_ddr_bus(cl_sh_ddr_bus)
+
+);
+
+cl_vio CL_VIO (
+
+ .clk_extra_a1(clk_extra_a1)
+
+);
+
+
+`endif // `ifndef DISABLE_VJTAG_DEBUG
+
+//-----------------------------------------
+// Virtual JATG ILA Debug core example
+//-----------------------------------------
+
+//-----------------------------------------
+// Simple DUT
+//-----------------------------------------
+wire [15:0] irq_upstream;
+wire [63:0] base_addr0;
+wire [63:0] base_addr1;
+cl_memdut_wrap CL_MEMDUT_WRAP (
+ .clk(clk),
+ .rstn(rst_main_n),
+ .irq_upstream(irq_upstream),
+ .base_addr0(base_addr0[63:0]),
+ .base_addr1(base_addr1[63:0]),
+
+ .cl_dut_axi_0(nvdla_dbb_axi_bus),
+ .cl_dut_axi_1(nvdla_cvsram_axi_bus),
+
+ .cl_dut_axi_cfg(sh_ocl_bus)
+);
+
+//-----------------------------------------
+// Simple DUT
+//-----------------------------------------
+
+//-----------------------------------------
+// interrupt upstream
+//-----------------------------------------
+wire [15:0] irq_status;
+wire [15:0] irq_pop;
+
+cl_irq_up CL_IRQ_UP(
+ .clk (clk),
+ .reset_ (int_slv_sync_rst_n),
+ .irq (irq_upstream[15:0]),
+ .irq_status (irq_status[15:0]),
+ .irq_pop (irq_pop[15:0]),
+ .irq_req (cl_sh_apppf_irq_req[15:0]),
+ .irq_ack (sh_cl_apppf_irq_ack[15:0])
+);
+
+
+//-----------------------------------------
+// interrupt upstream
+//-----------------------------------------
+
+//-----------------------------------------
+//custom configure registers
+//-----------------------------------------
+
+cl_cfgreg CL_CFGREG (
+ .clk(clk),
+ .rstn(bar1_slv_sync_rst_n),
+ .irq_status(irq_status[15:0]),
+ .irq_pop(irq_pop[15:0]),
+ .base_addr0(base_addr0[63:0]),
+ .base_addr1(base_addr1[63:0]),
+
+ .cfg_axi_bus(sh_bar1_bus)
+
+);
+
+
+endmodule
diff --git a/cl_memdut/design/cl_memdut_defines.vh b/cl_memdut/design/cl_memdut_defines.vh
new file mode 100644
index 0000000..6d82504
--- /dev/null
+++ b/cl_memdut/design/cl_memdut_defines.vh
@@ -0,0 +1,37 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+`ifndef CL_MEMDUT_DEFINES
+`define CL_MEMDUT_DEFINES
+
+//Put module name of the CL design here. This is used to instantiate in top.sv
+`define CL_NAME cl_memdut
+
+//Highly recommeneded. For lib FIFO block, uses less async reset (take advantage of
+// FPGA flop init capability). This will help with routing resources.
+`define FPGA_LESS_RST
+
+`define SH_SDA
+//uncomment below to make SH and CL async
+`define SH_CL_ASYNC
+
+// Uncomment to disable Virtual JTAG
+//`define DISABLE_VJTAG_DEBUG
+
+`endif
+
diff --git a/cl_memdut/design/cl_memdut_pkg.sv b/cl_memdut/design/cl_memdut_pkg.sv
new file mode 100644
index 0000000..813eb71
--- /dev/null
+++ b/cl_memdut/design/cl_memdut_pkg.sv
@@ -0,0 +1,98 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+`ifndef CL_MEMDUT_PKG
+`define CL_MEMDUT_PKG
+
+ interface axi_bus_t;
+ parameter AWS_FPGA_AXI_BUS_DATA_WIDTH = 512;
+ parameter AWS_FPGA_AXI_BUS_ID_WIDTH = 16;
+ parameter AWS_FPGA_AXI_BUS_ADDR_WIDTH = 64;
+ parameter AWS_FPGA_AXI_BUS_LEN_WIDTH = 8;
+ logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] awid;
+ logic[AWS_FPGA_AXI_BUS_ADDR_WIDTH-1:0] awaddr;
+ logic[AWS_FPGA_AXI_BUS_LEN_WIDTH-1:0] awlen;
+ logic [2:0] awsize;
+ logic awvalid;
+ logic awready;
+
+ logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] wid;
+ logic[AWS_FPGA_AXI_BUS_DATA_WIDTH-1:0] wdata;
+ logic[AWS_FPGA_AXI_BUS_DATA_WIDTH/8-1:0] wstrb;
+ logic wlast;
+ logic wvalid;
+ logic wready;
+
+ logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] bid;
+ logic[1:0] bresp;
+ logic bvalid;
+ logic bready;
+
+ logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] arid;
+ logic[AWS_FPGA_AXI_BUS_ADDR_WIDTH-1:0] araddr;
+ logic[AWS_FPGA_AXI_BUS_LEN_WIDTH-1:0] arlen;
+ logic [2:0] arsize;
+ logic arvalid;
+ logic arready;
+
+ logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] rid;
+ logic[AWS_FPGA_AXI_BUS_DATA_WIDTH-1:0] rdata;
+ logic[1:0] rresp;
+ logic rlast;
+ logic rvalid;
+ logic rready;
+
+ modport master (input awid, awaddr, awlen, awsize, awvalid, output awready,
+ input wid, wdata, wstrb, wlast, wvalid, output wready,
+ output bid, bresp, bvalid, input bready,
+ input arid, araddr, arlen, arsize, arvalid, output arready,
+ output rid, rdata, rresp, rlast, rvalid, input rready);
+
+ modport slave (output awid, awaddr, awlen, awsize, awvalid, input awready,
+ output wid, wdata, wstrb, wlast, wvalid, input wready,
+ input bid, bresp, bvalid, output bready,
+ output arid, araddr, arlen, arsize, arvalid, input arready,
+ input rid, rdata, rresp, rlast, rvalid, output rready);
+ endinterface
+
+
+ interface cfg_bus_t;
+ logic [31:0] addr;
+ logic [31:0] wdata;
+ logic wr;
+ logic rd;
+ logic ack;
+ logic[31:0] rdata;
+
+ modport master (input addr, wdata, wr, rd, output ack, rdata);
+
+ modport slave (output addr, wdata, wr, rd, input ack, rdata);
+ endinterface
+
+ interface scrb_bus_t;
+ logic [63:0] addr;
+ logic [2:0] state;
+ logic enable;
+ logic done;
+
+ modport master (input enable, output addr, state, done);
+
+ modport slave (output enable, input addr, state, done);
+ endinterface
+
+`endif //CL_MEMDUT_PKG
diff --git a/cl_memdut/design/cl_memdut_wrap.sv b/cl_memdut/design/cl_memdut_wrap.sv
new file mode 100644
index 0000000..1a6ba3b
--- /dev/null
+++ b/cl_memdut/design/cl_memdut_wrap.sv
@@ -0,0 +1,271 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: cl_memdut_wrap.sv
+
+module cl_memdut_wrap
+(
+ input clk,
+ input rstn,
+ output [31:0] irq_upstream,
+ input [63:0] base_addr0,
+ input [63:0] base_addr1,
+
+ axi_bus_t.slave cl_dut_axi_0,
+ axi_bus_t.slave cl_dut_axi_1,
+
+ axi_bus_t.master cl_dut_axi_cfg
+);
+
+wire [23:0] m_apb_paddr;
+wire m_apb_penable;
+wire m_apb_pns = 1'b0; // FIXME
+wire m_apb_psel;
+wire [12:0] m_apb_puser = 13'b0; // FIXME
+wire [31:0] m_apb_pwdata;
+wire m_apb_pwrite;
+wire [3:0] m_apb_pwstrb = 4'b1111; // FIXME
+wire [31:0] m_apb_prdata;
+wire m_apb_pready;
+wire m_apb_pslverr;
+
+axi_apb_bridge_0 axi2apb (
+ .s_axi_aclk (clk)
+,.s_axi_aresetn (rstn)
+,.s_axi_awaddr (cl_dut_axi_cfg.awaddr[31:0])
+,.s_axi_awvalid (cl_dut_axi_cfg.awvalid)
+,.s_axi_awready (cl_dut_axi_cfg.awready)
+,.s_axi_wdata (cl_dut_axi_cfg.wdata[31:0])
+,.s_axi_wvalid (cl_dut_axi_cfg.wvalid)
+,.s_axi_wready (cl_dut_axi_cfg.wready)
+,.s_axi_bresp (cl_dut_axi_cfg.bresp)
+,.s_axi_bvalid (cl_dut_axi_cfg.bvalid)
+,.s_axi_bready (cl_dut_axi_cfg.bready)
+,.s_axi_araddr (cl_dut_axi_cfg.araddr)
+,.s_axi_arvalid (cl_dut_axi_cfg.arvalid)
+,.s_axi_arready (cl_dut_axi_cfg.arready)
+,.s_axi_rdata (cl_dut_axi_cfg.rdata)
+,.s_axi_rresp (cl_dut_axi_cfg.rresp)
+,.s_axi_rvalid (cl_dut_axi_cfg.rvalid)
+,.s_axi_rready (cl_dut_axi_cfg.rready)
+,.m_apb_paddr (m_apb_paddr)
+,.m_apb_psel (m_apb_psel)
+,.m_apb_penable (m_apb_penable)
+,.m_apb_pwrite (m_apb_pwrite)
+,.m_apb_pwdata (m_apb_pwdata)
+,.m_apb_pready (m_apb_pready)
+,.m_apb_prdata (m_apb_prdata)
+,.m_apb_pslverr (m_apb_pslverr)
+);
+
+wire [63:0] axi_0_awaddr;
+wire [63:0] axi_1_awaddr;
+wire [63:0] axi_0_araddr;
+wire [63:0] axi_1_araddr;
+
+assign cl_dut_axi_0.awaddr = axi_0_awaddr - base_addr0[39:0];
+assign cl_dut_axi_0.araddr = axi_0_araddr - base_addr0[39:0];
+assign cl_dut_axi_1.awaddr = axi_1_awaddr - base_addr1[39:0];
+assign cl_dut_axi_1.araddr = axi_1_araddr - base_addr1[39:0];
+
+NV_FPGA_unit_checkbox_mem_dut simple_dut (
+ // inputs
+ .apb_clk (clk)
+ ,.apb_paddr (m_apb_paddr)
+ ,.apb_paddr_1 (24'b0)
+ ,.apb_penable (m_apb_penable)
+ ,.apb_penable_1 (1'b0)
+ ,.apb_pns (m_apb_pns)
+ ,.apb_pns_1 (1'b0)
+ ,.apb_psel (m_apb_psel)
+ ,.apb_psel_1 (1'b0)
+ ,.apb_puser (m_apb_puser)
+ ,.apb_puser_1 (13'b0)
+ ,.apb_pwdata (m_apb_pwdata)
+ ,.apb_pwdata_1 (32'b0)
+ ,.apb_pwrite (m_apb_pwrite)
+ ,.apb_pwrite_1 (1'b0)
+ ,.apb_pwstrb (m_apb_pwstrb)
+ ,.apb_pwstrb_1 (4'b0)
+ ,.apb_rstn (rstn)
+ ,.axi_0_arready (cl_dut_axi_0.arready)
+ ,.axi_0_awready (cl_dut_axi_0.awready)
+ ,.axi_0_bid ({6'b0, cl_dut_axi_0.bid}) // 14 bits
+ ,.axi_0_bresp (cl_dut_axi_0.bresp) // 2 bits
+ ,.axi_0_bvalid (cl_dut_axi_0.bvalid)
+ ,.axi_0_rdata (cl_dut_axi_0.rdata) // 256 bits
+ ,.axi_0_rid ({6'b0, cl_dut_axi_0.rid}) // 14 bits
+ ,.axi_0_rlast (cl_dut_axi_0.rlast)
+ ,.axi_0_rresp (cl_dut_axi_0.rresp) // 2 bits
+ ,.axi_0_rvalid (cl_dut_axi_0.rvalid)
+ ,.axi_0_wready (cl_dut_axi_0.wready)
+ ,.axi_1_arready (cl_dut_axi_1.arready)
+ ,.axi_1_awready (cl_dut_axi_1.awready)
+ ,.axi_1_bid ({6'b0, cl_dut_axi_1.bid})
+ ,.axi_1_bresp (cl_dut_axi_1.bresp)
+ ,.axi_1_bvalid (cl_dut_axi_1.bvalid)
+ ,.axi_1_rdata (cl_dut_axi_1.rdata)
+ ,.axi_1_rid ({6'b0, cl_dut_axi_1.rid})
+ ,.axi_1_rlast (cl_dut_axi_1.rlast)
+ ,.axi_1_rresp (cl_dut_axi_1.rresp)
+ ,.axi_1_rvalid (cl_dut_axi_1.rvalid)
+ ,.axi_1_wready (cl_dut_axi_1.wready)
+ ,.axi_2_arready (1'b1)
+ ,.axi_2_awready (1'b1)
+ ,.axi_2_bid (14'b0)
+ ,.axi_2_bresp (2'b0)
+ ,.axi_2_bvalid (1'b0)
+ ,.axi_2_rdata (256'b0)
+ ,.axi_2_rid (14'b0)
+ ,.axi_2_rlast (1'b0)
+ ,.axi_2_rresp (2'b0)
+ ,.axi_2_rvalid (1'b0)
+ ,.axi_2_wready (1'b1)
+ ,.axi_3_arready (1'b1)
+ ,.axi_3_awready (1'b1)
+ ,.axi_3_bid (14'b0)
+ ,.axi_3_bresp (2'b0)
+ ,.axi_3_bvalid (1'b0)
+ ,.axi_3_rdata (256'b0)
+ ,.axi_3_rid (14'b0)
+ ,.axi_3_rlast (1'b0)
+ ,.axi_3_rresp (2'b0)
+ ,.axi_3_rvalid (1'b0)
+ ,.axi_3_wready (1'b1)
+ ,.intr_in (32'b0)
+ // outputs
+ ,.apb_prdata (m_apb_prdata)
+ ,.apb_prdata_1 ()
+ ,.apb_pready (m_apb_pready)
+ ,.apb_pready_1 ()
+ ,.apb_pslverr (m_apb_pslverr)
+ ,.apb_pslverr_1 ()
+ ,.axi_0_araddr (axi_0_araddr)
+ ,.axi_0_arburst ()
+ ,.axi_0_arcache ()
+ ,.axi_0_arid (cl_dut_axi_0.arid)
+ ,.axi_0_arlen (cl_dut_axi_0.arlen)
+ ,.axi_0_arlock ()
+ ,.axi_0_arprot ()
+ ,.axi_0_arqos ()
+ ,.axi_0_arregion ()
+ ,.axi_0_arsize (cl_dut_axi_0.arsize)
+ ,.axi_0_aruser ()
+ ,.axi_0_arvalid (cl_dut_axi_0.arvalid)
+ ,.axi_0_awaddr (axi_0_awaddr)
+ ,.axi_0_awburst ()
+ ,.axi_0_awcache ()
+ ,.axi_0_awid (cl_dut_axi_0.awid)
+ ,.axi_0_awlen (cl_dut_axi_0.awlen)
+ ,.axi_0_awlock ()
+ ,.axi_0_awprot ()
+ ,.axi_0_awqos ()
+ ,.axi_0_awregion ()
+ ,.axi_0_awsize (cl_dut_axi_0.awsize)
+ ,.axi_0_awuser ()
+ ,.axi_0_awvalid (cl_dut_axi_0.awvalid)
+ ,.axi_0_bready (cl_dut_axi_0.bready)
+ ,.axi_0_rready (cl_dut_axi_0.rready)
+ ,.axi_0_wdata (cl_dut_axi_0.wdata)
+ ,.axi_0_wlast (cl_dut_axi_0.wlast)
+ ,.axi_0_wstrb (cl_dut_axi_0.wstrb)
+ ,.axi_0_wvalid (cl_dut_axi_0.wvalid)
+ ,.axi_1_araddr (axi_1_araddr)
+ ,.axi_1_arburst ()
+ ,.axi_1_arcache ()
+ ,.axi_1_arid (cl_dut_axi_1.arid)
+ ,.axi_1_arlen (cl_dut_axi_1.arlen)
+ ,.axi_1_arlock ()
+ ,.axi_1_arprot ()
+ ,.axi_1_arqos ()
+ ,.axi_1_arregion ()
+ ,.axi_1_arsize (cl_dut_axi_1.arsize)
+ ,.axi_1_aruser ()
+ ,.axi_1_arvalid (cl_dut_axi_1.arvalid)
+ ,.axi_1_awaddr (axi_1_awaddr)
+ ,.axi_1_awburst ()
+ ,.axi_1_awcache ()
+ ,.axi_1_awid (cl_dut_axi_1.awid)
+ ,.axi_1_awlen (cl_dut_axi_1.awlen)
+ ,.axi_1_awlock ()
+ ,.axi_1_awprot ()
+ ,.axi_1_awqos ()
+ ,.axi_1_awregion ()
+ ,.axi_1_awsize (cl_dut_axi_1.awsize)
+ ,.axi_1_awuser ()
+ ,.axi_1_awvalid (cl_dut_axi_1.awvalid)
+ ,.axi_1_bready (cl_dut_axi_1.bready)
+ ,.axi_1_rready (cl_dut_axi_1.rready)
+ ,.axi_1_wdata (cl_dut_axi_1.wdata)
+ ,.axi_1_wlast (cl_dut_axi_1.wlast)
+ ,.axi_1_wstrb (cl_dut_axi_1.wstrb)
+ ,.axi_1_wvalid (cl_dut_axi_1.wvalid)
+ ,.axi_2_araddr ()
+ ,.axi_2_arburst ()
+ ,.axi_2_arcache ()
+ ,.axi_2_arid ()
+ ,.axi_2_arlen ()
+ ,.axi_2_arlock ()
+ ,.axi_2_arprot ()
+ ,.axi_2_arqos ()
+ ,.axi_2_arregion ()
+ ,.axi_2_arsize ()
+ ,.axi_2_aruser ()
+ ,.axi_2_arvalid ()
+ ,.axi_2_awaddr ()
+ ,.axi_2_awburst ()
+ ,.axi_2_awcache ()
+ ,.axi_2_awid ()
+ ,.axi_2_awlen ()
+ ,.axi_2_awlock ()
+ ,.axi_2_awprot ()
+ ,.axi_2_awqos ()
+ ,.axi_2_awregion ()
+ ,.axi_2_awsize ()
+ ,.axi_2_awuser ()
+ ,.axi_2_awvalid ()
+ ,.axi_2_bready ()
+ ,.axi_2_rready ()
+ ,.axi_2_wdata ()
+ ,.axi_2_wlast ()
+ ,.axi_2_wstrb ()
+ ,.axi_2_wvalid ()
+ ,.axi_3_araddr ()
+ ,.axi_3_arburst ()
+ ,.axi_3_arcache ()
+ ,.axi_3_arid ()
+ ,.axi_3_arlen ()
+ ,.axi_3_arlock ()
+ ,.axi_3_arprot ()
+ ,.axi_3_arqos ()
+ ,.axi_3_arregion ()
+ ,.axi_3_arsize ()
+ ,.axi_3_aruser ()
+ ,.axi_3_arvalid ()
+ ,.axi_3_awaddr ()
+ ,.axi_3_awburst ()
+ ,.axi_3_awcache ()
+ ,.axi_3_awid ()
+ ,.axi_3_awlen ()
+ ,.axi_3_awlock ()
+ ,.axi_3_awprot ()
+ ,.axi_3_awqos ()
+ ,.axi_3_awregion ()
+ ,.axi_3_awsize ()
+ ,.axi_3_awuser ()
+ ,.axi_3_awvalid ()
+ ,.axi_3_bready ()
+ ,.axi_3_rready ()
+ ,.axi_3_wdata ()
+ ,.axi_3_wlast ()
+ ,.axi_3_wstrb ()
+ ,.axi_3_wvalid ()
+ ,.intr_out (irq_upstream[31:0]) // FIXME. need connect to interrupt transactor
+ );
+
+endmodule
diff --git a/cl_memdut/design/cl_vio.sv b/cl_memdut/design/cl_vio.sv
new file mode 100644
index 0000000..6605093
--- /dev/null
+++ b/cl_memdut/design/cl_vio.sv
@@ -0,0 +1,105 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+module cl_vio (
+ input clk_extra_a1
+
+);
+
+ // Counter running at 125MHz
+
+ logic vo_cnt_enable;
+ logic vo_cnt_load;
+ logic vo_cnt_clear;
+ logic vo_cnt_oneshot;
+ logic [7:0] vo_tick_value;
+ logic [15:0] vo_cnt_load_value;
+ logic [15:0] vo_cnt_watermark;
+
+ logic vo_cnt_enable_q = 0;
+ logic vo_cnt_load_q = 0;
+ logic vo_cnt_clear_q = 0;
+ logic vo_cnt_oneshot_q = 0;
+ logic [7:0] vo_tick_value_q = 0;
+ logic [15:0] vo_cnt_load_value_q = 0;
+ logic [15:0] vo_cnt_watermark_q = 0;
+
+ logic vi_tick;
+ logic vi_cnt_ge_watermark;
+ logic [7:0] vi_tick_cnt = 0;
+ logic [15:0] vi_cnt = 0;
+
+ // Tick counter and main counter
+ always @(posedge clk_extra_a1) begin
+
+ vo_cnt_enable_q <= vo_cnt_enable ;
+ vo_cnt_load_q <= vo_cnt_load ;
+ vo_cnt_clear_q <= vo_cnt_clear ;
+ vo_cnt_oneshot_q <= vo_cnt_oneshot ;
+ vo_tick_value_q <= vo_tick_value ;
+ vo_cnt_load_value_q <= vo_cnt_load_value;
+ vo_cnt_watermark_q <= vo_cnt_watermark ;
+
+ vi_tick_cnt = vo_cnt_clear_q ? 0 :
+ ~vo_cnt_enable_q ? vi_tick_cnt :
+ (vi_tick_cnt >= vo_tick_value_q) ? 0 :
+ vi_tick_cnt + 1;
+
+ vi_cnt = vo_cnt_clear_q ? 0 :
+ vo_cnt_load_q ? vo_cnt_load_value_q :
+ ~vo_cnt_enable_q ? vi_cnt :
+ (vi_tick_cnt >= vo_tick_value_q) && (~vo_cnt_oneshot_q || (vi_cnt <= 16'hFFFF)) ? vi_cnt + 1 :
+ vi_cnt;
+
+ vi_tick = (vi_tick_cnt >= vo_tick_value_q);
+
+ vi_cnt_ge_watermark = (vi_cnt >= vo_cnt_watermark_q);
+
+ end // always @ (posedge clk_extra_a1)
+
+
+ vio_0 CL_VIO_0 (
+ .clk (clk_extra_a1),
+ .probe_in0 (vi_tick),
+ .probe_in1 (vi_cnt_ge_watermark),
+ .probe_in2 (vi_tick_cnt),
+ .probe_in3 (vi_cnt),
+ .probe_out0 (vo_cnt_enable),
+ .probe_out1 (vo_cnt_load),
+ .probe_out2 (vo_cnt_clear),
+ .probe_out3 (vo_cnt_oneshot),
+ .probe_out4 (vo_tick_value),
+ .probe_out5 (vo_cnt_load_value),
+ .probe_out6 (vo_cnt_watermark)
+ );
+
+ ila_vio_counter CL_VIO_ILA (
+ .clk (clk_extra_a1),
+ .probe0 (vi_tick),
+ .probe1 (vi_cnt_ge_watermark),
+ .probe2 (vi_tick_cnt),
+ .probe3 (vi_cnt),
+ .probe4 (vo_cnt_enable_q),
+ .probe5 (vo_cnt_load_q),
+ .probe6 (vo_cnt_clear_q),
+ .probe7 (vo_cnt_oneshot_q),
+ .probe8 (vo_tick_value_q),
+ .probe9 (vo_cnt_load_value_q),
+ .probe10 (vo_cnt_watermark_q)
+ );
+
+
+endmodule
+
diff --git a/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut.v b/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut.v
new file mode 100644
index 0000000..f1210d2
--- /dev/null
+++ b/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut.v
@@ -0,0 +1,762 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: NV_FPGA_unit_checkbox_mem_dut.v
+
+`timescale 1ns/10ps
+module NV_FPGA_unit_checkbox_mem_dut (
+ apb_clk //|< i
+ ,apb_paddr //|< i
+ ,apb_paddr_1 //|< i
+ ,apb_penable //|< i
+ ,apb_penable_1 //|< i
+ ,apb_pns //|< i
+ ,apb_pns_1 //|< i
+ ,apb_psel //|< i
+ ,apb_psel_1 //|< i
+ ,apb_puser //|< i
+ ,apb_puser_1 //|< i
+ ,apb_pwdata //|< i
+ ,apb_pwdata_1 //|< i
+ ,apb_pwrite //|< i
+ ,apb_pwrite_1 //|< i
+ ,apb_pwstrb //|< i
+ ,apb_pwstrb_1 //|< i
+ ,apb_rstn //|< i
+ ,axi_0_arready //|< i
+ ,axi_0_awready //|< i
+ ,axi_0_bid //|< i
+ ,axi_0_bresp //|< i
+ ,axi_0_bvalid //|< i
+ ,axi_0_rdata //|< i
+ ,axi_0_rid //|< i
+ ,axi_0_rlast //|< i
+ ,axi_0_rresp //|< i
+ ,axi_0_rvalid //|< i
+ ,axi_0_wready //|< i
+ ,axi_1_arready //|< i
+ ,axi_1_awready //|< i
+ ,axi_1_bid //|< i
+ ,axi_1_bresp //|< i
+ ,axi_1_bvalid //|< i
+ ,axi_1_rdata //|< i
+ ,axi_1_rid //|< i
+ ,axi_1_rlast //|< i
+ ,axi_1_rresp //|< i
+ ,axi_1_rvalid //|< i
+ ,axi_1_wready //|< i
+ ,axi_2_arready //|< i
+ ,axi_2_awready //|< i
+ ,axi_2_bid //|< i
+ ,axi_2_bresp //|< i
+ ,axi_2_bvalid //|< i
+ ,axi_2_rdata //|< i
+ ,axi_2_rid //|< i
+ ,axi_2_rlast //|< i
+ ,axi_2_rresp //|< i
+ ,axi_2_rvalid //|< i
+ ,axi_2_wready //|< i
+ ,axi_3_arready //|< i
+ ,axi_3_awready //|< i
+ ,axi_3_bid //|< i
+ ,axi_3_bresp //|< i
+ ,axi_3_bvalid //|< i
+ ,axi_3_rdata //|< i
+ ,axi_3_rid //|< i
+ ,axi_3_rlast //|< i
+ ,axi_3_rresp //|< i
+ ,axi_3_rvalid //|< i
+ ,axi_3_wready //|< i
+ ,intr_in //|< i
+ ,apb_prdata //|> o
+ ,apb_prdata_1 //|> o
+ ,apb_pready //|> o
+ ,apb_pready_1 //|> o
+ ,apb_pslverr //|> o
+ ,apb_pslverr_1 //|> o
+ ,axi_0_araddr //|> o
+ ,axi_0_arburst //|> o
+ ,axi_0_arcache //|> o
+ ,axi_0_arid //|> o
+ ,axi_0_arlen //|> o
+ ,axi_0_arlock //|> o
+ ,axi_0_arprot //|> o
+ ,axi_0_arqos //|> o
+ ,axi_0_arregion //|> o
+ ,axi_0_arsize //|> o
+ ,axi_0_aruser //|> o
+ ,axi_0_arvalid //|> o
+ ,axi_0_awaddr //|> o
+ ,axi_0_awburst //|> o
+ ,axi_0_awcache //|> o
+ ,axi_0_awid //|> o
+ ,axi_0_awlen //|> o
+ ,axi_0_awlock //|> o
+ ,axi_0_awprot //|> o
+ ,axi_0_awqos //|> o
+ ,axi_0_awregion //|> o
+ ,axi_0_awsize //|> o
+ ,axi_0_awuser //|> o
+ ,axi_0_awvalid //|> o
+ ,axi_0_bready //|> o
+ ,axi_0_rready //|> o
+ ,axi_0_wdata //|> o
+ ,axi_0_wlast //|> o
+ ,axi_0_wstrb //|> o
+ ,axi_0_wvalid //|> o
+ ,axi_1_araddr //|> o
+ ,axi_1_arburst //|> o
+ ,axi_1_arcache //|> o
+ ,axi_1_arid //|> o
+ ,axi_1_arlen //|> o
+ ,axi_1_arlock //|> o
+ ,axi_1_arprot //|> o
+ ,axi_1_arqos //|> o
+ ,axi_1_arregion //|> o
+ ,axi_1_arsize //|> o
+ ,axi_1_aruser //|> o
+ ,axi_1_arvalid //|> o
+ ,axi_1_awaddr //|> o
+ ,axi_1_awburst //|> o
+ ,axi_1_awcache //|> o
+ ,axi_1_awid //|> o
+ ,axi_1_awlen //|> o
+ ,axi_1_awlock //|> o
+ ,axi_1_awprot //|> o
+ ,axi_1_awqos //|> o
+ ,axi_1_awregion //|> o
+ ,axi_1_awsize //|> o
+ ,axi_1_awuser //|> o
+ ,axi_1_awvalid //|> o
+ ,axi_1_bready //|> o
+ ,axi_1_rready //|> o
+ ,axi_1_wdata //|> o
+ ,axi_1_wlast //|> o
+ ,axi_1_wstrb //|> o
+ ,axi_1_wvalid //|> o
+ ,axi_2_araddr //|> o
+ ,axi_2_arburst //|> o
+ ,axi_2_arcache //|> o
+ ,axi_2_arid //|> o
+ ,axi_2_arlen //|> o
+ ,axi_2_arlock //|> o
+ ,axi_2_arprot //|> o
+ ,axi_2_arqos //|> o
+ ,axi_2_arregion //|> o
+ ,axi_2_arsize //|> o
+ ,axi_2_aruser //|> o
+ ,axi_2_arvalid //|> o
+ ,axi_2_awaddr //|> o
+ ,axi_2_awburst //|> o
+ ,axi_2_awcache //|> o
+ ,axi_2_awid //|> o
+ ,axi_2_awlen //|> o
+ ,axi_2_awlock //|> o
+ ,axi_2_awprot //|> o
+ ,axi_2_awqos //|> o
+ ,axi_2_awregion //|> o
+ ,axi_2_awsize //|> o
+ ,axi_2_awuser //|> o
+ ,axi_2_awvalid //|> o
+ ,axi_2_bready //|> o
+ ,axi_2_rready //|> o
+ ,axi_2_wdata //|> o
+ ,axi_2_wlast //|> o
+ ,axi_2_wstrb //|> o
+ ,axi_2_wvalid //|> o
+ ,axi_3_araddr //|> o
+ ,axi_3_arburst //|> o
+ ,axi_3_arcache //|> o
+ ,axi_3_arid //|> o
+ ,axi_3_arlen //|> o
+ ,axi_3_arlock //|> o
+ ,axi_3_arprot //|> o
+ ,axi_3_arqos //|> o
+ ,axi_3_arregion //|> o
+ ,axi_3_arsize //|> o
+ ,axi_3_aruser //|> o
+ ,axi_3_arvalid //|> o
+ ,axi_3_awaddr //|> o
+ ,axi_3_awburst //|> o
+ ,axi_3_awcache //|> o
+ ,axi_3_awid //|> o
+ ,axi_3_awlen //|> o
+ ,axi_3_awlock //|> o
+ ,axi_3_awprot //|> o
+ ,axi_3_awqos //|> o
+ ,axi_3_awregion //|> o
+ ,axi_3_awsize //|> o
+ ,axi_3_awuser //|> o
+ ,axi_3_awvalid //|> o
+ ,axi_3_bready //|> o
+ ,axi_3_rready //|> o
+ ,axi_3_wdata //|> o
+ ,axi_3_wlast //|> o
+ ,axi_3_wstrb //|> o
+ ,axi_3_wvalid //|> o
+ ,intr_out //|> o
+ );
+input apb_clk;
+input [23:0] apb_paddr;
+input [23:0] apb_paddr_1;
+input apb_penable;
+input apb_penable_1;
+input apb_pns;
+input apb_pns_1;
+input apb_psel;
+input apb_psel_1;
+input [12:0] apb_puser;
+input [12:0] apb_puser_1;
+input [31:0] apb_pwdata;
+input [31:0] apb_pwdata_1;
+input apb_pwrite;
+input apb_pwrite_1;
+input [3:0] apb_pwstrb;
+input [3:0] apb_pwstrb_1;
+input apb_rstn;
+input axi_0_arready;
+input axi_0_awready;
+input [13:0] axi_0_bid;
+input [1:0] axi_0_bresp;
+input axi_0_bvalid;
+input [255:0] axi_0_rdata;
+input [13:0] axi_0_rid;
+input axi_0_rlast;
+input [1:0] axi_0_rresp;
+input axi_0_rvalid;
+input axi_0_wready;
+input axi_1_arready;
+input axi_1_awready;
+input [13:0] axi_1_bid;
+input [1:0] axi_1_bresp;
+input axi_1_bvalid;
+input [255:0] axi_1_rdata;
+input [13:0] axi_1_rid;
+input axi_1_rlast;
+input [1:0] axi_1_rresp;
+input axi_1_rvalid;
+input axi_1_wready;
+input axi_2_arready;
+input axi_2_awready;
+input [13:0] axi_2_bid;
+input [1:0] axi_2_bresp;
+input axi_2_bvalid;
+input [255:0] axi_2_rdata;
+input [13:0] axi_2_rid;
+input axi_2_rlast;
+input [1:0] axi_2_rresp;
+input axi_2_rvalid;
+input axi_2_wready;
+input axi_3_arready;
+input axi_3_awready;
+input [13:0] axi_3_bid;
+input [1:0] axi_3_bresp;
+input axi_3_bvalid;
+input [255:0] axi_3_rdata;
+input [13:0] axi_3_rid;
+input axi_3_rlast;
+input [1:0] axi_3_rresp;
+input axi_3_rvalid;
+input axi_3_wready;
+input [31:0] intr_in;
+output [31:0] apb_prdata;
+output [31:0] apb_prdata_1;
+output apb_pready;
+output apb_pready_1;
+output apb_pslverr;
+output apb_pslverr_1;
+output [39:0] axi_0_araddr;
+output [1:0] axi_0_arburst;
+output [3:0] axi_0_arcache;
+output [13:0] axi_0_arid;
+output [7:0] axi_0_arlen;
+output [1:0] axi_0_arlock;
+output [2:0] axi_0_arprot;
+output [3:0] axi_0_arqos;
+output [3:0] axi_0_arregion;
+output [2:0] axi_0_arsize;
+output [25:0] axi_0_aruser;
+output axi_0_arvalid;
+output [39:0] axi_0_awaddr;
+output [1:0] axi_0_awburst;
+output [3:0] axi_0_awcache;
+output [13:0] axi_0_awid;
+output [7:0] axi_0_awlen;
+output [1:0] axi_0_awlock;
+output [2:0] axi_0_awprot;
+output [3:0] axi_0_awqos;
+output [3:0] axi_0_awregion;
+output [2:0] axi_0_awsize;
+output [25:0] axi_0_awuser;
+output axi_0_awvalid;
+output axi_0_bready;
+output axi_0_rready;
+output [255:0] axi_0_wdata;
+output axi_0_wlast;
+output [31:0] axi_0_wstrb;
+output axi_0_wvalid;
+output [39:0] axi_1_araddr;
+output [1:0] axi_1_arburst;
+output [3:0] axi_1_arcache;
+output [13:0] axi_1_arid;
+output [7:0] axi_1_arlen;
+output [1:0] axi_1_arlock;
+output [2:0] axi_1_arprot;
+output [3:0] axi_1_arqos;
+output [3:0] axi_1_arregion;
+output [2:0] axi_1_arsize;
+output [25:0] axi_1_aruser;
+output axi_1_arvalid;
+output [39:0] axi_1_awaddr;
+output [1:0] axi_1_awburst;
+output [3:0] axi_1_awcache;
+output [13:0] axi_1_awid;
+output [7:0] axi_1_awlen;
+output [1:0] axi_1_awlock;
+output [2:0] axi_1_awprot;
+output [3:0] axi_1_awqos;
+output [3:0] axi_1_awregion;
+output [2:0] axi_1_awsize;
+output [25:0] axi_1_awuser;
+output axi_1_awvalid;
+output axi_1_bready;
+output axi_1_rready;
+output [255:0] axi_1_wdata;
+output axi_1_wlast;
+output [31:0] axi_1_wstrb;
+output axi_1_wvalid;
+output [39:0] axi_2_araddr;
+output [1:0] axi_2_arburst;
+output [3:0] axi_2_arcache;
+output [13:0] axi_2_arid;
+output [7:0] axi_2_arlen;
+output [1:0] axi_2_arlock;
+output [2:0] axi_2_arprot;
+output [3:0] axi_2_arqos;
+output [3:0] axi_2_arregion;
+output [2:0] axi_2_arsize;
+output [25:0] axi_2_aruser;
+output axi_2_arvalid;
+output [39:0] axi_2_awaddr;
+output [1:0] axi_2_awburst;
+output [3:0] axi_2_awcache;
+output [13:0] axi_2_awid;
+output [7:0] axi_2_awlen;
+output [1:0] axi_2_awlock;
+output [2:0] axi_2_awprot;
+output [3:0] axi_2_awqos;
+output [3:0] axi_2_awregion;
+output [2:0] axi_2_awsize;
+output [25:0] axi_2_awuser;
+output axi_2_awvalid;
+output axi_2_bready;
+output axi_2_rready;
+output [255:0] axi_2_wdata;
+output axi_2_wlast;
+output [31:0] axi_2_wstrb;
+output axi_2_wvalid;
+output [39:0] axi_3_araddr;
+output [1:0] axi_3_arburst;
+output [3:0] axi_3_arcache;
+output [13:0] axi_3_arid;
+output [7:0] axi_3_arlen;
+output [1:0] axi_3_arlock;
+output [2:0] axi_3_arprot;
+output [3:0] axi_3_arqos;
+output [3:0] axi_3_arregion;
+output [2:0] axi_3_arsize;
+output [25:0] axi_3_aruser;
+output axi_3_arvalid;
+output [39:0] axi_3_awaddr;
+output [1:0] axi_3_awburst;
+output [3:0] axi_3_awcache;
+output [13:0] axi_3_awid;
+output [7:0] axi_3_awlen;
+output [1:0] axi_3_awlock;
+output [2:0] axi_3_awprot;
+output [3:0] axi_3_awqos;
+output [3:0] axi_3_awregion;
+output [2:0] axi_3_awsize;
+output [25:0] axi_3_awuser;
+output axi_3_awvalid;
+output axi_3_bready;
+output axi_3_rready;
+output [255:0] axi_3_wdata;
+output axi_3_wlast;
+output [31:0] axi_3_wstrb;
+output axi_3_wvalid;
+output [31:0] intr_out;
+wire apb_wr_op;
+wire axi_0_cmd_ram_sel;
+wire [23:0] axi_0_paddr;
+wire [31:0] axi_0_prdata;
+wire axi_0_rdata_ram_sel;
+wire axi_0_reg_sel;
+wire axi_0_wdata_ram_sel;
+wire axi_0_wstrb_ram_sel;
+wire axi_1_cmd_ram_sel;
+wire [23:0] axi_1_paddr;
+wire [31:0] axi_1_prdata;
+wire axi_1_rdata_ram_sel;
+wire axi_1_reg_sel;
+wire axi_1_wdata_ram_sel;
+wire axi_1_wstrb_ram_sel;
+wire axi_2_cmd_ram_sel;
+wire [23:0] axi_2_paddr;
+wire [31:0] axi_2_prdata;
+wire axi_2_rdata_ram_sel;
+wire axi_2_reg_sel;
+wire axi_2_wdata_ram_sel;
+wire axi_2_wstrb_ram_sel;
+wire axi_3_cmd_ram_sel;
+wire [23:0] axi_3_paddr;
+wire [31:0] axi_3_prdata;
+wire axi_3_rdata_ram_sel;
+wire axi_3_reg_sel;
+wire axi_3_wdata_ram_sel;
+wire axi_3_wstrb_ram_sel;
+wire test_complete_0;
+wire test_complete_1;
+wire test_complete_2;
+wire test_complete_3;
+
+parameter APB_TRAN_BASE_ADDR = 24'h000000;
+parameter MEM_DUT_AXI_PORT_SPACE = 24'h100000;
+
+parameter APB_TRAN_BASE_ADDR_1 = 24'hB00000;
+
+NV_FPGA_unit_checkbox_mem_dut_apb_slave #( .APB_BASE_ADDR(APB_TRAN_BASE_ADDR), .AXI_PORT_SPACE(MEM_DUT_AXI_PORT_SPACE)) u_apb_slave (
+ .apb_clk (apb_clk) //|< i
+ ,.apb_rstn (apb_rstn) //|< i
+ ,.apb_paddr (apb_paddr[23:0]) //|< i
+ ,.apb_penable (apb_penable) //|< i
+ ,.apb_pns (apb_pns) //|< i
+ ,.apb_psel (apb_psel) //|< i
+ ,.apb_puser (apb_puser[12:0]) //|< i
+ ,.apb_pwdata (apb_pwdata[31:0]) //|< i
+ ,.apb_pwrite (apb_pwrite) //|< i
+ ,.apb_pwstrb (apb_pwstrb[3:0]) //|< i
+ ,.axi_0_prdata (axi_0_prdata[31:0]) //|< w
+ ,.axi_1_prdata (axi_1_prdata[31:0]) //|< w
+ ,.axi_2_prdata (axi_2_prdata[31:0]) //|< w
+ ,.axi_3_prdata (axi_3_prdata[31:0]) //|< w
+ ,.intr_in (intr_in[31:0]) //|< i
+ ,.test_complete_0 (test_complete_0) //|< w
+ ,.test_complete_1 (test_complete_1) //|< w
+ ,.test_complete_2 (test_complete_2) //|< w
+ ,.test_complete_3 (test_complete_3) //|< w
+ ,.apb_prdata (apb_prdata[31:0]) //|> o
+ ,.apb_pready (apb_pready) //|> o
+ ,.apb_pslverr (apb_pslverr) //|> o
+ ,.apb_wr_op (apb_wr_op) //|> w
+ ,.axi_0_cmd_ram_sel (axi_0_cmd_ram_sel) //|> w
+ ,.axi_0_paddr (axi_0_paddr[23:0]) //|> w
+ ,.axi_0_rdata_ram_sel (axi_0_rdata_ram_sel) //|> w
+ ,.axi_0_reg_sel (axi_0_reg_sel) //|> w
+ ,.axi_0_wdata_ram_sel (axi_0_wdata_ram_sel) //|> w
+ ,.axi_0_wstrb_ram_sel (axi_0_wstrb_ram_sel) //|> w
+ ,.axi_1_cmd_ram_sel (axi_1_cmd_ram_sel) //|> w
+ ,.axi_1_paddr (axi_1_paddr[23:0]) //|> w
+ ,.axi_1_rdata_ram_sel (axi_1_rdata_ram_sel) //|> w
+ ,.axi_1_reg_sel (axi_1_reg_sel) //|> w
+ ,.axi_1_wdata_ram_sel (axi_1_wdata_ram_sel) //|> w
+ ,.axi_1_wstrb_ram_sel (axi_1_wstrb_ram_sel) //|> w
+ ,.axi_2_cmd_ram_sel (axi_2_cmd_ram_sel) //|> w
+ ,.axi_2_paddr (axi_2_paddr[23:0]) //|> w
+ ,.axi_2_rdata_ram_sel (axi_2_rdata_ram_sel) //|> w
+ ,.axi_2_reg_sel (axi_2_reg_sel) //|> w
+ ,.axi_2_wdata_ram_sel (axi_2_wdata_ram_sel) //|> w
+ ,.axi_2_wstrb_ram_sel (axi_2_wstrb_ram_sel) //|> w
+ ,.axi_3_cmd_ram_sel (axi_3_cmd_ram_sel) //|> w
+ ,.axi_3_paddr (axi_3_paddr[23:0]) //|> w
+ ,.axi_3_rdata_ram_sel (axi_3_rdata_ram_sel) //|> w
+ ,.axi_3_reg_sel (axi_3_reg_sel) //|> w
+ ,.axi_3_wdata_ram_sel (axi_3_wdata_ram_sel) //|> w
+ ,.axi_3_wstrb_ram_sel (axi_3_wstrb_ram_sel) //|> w
+ ,.intr_out (intr_out[31:0]) //|> o
+ );
+
+NV_FPGA_unit_checkbox_mem_dut_apb_slave #( .APB_BASE_ADDR(APB_TRAN_BASE_ADDR_1), .AXI_PORT_SPACE(MEM_DUT_AXI_PORT_SPACE)) u_apb_slave_1 (
+ .apb_clk (apb_clk) //|< i
+ ,.apb_rstn (apb_rstn) //|< i
+ ,.apb_paddr (apb_paddr_1[23:0]) //|< i
+ ,.apb_penable (apb_penable_1) //|< i
+ ,.apb_pns (apb_pns_1) //|< i
+ ,.apb_psel (apb_psel_1) //|< i
+ ,.apb_puser (apb_puser_1[12:0]) //|< i
+ ,.apb_pwdata (apb_pwdata_1[31:0]) //|< i
+ ,.apb_pwrite (apb_pwrite_1) //|< i
+ ,.apb_pwstrb (apb_pwstrb_1[3:0]) //|< i
+ ,.axi_0_prdata ({32{1'b0}}) //|< ?
+ ,.axi_1_prdata ({32{1'b0}}) //|< ?
+ ,.axi_2_prdata ({32{1'b0}}) //|< ?
+ ,.axi_3_prdata ({32{1'b0}}) //|< ?
+ ,.intr_in ({32{1'b0}}) //|< ?
+ ,.test_complete_0 ({1{1'b0}}) //|< ?
+ ,.test_complete_1 ({1{1'b0}}) //|< ?
+ ,.test_complete_2 ({1{1'b0}}) //|< ?
+ ,.test_complete_3 ({1{1'b0}}) //|< ?
+ ,.apb_prdata (apb_prdata_1[31:0]) //|> o
+ ,.apb_pready (apb_pready_1) //|> o
+ ,.apb_pslverr (apb_pslverr_1) //|> o
+ ,.apb_wr_op () //|> ?
+ ,.axi_0_cmd_ram_sel () //|> ?
+ ,.axi_0_paddr () //|> ?
+ ,.axi_0_rdata_ram_sel () //|> ?
+ ,.axi_0_reg_sel () //|> ?
+ ,.axi_0_wdata_ram_sel () //|> ?
+ ,.axi_0_wstrb_ram_sel () //|> ?
+ ,.axi_1_cmd_ram_sel () //|> ?
+ ,.axi_1_paddr () //|> ?
+ ,.axi_1_rdata_ram_sel () //|> ?
+ ,.axi_1_reg_sel () //|> ?
+ ,.axi_1_wdata_ram_sel () //|> ?
+ ,.axi_1_wstrb_ram_sel () //|> ?
+ ,.axi_2_cmd_ram_sel () //|> ?
+ ,.axi_2_paddr () //|> ?
+ ,.axi_2_rdata_ram_sel () //|> ?
+ ,.axi_2_reg_sel () //|> ?
+ ,.axi_2_wdata_ram_sel () //|> ?
+ ,.axi_2_wstrb_ram_sel () //|> ?
+ ,.axi_3_cmd_ram_sel () //|> ?
+ ,.axi_3_paddr () //|> ?
+ ,.axi_3_rdata_ram_sel () //|> ?
+ ,.axi_3_reg_sel () //|> ?
+ ,.axi_3_wdata_ram_sel () //|> ?
+ ,.axi_3_wstrb_ram_sel () //|> ?
+ ,.intr_out () //|> ?
+ );
+
+//Instance AXI Master PORT 0
+NV_FPGA_unit_checkbox_mem_dut_axi_256_256 axi_master_0 (
+ .apb_clk (apb_clk) //|< i
+ ,.apb_rstn (apb_rstn) //|< i
+ ,.apb_wr_op (apb_wr_op) //|< w
+ ,.axi_arready (axi_0_arready) //|< i
+ ,.axi_awready (axi_0_awready) //|< i
+ ,.axi_bid (axi_0_bid[13:0]) //|< i
+ ,.axi_bresp (axi_0_bresp[1:0]) //|< i
+ ,.axi_bvalid (axi_0_bvalid) //|< i
+ ,.axi_cmd_ram_sel (axi_0_cmd_ram_sel) //|< w
+ ,.axi_paddr (axi_0_paddr[19:0]) //|< w
+ ,.axi_pwdata (apb_pwdata[31:0]) //|< i
+ ,.axi_rdata (axi_0_rdata[255:0]) //|< i
+ ,.axi_rdata_ram_sel (axi_0_rdata_ram_sel) //|< w
+ ,.axi_reg_sel (axi_0_reg_sel) //|< w
+ ,.axi_rid (axi_0_rid[13:0]) //|< i
+ ,.axi_rlast (axi_0_rlast) //|< i
+ ,.axi_rresp (axi_0_rresp[1:0]) //|< i
+ ,.axi_rvalid (axi_0_rvalid) //|< i
+ ,.axi_wdata_ram_sel (axi_0_wdata_ram_sel) //|< w
+ ,.axi_wready (axi_0_wready) //|< i
+ ,.axi_wstrb_ram_sel (axi_0_wstrb_ram_sel) //|< w
+ ,.axi_araddr (axi_0_araddr[39:0]) //|> o
+ ,.axi_arburst (axi_0_arburst[1:0]) //|> o
+ ,.axi_arcache (axi_0_arcache[3:0]) //|> o
+ ,.axi_arid (axi_0_arid[13:0]) //|> o
+ ,.axi_arlen (axi_0_arlen[7:0]) //|> o
+ ,.axi_arlock (axi_0_arlock[1:0]) //|> o
+ ,.axi_arprot (axi_0_arprot[2:0]) //|> o
+ ,.axi_arqos (axi_0_arqos[3:0]) //|> o
+ ,.axi_arregion (axi_0_arregion[3:0]) //|> o
+ ,.axi_arsize (axi_0_arsize[2:0]) //|> o
+ ,.axi_aruser (axi_0_aruser[25:0]) //|> o
+ ,.axi_arvalid (axi_0_arvalid) //|> o
+ ,.axi_awaddr (axi_0_awaddr[39:0]) //|> o
+ ,.axi_awburst (axi_0_awburst[1:0]) //|> o
+ ,.axi_awcache (axi_0_awcache[3:0]) //|> o
+ ,.axi_awid (axi_0_awid[13:0]) //|> o
+ ,.axi_awlen (axi_0_awlen[7:0]) //|> o
+ ,.axi_awlock (axi_0_awlock[1:0]) //|> o
+ ,.axi_awprot (axi_0_awprot[2:0]) //|> o
+ ,.axi_awqos (axi_0_awqos[3:0]) //|> o
+ ,.axi_awregion (axi_0_awregion[3:0]) //|> o
+ ,.axi_awsize (axi_0_awsize[2:0]) //|> o
+ ,.axi_awuser (axi_0_awuser[25:0]) //|> o
+ ,.axi_awvalid (axi_0_awvalid) //|> o
+ ,.axi_bready (axi_0_bready) //|> o
+ ,.axi_prdata (axi_0_prdata[31:0]) //|> w
+ ,.axi_rready (axi_0_rready) //|> o
+ ,.axi_wdata (axi_0_wdata[255:0]) //|> o
+ ,.axi_wlast (axi_0_wlast) //|> o
+ ,.axi_wstrb (axi_0_wstrb[31:0]) //|> o
+ ,.axi_wvalid (axi_0_wvalid) //|> o
+ ,.test_complete (test_complete_0) //|> w
+ );
+//Instance AXI Master PORT 1
+NV_FPGA_unit_checkbox_mem_dut_axi_256_256 axi_master_1 (
+ .apb_clk (apb_clk) //|< i
+ ,.apb_rstn (apb_rstn) //|< i
+ ,.apb_wr_op (apb_wr_op) //|< w
+ ,.axi_arready (axi_1_arready) //|< i
+ ,.axi_awready (axi_1_awready) //|< i
+ ,.axi_bid (axi_1_bid[13:0]) //|< i
+ ,.axi_bresp (axi_1_bresp[1:0]) //|< i
+ ,.axi_bvalid (axi_1_bvalid) //|< i
+ ,.axi_cmd_ram_sel (axi_1_cmd_ram_sel) //|< w
+ ,.axi_paddr (axi_1_paddr[19:0]) //|< w
+ ,.axi_pwdata (apb_pwdata[31:0]) //|< i
+ ,.axi_rdata (axi_1_rdata[255:0]) //|< i
+ ,.axi_rdata_ram_sel (axi_1_rdata_ram_sel) //|< w
+ ,.axi_reg_sel (axi_1_reg_sel) //|< w
+ ,.axi_rid (axi_1_rid[13:0]) //|< i
+ ,.axi_rlast (axi_1_rlast) //|< i
+ ,.axi_rresp (axi_1_rresp[1:0]) //|< i
+ ,.axi_rvalid (axi_1_rvalid) //|< i
+ ,.axi_wdata_ram_sel (axi_1_wdata_ram_sel) //|< w
+ ,.axi_wready (axi_1_wready) //|< i
+ ,.axi_wstrb_ram_sel (axi_1_wstrb_ram_sel) //|< w
+ ,.axi_araddr (axi_1_araddr[39:0]) //|> o
+ ,.axi_arburst (axi_1_arburst[1:0]) //|> o
+ ,.axi_arcache (axi_1_arcache[3:0]) //|> o
+ ,.axi_arid (axi_1_arid[13:0]) //|> o
+ ,.axi_arlen (axi_1_arlen[7:0]) //|> o
+ ,.axi_arlock (axi_1_arlock[1:0]) //|> o
+ ,.axi_arprot (axi_1_arprot[2:0]) //|> o
+ ,.axi_arqos (axi_1_arqos[3:0]) //|> o
+ ,.axi_arregion (axi_1_arregion[3:0]) //|> o
+ ,.axi_arsize (axi_1_arsize[2:0]) //|> o
+ ,.axi_aruser (axi_1_aruser[25:0]) //|> o
+ ,.axi_arvalid (axi_1_arvalid) //|> o
+ ,.axi_awaddr (axi_1_awaddr[39:0]) //|> o
+ ,.axi_awburst (axi_1_awburst[1:0]) //|> o
+ ,.axi_awcache (axi_1_awcache[3:0]) //|> o
+ ,.axi_awid (axi_1_awid[13:0]) //|> o
+ ,.axi_awlen (axi_1_awlen[7:0]) //|> o
+ ,.axi_awlock (axi_1_awlock[1:0]) //|> o
+ ,.axi_awprot (axi_1_awprot[2:0]) //|> o
+ ,.axi_awqos (axi_1_awqos[3:0]) //|> o
+ ,.axi_awregion (axi_1_awregion[3:0]) //|> o
+ ,.axi_awsize (axi_1_awsize[2:0]) //|> o
+ ,.axi_awuser (axi_1_awuser[25:0]) //|> o
+ ,.axi_awvalid (axi_1_awvalid) //|> o
+ ,.axi_bready (axi_1_bready) //|> o
+ ,.axi_prdata (axi_1_prdata[31:0]) //|> w
+ ,.axi_rready (axi_1_rready) //|> o
+ ,.axi_wdata (axi_1_wdata[255:0]) //|> o
+ ,.axi_wlast (axi_1_wlast) //|> o
+ ,.axi_wstrb (axi_1_wstrb[31:0]) //|> o
+ ,.axi_wvalid (axi_1_wvalid) //|> o
+ ,.test_complete (test_complete_1) //|> w
+ );
+//Instance AXI Master PORT 2
+NV_FPGA_unit_checkbox_mem_dut_axi_256_256 axi_master_2 (
+ .apb_clk (apb_clk) //|< i
+ ,.apb_rstn (apb_rstn) //|< i
+ ,.apb_wr_op (apb_wr_op) //|< w
+ ,.axi_arready (axi_2_arready) //|< i
+ ,.axi_awready (axi_2_awready) //|< i
+ ,.axi_bid (axi_2_bid[13:0]) //|< i
+ ,.axi_bresp (axi_2_bresp[1:0]) //|< i
+ ,.axi_bvalid (axi_2_bvalid) //|< i
+ ,.axi_cmd_ram_sel (axi_2_cmd_ram_sel) //|< w
+ ,.axi_paddr (axi_2_paddr[19:0]) //|< w
+ ,.axi_pwdata (apb_pwdata[31:0]) //|< i
+ ,.axi_rdata (axi_2_rdata[255:0]) //|< i
+ ,.axi_rdata_ram_sel (axi_2_rdata_ram_sel) //|< w
+ ,.axi_reg_sel (axi_2_reg_sel) //|< w
+ ,.axi_rid (axi_2_rid[13:0]) //|< i
+ ,.axi_rlast (axi_2_rlast) //|< i
+ ,.axi_rresp (axi_2_rresp[1:0]) //|< i
+ ,.axi_rvalid (axi_2_rvalid) //|< i
+ ,.axi_wdata_ram_sel (axi_2_wdata_ram_sel) //|< w
+ ,.axi_wready (axi_2_wready) //|< i
+ ,.axi_wstrb_ram_sel (axi_2_wstrb_ram_sel) //|< w
+ ,.axi_araddr (axi_2_araddr[39:0]) //|> o
+ ,.axi_arburst (axi_2_arburst[1:0]) //|> o
+ ,.axi_arcache (axi_2_arcache[3:0]) //|> o
+ ,.axi_arid (axi_2_arid[13:0]) //|> o
+ ,.axi_arlen (axi_2_arlen[7:0]) //|> o
+ ,.axi_arlock (axi_2_arlock[1:0]) //|> o
+ ,.axi_arprot (axi_2_arprot[2:0]) //|> o
+ ,.axi_arqos (axi_2_arqos[3:0]) //|> o
+ ,.axi_arregion (axi_2_arregion[3:0]) //|> o
+ ,.axi_arsize (axi_2_arsize[2:0]) //|> o
+ ,.axi_aruser (axi_2_aruser[25:0]) //|> o
+ ,.axi_arvalid (axi_2_arvalid) //|> o
+ ,.axi_awaddr (axi_2_awaddr[39:0]) //|> o
+ ,.axi_awburst (axi_2_awburst[1:0]) //|> o
+ ,.axi_awcache (axi_2_awcache[3:0]) //|> o
+ ,.axi_awid (axi_2_awid[13:0]) //|> o
+ ,.axi_awlen (axi_2_awlen[7:0]) //|> o
+ ,.axi_awlock (axi_2_awlock[1:0]) //|> o
+ ,.axi_awprot (axi_2_awprot[2:0]) //|> o
+ ,.axi_awqos (axi_2_awqos[3:0]) //|> o
+ ,.axi_awregion (axi_2_awregion[3:0]) //|> o
+ ,.axi_awsize (axi_2_awsize[2:0]) //|> o
+ ,.axi_awuser (axi_2_awuser[25:0]) //|> o
+ ,.axi_awvalid (axi_2_awvalid) //|> o
+ ,.axi_bready (axi_2_bready) //|> o
+ ,.axi_prdata (axi_2_prdata[31:0]) //|> w
+ ,.axi_rready (axi_2_rready) //|> o
+ ,.axi_wdata (axi_2_wdata[255:0]) //|> o
+ ,.axi_wlast (axi_2_wlast) //|> o
+ ,.axi_wstrb (axi_2_wstrb[31:0]) //|> o
+ ,.axi_wvalid (axi_2_wvalid) //|> o
+ ,.test_complete (test_complete_2) //|> w
+ );
+//Instance AXI Master PORT 3
+NV_FPGA_unit_checkbox_mem_dut_axi_256_256 axi_master_3 (
+ .apb_clk (apb_clk) //|< i
+ ,.apb_rstn (apb_rstn) //|< i
+ ,.apb_wr_op (apb_wr_op) //|< w
+ ,.axi_arready (axi_3_arready) //|< i
+ ,.axi_awready (axi_3_awready) //|< i
+ ,.axi_bid (axi_3_bid[13:0]) //|< i
+ ,.axi_bresp (axi_3_bresp[1:0]) //|< i
+ ,.axi_bvalid (axi_3_bvalid) //|< i
+ ,.axi_cmd_ram_sel (axi_3_cmd_ram_sel) //|< w
+ ,.axi_paddr (axi_3_paddr[19:0]) //|< w
+ ,.axi_pwdata (apb_pwdata[31:0]) //|< i
+ ,.axi_rdata (axi_3_rdata[255:0]) //|< i
+ ,.axi_rdata_ram_sel (axi_3_rdata_ram_sel) //|< w
+ ,.axi_reg_sel (axi_3_reg_sel) //|< w
+ ,.axi_rid (axi_3_rid[13:0]) //|< i
+ ,.axi_rlast (axi_3_rlast) //|< i
+ ,.axi_rresp (axi_3_rresp[1:0]) //|< i
+ ,.axi_rvalid (axi_3_rvalid) //|< i
+ ,.axi_wdata_ram_sel (axi_3_wdata_ram_sel) //|< w
+ ,.axi_wready (axi_3_wready) //|< i
+ ,.axi_wstrb_ram_sel (axi_3_wstrb_ram_sel) //|< w
+ ,.axi_araddr (axi_3_araddr[39:0]) //|> o
+ ,.axi_arburst (axi_3_arburst[1:0]) //|> o
+ ,.axi_arcache (axi_3_arcache[3:0]) //|> o
+ ,.axi_arid (axi_3_arid[13:0]) //|> o
+ ,.axi_arlen (axi_3_arlen[7:0]) //|> o
+ ,.axi_arlock (axi_3_arlock[1:0]) //|> o
+ ,.axi_arprot (axi_3_arprot[2:0]) //|> o
+ ,.axi_arqos (axi_3_arqos[3:0]) //|> o
+ ,.axi_arregion (axi_3_arregion[3:0]) //|> o
+ ,.axi_arsize (axi_3_arsize[2:0]) //|> o
+ ,.axi_aruser (axi_3_aruser[25:0]) //|> o
+ ,.axi_arvalid (axi_3_arvalid) //|> o
+ ,.axi_awaddr (axi_3_awaddr[39:0]) //|> o
+ ,.axi_awburst (axi_3_awburst[1:0]) //|> o
+ ,.axi_awcache (axi_3_awcache[3:0]) //|> o
+ ,.axi_awid (axi_3_awid[13:0]) //|> o
+ ,.axi_awlen (axi_3_awlen[7:0]) //|> o
+ ,.axi_awlock (axi_3_awlock[1:0]) //|> o
+ ,.axi_awprot (axi_3_awprot[2:0]) //|> o
+ ,.axi_awqos (axi_3_awqos[3:0]) //|> o
+ ,.axi_awregion (axi_3_awregion[3:0]) //|> o
+ ,.axi_awsize (axi_3_awsize[2:0]) //|> o
+ ,.axi_awuser (axi_3_awuser[25:0]) //|> o
+ ,.axi_awvalid (axi_3_awvalid) //|> o
+ ,.axi_bready (axi_3_bready) //|> o
+ ,.axi_prdata (axi_3_prdata[31:0]) //|> w
+ ,.axi_rready (axi_3_rready) //|> o
+ ,.axi_wdata (axi_3_wdata[255:0]) //|> o
+ ,.axi_wlast (axi_3_wlast) //|> o
+ ,.axi_wstrb (axi_3_wstrb[31:0]) //|> o
+ ,.axi_wvalid (axi_3_wvalid) //|> o
+ ,.test_complete (test_complete_3) //|> w
+ );
+
+endmodule // NV_FPGA_unit_checkbox_mem_dut
+
+
diff --git a/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_apb_slave.v b/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_apb_slave.v
new file mode 100644
index 0000000..f78e811
--- /dev/null
+++ b/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_apb_slave.v
@@ -0,0 +1,761 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: NV_FPGA_unit_checkbox_mem_dut_apb_slave.v
+
+module NV_FPGA_unit_checkbox_mem_dut_apb_slave (
+ apb_clk
+ ,apb_rstn
+ ,apb_paddr
+ ,apb_penable
+ ,apb_pns
+ ,apb_psel
+ ,apb_puser
+ ,apb_pwdata
+ ,apb_pwrite
+ ,apb_pwstrb
+ ,axi_0_prdata
+ ,axi_1_prdata
+ ,axi_2_prdata
+ ,axi_3_prdata
+ ,intr_in
+ ,test_complete_0
+ ,test_complete_1
+ ,test_complete_2
+ ,test_complete_3
+ ,apb_prdata
+ ,apb_pready
+ ,apb_pslverr
+ ,apb_wr_op
+ ,axi_0_cmd_ram_sel
+ ,axi_0_paddr
+ ,axi_0_rdata_ram_sel
+ ,axi_0_reg_sel
+ ,axi_0_wdata_ram_sel
+ ,axi_0_wstrb_ram_sel
+ ,axi_1_cmd_ram_sel
+ ,axi_1_paddr
+ ,axi_1_rdata_ram_sel
+ ,axi_1_reg_sel
+ ,axi_1_wdata_ram_sel
+ ,axi_1_wstrb_ram_sel
+ ,axi_2_cmd_ram_sel
+ ,axi_2_paddr
+ ,axi_2_rdata_ram_sel
+ ,axi_2_reg_sel
+ ,axi_2_wdata_ram_sel
+ ,axi_2_wstrb_ram_sel
+ ,axi_3_cmd_ram_sel
+ ,axi_3_paddr
+ ,axi_3_rdata_ram_sel
+ ,axi_3_reg_sel
+ ,axi_3_wdata_ram_sel
+ ,axi_3_wstrb_ram_sel
+ ,intr_out
+ );
+input apb_clk;
+input apb_rstn;
+input [23:0] apb_paddr;
+input apb_penable;
+input apb_pns;
+input apb_psel;
+input [12:0] apb_puser;
+input [31:0] apb_pwdata;
+input apb_pwrite;
+input [3:0] apb_pwstrb;
+input [31:0] axi_0_prdata;
+input [31:0] axi_1_prdata;
+input [31:0] axi_2_prdata;
+input [31:0] axi_3_prdata;
+input [31:0] intr_in;
+input test_complete_0;
+input test_complete_1;
+input test_complete_2;
+input test_complete_3;
+output [31:0] apb_prdata;
+output apb_pready;
+output apb_pslverr;
+output apb_wr_op;
+output axi_0_cmd_ram_sel;
+output [23:0] axi_0_paddr;
+output axi_0_rdata_ram_sel;
+output axi_0_reg_sel;
+output axi_0_wdata_ram_sel;
+output axi_0_wstrb_ram_sel;
+output axi_1_cmd_ram_sel;
+output [23:0] axi_1_paddr;
+output axi_1_rdata_ram_sel;
+output axi_1_reg_sel;
+output axi_1_wdata_ram_sel;
+output axi_1_wstrb_ram_sel;
+output axi_2_cmd_ram_sel;
+output [23:0] axi_2_paddr;
+output axi_2_rdata_ram_sel;
+output axi_2_reg_sel;
+output axi_2_wdata_ram_sel;
+output axi_2_wstrb_ram_sel;
+output axi_3_cmd_ram_sel;
+output [23:0] axi_3_paddr;
+output axi_3_rdata_ram_sel;
+output axi_3_reg_sel;
+output axi_3_wdata_ram_sel;
+output axi_3_wstrb_ram_sel;
+output [31:0] intr_out;
+reg [31:0] apb_delay_reg;
+reg [31:0] apb_prdata;
+reg [7:0] apb_rd_cnt_reg;
+reg [31:0] apb_test_reg1;
+reg [31:0] apb_test_reg2;
+reg [31:0] apb_test_reg_prdata;
+reg [7:0] apb_wr_cnt_reg;
+reg [31:0] intr_reg;
+reg [31:0] reg_apb_timer;
+reg [31:0] reg_intr_test_clear;
+reg [31:0] reg_intr_test_clear_1t;
+reg [31:0] reg_intr_test_en;
+reg [31:0] reg_intr_test_mode1;
+reg [31:0] reg_intr_test_mode2;
+reg [31:0] reg_intr_test_set;
+wire apb_delay_done;
+wire apb_delay_reg_sel;
+wire [7:0] apb_rd_cnt;
+wire apb_rd_op;
+wire [7:0] apb_rd_random_delay;
+wire apb_test_reg1_sel;
+wire apb_test_reg2_sel;
+wire apb_test_reg3_sel;
+wire apb_test_reg4_sel;
+wire apb_test_reg_sel;
+wire apb_timer_reg_sel;
+wire [7:0] apb_wr_cnt;
+wire [7:0] apb_wr_random_delay;
+wire [3:0] axi_0_base_addr;
+wire axi_0_sel;
+wire [3:0] axi_1_base_addr;
+wire axi_1_sel;
+wire [3:0] axi_2_base_addr;
+wire axi_2_sel;
+wire [3:0] axi_3_base_addr;
+wire axi_3_sel;
+wire intr_test_reg_sel;
+wire [31:0] reg_intr_test_downstream;
+
+
+//input apb_psel;
+//input apb_penable;
+//input apb_pwrite;
+//input apb_pns;
+//input [3:0] apb_pwstrb;
+//input [23:0] apb_paddr;
+//input [31:0] apb_pwdata;
+//output apb_pslverr;
+//output apb_pready;
+//output [31:0] apb_prdata;
+
+
+
+
+/////////////////////////////////////////////////////////////////////////////////
+// address decode
+/////////////////////////////////////////////////////////////////////////////////
+
+parameter APB_BASE_ADDR = 24'h000000;
+parameter AXI_PORT_SPACE = 24'h100000;
+
+// use APB_REG1 to define APB_WR_RAMDOM_DELAY and APB_RD_RANDOM_DELAY.
+parameter APB_DELAY_REG_OFFSET = 16'h0080;
+parameter APB_TIMER_REG_OFFSET = 16'h0084;
+parameter APB_TEST_REG1_OFFSET = 16'h0100;
+parameter APB_TEST_REG2_OFFSET = 16'h0104;
+parameter APB_TEST_REG3_OFFSET = 16'h0108;
+parameter APB_TEST_REG4_OFFSET = 16'h010C;
+
+parameter INTR_TEST_REG_BASE = 16'h2000;
+parameter INTR_TEST_SET_REG = 8'h00; // write 1 to set interrupt bits
+parameter INTR_TEST_CLEAR_REG = 8'h04; // write 1 to clear interrupt bits
+parameter INTR_TEST_MODE1_REG = 8'h08; // set interrupt type: level or pulse
+parameter INTR_TEST_MODE2_REG = 8'h0C; // set 1 to enable assert interrupt imediately after clear that bit.
+parameter INTR_TEST_EN_REG = 8'h10; // enable interrupt bits.
+
+parameter INTR_TEST_DOWNSTREAM_REG = 8'h20;
+
+// bit [19:16]
+`define NV_FPGA_UNIT_MEM_DUT_AXI_REG_BASE 4'h0
+`define NV_FPGA_UNIT_MEM_DUT_AXI_CMD_RAM_BASE 4'h1
+`define NV_FPGA_UNIT_MEM_DUT_AXI_WE_RAM_BASE 4'h3
+`define NV_FPGA_UNIT_MEM_DUT_AXI_WDATA_RAM_BASE 4'h4
+`define NV_FPGA_UNIT_MEM_DUT_AXI_RDATA_RAM_BASE 4'hA
+
+assign axi_0_base_addr = (APB_BASE_ADDR[23:20] + (AXI_PORT_SPACE[23:20]*0));
+assign axi_0_paddr = (apb_paddr - {axi_0_base_addr, 20'b0}); // spyglass disable W484
+assign axi_0_sel = apb_psel & (apb_paddr[23:20] == axi_0_base_addr);
+assign axi_0_reg_sel = axi_0_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_REG_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_CMD_RAM_BASE );
+assign axi_0_cmd_ram_sel = axi_0_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_CMD_RAM_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_WE_RAM_BASE );
+assign axi_0_wstrb_ram_sel = axi_0_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_WE_RAM_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_WDATA_RAM_BASE);
+assign axi_0_wdata_ram_sel = axi_0_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_WDATA_RAM_BASE) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_RDATA_RAM_BASE);
+assign axi_0_rdata_ram_sel = axi_0_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_RDATA_RAM_BASE) & (apb_paddr[19:16] < AXI_PORT_SPACE[23:16]);
+
+assign axi_1_base_addr = (APB_BASE_ADDR[23:20] + (AXI_PORT_SPACE[23:20]*1));
+assign axi_1_paddr = (apb_paddr - {axi_1_base_addr, 20'b0}); // spyglass disable W484
+assign axi_1_sel = apb_psel & (apb_paddr[23:20] == axi_1_base_addr);
+assign axi_1_reg_sel = axi_1_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_REG_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_CMD_RAM_BASE );
+assign axi_1_cmd_ram_sel = axi_1_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_CMD_RAM_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_WE_RAM_BASE );
+assign axi_1_wstrb_ram_sel = axi_1_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_WE_RAM_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_WDATA_RAM_BASE);
+assign axi_1_wdata_ram_sel = axi_1_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_WDATA_RAM_BASE) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_RDATA_RAM_BASE);
+assign axi_1_rdata_ram_sel = axi_1_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_RDATA_RAM_BASE) & (apb_paddr[19:16] < AXI_PORT_SPACE[23:16]);
+
+assign axi_2_base_addr = (APB_BASE_ADDR[23:20] + (AXI_PORT_SPACE[23:20]*2));
+assign axi_2_paddr = (apb_paddr - {axi_2_base_addr, 20'b0}); // spyglass disable W484
+assign axi_2_sel = apb_psel & (apb_paddr[23:20] == axi_2_base_addr);
+assign axi_2_reg_sel = axi_2_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_REG_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_CMD_RAM_BASE );
+assign axi_2_cmd_ram_sel = axi_2_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_CMD_RAM_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_WE_RAM_BASE );
+assign axi_2_wstrb_ram_sel = axi_2_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_WE_RAM_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_WDATA_RAM_BASE);
+assign axi_2_wdata_ram_sel = axi_2_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_WDATA_RAM_BASE) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_RDATA_RAM_BASE);
+assign axi_2_rdata_ram_sel = axi_2_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_RDATA_RAM_BASE) & (apb_paddr[19:16] < AXI_PORT_SPACE[23:16]);
+
+assign axi_3_base_addr = (APB_BASE_ADDR[23:20] + (AXI_PORT_SPACE[23:20]*3));
+assign axi_3_paddr = (apb_paddr - {axi_3_base_addr, 20'b0}); // spyglass disable W484
+assign axi_3_sel = apb_psel & (apb_paddr[23:20] == axi_3_base_addr);
+assign axi_3_reg_sel = axi_3_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_REG_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_CMD_RAM_BASE );
+assign axi_3_cmd_ram_sel = axi_3_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_CMD_RAM_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_WE_RAM_BASE );
+assign axi_3_wstrb_ram_sel = axi_3_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_WE_RAM_BASE ) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_WDATA_RAM_BASE);
+assign axi_3_wdata_ram_sel = axi_3_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_WDATA_RAM_BASE) & (apb_paddr[19:16] < `NV_FPGA_UNIT_MEM_DUT_AXI_RDATA_RAM_BASE);
+assign axi_3_rdata_ram_sel = axi_3_sel & (apb_paddr[19:16] >= `NV_FPGA_UNIT_MEM_DUT_AXI_RDATA_RAM_BASE) & (apb_paddr[19:16] < AXI_PORT_SPACE[23:16]);
+
+
+assign apb_test_reg1_sel = axi_0_reg_sel & (apb_paddr[15:2] == APB_TEST_REG1_OFFSET[15:2]);
+assign apb_test_reg2_sel = axi_0_reg_sel & (apb_paddr[15:2] == APB_TEST_REG2_OFFSET[15:2]);
+assign apb_test_reg3_sel = axi_0_reg_sel & (apb_paddr[15:2] == APB_TEST_REG3_OFFSET[15:2]);
+assign apb_test_reg4_sel = axi_0_reg_sel & (apb_paddr[15:2] == APB_TEST_REG4_OFFSET[15:2]);
+assign apb_delay_reg_sel = axi_0_reg_sel & (apb_paddr[15:2] == APB_DELAY_REG_OFFSET[15:2]);
+assign intr_test_reg_sel = axi_0_reg_sel & (apb_paddr[15:8] == INTR_TEST_REG_BASE[15:8]);
+assign apb_timer_reg_sel = axi_0_reg_sel & (apb_paddr[15:2] == APB_TIMER_REG_OFFSET[15:2]);
+
+assign apb_test_reg_sel = apb_test_reg1_sel | apb_test_reg2_sel | apb_test_reg3_sel | apb_test_reg4_sel | apb_delay_reg_sel | intr_test_reg_sel;
+
+/////////////////////////////////////////////////////////////////////////////////
+// data path connect
+/////////////////////////////////////////////////////////////////////////////////
+
+always @(
+ axi_0_sel
+ or apb_test_reg_sel
+ or apb_test_reg_prdata
+ or axi_0_prdata
+ or axi_1_sel
+ or axi_1_prdata
+ or axi_2_sel
+ or axi_2_prdata
+ or axi_3_sel
+ or axi_3_prdata
+ ) begin
+ case(1'b1) // spyglass disable W226
+ axi_0_sel: apb_prdata = apb_test_reg_sel ? apb_test_reg_prdata : axi_0_prdata; // spyglass disable W171
+ axi_1_sel: apb_prdata = axi_1_prdata; // spyglass disable W171
+ axi_2_sel: apb_prdata = axi_2_prdata; // spyglass disable W171
+ axi_3_sel: apb_prdata = axi_3_prdata; // spyglass disable W171
+ default: apb_prdata = 0;
+ endcase
+end
+
+always @(
+ apb_test_reg1_sel
+ or apb_test_reg1
+ or apb_test_reg2_sel
+ or apb_test_reg2
+ or apb_test_reg3_sel
+ or apb_test_reg4_sel
+ or apb_puser
+ or apb_delay_reg_sel
+ or apb_delay_reg
+ or intr_test_reg_sel
+ or apb_paddr
+ or reg_intr_test_set
+ or reg_intr_test_clear
+ or reg_intr_test_mode1
+ or reg_intr_test_mode2
+ or reg_intr_test_en
+ or reg_intr_test_downstream
+ ) begin
+ if(apb_test_reg1_sel)
+ apb_test_reg_prdata = apb_test_reg1;
+ else if(apb_test_reg2_sel)
+ apb_test_reg_prdata = apb_test_reg2;
+ else if(apb_test_reg3_sel)
+ apb_test_reg_prdata = 32'b0;
+ else if(apb_test_reg4_sel)
+ apb_test_reg_prdata = {19'b0, apb_puser};
+ else if(apb_delay_reg_sel)
+ apb_test_reg_prdata = apb_delay_reg;
+ else if(intr_test_reg_sel)
+ case(apb_paddr[7:0])
+ INTR_TEST_SET_REG : apb_test_reg_prdata = reg_intr_test_set;
+ INTR_TEST_CLEAR_REG : apb_test_reg_prdata = reg_intr_test_clear;
+ INTR_TEST_MODE1_REG : apb_test_reg_prdata = reg_intr_test_mode1;
+ INTR_TEST_MODE2_REG : apb_test_reg_prdata = reg_intr_test_mode2;
+ INTR_TEST_EN_REG : apb_test_reg_prdata = reg_intr_test_en;
+ INTR_TEST_DOWNSTREAM_REG : apb_test_reg_prdata = reg_intr_test_downstream;
+ default: apb_test_reg_prdata = 0;
+ endcase
+ else
+ apb_test_reg_prdata = 0;
+end
+
+//&PerlBeg;
+// foreach my $axi_port_num (0..(AXI_MASTER_NUM-1)) {
+// vprintl
+//"assign axi_0_pwdata = axi_${axi_port_num}_sel ? apb_pwdata : 0;";
+// }
+//&PerlEnd;
+//
+//assign apb_test_reg_pwdata = apb_pwdata;
+
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ reg_intr_test_set <= {32{1'b0}};
+ reg_intr_test_clear <= {32{1'b0}};
+ reg_intr_test_clear_1t <= {32{1'b0}};
+ apb_test_reg1[7:0] <= {8{1'b0}};
+ apb_test_reg1[15:8] <= {8{1'b0}};
+ apb_test_reg1[23:16] <= {8{1'b0}};
+ apb_test_reg1[31:24] <= {8{1'b0}};
+ apb_test_reg2[7:0] <= {8{1'b0}};
+ apb_test_reg2[15:8] <= {8{1'b0}};
+ apb_test_reg2[23:16] <= {8{1'b0}};
+ apb_test_reg2[31:24] <= {8{1'b0}};
+ apb_delay_reg[31:0] <= {32{1'b0}};
+ reg_intr_test_mode1 <= {32{1'b0}};
+ reg_intr_test_mode2 <= {32{1'b0}};
+ reg_intr_test_en <= {32{1'b0}};
+ end else begin
+ reg_intr_test_set <= 0;
+ reg_intr_test_clear <= 0;
+ reg_intr_test_clear_1t <= reg_intr_test_clear;
+ if (apb_wr_op == 1'b1) begin
+ if(apb_test_reg1_sel) begin
+ apb_test_reg1[7:0] <= apb_pwstrb[0] ? apb_pwdata[7:0] : apb_test_reg1[7:0]; // spyglass disable W171
+ apb_test_reg1[15:8] <= apb_pwstrb[1] ? apb_pwdata[15:8] : apb_test_reg1[15:8]; // spyglass disable W171
+ apb_test_reg1[23:16] <= apb_pwstrb[2] ? apb_pwdata[23:16] : apb_test_reg1[23:16]; // spyglass disable W171
+ apb_test_reg1[31:24] <= apb_pwstrb[3] ? apb_pwdata[31:24] : apb_test_reg1[31:24]; // spyglass disable W171
+ end
+ else if(apb_test_reg2_sel) begin
+ apb_test_reg2[7:0] <= apb_pwstrb[0] ? apb_pwdata[7:0] : apb_test_reg2[7:0]; // spyglass disable W171
+ apb_test_reg2[15:8] <= apb_pwstrb[1] ? apb_pwdata[15:8] : apb_test_reg2[15:8]; // spyglass disable W171
+ apb_test_reg2[23:16] <= apb_pwstrb[2] ? apb_pwdata[23:16] : apb_test_reg2[23:16]; // spyglass disable W171
+ apb_test_reg2[31:24] <= apb_pwstrb[3] ? apb_pwdata[31:24] : apb_test_reg2[31:24]; // spyglass disable W171
+ end
+ else if(apb_delay_reg_sel)
+ apb_delay_reg[31:0] <= apb_pwdata[31:0]; // spyglass disable W171
+ else if(intr_test_reg_sel)
+ case(apb_paddr[7:0]) //spyglass disable W71
+ INTR_TEST_SET_REG : reg_intr_test_set <= apb_pwdata;
+ INTR_TEST_CLEAR_REG : reg_intr_test_clear <= apb_pwdata;
+ INTR_TEST_MODE1_REG : reg_intr_test_mode1 <= apb_pwdata | 32'h0000_000F;
+ INTR_TEST_MODE2_REG : reg_intr_test_mode2 <= apb_pwdata & 32'hFFFF_FFF0;
+ INTR_TEST_EN_REG : reg_intr_test_en <= apb_pwdata;
+ endcase
+ end
+ end
+end
+
+assign apb_wr_random_delay = apb_delay_reg[7:0];
+assign apb_rd_random_delay = apb_delay_reg[15:8];
+
+/////////////////////////////////////////////////////////////////////////////////
+// apb interface flow control
+/////////////////////////////////////////////////////////////////////////////////
+
+assign apb_pslverr = apb_test_reg3_sel;
+assign apb_pready = apb_penable & apb_delay_done;
+
+assign apb_delay_done = apb_pwrite ? (apb_wr_cnt > apb_wr_random_delay) : (apb_rd_cnt > apb_rd_random_delay);
+
+assign apb_wr_cnt = (apb_psel & apb_pwrite & ~apb_penable) ? 0 : (apb_wr_cnt_reg + 1'b1);
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ apb_wr_cnt_reg <= {8{1'b0}};
+ end else begin
+ apb_wr_cnt_reg <= apb_wr_cnt;
+ end
+end
+
+assign apb_rd_cnt = (apb_psel & ~apb_pwrite & ~apb_penable) ? 0 : (apb_rd_cnt_reg + 1'b1);
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ apb_rd_cnt_reg <= {8{1'b0}};
+ end else begin
+ apb_rd_cnt_reg <= apb_rd_cnt;
+ end
+end
+
+assign apb_wr_op = apb_psel & apb_pwrite & apb_penable;
+assign apb_rd_op = apb_psel & ~apb_pwrite & apb_penable;
+
+/////////////////////////////////////////////////////////////////////////////////
+// interrupt generation for testing
+/////////////////////////////////////////////////////////////////////////////////
+
+// upstream interrupt
+// bit 0: assert if test_complete assertd; de-assert if (clear it or in pulse intr mode)
+// bit 1-31: assert if (set it or clear it in back-to-back intr mode); de-assert if (clear it or in pulse intr mode)
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[0] <= 1'b0;
+ end else begin
+ if(test_complete_0)
+ intr_reg[0] <= 1'b1;
+ else if(intr_reg[0] & (reg_intr_test_clear[0] | reg_intr_test_mode1[0]))
+ intr_reg[0] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[1] <= 1'b0;
+ end else begin
+ if(test_complete_1)
+ intr_reg[1] <= 1'b1;
+ else if(intr_reg[1] & (reg_intr_test_clear[1] | reg_intr_test_mode1[1]))
+ intr_reg[1] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[2] <= 1'b0;
+ end else begin
+ if(test_complete_2)
+ intr_reg[2] <= 1'b1;
+ else if(intr_reg[2] & (reg_intr_test_clear[2] | reg_intr_test_mode1[2]))
+ intr_reg[2] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[3] <= 1'b0;
+ end else begin
+ if(test_complete_3)
+ intr_reg[3] <= 1'b1;
+ else if(intr_reg[3] & (reg_intr_test_clear[3] | reg_intr_test_mode1[3]))
+ intr_reg[3] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[4] <= 1'b0;
+ end else begin
+ if(~intr_reg[4] & (reg_intr_test_set[4] | (reg_intr_test_clear_1t[4] & reg_intr_test_mode2[4])))
+ intr_reg[4] <= 1'b1;
+ else if(intr_reg[4] & (reg_intr_test_clear[4] | reg_intr_test_mode1[4]))
+ intr_reg[4] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[5] <= 1'b0;
+ end else begin
+ if(~intr_reg[5] & (reg_intr_test_set[5] | (reg_intr_test_clear_1t[5] & reg_intr_test_mode2[5])))
+ intr_reg[5] <= 1'b1;
+ else if(intr_reg[5] & (reg_intr_test_clear[5] | reg_intr_test_mode1[5]))
+ intr_reg[5] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[6] <= 1'b0;
+ end else begin
+ if(~intr_reg[6] & (reg_intr_test_set[6] | (reg_intr_test_clear_1t[6] & reg_intr_test_mode2[6])))
+ intr_reg[6] <= 1'b1;
+ else if(intr_reg[6] & (reg_intr_test_clear[6] | reg_intr_test_mode1[6]))
+ intr_reg[6] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[7] <= 1'b0;
+ end else begin
+ if(~intr_reg[7] & (reg_intr_test_set[7] | (reg_intr_test_clear_1t[7] & reg_intr_test_mode2[7])))
+ intr_reg[7] <= 1'b1;
+ else if(intr_reg[7] & (reg_intr_test_clear[7] | reg_intr_test_mode1[7]))
+ intr_reg[7] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[8] <= 1'b0;
+ end else begin
+ if(~intr_reg[8] & (reg_intr_test_set[8] | (reg_intr_test_clear_1t[8] & reg_intr_test_mode2[8])))
+ intr_reg[8] <= 1'b1;
+ else if(intr_reg[8] & (reg_intr_test_clear[8] | reg_intr_test_mode1[8]))
+ intr_reg[8] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[9] <= 1'b0;
+ end else begin
+ if(~intr_reg[9] & (reg_intr_test_set[9] | (reg_intr_test_clear_1t[9] & reg_intr_test_mode2[9])))
+ intr_reg[9] <= 1'b1;
+ else if(intr_reg[9] & (reg_intr_test_clear[9] | reg_intr_test_mode1[9]))
+ intr_reg[9] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[10] <= 1'b0;
+ end else begin
+ if(~intr_reg[10] & (reg_intr_test_set[10] | (reg_intr_test_clear_1t[10] & reg_intr_test_mode2[10])))
+ intr_reg[10] <= 1'b1;
+ else if(intr_reg[10] & (reg_intr_test_clear[10] | reg_intr_test_mode1[10]))
+ intr_reg[10] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[11] <= 1'b0;
+ end else begin
+ if(~intr_reg[11] & (reg_intr_test_set[11] | (reg_intr_test_clear_1t[11] & reg_intr_test_mode2[11])))
+ intr_reg[11] <= 1'b1;
+ else if(intr_reg[11] & (reg_intr_test_clear[11] | reg_intr_test_mode1[11]))
+ intr_reg[11] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[12] <= 1'b0;
+ end else begin
+ if(~intr_reg[12] & (reg_intr_test_set[12] | (reg_intr_test_clear_1t[12] & reg_intr_test_mode2[12])))
+ intr_reg[12] <= 1'b1;
+ else if(intr_reg[12] & (reg_intr_test_clear[12] | reg_intr_test_mode1[12]))
+ intr_reg[12] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[13] <= 1'b0;
+ end else begin
+ if(~intr_reg[13] & (reg_intr_test_set[13] | (reg_intr_test_clear_1t[13] & reg_intr_test_mode2[13])))
+ intr_reg[13] <= 1'b1;
+ else if(intr_reg[13] & (reg_intr_test_clear[13] | reg_intr_test_mode1[13]))
+ intr_reg[13] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[14] <= 1'b0;
+ end else begin
+ if(~intr_reg[14] & (reg_intr_test_set[14] | (reg_intr_test_clear_1t[14] & reg_intr_test_mode2[14])))
+ intr_reg[14] <= 1'b1;
+ else if(intr_reg[14] & (reg_intr_test_clear[14] | reg_intr_test_mode1[14]))
+ intr_reg[14] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[15] <= 1'b0;
+ end else begin
+ if(~intr_reg[15] & (reg_intr_test_set[15] | (reg_intr_test_clear_1t[15] & reg_intr_test_mode2[15])))
+ intr_reg[15] <= 1'b1;
+ else if(intr_reg[15] & (reg_intr_test_clear[15] | reg_intr_test_mode1[15]))
+ intr_reg[15] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[16] <= 1'b0;
+ end else begin
+ if(~intr_reg[16] & (reg_intr_test_set[16] | (reg_intr_test_clear_1t[16] & reg_intr_test_mode2[16])))
+ intr_reg[16] <= 1'b1;
+ else if(intr_reg[16] & (reg_intr_test_clear[16] | reg_intr_test_mode1[16]))
+ intr_reg[16] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[17] <= 1'b0;
+ end else begin
+ if(~intr_reg[17] & (reg_intr_test_set[17] | (reg_intr_test_clear_1t[17] & reg_intr_test_mode2[17])))
+ intr_reg[17] <= 1'b1;
+ else if(intr_reg[17] & (reg_intr_test_clear[17] | reg_intr_test_mode1[17]))
+ intr_reg[17] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[18] <= 1'b0;
+ end else begin
+ if(~intr_reg[18] & (reg_intr_test_set[18] | (reg_intr_test_clear_1t[18] & reg_intr_test_mode2[18])))
+ intr_reg[18] <= 1'b1;
+ else if(intr_reg[18] & (reg_intr_test_clear[18] | reg_intr_test_mode1[18]))
+ intr_reg[18] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[19] <= 1'b0;
+ end else begin
+ if(~intr_reg[19] & (reg_intr_test_set[19] | (reg_intr_test_clear_1t[19] & reg_intr_test_mode2[19])))
+ intr_reg[19] <= 1'b1;
+ else if(intr_reg[19] & (reg_intr_test_clear[19] | reg_intr_test_mode1[19]))
+ intr_reg[19] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[20] <= 1'b0;
+ end else begin
+ if(~intr_reg[20] & (reg_intr_test_set[20] | (reg_intr_test_clear_1t[20] & reg_intr_test_mode2[20])))
+ intr_reg[20] <= 1'b1;
+ else if(intr_reg[20] & (reg_intr_test_clear[20] | reg_intr_test_mode1[20]))
+ intr_reg[20] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[21] <= 1'b0;
+ end else begin
+ if(~intr_reg[21] & (reg_intr_test_set[21] | (reg_intr_test_clear_1t[21] & reg_intr_test_mode2[21])))
+ intr_reg[21] <= 1'b1;
+ else if(intr_reg[21] & (reg_intr_test_clear[21] | reg_intr_test_mode1[21]))
+ intr_reg[21] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[22] <= 1'b0;
+ end else begin
+ if(~intr_reg[22] & (reg_intr_test_set[22] | (reg_intr_test_clear_1t[22] & reg_intr_test_mode2[22])))
+ intr_reg[22] <= 1'b1;
+ else if(intr_reg[22] & (reg_intr_test_clear[22] | reg_intr_test_mode1[22]))
+ intr_reg[22] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[23] <= 1'b0;
+ end else begin
+ if(~intr_reg[23] & (reg_intr_test_set[23] | (reg_intr_test_clear_1t[23] & reg_intr_test_mode2[23])))
+ intr_reg[23] <= 1'b1;
+ else if(intr_reg[23] & (reg_intr_test_clear[23] | reg_intr_test_mode1[23]))
+ intr_reg[23] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[24] <= 1'b0;
+ end else begin
+ if(~intr_reg[24] & (reg_intr_test_set[24] | (reg_intr_test_clear_1t[24] & reg_intr_test_mode2[24])))
+ intr_reg[24] <= 1'b1;
+ else if(intr_reg[24] & (reg_intr_test_clear[24] | reg_intr_test_mode1[24]))
+ intr_reg[24] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[25] <= 1'b0;
+ end else begin
+ if(~intr_reg[25] & (reg_intr_test_set[25] | (reg_intr_test_clear_1t[25] & reg_intr_test_mode2[25])))
+ intr_reg[25] <= 1'b1;
+ else if(intr_reg[25] & (reg_intr_test_clear[25] | reg_intr_test_mode1[25]))
+ intr_reg[25] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[26] <= 1'b0;
+ end else begin
+ if(~intr_reg[26] & (reg_intr_test_set[26] | (reg_intr_test_clear_1t[26] & reg_intr_test_mode2[26])))
+ intr_reg[26] <= 1'b1;
+ else if(intr_reg[26] & (reg_intr_test_clear[26] | reg_intr_test_mode1[26]))
+ intr_reg[26] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[27] <= 1'b0;
+ end else begin
+ if(~intr_reg[27] & (reg_intr_test_set[27] | (reg_intr_test_clear_1t[27] & reg_intr_test_mode2[27])))
+ intr_reg[27] <= 1'b1;
+ else if(intr_reg[27] & (reg_intr_test_clear[27] | reg_intr_test_mode1[27]))
+ intr_reg[27] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[28] <= 1'b0;
+ end else begin
+ if(~intr_reg[28] & (reg_intr_test_set[28] | (reg_intr_test_clear_1t[28] & reg_intr_test_mode2[28])))
+ intr_reg[28] <= 1'b1;
+ else if(intr_reg[28] & (reg_intr_test_clear[28] | reg_intr_test_mode1[28]))
+ intr_reg[28] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[29] <= 1'b0;
+ end else begin
+ if(~intr_reg[29] & (reg_intr_test_set[29] | (reg_intr_test_clear_1t[29] & reg_intr_test_mode2[29])))
+ intr_reg[29] <= 1'b1;
+ else if(intr_reg[29] & (reg_intr_test_clear[29] | reg_intr_test_mode1[29]))
+ intr_reg[29] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[30] <= 1'b0;
+ end else begin
+ if(~intr_reg[30] & (reg_intr_test_set[30] | (reg_intr_test_clear_1t[30] & reg_intr_test_mode2[30])))
+ intr_reg[30] <= 1'b1;
+ else if(intr_reg[30] & (reg_intr_test_clear[30] | reg_intr_test_mode1[30]))
+ intr_reg[30] <= 1'b0;
+ end
+end
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ intr_reg[31] <= 1'b0;
+ end else begin
+ if(~intr_reg[31] & (reg_intr_test_set[31] | (reg_intr_test_clear_1t[31] & reg_intr_test_mode2[31])))
+ intr_reg[31] <= 1'b1;
+ else if(intr_reg[31] & (reg_intr_test_clear[31] | reg_intr_test_mode1[31]))
+ intr_reg[31] <= 1'b0;
+ end
+end
+
+assign intr_out = reg_intr_test_en & intr_reg;
+
+// downstream interrupt
+//assign reg_intr_test_downstream_wr = apb_wr_op & intr_test_reg_sel & (apb_paddr[7:0] == INTR_TEST_DOWNSTREAM_REG);
+//
+//&PerlBeg;
+//foreach my $i (0..31) {
+// vprintl
+//"&Always posedge;",
+//" if(intr_in[$i])",
+//" reg_intr_test_downstream[$i] <0= 1'b1;",
+//" else if(reg_intr_test_downstream_wr & apb_pwdata[$i])",
+//" reg_intr_test_downstream[$i] <0= 1'b0;",
+//"&End;";
+//}
+//&PerlEnd;
+assign reg_intr_test_downstream[31:0] = intr_in[31:0];
+
+/////////////////////////////////////////////////////////////////////////////////
+// general timer for debug use
+/////////////////////////////////////////////////////////////////////////////////
+
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ reg_apb_timer <= {32{1'b0}};
+ end else begin
+ if(apb_wr_op & apb_timer_reg_sel)
+ reg_apb_timer <= apb_pwdata;
+ else
+ reg_apb_timer <= reg_apb_timer + 1;
+ end
+end
+
+endmodule // NV_FPGA_unit_checkbox_mem_dut_apb_slave
+
diff --git a/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_256_256.v b/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_256_256.v
new file mode 100644
index 0000000..2bbef74
--- /dev/null
+++ b/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_256_256.v
@@ -0,0 +1,1175 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: NV_FPGA_unit_checkbox_mem_dut_axi_256_256.v
+
+`timescale 1ns/10ps
+module NV_FPGA_unit_checkbox_mem_dut_axi_256_256 (
+ apb_clk //|< i
+ ,apb_rstn //|< i
+ ,apb_wr_op //|< i
+ ,axi_arready //|< i
+ ,axi_awready //|< i
+ ,axi_bid //|< i
+ ,axi_bresp //|< i
+ ,axi_bvalid //|< i
+ ,axi_cmd_ram_sel //|< i
+ ,axi_paddr //|< i
+ ,axi_pwdata //|< i
+ ,axi_rdata //|< i
+ ,axi_rdata_ram_sel //|< i
+ ,axi_reg_sel //|< i
+ ,axi_rid //|< i
+ ,axi_rlast //|< i
+ ,axi_rresp //|< i
+ ,axi_rvalid //|< i
+ ,axi_wdata_ram_sel //|< i
+ ,axi_wready //|< i
+ ,axi_wstrb_ram_sel //|< i
+ ,axi_araddr //|> o
+ ,axi_arburst //|> o
+ ,axi_arcache //|> o
+ ,axi_arid //|> o
+ ,axi_arlen //|> o
+ ,axi_arlock //|> o
+ ,axi_arprot //|> o
+ ,axi_arqos //|> o
+ ,axi_arregion //|> o
+ ,axi_arsize //|> o
+ ,axi_aruser //|> o
+ ,axi_arvalid //|> o
+ ,axi_awaddr //|> o
+ ,axi_awburst //|> o
+ ,axi_awcache //|> o
+ ,axi_awid //|> o
+ ,axi_awlen //|> o
+ ,axi_awlock //|> o
+ ,axi_awprot //|> o
+ ,axi_awqos //|> o
+ ,axi_awregion //|> o
+ ,axi_awsize //|> o
+ ,axi_awuser //|> o
+ ,axi_awvalid //|> o
+ ,axi_bready //|> o
+ ,axi_prdata //|> o
+ ,axi_rready //|> o
+ ,axi_wdata //|> o
+ ,axi_wlast //|> o
+ ,axi_wstrb //|> o
+ ,axi_wvalid //|> o
+ ,test_complete //|> o
+ );
+
+parameter NV_FPGA_UNIT_MEM_DUT_AXI_CMD_PADDR_SHIFT = 4;
+parameter NV_FPGA_UNIT_MEM_DUT_AXI_WE_PADDR_SHIFT = 2;
+parameter NV_FPGA_UNIT_MEM_DUT_AXI_DATA_PADDR_SHIFT = 5;
+
+input apb_clk;
+input apb_rstn;
+input apb_wr_op;
+input axi_arready;
+input axi_awready;
+input [13:0] axi_bid;
+input [1:0] axi_bresp;
+input axi_bvalid;
+input axi_cmd_ram_sel;
+input [19:0] axi_paddr;
+input [31:0] axi_pwdata;
+input [255:0] axi_rdata;
+input axi_rdata_ram_sel;
+input axi_reg_sel;
+input [13:0] axi_rid;
+input axi_rlast;
+input [1:0] axi_rresp;
+input axi_rvalid;
+input axi_wdata_ram_sel;
+input axi_wready;
+input axi_wstrb_ram_sel;
+output [39:0] axi_araddr;
+output [1:0] axi_arburst;
+output [3:0] axi_arcache;
+output [13:0] axi_arid;
+output [7:0] axi_arlen;
+output [1:0] axi_arlock;
+output [2:0] axi_arprot;
+output [3:0] axi_arqos;
+output [3:0] axi_arregion;
+output [2:0] axi_arsize;
+output [25:0] axi_aruser;
+output axi_arvalid;
+output [39:0] axi_awaddr;
+output [1:0] axi_awburst;
+output [3:0] axi_awcache;
+output [13:0] axi_awid;
+output [7:0] axi_awlen;
+output [1:0] axi_awlock;
+output [2:0] axi_awprot;
+output [3:0] axi_awqos;
+output [3:0] axi_awregion;
+output [2:0] axi_awsize;
+output [25:0] axi_awuser;
+output axi_awvalid;
+output axi_bready;
+output [31:0] axi_prdata;
+output axi_rready;
+output [255:0] axi_wdata;
+output axi_wlast;
+output [31:0] axi_wstrb;
+output axi_wvalid;
+output test_complete;
+reg [7:0] axi_arcmd_line_end;
+reg [7:0] axi_arcmd_line_reg;
+reg [7:0] axi_awcmd_line_end;
+reg [7:0] axi_awcmd_line_reg;
+reg [127:0] axi_cmd_ram_di;
+reg [7:0] axi_cmd_ram_ra_reg;
+reg [7:0] axi_cmd_ram_wa;
+reg axi_cmd_ram_we;
+reg [31:0] axi_prdata;
+reg axi_rd_req_wait_reg;
+reg [8:0] axi_rdata_line_end;
+reg [8:0] axi_rdata_line_reg;
+reg [255:0] axi_rdata_ram_di_i;
+reg [8:0] axi_rdata_ram_wa_i;
+reg axi_rdata_ram_we_i;
+reg [31:0] axi_reg_prdata;
+reg [8:0] axi_wdata_line_end;
+reg [255:0] axi_wdata_ram_di;
+reg [8:0] axi_wdata_ram_ra_reg;
+reg [8:0] axi_wdata_ram_wa;
+reg axi_wdata_ram_we;
+reg [8:0] axi_wstrb_line_end;
+reg [31:0] axi_wstrb_ram_di;
+reg [8:0] axi_wstrb_ram_wa;
+reg axi_wstrb_ram_we;
+reg [23:0] reg_cmd_line_ctrl;
+reg [23:0] reg_cmd_num_total;
+reg [31:0] reg_cmd_pend_num;
+reg [31:0] reg_pg_addr_base;
+reg [31:0] reg_pg_addr_low;
+reg [31:0] reg_pg_cmd_ctrl;
+reg [15:0] reg_pg_data_ctrl;
+reg [31:0] reg_pg_wstrb_preset;
+reg [31:0] reg_rdata_line_ctrl;
+reg [26:1] reg_test_ctrl;
+reg [23:0] reg_wcmd_line_ctrl;
+reg [31:0] reg_wdata_line_ctrl;
+reg test_complete;
+reg test_finish_1t;
+reg test_reset_reg;
+reg test_run;
+reg [31:0] test_timer;
+reg [31:0] reg_resp_delay_ctrl; // spyglass disable W498
+reg [29:0] reg_pg_axi_id; // spyglass disable W498
+
+wire arcmd_info_update;
+wire awcmd_info_update;
+wire [26:0] axi_arcmd_info;
+wire [26:0] axi_arcmd_info_ram_di;
+wire [26:0] axi_arcmd_info_ram_dout;
+wire [7:0] axi_arcmd_info_ram_ra;
+wire axi_arcmd_info_ram_re;
+wire [7:0] axi_arcmd_info_ram_wa;
+wire axi_arcmd_info_ram_we;
+wire [7:0] axi_arcmd_line;
+wire [7:0] axi_arcmd_line_repeat_end;
+wire [7:0] axi_arcmd_line_start;
+wire [8:0] axi_arcmd_pend_cnt;
+wire [26:0] axi_awcmd_info;
+wire [26:0] axi_awcmd_info_ram_di;
+wire [26:0] axi_awcmd_info_ram_dout;
+wire [7:0] axi_awcmd_info_ram_ra;
+wire axi_awcmd_info_ram_re;
+wire [7:0] axi_awcmd_info_ram_wa;
+wire axi_awcmd_info_ram_we;
+wire [7:0] axi_awcmd_line;
+wire [7:0] axi_awcmd_line_repeat_end;
+wire [7:0] axi_awcmd_line_start;
+wire [8:0] axi_awcmd_pend_cnt;
+wire axi_clk;
+wire [23:0] axi_cmd_error_loc;
+wire [11:0] axi_cmd_line_end;
+wire axi_cmd_line_mismatch;
+wire [11:0] axi_cmd_line_repeat_end;
+wire [11:0] axi_cmd_line_start;
+wire [7:0] axi_cmd_pend_num_max;
+wire [7:0] axi_cmd_pend_num_min;
+wire [127:0] axi_cmd_ram_dout;
+wire [7:0] axi_cmd_ram_ra;
+wire axi_cmd_ram_re;
+wire axi_i_clk;
+wire axi_i_rstn;
+wire axi_rd_req_wait;
+wire axi_rdata_check_en;
+wire [31:0] axi_rdata_cnt_total;
+wire [255:0] axi_rdata_gold;
+wire [8:0] axi_rdata_line;
+wire [15:0] axi_rdata_line_repeat_end;
+wire [15:0] axi_rdata_line_start;
+wire [255:0] axi_rdata_ram_di;
+wire [255:0] axi_rdata_ram_dout;
+wire [8:0] axi_rdata_ram_ra;
+wire axi_rdata_ram_re;
+wire axi_rdata_ram_re_apb;
+wire [8:0] axi_rdata_ram_wa;
+wire axi_rdata_ram_we;
+wire axi_rdata_ram_we_apb;
+wire axi_rdata_sel;
+wire axi_rdata_update;
+wire [127:0] axi_req_cmd;
+wire [23:0] axi_req_cnt;
+wire [26:0] axi_req_info;
+wire [23:0] axi_req_num_total;
+wire [23:0] axi_req_rd_cnt;
+wire axi_req_rd_wr;
+wire axi_req_update;
+wire [31:0] axi_req_wd_cnt;
+wire axi_req_wd_update;
+wire [255:0] axi_req_wdata;
+wire [23:0] axi_req_wr_cnt;
+wire [31:0] axi_req_wstrb;
+wire [23:0] axi_resp_cnt_total;
+wire [255:0] axi_resp_rdata_di;
+wire axi_resp_rdata_we;
+wire [23:0] axi_rresp_cnt_total;
+wire axi_rstn;
+wire [63:0] axi_rstrb_gold;
+wire [63:0] axi_rstrb_ram_dout;
+wire [15:0] axi_wdata_line_repeat_end;
+wire [15:0] axi_wdata_line_start;
+wire [8:0] axi_wdata_phase_cnt_reg;
+wire [255:0] axi_wdata_ram_dout;
+wire [8:0] axi_wdata_ram_ra;
+wire axi_wdata_ram_re;
+wire axi_wstrb_line_mismatch;
+wire [31:0] axi_wstrb_ram_dout;
+wire [8:0] axi_wstrb_ram_ra;
+wire axi_wstrb_ram_re;
+wire last_cmd_issued;
+wire [26:0] pg_axi_arcmd_info;
+wire [26:0] pg_axi_awcmd_info;
+wire [127:0] pg_axi_cmd;
+wire [255:0] pg_axi_rdata;
+wire [63:0] pg_axi_rstrb;
+wire [255:0] pg_axi_wdata;
+wire [31:0] pg_axi_wstrb;
+wire pg_clk;
+wire pg_en;
+wire pg_rstn;
+wire pg_wr_and_rd_back_mode;
+wire [31:0] reg_cmd_line_ctrl_i;
+wire [31:0] reg_cmd_num_total_i;
+wire [31:0] reg_cmd_pend_num_i;
+wire [31:0] reg_outstand_status_i;
+wire [31:0] reg_pg_addr_base_i;
+wire [31:0] reg_pg_addr_low_i;
+wire [31:0] reg_pg_axi_id_i;
+wire [31:0] reg_pg_cmd_ctrl_i;
+wire [31:0] reg_pg_data_ctrl_i;
+wire [31:0] reg_pg_wstrb_preset_i;
+wire [31:0] reg_rdata_cnt_i;
+wire [31:0] reg_rdata_line_ctrl_i;
+wire [31:0] reg_req_cnt_i;
+wire [31:0] reg_req_wd_cnt_i;
+wire [31:0] reg_req_wr_cnt_i;
+wire [31:0] reg_resp_cnt_i;
+wire [31:0] reg_resp_delay_ctrl_i;
+wire [31:0] reg_rresp_cnt_i;
+wire [31:0] reg_test_ctrl_i;
+wire [31:0] reg_test_err_loc_i;
+wire [31:0] reg_test_status_i;
+wire [31:0] reg_wcmd_line_ctrl_i;
+wire [31:0] reg_wdata_line_ctrl_i;
+wire repeat_mode;
+wire rstn;
+wire status_clear;
+wire test_cmd_issuing;
+wire [12:0] test_error_out;
+wire test_finish;
+wire test_reset;
+wire test_run_i;
+
+
+
+// Power Controls can be tied off to 0
+
+// delay test_run by 1 cycle, in case the test mode and test_run are set at the same time
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ test_run <= 1'b0;
+ end else begin
+ test_run <= test_run_i;
+ end
+end
+assign status_clear = (~test_run & test_run_i) | (test_run & ~test_run_i); // 1T high pulse to clear all test status, but not clear test configuration.
+
+/////////////////////////////////////////////////////////////////////////
+// axi_cmd_ram
+/////////////////////////////////////////////////////////////////////////
+
+// write data concentration
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_cmd_ram_di[31:0] <= {32{1'b0}};
+ axi_cmd_ram_di[63:32] <= {32{1'b0}};
+ axi_cmd_ram_di[95:64] <= {32{1'b0}};
+ axi_cmd_ram_di[127:96] <= {32{1'b0}};
+ end else begin
+ if(apb_wr_op & axi_cmd_ram_sel)
+ case (axi_paddr[3:2]) // spyglass disable W71
+ 2'b00: axi_cmd_ram_di[31:0] <= axi_pwdata;
+ 2'b01: axi_cmd_ram_di[63:32] <= axi_pwdata;
+ 2'b10: axi_cmd_ram_di[95:64] <= axi_pwdata;
+ 2'b11: axi_cmd_ram_di[127:96] <= axi_pwdata;
+ endcase
+ end
+end
+
+// write control
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_cmd_ram_wa <= {8{1'b0}};
+ axi_cmd_ram_we <= 1'b0;
+ end else begin
+ axi_cmd_ram_wa <= axi_paddr>>NV_FPGA_UNIT_MEM_DUT_AXI_CMD_PADDR_SHIFT; // spyglass disable W164a W486
+ if(apb_wr_op & axi_cmd_ram_sel & (axi_paddr[3:2] == 2'b11))
+ axi_cmd_ram_we <= 1'b1;
+ else
+ axi_cmd_ram_we <= 1'b0;
+ end
+end
+
+// read control
+assign axi_cmd_ram_re = 1'b1;
+assign axi_cmd_ram_ra = ~test_run_i ? (axi_paddr>>NV_FPGA_UNIT_MEM_DUT_AXI_CMD_PADDR_SHIFT) // spyglass disable W164a W362 W486
+ : ~test_run ? axi_cmd_line_start
+ : ~axi_req_update ? axi_cmd_ram_ra_reg
+ : ~repeat_mode ? ((axi_cmd_ram_ra_reg > axi_cmd_line_end) ? 0 : (axi_cmd_ram_ra_reg+1'b1))
+ : ((axi_cmd_ram_ra_reg > axi_cmd_line_repeat_end) ? axi_cmd_line_start : (axi_cmd_ram_ra_reg+1'b1));
+
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_cmd_ram_ra_reg <= {8{1'b0}};
+ end else begin
+ axi_cmd_ram_ra_reg <= axi_cmd_ram_ra;
+ end
+end
+
+nv_ram_rws_256x128 axi_cmd_ram (
+ .clk (axi_i_clk) //|< w
+ ,.ra (axi_cmd_ram_ra[7:0]) //|< w
+ ,.re (axi_cmd_ram_re) //|< w
+ ,.dout (axi_cmd_ram_dout[127:0]) //|> w
+ ,.wa (axi_cmd_ram_wa[7:0]) //|< r
+ ,.we (axi_cmd_ram_we) //|< r
+ ,.di (axi_cmd_ram_di[127:0]) //|< r
+ ,.pwrbus_ram_pd ({32{1'b0}}) //|< ?
+ );
+
+/////////////////////////////////////////////////////////////////////////
+// axi_cmd_info_ram used for response check
+/////////////////////////////////////////////////////////////////////////
+
+//signal info_ram cmd_ram
+//axi_id [13:0] [13:0]
+//axi_len [21:14] [79:72]
+//axi_burst [23:22] [107:106]
+//axi_size [26:24] [110:108]
+
+assign axi_req_rd_wr = axi_cmd_ram_di[15];
+assign axi_req_info = {axi_cmd_ram_di[110:108], axi_cmd_ram_di[107:106], axi_cmd_ram_di[79:72], axi_cmd_ram_di[13:0]};
+
+// arcmd_info_ram
+
+assign axi_arcmd_info_ram_di = axi_req_rd_wr ? axi_req_info : 0;
+assign axi_arcmd_info_ram_wa = axi_req_rd_wr ? axi_cmd_ram_wa : 0;
+assign axi_arcmd_info_ram_we = axi_req_rd_wr & axi_cmd_ram_we;
+assign axi_arcmd_info_ram_re = 1'b1;
+assign axi_arcmd_info_ram_ra = axi_arcmd_line;
+assign axi_arcmd_line = ~test_run ? axi_arcmd_line_start
+ : ~arcmd_info_update ? axi_arcmd_line_reg
+ : ~repeat_mode ? ((axi_arcmd_line_reg > axi_arcmd_line_end) ? 0 : (axi_arcmd_line_reg+1'b1))
+ : ((axi_arcmd_line_reg > axi_arcmd_line_repeat_end) ? axi_arcmd_line_start : (axi_arcmd_line_reg+1'b1));
+
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_arcmd_line_reg <= {8{1'b0}};
+ axi_arcmd_line_end <= {8{1'b0}};
+ end else begin
+ axi_arcmd_line_reg <= axi_arcmd_line;
+ if(axi_arcmd_info_ram_wa > axi_arcmd_line_end)
+ axi_arcmd_line_end <= axi_arcmd_info_ram_wa;
+ end
+end
+
+nv_ram_rws_256x27 axi_arcmd_info_ram (
+ .clk (axi_i_clk) //|< w
+ ,.ra (axi_arcmd_info_ram_ra[7:0]) //|< w
+ ,.re (axi_arcmd_info_ram_re) //|< w
+ ,.dout (axi_arcmd_info_ram_dout[26:0]) //|> w
+ ,.wa (axi_arcmd_info_ram_wa[7:0]) //|< w
+ ,.we (axi_arcmd_info_ram_we) //|< w
+ ,.di (axi_arcmd_info_ram_di[26:0]) //|< w
+ ,.pwrbus_ram_pd ({32{1'b0}}) //|< ?
+ );
+
+// awcmd_info_ram
+
+assign axi_awcmd_info_ram_di = ~axi_req_rd_wr ? axi_req_info : 0;
+assign axi_awcmd_info_ram_wa = ~axi_req_rd_wr ? axi_cmd_ram_wa : 0;
+assign axi_awcmd_info_ram_we = ~axi_req_rd_wr & axi_cmd_ram_we;
+assign axi_awcmd_info_ram_re = 1'b1;
+assign axi_awcmd_info_ram_ra = axi_awcmd_line;
+assign axi_awcmd_line = ~test_run ? axi_awcmd_line_start
+ : ~awcmd_info_update ? axi_awcmd_line_reg
+ : ~repeat_mode ? ((axi_awcmd_line_reg > axi_awcmd_line_end) ? 0 : (axi_awcmd_line_reg+1'b1))
+ : ((axi_awcmd_line_reg > axi_awcmd_line_repeat_end) ? axi_awcmd_line_start : (axi_awcmd_line_reg+1'b1));
+
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_awcmd_line_reg <= {8{1'b0}};
+ axi_awcmd_line_end <= {8{1'b0}};
+ end else begin
+ axi_awcmd_line_reg <= axi_arcmd_line;
+ if(axi_awcmd_info_ram_wa > axi_awcmd_line_end)
+ axi_awcmd_line_end <= axi_awcmd_info_ram_wa;
+ end
+end
+
+nv_ram_rws_256x27 axi_awcmd_info_ram (
+ .clk (axi_i_clk) //|< w
+ ,.ra (axi_awcmd_info_ram_ra[7:0]) //|< w
+ ,.re (axi_awcmd_info_ram_re) //|< w
+ ,.dout (axi_awcmd_info_ram_dout[26:0]) //|> w
+ ,.wa (axi_awcmd_info_ram_wa[7:0]) //|< w
+ ,.we (axi_awcmd_info_ram_we) //|< w
+ ,.di (axi_awcmd_info_ram_di[26:0]) //|< w
+ ,.pwrbus_ram_pd ({32{1'b0}}) //|< ?
+ );
+
+/////////////////////////////////////////////////////////////////////////
+// axi_wdata_ram
+/////////////////////////////////////////////////////////////////////////
+
+// data concentration
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_wdata_ram_di[31:0] <= {32{1'b0}};
+ axi_wdata_ram_di[63:32] <= {32{1'b0}};
+ axi_wdata_ram_di[95:64] <= {32{1'b0}};
+ axi_wdata_ram_di[127:96] <= {32{1'b0}};
+ axi_wdata_ram_di[159:128] <= {32{1'b0}};
+ axi_wdata_ram_di[191:160] <= {32{1'b0}};
+ axi_wdata_ram_di[223:192] <= {32{1'b0}};
+ axi_wdata_ram_di[255:224] <= {32{1'b0}};
+ end else begin
+ if(apb_wr_op & axi_wdata_ram_sel)
+ case (axi_paddr[4:2]) // spyglass disable W71
+ 0: axi_wdata_ram_di[31:0] <= axi_pwdata;
+ 1: axi_wdata_ram_di[63:32] <= axi_pwdata;
+ 2: axi_wdata_ram_di[95:64] <= axi_pwdata;
+ 3: axi_wdata_ram_di[127:96] <= axi_pwdata;
+ 4: axi_wdata_ram_di[159:128] <= axi_pwdata;
+ 5: axi_wdata_ram_di[191:160] <= axi_pwdata;
+ 6: axi_wdata_ram_di[223:192] <= axi_pwdata;
+ 7: axi_wdata_ram_di[255:224] <= axi_pwdata;
+ endcase
+ end
+end
+
+// write control
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_wdata_ram_wa <= {9{1'b0}};
+ axi_wdata_ram_we <= 1'b0;
+ end else begin
+ axi_wdata_ram_wa <= axi_paddr[19:5]; // spyglass disable W164a
+ if(apb_wr_op & axi_wdata_ram_sel & (axi_paddr[4:2] == 7))
+ axi_wdata_ram_we <= 1'b1;
+ else
+ axi_wdata_ram_we <= 1'b0;
+ end
+end
+
+// read control
+assign axi_wdata_ram_re = 1'b1;
+assign axi_wdata_ram_ra = ~test_run_i ? (axi_paddr>>NV_FPGA_UNIT_MEM_DUT_AXI_DATA_PADDR_SHIFT) // spyglass disable W164a W362 W486
+ : ~test_run ? axi_wdata_line_start
+ : ~axi_req_wd_update ? axi_wdata_ram_ra_reg
+ : ~repeat_mode ? ((axi_wdata_ram_ra_reg > axi_wdata_line_end) ? 0 : (axi_wdata_ram_ra_reg+1'b1))
+ : ((axi_wdata_ram_ra_reg > axi_wdata_line_repeat_end) ? axi_wdata_line_start : (axi_wdata_ram_ra_reg+1'b1));
+
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_wdata_ram_ra_reg <= {9{1'b0}};
+ axi_wdata_line_end <= {9{1'b0}};
+ end else begin
+ axi_wdata_ram_ra_reg <= axi_wdata_ram_ra;
+ if(axi_wdata_line_end < axi_wdata_ram_wa)
+ axi_wdata_line_end <= axi_wdata_ram_wa;
+ end
+end
+
+nv_ram_rws_512x256 axi_wdata_ram (
+ .clk (axi_i_clk) //|< w
+ ,.ra (axi_wdata_ram_ra[8:0]) //|< w
+ ,.re (axi_wdata_ram_re) //|< w
+ ,.dout (axi_wdata_ram_dout[255:0]) //|> w
+ ,.wa (axi_wdata_ram_wa[8:0]) //|< r
+ ,.we (axi_wdata_ram_we) //|< r
+ ,.di (axi_wdata_ram_di[255:0]) //|< r
+ ,.pwrbus_ram_pd ({32{1'b0}}) //|< ?
+ );
+
+/////////////////////////////////////////////////////////////////////////
+// axi_wstrb_ram
+/////////////////////////////////////////////////////////////////////////
+
+// data concentration
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_wstrb_ram_di[31:0] <= {32{1'b0}};
+ end else begin
+ if(apb_wr_op & axi_wstrb_ram_sel)
+ axi_wstrb_ram_di[31:0] <= axi_pwdata; // spyglass disable W164a
+ end
+end
+
+// write control
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_wstrb_ram_wa <= {9{1'b0}};
+ axi_wstrb_ram_we <= 1'b0;
+ end else begin
+ axi_wstrb_ram_wa <= axi_paddr[19:2]; // spyglass disable W164a
+ if(apb_wr_op & axi_wstrb_ram_sel)
+ axi_wstrb_ram_we <= 1'b1;
+ else
+ axi_wstrb_ram_we <= 1'b0;
+ end
+end
+
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_wstrb_line_end <= {9{1'b0}};
+ end else begin
+ if(axi_wstrb_ram_wa > axi_wstrb_line_end)
+ axi_wstrb_line_end <= axi_wstrb_ram_wa;
+ end
+end
+
+// read control
+assign axi_wstrb_ram_re = 1'b1;
+assign axi_wstrb_ram_ra = ~test_run_i ? (axi_paddr>>NV_FPGA_UNIT_MEM_DUT_AXI_WE_PADDR_SHIFT) : axi_wdata_ram_ra; // spyglass disable W164a W486
+
+nv_ram_rws_512x32 axi_wstrb_ram (
+ .clk (axi_i_clk) //|< w
+ ,.ra (axi_wstrb_ram_ra[8:0]) //|< w
+ ,.re (axi_wstrb_ram_re) //|< w
+ ,.dout (axi_wstrb_ram_dout[31:0]) //|> w
+ ,.wa (axi_wstrb_ram_wa[8:0]) //|< r
+ ,.we (axi_wstrb_ram_we) //|< r
+ ,.di (axi_wstrb_ram_di[31:0]) //|< r
+ ,.pwrbus_ram_pd ({32{1'b0}}) //|< ?
+ );
+
+/////////////////////////////////////////////////////////////////////////
+// axi_rdata_ram
+/////////////////////////////////////////////////////////////////////////
+
+// data concentration
+always @(posedge axi_i_clk or negedge axi_i_rstn) begin
+ if (!axi_i_rstn) begin
+ axi_rdata_ram_di_i[31:0] <= {32{1'b0}};
+ axi_rdata_ram_di_i[63:32] <= {32{1'b0}};
+ axi_rdata_ram_di_i[95:64] <= {32{1'b0}};
+ axi_rdata_ram_di_i[127:96] <= {32{1'b0}};
+ axi_rdata_ram_di_i[159:128] <= {32{1'b0}};
+ axi_rdata_ram_di_i[191:160] <= {32{1'b0}};
+ axi_rdata_ram_di_i[223:192] <= {32{1'b0}};
+ axi_rdata_ram_di_i[255:224] <= {32{1'b0}};
+ end else begin
+ if(apb_wr_op & axi_rdata_ram_sel)
+ case (axi_paddr[4:2]) // spyglass disable W71
+ 0: axi_rdata_ram_di_i[31:0] <= axi_pwdata;
+ 1: axi_rdata_ram_di_i[63:32] <= axi_pwdata;
+ 2: axi_rdata_ram_di_i[95:64] <= axi_pwdata;
+ 3: axi_rdata_ram_di_i[127:96] <= axi_pwdata;
+ 4: axi_rdata_ram_di_i[159:128] <= axi_pwdata;
+ 5: axi_rdata_ram_di_i[191:160] <= axi_pwdata;
+ 6: axi_rdata_ram_di_i[223:192] <= axi_pwdata;
+ 7: axi_rdata_ram_di_i[255:224] <= axi_pwdata;
+ endcase
+ end
+end
+
+// write control
+always @(posedge axi_i_clk or negedge axi_i_rstn) begin
+ if (!axi_i_rstn) begin
+ axi_rdata_ram_wa_i <= {9{1'b0}};
+ axi_rdata_ram_we_i <= 1'b0;
+ end else begin
+ axi_rdata_ram_wa_i <= axi_paddr[19:5]; // spyglass disable W164a
+ if(apb_wr_op & axi_rdata_ram_sel & (axi_paddr[4:2] == 7))
+ axi_rdata_ram_we_i <= 1'b1;
+ else
+ axi_rdata_ram_we_i <= 1'b0;
+ end
+end
+
+// write source select
+assign axi_rdata_ram_we_apb = (~test_run_i | test_finish | axi_rdata_check_en); // 1) not start issue cmd; 2) received all response; 3) rdata self check mode.
+assign axi_rdata_ram_we = axi_rdata_ram_we_apb ? axi_rdata_ram_we_i : axi_resp_rdata_we;
+assign axi_rdata_ram_di = axi_rdata_ram_we_apb ? axi_rdata_ram_di_i : axi_resp_rdata_di;
+assign axi_rdata_ram_wa = axi_rdata_ram_we_apb ? axi_rdata_ram_wa_i : axi_rdata_line;
+assign axi_rdata_line = ~test_run ? axi_rdata_line_start // spyglass disable W164a W362
+ : ~axi_rdata_update ? axi_rdata_line_reg
+ : ~repeat_mode ? ((axi_rdata_line_reg > axi_rdata_line_end) ? 0 : (axi_rdata_line_reg+1'b1))
+ : ((axi_rdata_line_reg > axi_rdata_line_repeat_end) ? axi_rdata_line_start : (axi_rdata_line_reg+1'b1));
+
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ axi_rdata_line_reg <= {9{1'b0}};
+ axi_rdata_line_end <= {9{1'b0}};
+ end else begin
+ axi_rdata_line_reg <= axi_rdata_line;
+ if(axi_rdata_ram_wa > axi_rdata_line_end)
+ axi_rdata_line_end <= axi_rdata_ram_wa;
+ end
+end
+
+// read control
+assign axi_rdata_ram_re_apb = (~test_run_i | test_finish | ~axi_rdata_check_en);
+assign axi_rdata_ram_ra = axi_rdata_ram_re_apb ? axi_paddr>>NV_FPGA_UNIT_MEM_DUT_AXI_DATA_PADDR_SHIFT : axi_rdata_line; // spyglass disable W164a W486
+assign axi_rdata_ram_re = 1'b1;
+
+nv_ram_rws_512x256 axi_rdata_ram (
+ .clk (apb_clk) //|< i
+ ,.ra (axi_rdata_ram_ra[8:0]) //|< w
+ ,.re (axi_rdata_ram_re) //|< w
+ ,.dout (axi_rdata_ram_dout[255:0]) //|> w
+ ,.wa (axi_rdata_ram_wa[8:0]) //|< w
+ ,.we (axi_rdata_ram_we) //|< w
+ ,.di (axi_rdata_ram_di[255:0]) //|< w
+ ,.pwrbus_ram_pd ({32{1'b0}}) //|< ?
+ );
+
+/////////////////////////////////////////////////////////////////////////
+// read ram data through APB bus
+/////////////////////////////////////////////////////////////////////////
+
+always @(
+ axi_reg_sel
+ or axi_reg_prdata
+ or axi_cmd_ram_sel
+ or axi_paddr
+ or axi_cmd_ram_dout
+ or axi_wstrb_ram_sel
+ or axi_wstrb_ram_dout
+ or axi_wdata_ram_sel
+ or axi_wdata_ram_dout
+ or axi_rdata_ram_sel
+ or axi_rdata_ram_dout
+ ) begin
+ if(axi_reg_sel)
+ axi_prdata = axi_reg_prdata;
+ else if(axi_cmd_ram_sel)
+ case (axi_paddr[3:2])
+ 2'b00: axi_prdata = axi_cmd_ram_dout[31:0] ;
+ 2'b01: axi_prdata = axi_cmd_ram_dout[63:32] ;
+ 2'b10: axi_prdata = axi_cmd_ram_dout[95:64] ;
+ 2'b11: axi_prdata = axi_cmd_ram_dout[127:96] ;
+ default: axi_prdata = 32'b0;
+ endcase
+ else if(axi_wstrb_ram_sel)
+ axi_prdata = axi_wstrb_ram_dout; // spyglass disable W164b
+ else if(axi_wdata_ram_sel)
+ case (axi_paddr[4:2])
+ 0: axi_prdata = axi_wdata_ram_dout[31:0]; // spyglass disable W164b
+ 1: axi_prdata = axi_wdata_ram_dout[63:32]; // spyglass disable W164b
+ 2: axi_prdata = axi_wdata_ram_dout[95:64]; // spyglass disable W164b
+ 3: axi_prdata = axi_wdata_ram_dout[127:96]; // spyglass disable W164b
+ 4: axi_prdata = axi_wdata_ram_dout[159:128]; // spyglass disable W164b
+ 5: axi_prdata = axi_wdata_ram_dout[191:160]; // spyglass disable W164b
+ 6: axi_prdata = axi_wdata_ram_dout[223:192]; // spyglass disable W164b
+ 7: axi_prdata = axi_wdata_ram_dout[255:224]; // spyglass disable W164b
+ default: axi_prdata = 32'b0;
+ endcase
+ else if(axi_rdata_ram_sel)
+ case (axi_paddr[4:2])
+ 0: axi_prdata = axi_rdata_ram_dout[31:0];
+ 1: axi_prdata = axi_rdata_ram_dout[63:32];
+ 2: axi_prdata = axi_rdata_ram_dout[95:64];
+ 3: axi_prdata = axi_rdata_ram_dout[127:96];
+ 4: axi_prdata = axi_rdata_ram_dout[159:128];
+ 5: axi_prdata = axi_rdata_ram_dout[191:160];
+ 6: axi_prdata = axi_rdata_ram_dout[223:192];
+ 7: axi_prdata = axi_rdata_ram_dout[255:224];
+ default: axi_prdata = 32'b0;
+ endcase
+ else
+ axi_prdata = 32'b0;
+end
+
+//&Always;
+// case(1'b1)
+// axi_reg_sel : axi_prdata = axi_reg_prdata;
+// axi_cmd_ram_sel : axi_prdata = axi_cmd_ram_prdata;
+// axi_wstrb_ram_sel : axi_prdata = axi_wstrb_ram_prdata;
+// axi_wdata_ram_sel : axi_prdata = axi_wdata_ram_prdata;
+// axi_rdata_ram_sel : axi_prdata = axi_rdata_ram_prdata;
+// default: axi_prdata = 0;
+// endcase
+//&End;
+//
+
+/////////////////////////////////////////////////////////////////////////////
+// sub module instances and port connection
+/////////////////////////////////////////////////////////////////////////////
+
+NV_FPGA_unit_checkbox_mem_dut_axi_req_256 axi_req (
+ .axi_clk (axi_clk) //|< w
+ ,.axi_rstn (axi_rstn) //|< w
+ ,.axi_arcmd_pend_cnt (axi_arcmd_pend_cnt[8:0]) //|< w
+ ,.axi_arready (axi_arready) //|< i
+ ,.axi_awcmd_pend_cnt (axi_awcmd_pend_cnt[8:0]) //|< w
+ ,.axi_awready (axi_awready) //|< i
+ ,.axi_cmd_pend_num_max (axi_cmd_pend_num_max[7:0]) //|< w
+ ,.axi_rd_req_wait (axi_rd_req_wait) //|< w
+ ,.axi_req_cmd (axi_req_cmd[127:0]) //|< w
+ ,.axi_req_wdata (axi_req_wdata[255:0]) //|< w
+ ,.axi_req_wstrb (axi_req_wstrb[31:0]) //|< w
+ ,.axi_wready (axi_wready) //|< i
+ ,.status_clear (status_clear) //|< w
+ ,.test_cmd_issuing (test_cmd_issuing) //|< w
+ ,.axi_araddr (axi_araddr[39:0]) //|> o
+ ,.axi_arburst (axi_arburst[1:0]) //|> o
+ ,.axi_arcache (axi_arcache[3:0]) //|> o
+ ,.axi_arid (axi_arid[13:0]) //|> o
+ ,.axi_arlen (axi_arlen[7:0]) //|> o
+ ,.axi_arlock (axi_arlock[1:0]) //|> o
+ ,.axi_arprot (axi_arprot[2:0]) //|> o
+ ,.axi_arqos (axi_arqos[3:0]) //|> o
+ ,.axi_arregion (axi_arregion[3:0]) //|> o
+ ,.axi_arsize (axi_arsize[2:0]) //|> o
+ ,.axi_aruser (axi_aruser[25:0]) //|> o
+ ,.axi_arvalid (axi_arvalid) //|> o
+ ,.axi_awaddr (axi_awaddr[39:0]) //|> o
+ ,.axi_awburst (axi_awburst[1:0]) //|> o
+ ,.axi_awcache (axi_awcache[3:0]) //|> o
+ ,.axi_awid (axi_awid[13:0]) //|> o
+ ,.axi_awlen (axi_awlen[7:0]) //|> o
+ ,.axi_awlock (axi_awlock[1:0]) //|> o
+ ,.axi_awprot (axi_awprot[2:0]) //|> o
+ ,.axi_awqos (axi_awqos[3:0]) //|> o
+ ,.axi_awregion (axi_awregion[3:0]) //|> o
+ ,.axi_awsize (axi_awsize[2:0]) //|> o
+ ,.axi_awuser (axi_awuser[25:0]) //|> o
+ ,.axi_awvalid (axi_awvalid) //|> o
+ ,.axi_req_cnt (axi_req_cnt[23:0]) //|> w
+ ,.axi_req_rd_cnt (axi_req_rd_cnt[23:0]) //|> w
+ ,.axi_req_update (axi_req_update) //|> w
+ ,.axi_req_wd_cnt (axi_req_wd_cnt[31:0]) //|> w
+ ,.axi_req_wd_update (axi_req_wd_update) //|> w
+ ,.axi_req_wr_cnt (axi_req_wr_cnt[23:0]) //|> w
+ ,.axi_wdata (axi_wdata[255:0]) //|> o
+ ,.axi_wdata_phase_cnt_reg (axi_wdata_phase_cnt_reg[8:0]) //|> w
+ ,.axi_wlast (axi_wlast) //|> o
+ ,.axi_wstrb (axi_wstrb[31:0]) //|> o
+ ,.axi_wvalid (axi_wvalid) //|> o
+ );
+NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256 axi_req_gen (
+ .pg_clk (pg_clk) //|< w
+ ,.pg_rstn (pg_rstn) //|< w
+ ,.arcmd_info_update (arcmd_info_update) //|< w
+ ,.awcmd_info_update (awcmd_info_update) //|< w
+ ,.axi_rdata_cnt_total (axi_rdata_cnt_total[31:0]) //|< w
+ ,.axi_req_update (axi_req_update) //|< w
+ ,.axi_req_wd_cnt (axi_req_wd_cnt[15:0]) //|< w
+ ,.axi_wdata_phase_cnt_reg (axi_wdata_phase_cnt_reg[8:0]) //|< w
+ ,.reg_pg_addr_base (reg_pg_addr_base[31:0]) //|< r
+ ,.reg_pg_addr_low (reg_pg_addr_low[31:0]) //|< r
+ ,.reg_pg_axi_id (reg_pg_axi_id[29:0]) //|< r
+ ,.reg_pg_cmd_ctrl (reg_pg_cmd_ctrl[31:0]) //|< r
+ ,.reg_pg_data_ctrl (reg_pg_data_ctrl[15:0]) //|< r
+ ,.reg_pg_wstrb_preset (reg_pg_wstrb_preset[31:0]) //|< r
+ ,.status_clear (status_clear) //|< w
+ ,.pg_axi_arcmd_info (pg_axi_arcmd_info[26:0]) //|> w
+ ,.pg_axi_awcmd_info (pg_axi_awcmd_info[26:0]) //|> w
+ ,.pg_axi_cmd (pg_axi_cmd[127:0]) //|> w
+ ,.pg_axi_rdata (pg_axi_rdata[255:0]) //|> w
+ ,.pg_axi_rstrb (pg_axi_rstrb[63:0]) //|> w
+ ,.pg_axi_wdata (pg_axi_wdata[255:0]) //|> w
+ ,.pg_axi_wstrb (pg_axi_wstrb[31:0]) //|> w
+ ,.pg_wr_and_rd_back_mode (pg_wr_and_rd_back_mode) //|> w
+ ,.reg_pg_addr_base_i (reg_pg_addr_base_i[31:0]) //|> w
+ ,.reg_pg_addr_low_i (reg_pg_addr_low_i[31:0]) //|> w
+ ,.reg_pg_axi_id_i (reg_pg_axi_id_i[31:0]) //|> w
+ ,.reg_pg_cmd_ctrl_i (reg_pg_cmd_ctrl_i[31:0]) //|> w
+ ,.reg_pg_data_ctrl_i (reg_pg_data_ctrl_i[31:0]) //|> w
+ ,.reg_pg_wstrb_preset_i (reg_pg_wstrb_preset_i[31:0]) //|> w
+ );
+NV_FPGA_unit_checkbox_mem_dut_axi_resp_256 axi_resp (
+ .axi_clk (axi_clk) //|< w
+ ,.axi_rstn (axi_rstn) //|< w
+ ,.axi_arcmd_info (axi_arcmd_info[26:0]) //|< w
+ ,.axi_awcmd_info (axi_awcmd_info[13:0]) //|< w
+ ,.axi_bid (axi_bid[13:0]) //|< i
+ ,.axi_bresp (axi_bresp[1:0]) //|< i
+ ,.axi_bvalid (axi_bvalid) //|< i
+ ,.axi_cmd_pend_num_min (axi_cmd_pend_num_min[7:0]) //|< w
+ ,.axi_rdata (axi_rdata[255:0]) //|< i
+ ,.axi_rdata_check_en (axi_rdata_check_en) //|< w
+ ,.axi_rdata_gold (axi_rdata_gold[255:0]) //|< w
+ ,.axi_req_rd_cnt (axi_req_rd_cnt[23:0]) //|< w
+ ,.axi_req_wr_cnt (axi_req_wr_cnt[23:0]) //|< w
+ ,.axi_rid (axi_rid[13:0]) //|< i
+ ,.axi_rlast (axi_rlast) //|< i
+ ,.axi_rresp (axi_rresp[1:0]) //|< i
+ ,.axi_rstrb_gold (axi_rstrb_gold[31:0]) //|< w
+ ,.axi_rvalid (axi_rvalid) //|< i
+ ,.reg_resp_delay_ctrl (reg_resp_delay_ctrl[25:0]) //|< r
+ ,.status_clear (status_clear) //|< w
+ ,.arcmd_info_update (arcmd_info_update) //|> w
+ ,.awcmd_info_update (awcmd_info_update) //|> w
+ ,.axi_arcmd_pend_cnt (axi_arcmd_pend_cnt[8:0]) //|> w
+ ,.axi_awcmd_pend_cnt (axi_awcmd_pend_cnt[8:0]) //|> w
+ ,.axi_bready (axi_bready) //|> o
+ ,.axi_cmd_error_loc (axi_cmd_error_loc[23:0]) //|> w
+ ,.axi_rdata_cnt_total (axi_rdata_cnt_total[31:0]) //|> w
+ ,.axi_rdata_update (axi_rdata_update) //|> w
+ ,.axi_resp_cnt_total (axi_resp_cnt_total[23:0]) //|> w
+ ,.axi_resp_rdata_di (axi_resp_rdata_di[255:0]) //|> w
+ ,.axi_resp_rdata_we (axi_resp_rdata_we) //|> w
+ ,.axi_rready (axi_rready) //|> o
+ ,.axi_rresp_cnt_total (axi_rresp_cnt_total[23:0]) //|> w
+ ,.reg_resp_delay_ctrl_i (reg_resp_delay_ctrl_i[31:0]) //|> w
+ ,.test_error_out (test_error_out[12:0]) //|> w
+ );
+
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ test_reset_reg <= 1'b0;
+ end else begin
+ test_reset_reg <= test_reset;
+ end
+end
+
+assign rstn = apb_rstn & ~test_reset_reg;
+
+assign axi_i_clk = apb_clk;
+assign axi_i_rstn = rstn;
+
+assign axi_clk = apb_clk;
+assign axi_rstn = rstn;
+
+assign pg_clk = apb_clk;
+assign pg_rstn = rstn;
+
+// select axi request from pattern gen or ram output
+assign axi_req_cmd = pg_en ? pg_axi_cmd : axi_cmd_ram_dout;
+assign axi_req_wdata = pg_en ? pg_axi_wdata : axi_wdata_ram_dout;
+assign axi_req_wstrb = pg_en ? pg_axi_wstrb : axi_wstrb_ram_dout;
+
+// select axi response rdata golden from pg or axi_rdata_ram.
+assign axi_rdata_gold = axi_rdata_sel ? axi_rdata_ram_dout : pg_axi_rdata;
+assign axi_rstrb_gold = axi_rdata_sel ? axi_rstrb_ram_dout : pg_axi_rstrb;
+assign axi_rstrb_ram_dout = {2{32'hFFFF_FFFF}};
+
+// select axi request info from pattern gen or info ram output. those info are used for response check.
+assign axi_arcmd_info = pg_en ? pg_axi_arcmd_info : axi_arcmd_info_ram_dout;
+assign axi_awcmd_info = pg_en ? pg_axi_awcmd_info : axi_awcmd_info_ram_dout;
+
+assign last_cmd_issued = (axi_req_cnt == axi_req_num_total);
+assign test_cmd_issuing = test_run & !last_cmd_issued;
+
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_rd_req_wait_reg <= 1'b0;
+ end else begin
+ axi_rd_req_wait_reg <= axi_rd_req_wait;
+ end
+end
+
+assign axi_rd_req_wait = ~(pg_en & pg_wr_and_rd_back_mode) ? 1'b0
+ : axi_awvalid & axi_awready ? 1'b1
+ : axi_bvalid & axi_bready ? 1'b0 : axi_rd_req_wait_reg;
+
+// test status
+assign test_finish = (axi_req_num_total == axi_resp_cnt_total);
+assign axi_cmd_line_mismatch = test_run & ~pg_en & (axi_cmd_line_end != (axi_arcmd_line_end + axi_awcmd_line_end + 1)); // spyglass disable W362
+assign axi_wstrb_line_mismatch = test_run & ~pg_en & (axi_wstrb_line_end != axi_wdata_line_end);
+
+//// axi outstanding control
+//&Vector 10 axi_arcmd_pend_cnt;
+//&Vector 10 axi_awcmd_pend_cnt;
+//&Always posedge;
+// if((axi_arvalid & axi_arready) & ~(axi_rvalid & axi_rready & axi_rlast))
+// axi_arcmd_pend_cnt <0= axi_arcmd_pend_cnt + 1'b1;
+// else if(~(axi_arvalid & axi_arready) & (axi_rvalid & axi_rready & axi_rlast))
+// axi_arcmd_pend_cnt <= axi_arcmd_pend_cnt - 1'b1;
+//&End;
+//
+//&Always posedge;
+// if((axi_awvalid & axi_awready) & ~(axi_bvalid & axi_bready))
+// axi_awcmd_pend_cnt <0= axi_awcmd_pend_cnt + 1'b1;
+// else if(~(axi_awvalid & axi_awready) & (axi_bvalid & axi_bready))
+// axi_awcmd_pend_cnt <= axi_awcmd_pend_cnt - 1'b1;
+//&End;
+
+// test timer
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ test_timer <= {32{1'b0}};
+ end else begin
+ if(status_clear)
+ test_timer <= 32'b0;
+ else if(~test_finish)
+ test_timer <= test_timer + 1;
+ end
+end
+
+// finish interrupt
+always @(posedge apb_clk or negedge apb_rstn) begin
+ if (!apb_rstn) begin
+ test_finish_1t <= 1'b0;
+ test_complete <= 1'b0;
+ end else begin
+ test_finish_1t <= test_finish;
+ if(test_finish & ~test_finish_1t & (|axi_resp_cnt_total))
+ test_complete <= 1'b1;
+ if(test_complete)
+ test_complete <= 1'b0;
+ end
+end
+
+/////////////////////////////////////////////////////////////////////////////
+// apb registers
+/////////////////////////////////////////////////////////////////////////////
+
+`define NV_FPGA_UNIT_MEM_DUT_REG_TEST_CTRL 16'h0000
+`define NV_FPGA_UNIT_MEM_DUT_REG_CMD_NUM_TOTAL 16'h0004
+`define NV_FPGA_UNIT_MEM_DUT_REG_CMD_LINE_CTRL 16'h0008
+`define NV_FPGA_UNIT_MEM_DUT_REG_WDATA_LINE_CTRL 16'h000C
+`define NV_FPGA_UNIT_MEM_DUT_REG_WCMD_LINE_CTRL 16'h0010
+`define NV_FPGA_UNIT_MEM_DUT_REG_RDATA_LINE_CTRL 16'h0014
+`define NV_FPGA_UNIT_MEM_DUT_REG_RESP_DELAY_CTRL 16'h0018
+`define NV_FPGA_UNIT_MEM_DUT_REG_CMD_PEND_NUM 16'h001C
+
+`define NV_FPGA_UNIT_MEM_DUT_REG_PG_CMD_CTRL 16'h0020
+`define NV_FPGA_UNIT_MEM_DUT_REG_PG_AXI_ID 16'h0024
+`define NV_FPGA_UNIT_MEM_DUT_REG_PG_ADDR_BASE 16'h0028
+`define NV_FPGA_UNIT_MEM_DUT_REG_PG_ADDR_LOW 16'h002C
+`define NV_FPGA_UNIT_MEM_DUT_REG_PG_DATA_CTRL 16'h0030
+`define NV_FPGA_UNIT_MEM_DUT_REG_PG_WSTRB 16'h0034
+
+`define NV_FPGA_UNIT_MEM_DUT_REG_OUTSTAND_STATUS 16'h0040
+`define NV_FPGA_UNIT_MEM_DUT_REG_TEST_STATUS 16'h0044
+`define NV_FPGA_UNIT_MEM_DUT_REG_TEST_ERR_LOC 16'h0048
+`define NV_FPGA_UNIT_MEM_DUT_REG_RESP_CNT 16'h004C
+`define NV_FPGA_UNIT_MEM_DUT_REG_RRESP_CNT 16'h0050
+`define NV_FPGA_UNIT_MEM_DUT_REG_RDATA_CNT 16'h0054
+`define NV_FPGA_UNIT_MEM_DUT_REG_REQ_CNT 16'h0058
+`define NV_FPGA_UNIT_MEM_DUT_REG_REQ_WR_CNT 16'h005C
+`define NV_FPGA_UNIT_MEM_DUT_REG_REQ_WD_CNT 16'h0060
+`define NV_FPGA_UNIT_MEM_DUT_REG_TEST_TIMER 16'h0064
+
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ reg_test_ctrl[26:1] <= {26{1'b0}};
+ reg_cmd_num_total <= {24{1'b0}};
+ reg_cmd_line_ctrl <= {24{1'b0}};
+ reg_wdata_line_ctrl <= {32{1'b0}};
+ reg_wcmd_line_ctrl <= {24{1'b0}};
+ reg_rdata_line_ctrl <= {32{1'b0}};
+ reg_resp_delay_ctrl <= {32{1'b0}};
+ reg_cmd_pend_num <= 32'h80;
+ reg_pg_cmd_ctrl <= {32{1'b0}};
+ reg_pg_axi_id <= {30{1'b0}};
+ reg_pg_addr_base <= {32{1'b0}};
+ reg_pg_addr_low <= {32{1'b0}};
+ reg_pg_data_ctrl <= {16{1'b0}};
+ reg_pg_wstrb_preset <= {32{1'b0}};
+ end else begin
+ if(axi_reg_sel & apb_wr_op) begin
+ case(axi_paddr[15:0]) // spyglass disable W71
+ `NV_FPGA_UNIT_MEM_DUT_REG_TEST_CTRL : reg_test_ctrl[26:1] <= axi_pwdata[26:1];
+ `NV_FPGA_UNIT_MEM_DUT_REG_CMD_NUM_TOTAL : reg_cmd_num_total <= axi_pwdata[23:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_CMD_LINE_CTRL : reg_cmd_line_ctrl <= axi_pwdata[23:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_WDATA_LINE_CTRL : reg_wdata_line_ctrl <= axi_pwdata[31:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_WCMD_LINE_CTRL : reg_wcmd_line_ctrl <= axi_pwdata[23:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_RDATA_LINE_CTRL : reg_rdata_line_ctrl <= axi_pwdata[31:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_RESP_DELAY_CTRL : reg_resp_delay_ctrl <= axi_pwdata[31:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_CMD_PEND_NUM : reg_cmd_pend_num <= axi_pwdata[31:0];
+
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_CMD_CTRL : reg_pg_cmd_ctrl <= axi_pwdata[31:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_AXI_ID : reg_pg_axi_id <= axi_pwdata[29:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_ADDR_BASE : reg_pg_addr_base <= axi_pwdata[31:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_ADDR_LOW : reg_pg_addr_low <= axi_pwdata[31:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_DATA_CTRL : reg_pg_data_ctrl <= axi_pwdata[15:0];
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_WSTRB : reg_pg_wstrb_preset <= axi_pwdata[31:0];
+
+// below register are not writable
+// `NV_FPGA_UNIT_MEM_DUT_REG_OUTSTAND_STATUS : reg_outstand_status <0= axi_pwdata[19:0];
+// `NV_FPGA_UNIT_MEM_DUT_REG_TEST_STATUS : reg_test_status <0= axi_pwdata[31:0];
+// `NV_FPGA_UNIT_MEM_DUT_REG_TEST_ERR_LOC : reg_test_err_loc <0= axi_pwdata[23:0];
+// `NV_FPGA_UNIT_MEM_DUT_REG_RESP_CNT : reg_resp_cnt <0= axi_pwdata[23:0];
+// `NV_FPGA_UNIT_MEM_DUT_REG_RRESP_CNT : reg_rresp_cnt <0= axi_pwdata[23:0];
+// `NV_FPGA_UNIT_MEM_DUT_REG_RDATA_CNT : reg_rdata_cnt <0= axi_pwdata[31:0];
+ endcase
+ end
+ end
+end
+
+always @(
+ axi_reg_sel
+ or axi_paddr
+ or reg_test_ctrl_i
+ or reg_cmd_num_total_i
+ or reg_cmd_line_ctrl_i
+ or reg_wdata_line_ctrl_i
+ or reg_wcmd_line_ctrl_i
+ or reg_rdata_line_ctrl_i
+ or reg_resp_delay_ctrl_i
+ or reg_cmd_pend_num_i
+ or reg_pg_cmd_ctrl_i
+ or reg_pg_axi_id_i
+ or reg_pg_addr_base_i
+ or reg_pg_addr_low_i
+ or reg_pg_data_ctrl_i
+ or reg_pg_wstrb_preset_i
+ or reg_outstand_status_i
+ or reg_test_status_i
+ or reg_test_err_loc_i
+ or reg_resp_cnt_i
+ or reg_rresp_cnt_i
+ or reg_rdata_cnt_i
+ or reg_req_cnt_i
+ or reg_req_wr_cnt_i
+ or reg_req_wd_cnt_i
+ or test_timer
+ ) begin
+ if(axi_reg_sel) begin
+ case(axi_paddr[15:0])
+ `NV_FPGA_UNIT_MEM_DUT_REG_TEST_CTRL : axi_reg_prdata = reg_test_ctrl_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_CMD_NUM_TOTAL : axi_reg_prdata = reg_cmd_num_total_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_CMD_LINE_CTRL : axi_reg_prdata = reg_cmd_line_ctrl_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_WDATA_LINE_CTRL : axi_reg_prdata = reg_wdata_line_ctrl_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_WCMD_LINE_CTRL : axi_reg_prdata = reg_wcmd_line_ctrl_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_RDATA_LINE_CTRL : axi_reg_prdata = reg_rdata_line_ctrl_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_RESP_DELAY_CTRL : axi_reg_prdata = reg_resp_delay_ctrl_i ; // spyglass disable W164b
+ `NV_FPGA_UNIT_MEM_DUT_REG_CMD_PEND_NUM : axi_reg_prdata = reg_cmd_pend_num_i ;
+
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_CMD_CTRL : axi_reg_prdata = reg_pg_cmd_ctrl_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_AXI_ID : axi_reg_prdata = reg_pg_axi_id_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_ADDR_BASE : axi_reg_prdata = reg_pg_addr_base_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_ADDR_LOW : axi_reg_prdata = reg_pg_addr_low_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_DATA_CTRL : axi_reg_prdata = reg_pg_data_ctrl_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_PG_WSTRB : axi_reg_prdata = reg_pg_wstrb_preset_i ;
+
+ `NV_FPGA_UNIT_MEM_DUT_REG_OUTSTAND_STATUS : axi_reg_prdata = reg_outstand_status_i ; // spyglass disable W164b
+ `NV_FPGA_UNIT_MEM_DUT_REG_TEST_STATUS : axi_reg_prdata = reg_test_status_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_TEST_ERR_LOC : axi_reg_prdata = reg_test_err_loc_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_RESP_CNT : axi_reg_prdata = reg_resp_cnt_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_RRESP_CNT : axi_reg_prdata = reg_rresp_cnt_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_RDATA_CNT : axi_reg_prdata = reg_rdata_cnt_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_REQ_CNT : axi_reg_prdata = reg_req_cnt_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_REQ_WR_CNT : axi_reg_prdata = reg_req_wr_cnt_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_REQ_WD_CNT : axi_reg_prdata = reg_req_wd_cnt_i ;
+ `NV_FPGA_UNIT_MEM_DUT_REG_TEST_TIMER : axi_reg_prdata = test_timer ;
+ default: axi_reg_prdata = 32'b0;
+ endcase
+ end
+ else
+ axi_reg_prdata = 32'b0;
+end
+
+// TEST_CTRL_REG
+assign axi_rdata_sel = reg_test_ctrl[26]; // rdata golden source select. 0-pg, 1-axi_rdata_ram
+assign axi_rdata_check_en = reg_test_ctrl[25]; // enable rdata checking.
+//assign axi_cmd_pend_num = reg_test_ctrl[24:16]; // set the outstanding requests on AXI bus.
+assign axi_cmd_line_end = reg_test_ctrl[15:4]; // set the last valid axi cmd location in AXI_CMD_RAM
+assign pg_en = reg_test_ctrl[3]; // enable pattern gen function.
+assign repeat_mode = reg_test_ctrl[2]; // enable repeat mode to repeat a paragraph from axi_cmd_line_start to axi_cmd_line_repeat_end in AXI_CMD_RAM.
+assign test_run_i = reg_test_ctrl[1]; // begin to issue axi cmd until axi_req_num_total reached.
+assign test_reset = axi_reg_sel & apb_wr_op & (axi_paddr[15:0] == `NV_FPGA_UNIT_MEM_DUT_REG_TEST_CTRL) & axi_pwdata[0];
+assign reg_test_ctrl_i = {5'b0, reg_test_ctrl[26:25], 9'b0, reg_test_ctrl[15:1], 1'b0};
+
+// CMD_NUM_TOTAL_REG
+assign axi_req_num_total = reg_cmd_num_total[23:0]; // indicate how many axi requests will be issued.
+assign reg_cmd_num_total_i = {8'b0, axi_req_num_total};
+
+// CMD_LINE_CTRL_REG
+assign axi_cmd_line_repeat_end = reg_cmd_line_ctrl[23:12];
+assign axi_cmd_line_start = reg_cmd_line_ctrl[11:0];
+assign reg_cmd_line_ctrl_i = {8'b0, reg_cmd_line_ctrl[23:0]};
+
+// WDATA_LINE_CTRL_REG
+assign axi_wdata_line_repeat_end = reg_wdata_line_ctrl[31:16];
+assign axi_wdata_line_start = reg_wdata_line_ctrl[15:0];
+assign reg_wdata_line_ctrl_i = reg_wdata_line_ctrl;
+
+// WCMD_LINE_CTRL_REG
+assign axi_awcmd_line_repeat_end = reg_wcmd_line_ctrl[23:12]; // spyglass disable W164a
+assign axi_awcmd_line_start = reg_wcmd_line_ctrl[11:0]; // spyglass disable W164a
+assign reg_wcmd_line_ctrl_i = {8'b0, reg_wcmd_line_ctrl[23:0]};
+
+// the ar info ram can be caculated by (axi_cmd_line_start - axi_awcmd_line_start)
+assign axi_arcmd_line_start = axi_cmd_line_start - axi_awcmd_line_start - 1'b1; // spyglass disable W164a
+assign axi_arcmd_line_repeat_end = axi_cmd_line_repeat_end - axi_awcmd_line_repeat_end - 1'b1; // spyglass disable W164a
+
+// RDATA_LINE_NUM_REG
+assign axi_rdata_line_repeat_end = reg_rdata_line_ctrl[31:16];
+assign axi_rdata_line_start = reg_rdata_line_ctrl[15:0];
+assign reg_rdata_line_ctrl_i = reg_rdata_line_ctrl;
+
+// CMD_PEND_NUM_REG, define in axi_resp module
+assign axi_cmd_pend_num_min = reg_cmd_pend_num[15:8];
+assign axi_cmd_pend_num_max = reg_cmd_pend_num[7:0];
+assign reg_cmd_pend_num_i = {16'b0, reg_cmd_pend_num[15:0]};
+
+// below register are defined in axi_req_gen module
+// PG_CMD_CTRL_REG
+// PG_AID_REG
+// PG_ADDR_BASE_REG
+// PG_ADDR_LOW_REG
+// PG_DATA_CTRL_REG
+// PG_WSTRB_REG
+
+// below are status registers
+
+// OUTSTAND_STATUS_REG
+assign reg_outstand_status_i = {14'b0, axi_awcmd_pend_cnt, axi_arcmd_pend_cnt};
+
+// TEST_STATUS_REG, test_error_out is defined in axi_resp module
+assign reg_test_status_i = {test_finish, 16'b0, axi_cmd_line_mismatch, axi_wstrb_line_mismatch, test_error_out[12:0]};
+
+// TEST_ERR_LOC_REG
+assign reg_test_err_loc_i = {8'b0, axi_cmd_error_loc};
+
+// RESP_CNT_REG
+assign reg_resp_cnt_i = {8'b0, axi_resp_cnt_total};
+
+// RRESP_CNT_REG
+assign reg_rresp_cnt_i = {8'b0, axi_rresp_cnt_total};
+
+// RDATA_CNT_REG
+assign reg_rdata_cnt_i = axi_rdata_cnt_total;
+
+// REQ_CNT_REG
+assign reg_req_cnt_i = {8'b0, axi_req_cnt[23:0]};
+
+// REQ_WR_CNT_REG
+assign reg_req_wr_cnt_i = {8'b0, axi_req_wr_cnt[23:0]};
+
+// REQ_WDATA_CNT_REG
+assign reg_req_wd_cnt_i = axi_req_wd_cnt;
+
+endmodule // NV_FPGA_unit_checkbox_mem_dut_axi_256_256
+
+
diff --git a/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_256.v b/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_256.v
new file mode 100644
index 0000000..9bf06bd
--- /dev/null
+++ b/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_256.v
@@ -0,0 +1,594 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: NV_FPGA_unit_checkbox_mem_dut_axi_req_256.v
+
+module NV_FPGA_unit_checkbox_mem_dut_axi_req_256 (
+ axi_clk
+ ,axi_rstn
+ ,axi_arcmd_pend_cnt
+ ,axi_arready
+ ,axi_awcmd_pend_cnt
+ ,axi_awready
+ ,axi_cmd_pend_num_max
+ ,axi_rd_req_wait
+ ,axi_req_cmd
+ ,axi_req_wdata
+ ,axi_req_wstrb
+ ,axi_wready
+ ,status_clear
+ ,test_cmd_issuing
+ ,axi_araddr
+ ,axi_arburst
+ ,axi_arcache
+ ,axi_arid
+ ,axi_arlen
+ ,axi_arlock
+ ,axi_arprot
+ ,axi_arqos
+ ,axi_arregion
+ ,axi_arsize
+ ,axi_aruser
+ ,axi_arvalid
+ ,axi_awaddr
+ ,axi_awburst
+ ,axi_awcache
+ ,axi_awid
+ ,axi_awlen
+ ,axi_awlock
+ ,axi_awprot
+ ,axi_awqos
+ ,axi_awregion
+ ,axi_awsize
+ ,axi_awuser
+ ,axi_awvalid
+ ,axi_req_cnt
+ ,axi_req_rd_cnt
+ ,axi_req_update
+ ,axi_req_wd_cnt
+ ,axi_req_wd_update
+ ,axi_req_wr_cnt
+ ,axi_wdata
+ ,axi_wdata_phase_cnt_reg
+ ,axi_wlast
+ ,axi_wstrb
+ ,axi_wvalid
+ );
+input axi_clk;
+input axi_rstn;
+input [8:0] axi_arcmd_pend_cnt;
+input axi_arready;
+input [8:0] axi_awcmd_pend_cnt;
+input axi_awready;
+input [7:0] axi_cmd_pend_num_max;
+input axi_rd_req_wait;
+input [127:0] axi_req_cmd;
+input [255:0] axi_req_wdata;
+input [31:0] axi_req_wstrb;
+input axi_wready;
+input status_clear;
+input test_cmd_issuing;
+output [39:0] axi_araddr;
+output [1:0] axi_arburst;
+output [3:0] axi_arcache;
+output [13:0] axi_arid;
+output [7:0] axi_arlen;
+output [1:0] axi_arlock;
+output [2:0] axi_arprot;
+output [3:0] axi_arqos;
+output [3:0] axi_arregion;
+output [2:0] axi_arsize;
+output [25:0] axi_aruser;
+output axi_arvalid;
+output [39:0] axi_awaddr;
+output [1:0] axi_awburst;
+output [3:0] axi_awcache;
+output [13:0] axi_awid;
+output [7:0] axi_awlen;
+output [1:0] axi_awlock;
+output [2:0] axi_awprot;
+output [3:0] axi_awqos;
+output [3:0] axi_awregion;
+output [2:0] axi_awsize;
+output [25:0] axi_awuser;
+output axi_awvalid;
+output [23:0] axi_req_cnt;
+output [23:0] axi_req_rd_cnt;
+output axi_req_update;
+output [31:0] axi_req_wd_cnt;
+output axi_req_wd_update;
+output [23:0] axi_req_wr_cnt;
+output [255:0] axi_wdata;
+output [8:0] axi_wdata_phase_cnt_reg;
+output axi_wlast;
+output [31:0] axi_wstrb;
+output axi_wvalid;
+reg axi_arcmd_accept_reg;
+reg axi_arvalid_reg;
+reg axi_awcmd_accept_reg;
+reg axi_awvalid_reg;
+reg [23:0] axi_req_cnt_reg;
+reg [7:0] axi_req_dly1_cnt;
+reg [7:0] axi_req_dly2_cnt;
+reg [23:0] axi_req_rd_cnt_reg;
+reg axi_req_update;
+reg [31:0] axi_req_wd_cnt_reg;
+reg [23:0] axi_req_wr_cnt_reg;
+reg axi_wdata_accept_reg;
+reg [8:0] axi_wdata_phase_cnt_reg;
+reg [3:0] nxt_req_state;
+reg [3:0] req_state;
+wire axi_arcmd_accept;
+wire axi_awcmd_accept;
+wire [39:0] axi_axaddr;
+wire [39:0] axi_axaddr_reg;
+wire [1:0] axi_axburst;
+wire [1:0] axi_axburst_reg;
+wire [3:0] axi_axcache;
+wire [3:0] axi_axcache_reg;
+wire [7:0] axi_axdly1_reg;
+wire [7:0] axi_axdly2_reg;
+wire [13:0] axi_axid;
+wire [13:0] axi_axid_reg;
+wire [7:0] axi_axlen;
+wire [7:0] axi_axlen_reg;
+wire [1:0] axi_axlock;
+wire [1:0] axi_axlock_reg;
+wire [2:0] axi_axprot;
+wire [2:0] axi_axprot_reg;
+wire [3:0] axi_axqos;
+wire [3:0] axi_axqos_reg;
+wire [3:0] axi_axregion;
+wire [3:0] axi_axregion_reg;
+wire axi_axrw;
+wire axi_axrw_reg;
+wire [2:0] axi_axsize;
+wire [2:0] axi_axsize_reg;
+wire [25:0] axi_axuser;
+wire [25:0] axi_axuser_reg;
+wire axi_dual_cmd_mode;
+wire axi_req_dly1_done;
+wire axi_req_dly2_done;
+wire axi_single_rwcmd_accept;
+wire axi_wdata_accept;
+wire [8:0] axi_wdata_phase_cnt;
+
+
+
+// AXI request signals declaration
+
+
+
+// control singals declaration
+
+
+
+// output control singals for other module
+
+
+reg [127:0] axi_req_cmd_reg; // spyglass disable W498
+// latest axi request are present on output of axi_cmd_ram
+// axi_reg_cmd_reg store last axi cmd
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_req_cmd_reg <= {128{1'b0}};
+ end else begin
+ if(axi_req_update) begin
+ axi_req_cmd_reg <= axi_req_cmd;
+ end
+ end
+end
+
+// de-concentrate the axi request information
+assign axi_axregion[3:0] = axi_req_cmd[127:124];
+assign axi_axqos[3:0] = axi_req_cmd[123:120];
+assign axi_axlock[1:0] = axi_req_cmd[119:118];
+assign axi_axprot[2:0] = axi_req_cmd[117:115];
+assign axi_axcache[3:0] = axi_req_cmd[114:111];
+assign axi_axsize[2:0] = axi_req_cmd[110:108];
+assign axi_axburst[1:0] = axi_req_cmd[107:106];
+assign axi_axuser[25:0] = axi_req_cmd[105:80];
+assign axi_axlen[7:0] = axi_req_cmd[79:72];
+assign axi_axaddr[39:0] = axi_req_cmd[71:32];
+//assign axi_axdly2 = axi_req_cmd[27:24];
+//assign axi_axdly1 = axi_req_cmd[19:16];
+assign axi_axrw = axi_req_cmd[15];
+assign axi_dual_cmd_mode = axi_req_cmd[14];
+assign axi_axid[13:0] = axi_req_cmd[13:0];
+
+assign axi_axregion_reg[3:0]= axi_req_cmd_reg[127:124];
+assign axi_axqos_reg[3:0] = axi_req_cmd_reg[123:120];
+assign axi_axlock_reg[1:0] = axi_req_cmd_reg[119:118];
+assign axi_axprot_reg[2:0] = axi_req_cmd_reg[117:115];
+assign axi_axcache_reg[3:0] = axi_req_cmd_reg[114:111];
+assign axi_axsize_reg[2:0] = axi_req_cmd_reg[110:108];
+assign axi_axburst_reg[1:0] = axi_req_cmd_reg[107:106];
+assign axi_axuser_reg[25:0] = axi_req_cmd_reg[105:80];
+assign axi_axlen_reg[7:0] = axi_req_cmd_reg[79:72];
+assign axi_axaddr_reg[39:0] = axi_req_cmd_reg[71:32];
+assign axi_axdly2_reg[7:0] = axi_req_cmd_reg[31:24];
+assign axi_axdly1_reg[7:0] = axi_req_cmd_reg[23:16];
+assign axi_axrw_reg = axi_req_cmd_reg[15];
+//axi_dual_cmd_mode_reg
+assign axi_axid_reg[13:0] = axi_req_cmd_reg[13:0];
+
+// count the totol requests and the total wdata phases.
+// axi_req_cnt indicate which cmd (1..N) is being accepted. N is the total cmd number
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_req_cnt_reg <= {24{1'b0}};
+ axi_req_wd_cnt_reg <= {32{1'b0}};
+ axi_req_rd_cnt_reg <= {24{1'b0}};
+ axi_req_wr_cnt_reg <= {24{1'b0}};
+ end else begin
+ if(status_clear) begin
+ axi_req_cnt_reg <= 0;
+ axi_req_wd_cnt_reg <= 0;
+ axi_req_rd_cnt_reg <= 0;
+ axi_req_wr_cnt_reg <= 0;
+ end
+ else begin
+ axi_req_cnt_reg <= axi_req_cnt;
+ axi_req_wd_cnt_reg <= axi_req_wd_cnt;
+ axi_req_rd_cnt_reg <= axi_req_rd_cnt;
+ axi_req_wr_cnt_reg <= axi_req_wr_cnt;
+ end
+ end
+end
+
+assign axi_req_cnt = axi_req_update ? (axi_req_cnt_reg + 1'b1) : axi_req_cnt_reg;
+assign axi_req_wd_cnt = axi_req_wd_update ? (axi_req_wd_cnt_reg + 1'b1) : axi_req_wd_cnt_reg;
+
+assign axi_req_rd_cnt = (axi_arvalid & axi_arready) ? (axi_req_rd_cnt_reg + 1'b1) : axi_req_rd_cnt_reg;
+assign axi_req_wr_cnt = (axi_wvalid & axi_wready & axi_wlast) ? (axi_req_wr_cnt_reg + 1'b1) : axi_req_wr_cnt_reg;
+
+// single read or write cmd(with only 1 data phase) accepted
+assign axi_single_rwcmd_accept = axi_axrw ? (axi_arvalid & axi_arready) : (axi_awvalid & axi_awready & axi_wvalid & axi_wready & axi_wlast);
+
+// state machine for axi request channel
+// ISSUE:
+// 1) if axi_dual_cmd_mode==1, fetch next cmd and jump to ISSUE_DUAL state
+// 2) else if arcmd or awcmd/wlast accepted
+// a) if more wdata phase required for a write cmd, jump to WDATA state
+// b) else if it's the last cmd, return to IDLE state
+// c) else fetch next cmd and stay ISSUE state
+// ISSUE_DUAL:
+// 1) if both r/w cmd accepted
+// a) if more data phase required, jump to WDATA state
+// b) else if it's the last cmd, jump to IDLE state
+// a) else jump to ISSUE state
+// 2) else stay ISSUE_DUAL state
+// WDATA:
+// 1) if it's the last cmd, jump to IDLE state
+// 2) else if it's the last wdata phase for curr cmd, jump to ISSUE state
+// 3) else stay WDATA state.
+
+
+//## fsm (1) output
+
+//| -one_hot_states
+//| -no_assert_state_x
+//| -no_testpoints
+//| REGISTERS
+//| req_state <= nxt_req_state;
+//| axi_req_update = 1'b0;
+//| RESET
+//| IDLE <- ;
+//| ADVANCE
+//| <- 1;
+//| STATES
+//| IDLE :
+//| ISSUE <- test_cmd_issuing;
+//| ISSUE :
+//| if(axi_dual_cmd_mode | axi_single_rwcmd_accept)
+//| axi_req_update=1;
+//| ISSUE_DUAL <- axi_dual_cmd_mode;
+//| WDATA <- (~axi_axrw & axi_awvalid & axi_awready & (~(axi_wvalid & axi_wready) | (|axi_awlen)));
+//| IDLE <- !test_cmd_issuing;
+//| ISSUE_DUAL :
+//| if(axi_arcmd_accept & axi_awcmd_accept & axi_wdata_accept & (axi_wdata_phase_cnt == axi_awlen+1))
+//| axi_req_update=1;
+//| WDATA <- (axi_arcmd_accept & axi_awcmd_accept & (axi_wdata_phase_cnt < axi_awlen+1));
+//| IDLE <- (axi_arcmd_accept & axi_awcmd_accept & !test_cmd_issuing);
+//| ISSUE <- (axi_arcmd_accept & axi_awcmd_accept);
+//| if(axi_wdata_phase_cnt == (axi_awlen+1))
+//| axi_req_update=1;
+//| IDLE <- !test_cmd_issuing;
+//| ISSUE <- (axi_wvalid & axi_wready & (axi_wdata_phase_cnt == axi_awlen+1));
+//|)
+
+//## fsm (1) defines
+
+`define IDLE 0
+`define ISSUE 1
+`define ISSUE_DUAL 2
+`define WDATA 3
+
+//## fsm (1) com block
+
+always @(
+ req_state
+ or test_cmd_issuing
+ or axi_dual_cmd_mode
+ or axi_single_rwcmd_accept
+ or axi_axrw
+ or axi_awvalid
+ or axi_awready
+ or axi_wvalid
+ or axi_wready
+ or axi_awlen
+ or axi_arcmd_accept
+ or axi_awcmd_accept
+ or axi_wdata_accept
+ or axi_wdata_phase_cnt
+ ) begin
+ nxt_req_state = req_state;
+ axi_req_update = 1'b0;
+ begin
+ casez (1'b1) // spyglass disable W226
+ req_state[`IDLE]: begin // spyglass disable W225 W171
+ if (test_cmd_issuing) begin
+ nxt_req_state = 4'd1 << `ISSUE; // spyglass disable W459
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if ((test_cmd_issuing) === 1'bx) begin
+ nxt_req_state = 'bx;
+ end
+ // VCS coverage on
+ `endif
+ end
+ req_state[`ISSUE]: begin // spyglass disable W225 W171
+ if(axi_dual_cmd_mode | axi_single_rwcmd_accept)
+ axi_req_update=1;
+ if (axi_dual_cmd_mode) begin
+ nxt_req_state = 4'd1 << `ISSUE_DUAL; // spyglass disable W459
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if ((axi_dual_cmd_mode) === 1'bx) begin
+ nxt_req_state = 'bx;
+ end
+ // VCS coverage on
+ `endif
+ else if ((~axi_axrw & axi_awvalid & axi_awready & (~(axi_wvalid & axi_wready) | (|axi_awlen)))) begin
+ nxt_req_state = 4'd1 << `WDATA; // spyglass disable W459
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if (((~axi_axrw & axi_awvalid & axi_awready & (~(axi_wvalid & axi_wready) | (|axi_awlen)))) === 1'bx) begin
+ nxt_req_state = 'bx;
+ end
+ // VCS coverage on
+ `endif
+ else if (!test_cmd_issuing) begin
+ nxt_req_state = 4'd1 << `IDLE; // spyglass disable W459
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if ((!test_cmd_issuing) === 1'bx) begin
+ nxt_req_state = 'bx;
+ end
+ // VCS coverage on
+ `endif
+ end
+ req_state[`ISSUE_DUAL]: begin // spyglass disable W225 W171
+ if(axi_arcmd_accept & axi_awcmd_accept & axi_wdata_accept & (axi_wdata_phase_cnt == axi_awlen+1))
+ axi_req_update=1;
+ if ((axi_arcmd_accept & axi_awcmd_accept & (axi_wdata_phase_cnt < axi_awlen+1))) begin
+ nxt_req_state = 4'd1 << `WDATA; // spyglass disable W459
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if (((axi_arcmd_accept & axi_awcmd_accept & (axi_wdata_phase_cnt < axi_awlen+1))) === 1'bx) begin
+ nxt_req_state = 'bx;
+ end
+ // VCS coverage on
+ `endif
+ else if ((axi_arcmd_accept & axi_awcmd_accept & !test_cmd_issuing)) begin
+ nxt_req_state = 4'd1 << `IDLE; // spyglass disable W459
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if (((axi_arcmd_accept & axi_awcmd_accept & !test_cmd_issuing)) === 1'bx) begin
+ nxt_req_state = 'bx;
+ end
+ // VCS coverage on
+ `endif
+ else if ((axi_arcmd_accept & axi_awcmd_accept)) begin
+ nxt_req_state = 4'd1 << `ISSUE; // spyglass disable W459
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if (((axi_arcmd_accept & axi_awcmd_accept)) === 1'bx) begin
+ nxt_req_state = 'bx;
+ end
+ // VCS coverage on
+ `endif
+ end
+ req_state[`WDATA]: begin // spyglass disable W225 W171
+ if(axi_wdata_phase_cnt == (axi_awlen+1))
+ axi_req_update=1;
+ if (!test_cmd_issuing) begin
+ nxt_req_state = 4'd1 << `IDLE; // spyglass disable W459
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if ((!test_cmd_issuing) === 1'bx) begin
+ nxt_req_state = 'bx;
+ end
+ // VCS coverage on
+ `endif
+ else if ((axi_wvalid & axi_wready & (axi_wdata_phase_cnt == axi_awlen+1))) begin
+ nxt_req_state = 4'd1 << `ISSUE; // spyglass disable W459
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if (((axi_wvalid & axi_wready & (axi_wdata_phase_cnt == axi_awlen+1))) === 1'bx) begin
+ nxt_req_state = 'bx;
+ end
+ // VCS coverage on
+ `endif
+ end
+ // VCS coverage off
+ default: begin
+ nxt_req_state = 4'd1 << `IDLE; // spyglass disable W459
+ `ifndef SYNTHESIS
+ nxt_req_state = {4{1'bx}};
+ `endif
+ end
+ // VCS coverage on
+ endcase
+ end
+end
+
+//## fsm (1) seq block
+
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ req_state <= 4'd1 << 0; // spyglass disable W459
+ end else begin
+ req_state <= nxt_req_state;
+ end
+end
+
+
+assign axi_req_wd_update = axi_wvalid & axi_wready;
+
+// judge when to exit from ISSUE_DUAL state.
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_arcmd_accept_reg <= 1'b0;
+ axi_awcmd_accept_reg <= 1'b0;
+ axi_wdata_accept_reg <= 1'b0;
+ end else begin
+ if(req_state[`ISSUE_DUAL]) begin
+ axi_arcmd_accept_reg <= axi_arcmd_accept;
+ axi_awcmd_accept_reg <= axi_awcmd_accept;
+ axi_wdata_accept_reg <= axi_wdata_accept;
+ end
+ else begin
+ axi_arcmd_accept_reg <= 0;
+ axi_awcmd_accept_reg <= 0;
+ axi_wdata_accept_reg <= 0;
+ end
+ end
+end
+
+assign axi_arcmd_accept = req_state[`ISSUE_DUAL] ? (axi_arcmd_accept_reg | axi_arready) : 0;
+assign axi_awcmd_accept = req_state[`ISSUE_DUAL] ? (axi_awcmd_accept_reg | axi_awready) : 0;
+assign axi_wdata_accept = req_state[`ISSUE_DUAL] ? (axi_wdata_accept_reg | (axi_wvalid & axi_wready)) : 0;
+
+// caculate how many wdata phase finished in one single cmd
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_wdata_phase_cnt_reg <= {9{1'b0}};
+ end else begin
+ if(status_clear)
+ axi_wdata_phase_cnt_reg <= 9'b0;
+ else
+ axi_wdata_phase_cnt_reg <= axi_wdata_phase_cnt;
+ end
+end
+
+assign axi_wdata_phase_cnt = (axi_wvalid & axi_wready) ? (axi_awvalid & axi_awready) ? 1 : (axi_wdata_phase_cnt_reg + 1'b1)
+ : (axi_awvalid & axi_awready) ? 0 : axi_wdata_phase_cnt_reg;
+
+// assignment of axi cmd channel
+assign axi_arid = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axid_reg : axi_axrw ? axi_axid : 0;
+assign axi_araddr = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axaddr_reg : axi_axrw ? axi_axaddr : 0;
+assign axi_arlen = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axlen_reg : axi_axrw ? axi_axlen : 0;
+assign axi_arburst = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axburst_reg : axi_axrw ? axi_axburst : 0;
+assign axi_arsize = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axsize_reg : axi_axrw ? axi_axsize : 0;
+assign axi_aruser = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axuser_reg : axi_axrw ? axi_axuser : 0;
+assign axi_arcache = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axcache_reg : axi_axrw ? axi_axcache : 0;
+assign axi_arprot = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axprot_reg : axi_axrw ? axi_axprot : 0;
+assign axi_arlock = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axlock_reg : axi_axrw ? axi_axlock : 0;
+assign axi_arqos = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axqos_reg : axi_axrw ? axi_axqos : 0;
+assign axi_arregion = (req_state[`ISSUE_DUAL] & axi_axrw_reg) ? axi_axregion_reg : axi_axrw ? axi_axregion : 0;
+
+assign axi_awid = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axid_reg : ~axi_axrw ? axi_axid : 0;
+assign axi_awaddr = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axaddr_reg : ~axi_axrw ? axi_axaddr : 0;
+assign axi_awlen = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axlen_reg : ~axi_axrw ? axi_axlen : 0;
+assign axi_awburst = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axburst_reg : ~axi_axrw ? axi_axburst : 0;
+assign axi_awsize = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axsize_reg : ~axi_axrw ? axi_axsize : 0;
+assign axi_awuser = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axuser_reg : ~axi_axrw ? axi_axuser : 0;
+assign axi_awcache = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axcache_reg : ~axi_axrw ? axi_axcache : 0;
+assign axi_awprot = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axprot_reg : ~axi_axrw ? axi_axprot : 0;
+assign axi_awlock = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axlock_reg : ~axi_axrw ? axi_axlock : 0;
+assign axi_awqos = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axqos_reg : ~axi_axrw ? axi_axqos : 0;
+assign axi_awregion = (req_state[`ISSUE_DUAL] & ~axi_axrw_reg) ? axi_axregion_reg : ~axi_axrw ? axi_axregion : 0;
+
+// generate axi_arvalid signal
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_arvalid_reg <= 1'b0;
+ end else begin
+ if(axi_arvalid & axi_arready) //de-assert it when received arready in ISSUE_DUAL state
+ axi_arvalid_reg <= 0;
+ else if(req_state[`ISSUE] & axi_dual_cmd_mode) // assert it before enter ISSUE_DUAL state
+ axi_arvalid_reg <= 1;
+ else
+ axi_arvalid_reg <= axi_arvalid;
+ end
+end
+
+assign axi_arvalid = ((req_state[`ISSUE] & axi_axrw & !axi_dual_cmd_mode & axi_req_dly1_done & !axi_rd_req_wait) | (req_state[`ISSUE_DUAL] & axi_arvalid_reg)) & (axi_arcmd_pend_cnt = axi_axdly1_reg);
+assign axi_req_dly2_done = (axi_req_dly2_cnt >= axi_axdly2_reg);
+
+// registers assignment
+
+endmodule // NV_FPGA_unit_checkbox_mem_dut_axi_req_256
+
+
diff --git a/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256.v b/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256.v
new file mode 100644
index 0000000..8e180cd
--- /dev/null
+++ b/cl_memdut/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256.v
@@ -0,0 +1,327 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256.v
+
+module NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256 (
+ pg_clk
+ ,pg_rstn
+ ,arcmd_info_update
+ ,awcmd_info_update
+ ,axi_rdata_cnt_total
+ ,axi_req_update
+ ,axi_req_wd_cnt
+ ,axi_wdata_phase_cnt_reg
+ ,reg_pg_addr_base
+ ,reg_pg_addr_low
+ ,reg_pg_axi_id
+ ,reg_pg_cmd_ctrl
+ ,reg_pg_data_ctrl
+ ,reg_pg_wstrb_preset
+ ,status_clear
+ ,pg_axi_arcmd_info
+ ,pg_axi_awcmd_info
+ ,pg_axi_cmd
+ ,pg_axi_rdata
+ ,pg_axi_rstrb
+ ,pg_axi_wdata
+ ,pg_axi_wstrb
+ ,pg_wr_and_rd_back_mode
+ ,reg_pg_addr_base_i
+ ,reg_pg_addr_low_i
+ ,reg_pg_axi_id_i
+ ,reg_pg_cmd_ctrl_i
+ ,reg_pg_data_ctrl_i
+ ,reg_pg_wstrb_preset_i
+ );
+input pg_clk;
+input pg_rstn;
+input arcmd_info_update;
+input awcmd_info_update;
+input [31:0] axi_rdata_cnt_total;
+input axi_req_update;
+input [15:0] axi_req_wd_cnt;
+input [8:0] axi_wdata_phase_cnt_reg;
+input [31:0] reg_pg_addr_base;
+input [31:0] reg_pg_addr_low;
+input [29:0] reg_pg_axi_id;
+input [31:0] reg_pg_cmd_ctrl;
+input [15:0] reg_pg_data_ctrl;
+input [31:0] reg_pg_wstrb_preset;
+input status_clear;
+output [26:0] pg_axi_arcmd_info;
+output [26:0] pg_axi_awcmd_info;
+output [127:0] pg_axi_cmd;
+output [255:0] pg_axi_rdata;
+output [63:0] pg_axi_rstrb;
+output [255:0] pg_axi_wdata;
+output [31:0] pg_axi_wstrb;
+output pg_wr_and_rd_back_mode;
+output [31:0] reg_pg_addr_base_i;
+output [31:0] reg_pg_addr_low_i;
+output [31:0] reg_pg_axi_id_i;
+output [31:0] reg_pg_cmd_ctrl_i;
+output [31:0] reg_pg_data_ctrl_i;
+output [31:0] reg_pg_wstrb_preset_i;
+reg [7:0] arcmd_info_arid;
+reg [7:0] awcmd_info_awid;
+reg [39:0] axi_araddr;
+reg [7:0] axi_arid;
+reg [39:0] axi_awaddr;
+reg [7:0] axi_awid;
+reg [0:0] axi_axrw;
+reg [255:0] pg_axi_rdata;
+reg [255:0] pg_axi_wdata;
+wire [39:0] axi_axaddr;
+wire [1:0] axi_axburst;
+wire [3:0] axi_axcache;
+wire [7:0] axi_axdly1;
+wire [7:0] axi_axdly2;
+wire [13:0] axi_axid;
+wire [7:0] axi_axlen;
+wire [1:0] axi_axlock;
+wire [2:0] axi_axprot;
+wire [3:0] axi_axqos;
+wire [2:0] axi_axsize;
+wire [25:0] axi_axuser;
+wire [0:0] axi_dual_cmd_mode;
+wire [39:0] pg_addr_base;
+wire [15:0] pg_araddr_preset;
+wire [13:0] pg_arid_preset;
+wire [15:0] pg_awaddr_preset;
+wire [13:0] pg_awid_preset;
+wire [7:0] pg_axdly1;
+wire [7:0] pg_axdly2;
+wire [5:0] pg_axi_wstrb_shift;
+wire [63:0] pg_axi_wstrb_tmp;
+wire [2:0] pg_axprot;
+wire [1:0] pg_cmd_aburst;
+wire [2:0] pg_cmd_asize;
+wire [11:0] pg_cmd_data_length;
+wire [2:0] pg_cmd_mode;
+wire [2:0] pg_data_mode;
+wire pg_dual_cmd_mode;
+wire pg_fix_addr;
+wire pg_fix_id;
+wire pg_wstrb_change;
+wire [31:0] pg_wstrb_preset;
+
+
+
+/////////////////////////////////////////////////////////////////////////
+// generate aw/ar cmd output for request issue
+/////////////////////////////////////////////////////////////////////////
+
+
+
+assign pg_axi_cmd = {
+ 4'b0,
+ axi_axqos,
+ axi_axlock,
+ axi_axprot,
+ axi_axcache,
+ axi_axsize,
+ axi_axburst,
+ axi_axuser,
+ axi_axlen,
+ axi_axaddr,
+ axi_axdly2,
+ axi_axdly1,
+ axi_axrw,
+ axi_dual_cmd_mode,
+ axi_axid};
+
+assign axi_dual_cmd_mode = pg_dual_cmd_mode;
+assign axi_axdly1 = pg_axdly1;
+assign axi_axdly2 = pg_axdly2;
+
+assign axi_axcache = 4'b0;
+assign axi_axprot = pg_axprot;
+assign axi_axlock = 2'b0;
+assign axi_axqos = 4'b0;
+
+// burst/size/length are set in registers
+assign axi_axburst = pg_cmd_aburst;
+assign axi_axsize = pg_cmd_asize;
+assign axi_axlen = (pg_cmd_data_length >> pg_cmd_asize) - 1'b1; // spyglass disable W164a
+
+assign axi_axuser = 26'b0;
+
+// read/write assign
+always @(posedge pg_clk or negedge pg_rstn) begin
+ if (!pg_rstn) begin
+ axi_axrw <= 1'b0;
+ end else begin
+ case(pg_cmd_mode)
+ 3'b000: axi_axrw <= 1'b0;
+ 3'b001: axi_axrw <= 1'b1;
+ 3'b010: axi_axrw <= axi_req_update ? ~axi_axrw : axi_axrw;
+ 3'b011: axi_axrw <= 1'b1;
+ default: axi_axrw <= 1'b0;
+ endcase
+ end
+end
+
+assign pg_wr_and_rd_back_mode = (pg_cmd_mode == 3'b010);
+
+// arid/awid and addr generator
+always @(posedge pg_clk or negedge pg_rstn) begin
+ if (!pg_rstn) begin
+ axi_arid <= {8{1'b0}};
+ axi_awid <= {8{1'b0}};
+ axi_araddr <= {40{1'b0}};
+ axi_awaddr <= {40{1'b0}};
+ end else begin
+ if(status_clear) begin
+ axi_arid <= pg_arid_preset[7:0];
+ axi_awid <= pg_awid_preset[7:0];
+ axi_araddr <= pg_addr_base + pg_araddr_preset; // spyglass disable W484
+ axi_awaddr <= pg_addr_base + pg_awaddr_preset; // spyglass disable W484
+ end
+ else if(axi_req_update) begin
+ if(axi_axrw) begin
+ axi_arid <= pg_fix_id ? axi_arid : (axi_arid + 1'b1);
+ axi_araddr <= pg_fix_addr ? axi_araddr: (axi_araddr + pg_cmd_data_length); // spyglass disable W484
+ end
+ else begin
+ axi_awid <= pg_fix_id ? axi_awid : (axi_awid + 1'b1);
+ axi_awaddr <= pg_fix_addr ? axi_awaddr: (axi_awaddr + pg_cmd_data_length); // spyglass disable W484
+ end
+ end
+ end
+end
+
+assign axi_axid = axi_axrw ? {pg_arid_preset[13:8], axi_arid} : {pg_awid_preset[13:8], axi_awid};
+assign axi_axaddr = axi_axrw ? axi_araddr : axi_awaddr;
+
+// wdata assignment.
+always @(
+ pg_data_mode
+ or axi_req_wd_cnt
+ ) begin
+ //if(pg_en) begin
+ case(pg_data_mode)
+ 3'b000: pg_axi_wdata = 0;
+ 3'b001: pg_axi_wdata = {8{32'hFFFF_FFFF}};
+ 3'b010: pg_axi_wdata = {16{axi_req_wd_cnt[15:0]}}; // spyglass disable W164a
+ 3'b011: pg_axi_wdata = {16{~axi_req_wd_cnt[15:0]}}; // spyglass disable W164a
+ 3'b100: pg_axi_wdata = {8{32'h55AA_AA55}};
+ 3'b101: pg_axi_wdata = {8{32'h33CC_CC33}};
+ default: pg_axi_wdata = 0;
+ endcase
+ //end
+end
+
+assign pg_axi_wstrb_tmp = ~pg_wstrb_change ? {2{pg_wstrb_preset}}
+ : (axi_req_wd_cnt[1:0] == 2'b11) ? {2{32'hFFFFFFFF}}
+ : (axi_req_wd_cnt[1:0] == 2'b10) ? {2{32'h00FFFFFF}}
+ : (axi_req_wd_cnt[1:0] == 2'b01) ? {2{32'h0000FFFF}} : {2{32'h000000FF}};
+assign pg_axi_wstrb_shift = (axi_wdata_phase_cnt_reg<= axi_rready_delay_cycles)) & (axi_arcmd_pend_cnt >= axi_cmd_pend_num_min); // spyglass disable W362
+
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_rready_delay_cnt <= {8{1'b0}};
+ end else begin
+ if(axi_rvalid) begin
+ if(axi_rready)
+ axi_rready_delay_cnt <= 0;
+ else
+ axi_rready_delay_cnt <= axi_rready_delay_cnt + 1'b1;
+ end
+ end
+end
+
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_rready_delay_cycles <= {8{1'b0}};
+ end else begin
+ if(axi_rready_delay_en) begin
+ if(~axi_rready_delay_random)
+ axi_rready_delay_cycles <= axi_rready_delay_cycles_preset;
+ else if(axi_rvalid & axi_rready)
+ axi_rready_delay_cycles <= (axi_rready_delay_cycles + 1) % 4;
+ end
+ else
+ axi_rready_delay_cycles <= 0;
+ end
+end
+
+// axi read response error case detect
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_rresp_error_id <= 1'b0;
+ axi_rresp_error_phase_more <= 1'b0;
+ axi_rresp_error_phase_less <= 1'b0;
+ axi_rresp_error_code <= 1'b0;
+ axi_rresp_error_resp <= {2{1'b0}};
+ axi_rdata_match_reg <= 1'b0;
+ end else begin
+ if(status_clear) begin
+ axi_rresp_error_id <= 0;
+ axi_rresp_error_phase_more <= 0;
+ axi_rresp_error_phase_less <= 0;
+ axi_rresp_error_code <= 0;
+ axi_rresp_error_resp <= 0;
+ axi_rdata_match_reg <= 1;
+ end
+ if(axi_rvalid & axi_rready) begin
+ axi_rresp_error_id <= axi_rresp_error_id | (axi_rid != axi_arid_gold);
+ axi_rresp_error_phase_more <= axi_rresp_error_phase_more | (axi_rlast & (axi_rdata_cnt > axi_arlen_gold)); // spyglass disable W362
+ axi_rresp_error_phase_less <= axi_rresp_error_phase_less | (axi_rlast & (axi_rdata_cnt < axi_arlen_gold)); // spyglass disable W362
+ axi_rresp_error_code <= axi_rresp_error_code | (|axi_rresp);
+ axi_rresp_error_resp <= (axi_rresp != 2'b00) ? axi_rresp : axi_rresp_error_resp;
+ axi_rdata_match_reg <= axi_rdata_match_reg & axi_rdata_match;
+ end
+ end
+end
+
+///////////////////////////////////////////////////////////////////
+// write response
+///////////////////////////////////////////////////////////////////
+
+assign awcmd_info_update = axi_bvalid & axi_bready;
+assign axi_awid_gold = axi_awcmd_info[13:0];
+
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_bresp_cnt_total <= {24{1'b0}};
+ end else begin
+ if(status_clear)
+ axi_bresp_cnt_total <= 0;
+ else if(axi_bvalid & axi_bready) begin
+ axi_bresp_cnt_total <= axi_bresp_cnt_total + 1'b1;
+ end
+ end
+end
+
+// axi read resp valid-ready delay cycles control
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_awcmd_pend_cnt <= {9{1'b0}};
+ end else begin
+ axi_awcmd_pend_cnt <= axi_req_wr_cnt - axi_bresp_cnt_total; // spyglass disable W164a
+ end
+end
+assign axi_bready = (~axi_bready_delay_en | (axi_bready_delay_cnt >= axi_bready_delay_cycles)) & (axi_awcmd_pend_cnt >= axi_cmd_pend_num_min); // spyglass disable W362
+
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_bready_delay_cnt <= {8{1'b0}};
+ end else begin
+ if(axi_bvalid) begin
+ if(axi_bready)
+ axi_bready_delay_cnt <= 0;
+ else
+ axi_bready_delay_cnt <= axi_bready_delay_cnt + 1'b1;
+ end
+ end
+end
+
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_bready_delay_cycles <= {8{1'b0}};
+ end else begin
+ if(axi_bready_delay_en) begin
+ if(axi_bready_delay_random)
+ axi_bready_delay_cycles <= axi_bready_delay_cycles_preset;
+ else if(axi_bvalid & axi_bready)
+ axi_bready_delay_cycles <= (axi_bready_delay_cycles + 1) % 4;
+ end
+ else
+ axi_bready_delay_cycles <= 0;
+ end
+end
+
+// axi read response error case detect
+always @(posedge axi_clk or negedge axi_rstn) begin
+ if (!axi_rstn) begin
+ axi_bresp_error_id <= 1'b0;
+ axi_bresp_error_code <= 1'b0;
+ axi_bresp_error_resp <= {2{1'b0}};
+ end else begin
+ if(status_clear) begin
+ axi_bresp_error_id <= 0;
+ axi_bresp_error_code <= 0;
+ axi_bresp_error_resp <= 0;
+ end
+ if(axi_bvalid & axi_bready) begin
+ axi_bresp_error_id <= axi_bresp_error_id | (axi_bid != axi_awid_gold);
+ axi_bresp_error_code <= axi_bresp_error_code | (axi_bresp != 2'b00);
+ axi_bresp_error_resp <= (axi_bresp != 2'b00) ? axi_bresp : axi_bresp_error_resp;
+ end
+ end
+end
+
+////////////////////////////////////////////////////////////////
+// axi read data check
+////////////////////////////////////////////////////////////////
+
+assign axi_rdata_update = axi_rvalid & axi_rready;
+
+assign rdata_match_byte[0] = !axi_rstrb_gold[0] | (axi_rdata[7:0] == axi_rdata_gold[7:0]);
+assign rdata_match_byte[1] = !axi_rstrb_gold[1] | (axi_rdata[15:8] == axi_rdata_gold[15:8]);
+assign rdata_match_byte[2] = !axi_rstrb_gold[2] | (axi_rdata[23:16] == axi_rdata_gold[23:16]);
+assign rdata_match_byte[3] = !axi_rstrb_gold[3] | (axi_rdata[31:24] == axi_rdata_gold[31:24]);
+assign rdata_match_byte[4] = !axi_rstrb_gold[4] | (axi_rdata[39:32] == axi_rdata_gold[39:32]);
+assign rdata_match_byte[5] = !axi_rstrb_gold[5] | (axi_rdata[47:40] == axi_rdata_gold[47:40]);
+assign rdata_match_byte[6] = !axi_rstrb_gold[6] | (axi_rdata[55:48] == axi_rdata_gold[55:48]);
+assign rdata_match_byte[7] = !axi_rstrb_gold[7] | (axi_rdata[63:56] == axi_rdata_gold[63:56]);
+assign rdata_match_byte[8] = !axi_rstrb_gold[8] | (axi_rdata[71:64] == axi_rdata_gold[71:64]);
+assign rdata_match_byte[9] = !axi_rstrb_gold[9] | (axi_rdata[79:72] == axi_rdata_gold[79:72]);
+assign rdata_match_byte[10] = !axi_rstrb_gold[10] | (axi_rdata[87:80] == axi_rdata_gold[87:80]);
+assign rdata_match_byte[11] = !axi_rstrb_gold[11] | (axi_rdata[95:88] == axi_rdata_gold[95:88]);
+assign rdata_match_byte[12] = !axi_rstrb_gold[12] | (axi_rdata[103:96] == axi_rdata_gold[103:96]);
+assign rdata_match_byte[13] = !axi_rstrb_gold[13] | (axi_rdata[111:104] == axi_rdata_gold[111:104]);
+assign rdata_match_byte[14] = !axi_rstrb_gold[14] | (axi_rdata[119:112] == axi_rdata_gold[119:112]);
+assign rdata_match_byte[15] = !axi_rstrb_gold[15] | (axi_rdata[127:120] == axi_rdata_gold[127:120]);
+assign rdata_match_byte[16] = !axi_rstrb_gold[16] | (axi_rdata[135:128] == axi_rdata_gold[135:128]);
+assign rdata_match_byte[17] = !axi_rstrb_gold[17] | (axi_rdata[143:136] == axi_rdata_gold[143:136]);
+assign rdata_match_byte[18] = !axi_rstrb_gold[18] | (axi_rdata[151:144] == axi_rdata_gold[151:144]);
+assign rdata_match_byte[19] = !axi_rstrb_gold[19] | (axi_rdata[159:152] == axi_rdata_gold[159:152]);
+assign rdata_match_byte[20] = !axi_rstrb_gold[20] | (axi_rdata[167:160] == axi_rdata_gold[167:160]);
+assign rdata_match_byte[21] = !axi_rstrb_gold[21] | (axi_rdata[175:168] == axi_rdata_gold[175:168]);
+assign rdata_match_byte[22] = !axi_rstrb_gold[22] | (axi_rdata[183:176] == axi_rdata_gold[183:176]);
+assign rdata_match_byte[23] = !axi_rstrb_gold[23] | (axi_rdata[191:184] == axi_rdata_gold[191:184]);
+assign rdata_match_byte[24] = !axi_rstrb_gold[24] | (axi_rdata[199:192] == axi_rdata_gold[199:192]);
+assign rdata_match_byte[25] = !axi_rstrb_gold[25] | (axi_rdata[207:200] == axi_rdata_gold[207:200]);
+assign rdata_match_byte[26] = !axi_rstrb_gold[26] | (axi_rdata[215:208] == axi_rdata_gold[215:208]);
+assign rdata_match_byte[27] = !axi_rstrb_gold[27] | (axi_rdata[223:216] == axi_rdata_gold[223:216]);
+assign rdata_match_byte[28] = !axi_rstrb_gold[28] | (axi_rdata[231:224] == axi_rdata_gold[231:224]);
+assign rdata_match_byte[29] = !axi_rstrb_gold[29] | (axi_rdata[239:232] == axi_rdata_gold[239:232]);
+assign rdata_match_byte[30] = !axi_rstrb_gold[30] | (axi_rdata[247:240] == axi_rdata_gold[247:240]);
+assign rdata_match_byte[31] = !axi_rstrb_gold[31] | (axi_rdata[255:248] == axi_rdata_gold[255:248]);
+assign rdata_match_byte[32] = 1'b1;
+assign rdata_match_byte[33] = 1'b1;
+assign rdata_match_byte[34] = 1'b1;
+assign rdata_match_byte[35] = 1'b1;
+assign rdata_match_byte[36] = 1'b1;
+assign rdata_match_byte[37] = 1'b1;
+assign rdata_match_byte[38] = 1'b1;
+assign rdata_match_byte[39] = 1'b1;
+assign rdata_match_byte[40] = 1'b1;
+assign rdata_match_byte[41] = 1'b1;
+assign rdata_match_byte[42] = 1'b1;
+assign rdata_match_byte[43] = 1'b1;
+assign rdata_match_byte[44] = 1'b1;
+assign rdata_match_byte[45] = 1'b1;
+assign rdata_match_byte[46] = 1'b1;
+assign rdata_match_byte[47] = 1'b1;
+assign rdata_match_byte[48] = 1'b1;
+assign rdata_match_byte[49] = 1'b1;
+assign rdata_match_byte[50] = 1'b1;
+assign rdata_match_byte[51] = 1'b1;
+assign rdata_match_byte[52] = 1'b1;
+assign rdata_match_byte[53] = 1'b1;
+assign rdata_match_byte[54] = 1'b1;
+assign rdata_match_byte[55] = 1'b1;
+assign rdata_match_byte[56] = 1'b1;
+assign rdata_match_byte[57] = 1'b1;
+assign rdata_match_byte[58] = 1'b1;
+assign rdata_match_byte[59] = 1'b1;
+assign rdata_match_byte[60] = 1'b1;
+assign rdata_match_byte[61] = 1'b1;
+assign rdata_match_byte[62] = 1'b1;
+assign rdata_match_byte[63] = 1'b1;
+assign rdata_match_byte_shift = rdata_match_byte >> ((axi_rdata_cnt<
+
+// Registers in CL_MEMDUT
+typedef enum {WONLY_64_BYTES, RONLY_64_BYTES, WR_VERIFY_64_BYTES, RONLY_VERIFY_64_BYTES} ATG_CMD_MODE;
+typedef enum {BURST_FIXED, BURST_INCR, BURST_WRAP} ATG_CMD_ABURST;
+typedef enum {SIZE_1, SIZE_2, SIZE_4, SIZE_8, SIZE_16, SIZE_32, SIZE_64, SIZE_128} ATG_CMD_ASIZE;
+typedef enum {ALL_0, ALL_1, NUM_16_BIT, NUM_16_BIT_REVERSE, FIX_55AAAA55, FIX_33CCCC33} ATG_DATA_MODE;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ ATG_CMD_MODE cmd_mode : 3;
+ ATG_CMD_ABURST cmd_aburst : 2;
+ ATG_CMD_ASIZE cmd_asize : 3;
+ uint32_t fix_id : 1;
+ uint32_t fix_addr : 1;
+ uint32_t dual_cmd_mode : 1;
+ uint32_t axprot : 3;
+ uint32_t rsv : 2;
+ uint32_t axidly1 : 8;
+ uint32_t axidly2 : 8;
+ }__attribute__((packed)) field;
+} atg_cmd_ctrl_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t arid_preset : 14;
+ uint32_t rsv0 : 2;
+ uint32_t awid_preset : 14;
+ uint32_t rsv1 : 2;
+ }__attribute__((packed)) field;
+} atg_axi_id_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t addr_base : 32;
+ }__attribute__((packed)) field;
+} atg_addr_base_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t araddr_preset : 16;
+ uint32_t awaddr_preset : 16;
+ }__attribute__((packed)) field;
+} atg_addr_low_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t data_length : 12;
+ ATG_DATA_MODE data_mode : 3;
+ uint32_t wstrb_change : 1;
+ uint32_t rsv : 16;
+ }__attribute__((packed)) field;
+} atg_data_ctrl_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t wstrb_preset : 32;
+ }__attribute__((packed)) field;
+} atg_wstrb_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t reset : 1;
+ uint32_t run : 1;
+ uint32_t repeat : 1;
+ uint32_t atg_en : 1;
+ uint32_t cmd_line_end : 12;
+ uint32_t cmd_pend_num : 9;
+ uint32_t rdata_check_en : 1;
+ uint32_t rdata_sel : 1;
+ uint32_t rsv : 5;
+ }__attribute__((packed)) field;
+} test_ctrl_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t axi_req_num_total : 32;
+ }__attribute__((packed)) field;
+} num_req_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t arcmd_pend_cnt : 10;
+ uint32_t awcmd_pend_cnt : 10;
+ uint32_t rsv : 12;
+ }__attribute__((packed)) field;
+} outstand_status_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t wdata_corrupt : 1;
+ uint32_t bresp : 2;
+ uint32_t bresp_code : 1;
+ uint32_t bresp_id : 1;
+ uint32_t rdata_corrupt : 1;
+ uint32_t rresp : 2;
+ uint32_t rresp_code : 1;
+ uint32_t rresp_phase_less : 1;
+ uint32_t rresp_phase_more : 1;
+ uint32_t rresp_id : 1;
+ uint32_t protocol_error : 1;
+ uint32_t wstrb_line_mismatch : 1;
+ uint32_t cmd_line_mismatch : 1;
+ uint32_t rsv : 16;
+ uint32_t test_finish : 1;
+ }__attribute__((packed)) field;
+} test_status_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t axi_cmd_error_loc : 24;
+ uint32_t rsv : 8;
+ }__attribute__((packed)) field;
+} test_err_loc_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t axi_resp_cnt_total : 24;
+ uint32_t rsv : 8;
+ }__attribute__((packed)) field;
+} resp_cnt_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t axi_rresp_cnt_total : 24;
+ uint32_t rsv : 8;
+ }__attribute__((packed)) field;
+} rresp_cnt_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t axi_rdata_cnt_total : 32;
+ }__attribute__((packed)) field;
+} rdata_cnt_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t axi_req_cnt : 24;
+ uint32_t rsv : 8;
+ }__attribute__((packed)) field;
+} req_cnt_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t axi_req_wr_cnt : 24;
+ uint32_t rsv : 8;
+ }__attribute__((packed)) field;
+} req_wr_cnt_reg;
+
+typedef union {
+ uint32_t value;
+ uint8_t bytes[4];
+ struct {
+ uint32_t axi_req_wd_cnt : 32;
+ }__attribute__((packed)) field;
+} req_wd_cnt_reg;
+
+typedef struct
+{
+ atg_cmd_ctrl_reg atg_cmd_ctrl;
+ atg_axi_id_reg atg_axi_id;
+ atg_addr_base_reg atg_addr_base;
+ atg_addr_low_reg atg_addr_low;
+ atg_data_ctrl_reg atg_data_ctrl;
+ atg_wstrb_reg atg_wstrb;
+} memdut_atg_ctrl;
+
+typedef struct
+{
+ resp_cnt_reg resp_cnt;
+ rresp_cnt_reg rresp_cnt;
+ rdata_cnt_reg rdata_cnt;
+ req_cnt_reg req_cnt;
+ req_wr_cnt_reg req_wr_cnt;
+ req_wd_cnt_reg req_wd_cnt;
+} memdut_test_cnt;
+
+// Util functions
+void apb_write_test_reg(uint32_t reg_n, uint32_t data);
+void apb_read_test_reg(uint32_t reg_n, uint32_t *data);
+void apb_write_cmd_ram(uint32_t inst, uint32_t offset, const uint32_t* wdata);
+void apb_read_cmd_ram(uint32_t inst, uint32_t offset, uint32_t* rdata);
+void apb_write_we_ram(uint32_t inst, uint32_t offset, uint32_t wdata);
+void apb_read_we_ram(uint32_t inst, uint32_t offset, uint32_t* rdata);
+void apb_write_wdata_ram(uint32_t inst, uint32_t offset, const uint32_t* wdata);
+void apb_read_wdata_ram(uint32_t inst, uint32_t offset, uint32_t* rdata);
+void apb_write_rdata_ram(uint32_t inst, uint32_t offset, const uint32_t* wdata);
+void apb_read_rdata_ram(uint32_t inst, uint32_t offset, uint32_t* rdata);
+void memdut_set_atg_ctrl(const memdut_atg_ctrl *atg_ctrl, uint32_t inst);
+void memdut_set_num_req(const num_req_reg num_req, uint32_t inst);
+void memdut_set_test_ctrl(const test_ctrl_reg ctrl, uint32_t inst);
+void memdut_get_test_ctrl(test_ctrl_reg *ctrl, uint32_t inst);
+void memdut_get_test_cnt(memdut_test_cnt *cnt, uint32_t inst);
+void memdut_get_test_status(test_status_reg *status, uint32_t inst);
+
+#endif
diff --git a/cl_memdut/software/src/Makefile b/cl_memdut/software/src/Makefile
new file mode 100644
index 0000000..7d33427
--- /dev/null
+++ b/cl_memdut/software/src/Makefile
@@ -0,0 +1,66 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+#VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include
+VPATH = src:../../../common/software/src
+
+INCLUDES = -I../../../common/software/include -I../include
+ifndef VP_TEST
+INCLUDES += -I$(SDK_DIR)/userspace/include
+endif
+
+ifdef VP_TEST
+CC = aarch64-linux-gnu-gcc
+else
+CC = gcc
+endif
+
+CFLAGS = -DCONFIG_LOGLEVEL=4 -g -Wall $(INCLUDES)
+ifdef VP_TEST
+CFLAGS += -DVP_TEST
+else
+CFLAGS += -L$(SDK_DIR)/userspace/lib/so
+endif
+
+ifndef VP_TEST
+LDLIBS = -lfpga_mgmt -lrt -lpthread
+endif
+
+SRC = test_memdut.c cl_common_utils.c test_utils.c
+OBJ = $(SRC:.c=.o)
+ifdef VP_TEST
+BIN = aarch64_test_memdut
+else
+BIN = test_memdut
+endif
+
+ifdef VP_TEST
+all: $(BIN)
+else
+all: $(BIN) check_env
+endif
+
+$(BIN): $(OBJ)
+ $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LDLIBS)
+
+clean:
+ rm -f *.o $(BIN)
+
+ifndef VP_TEST
+check_env:
+ifndef SDK_DIR
+ $(error SDK_DIR is undefined. Try "source sdk_setup.sh" to set the software environment)
+endif
+endif
diff --git a/cl_memdut/software/src/test_memdut.c b/cl_memdut/software/src/test_memdut.c
new file mode 100644
index 0000000..68879f3
--- /dev/null
+++ b/cl_memdut/software/src/test_memdut.c
@@ -0,0 +1,381 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cl_common_utils.h"
+#include "test_utils.h"
+#include "memdut_regs.h"
+
+#define CFG_INT_STATUS_ADDR UINT64_C(0x0)
+#define DDR_C_BASE_ADDR UINT64_C(0x00000000)
+#ifdef SV_TEST
+#define NUM_AXI_PORTS 2
+#define NUM_LOOP 1
+#else
+#define NUM_AXI_PORTS 1
+#define NUM_LOOP 10
+#endif
+
+typedef enum { INT_INIT, INT_ASSERT, INT_DEASSERT } IRQ_STATE_t;
+
+static IRQ_STATE_t irq_state[NUM_AXI_PORTS];
+
+/*
+ * pci_vendor_id and pci_device_id values below are Amazon's and avaliable to use for a given FPGA slot.
+ * Users may replace these with their own if allocated to them by PCI SIG
+ */
+static uint16_t pci_vendor_id = 0x1D0F; /* Amazon PCI Vendor ID */
+static uint16_t pci_device_id = 0xF001; /* PCI Device ID preassigned by Amazon for F1 applications */
+static uint32_t int_mask = 0x1;
+
+int apb_test(void);
+int ram_test(void);
+int ddr_c_test(void);
+int axi_test(void);
+
+#ifdef SV_TEST
+void test_main(uint32_t *exit_code)
+#else
+int main(int argc, char **argv)
+#endif
+{
+ int rc = 0;
+
+ if (cl_common_init(pci_vendor_id, pci_device_id, int_mask)) {
+ log_printf("Errors on initialization!\n");
+ assert(0);
+ }
+
+ /* APB test */
+ if (apb_test()) {
+ rc = 1;
+ }
+
+ /* RAM test */
+ if (ram_test()) {
+ rc = 1;
+ }
+
+ /* DDR_C test */
+ if (ddr_c_test()) {
+ rc = 1;
+ }
+
+ /* AXI test */
+ if (axi_test()) {
+ rc = 1;
+ }
+
+ /* cleanup */
+ if (cl_common_cleanup()) {
+ rc = 1;
+ }
+
+ if (!rc) {
+ log_printf("Test PASSED\n");
+ } else {
+ log_printf("Test FAILED\n");
+ }
+
+#ifdef SV_TEST
+ *exit_code = rc;
+#else
+ return rc;
+#endif
+}
+
+void cl_int_handler(uint32_t int_num)
+{
+
+ log_printf("CL_INT_HANDLER: enter cl_int_handler, int_num=%d\n", int_num);
+
+ assert(int_num < NUM_AXI_PORTS);
+
+ uint32_t status;
+ static uint32_t last_status = 0;
+
+ cfg_read(CFG_INT_STATUS_ADDR, &status);
+
+ log_printf("CL_INT_HANDLER: int_status=0x%x, last_status=0x%x\n", status, last_status);
+
+ assert(status != last_status);
+
+ if (status & (0x1< 0) {
+ if (cl_msi_is_active(i)) {
+ cl_int_handler(i);
+ } else {
+ printf("Error! interrupt %d is not active\n", i);
+ assert(0);
+ }
+ }
+#endif // #ifdef SV_TEST
+ if (irq_state[i] == INT_DEASSERT || --poll_limit == 0) {
+ break;
+ }
+#endif // #ifdef VP_TEST
+ }
+
+ if (poll_limit == 0) {
+ log_printf("ERROR! Polling timeout\n");
+ return 1;
+ }
+
+ memdut_get_test_status(&test_status[i], i);
+ if (!(test_status[i].field.test_finish == 1)) {
+ log_printf("ERROR! test_finish != 1\n");
+ return 1;
+ }
+
+ memdut_get_test_cnt(&test_cnt[i], i);
+ log_printf("AXI_TEST: Total responses received: %d\n", test_cnt[i].resp_cnt.value);
+ log_printf("AXI_TEST: Total read responses received: %d\n", test_cnt[i].rresp_cnt.value);
+ log_printf("AXI_TEST: Total read data phases received: %d\n", test_cnt[i].rdata_cnt.value);
+ log_printf("AXI_TEST: Total requests issued: %d\n", test_cnt[i].req_cnt.value);
+ log_printf("AXI_TEST: Total write requests issued: %d\n", test_cnt[i].req_wr_cnt.value);
+ log_printf("AXI_TEST: Total write data phases issued: %d\n", test_cnt[i].req_wd_cnt.value);
+ if (!(test_status[i].value & 0xefff)) {
+ log_printf("AXI_TEST: test passed for axi port %d\n", i);
+ } else {
+ log_printf("AXI_TEST: test failed for axi port %d\n with error status=0x%x", i, test_status[i].value);
+ rc = 1;
+ }
+
+ memdut_get_test_ctrl(&test_ctrl[i], i);
+ log_printf("AXI_TEST: Clear the run bit: 0x%08x\n", test_ctrl[i].value);
+ test_ctrl[i].value = 0;
+ memdut_set_test_ctrl(test_ctrl[i], i);
+ memdut_get_test_status(&test_status[i], i);
+ log_printf("AXI_TEST: Check MEMDUT_N_TEST_STATUS: %d\n", test_status[i].value);
+ }
+ }
+
+ return rc;
+}
diff --git a/cl_memdut/software/src/test_null.c b/cl_memdut/software/src/test_null.c
new file mode 100644
index 0000000..4b11367
--- /dev/null
+++ b/cl_memdut/software/src/test_null.c
@@ -0,0 +1,34 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include
+#include
+#include
+
+// Vivado does not support svGetScopeFromName
+#ifdef INCLUDE_DPI_CALLS
+#ifndef VIVADO_SIM
+#include "svdpi.h"
+#endif
+#endif
+
+#include "sh_dpi_tasks.h"
+
+void test_main(uint32_t *exit_code) {
+
+ // NULL Test
+
+ *exit_code = 0;
+}
diff --git a/cl_memdut/software/src/test_utils.c b/cl_memdut/software/src/test_utils.c
new file mode 100644
index 0000000..553e989
--- /dev/null
+++ b/cl_memdut/software/src/test_utils.c
@@ -0,0 +1,122 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: test_utils.c
+
+#include "test_utils.h"
+#include "cl_common_utils.h"
+#include "memdut_regs.h"
+
+// Util functions
+void apb_write_test_reg(uint32_t reg_n, uint32_t data)
+{
+ apb_write(MEMDUT_APB_TEST_REG(reg_n), data);
+}
+
+void apb_read_test_reg(uint32_t reg_n, uint32_t *data)
+{
+ apb_read(MEMDUT_APB_TEST_REG(reg_n), data);
+}
+
+void apb_write_cmd_ram(uint32_t inst, uint32_t offset, const uint32_t* wdata)
+{
+ int i;
+ for (i=0; i<4; i++) {
+ apb_write(MEMDUT_N_CMD_RAM_BASE(inst)+(offset<<4)+(i<<2), wdata[i]);
+ }
+}
+
+void apb_read_cmd_ram(uint32_t inst, uint32_t offset, uint32_t* rdata)
+{
+ int i;
+ for (i=0; i<4; i++) {
+ apb_read(MEMDUT_N_CMD_RAM_BASE(inst)+(offset<<4)+(i<<2), &rdata[i]);
+ }
+}
+
+void apb_write_we_ram(uint32_t inst, uint32_t offset, uint32_t wdata)
+{
+ apb_write(MEMDUT_N_WE_RAM_BASE(inst)+(offset<<2), wdata);
+}
+
+void apb_read_we_ram(uint32_t inst, uint32_t offset, uint32_t* rdata)
+{
+ apb_read(MEMDUT_N_WE_RAM_BASE(inst)+(offset<<2), rdata);
+}
+
+void apb_write_wdata_ram(uint32_t inst, uint32_t offset, const uint32_t* wdata)
+{
+ int i;
+ for (i=0; i<8; i++) {
+ apb_write(MEMDUT_N_WDATA_RAM_BASE(inst)+(offset<<5)+(i<<2), wdata[i]);
+ }
+}
+
+void apb_read_wdata_ram(uint32_t inst, uint32_t offset, uint32_t* rdata)
+{
+ int i;
+ for (i=0; i<8; i++) {
+ apb_read(MEMDUT_N_WDATA_RAM_BASE(inst)+(offset<<5)+(i<<2), &rdata[i]);
+ }
+}
+
+void apb_write_rdata_ram(uint32_t inst, uint32_t offset, const uint32_t* wdata)
+{
+ int i;
+ for (i=0; i<8; i++) {
+ apb_write(MEMDUT_N_RDATA_RAM_BASE(inst)+(offset<<5)+(i<<2), wdata[i]);
+ }
+}
+
+void apb_read_rdata_ram(uint32_t inst, uint32_t offset, uint32_t* rdata)
+{
+ int i;
+ for (i=0; i<8; i++) {
+ apb_read(MEMDUT_N_RDATA_RAM_BASE(inst)+(offset<<5)+(i<<2), &rdata[i]);
+ }
+}
+
+void memdut_set_atg_ctrl(const memdut_atg_ctrl *atg_ctrl, uint32_t inst)
+{
+ apb_write(MEMDUT_N_ATG_CMD_CTRL(inst), atg_ctrl->atg_cmd_ctrl.value);
+ apb_write(MEMDUT_N_ATG_AXI_ID(inst), atg_ctrl->atg_axi_id.value);
+ apb_write(MEMDUT_N_ATG_ADDR_BASE(inst), atg_ctrl->atg_addr_base.value);
+ apb_write(MEMDUT_N_ATG_ADDR_LOW(inst), atg_ctrl->atg_addr_low.value);
+ apb_write(MEMDUT_N_ATG_DATA_CTRL(inst), atg_ctrl->atg_data_ctrl.value);
+ apb_write(MEMDUT_N_ATG_WSTRB(inst), atg_ctrl->atg_wstrb.value);
+}
+
+void memdut_set_num_req(const num_req_reg num_req, uint32_t inst)
+{
+ apb_write(MEMDUT_N_CMD_NUM_TOTAL(inst), num_req.value);
+}
+
+void memdut_set_test_ctrl(const test_ctrl_reg ctrl, uint32_t inst)
+{
+ apb_write(MEMDUT_N_TEST_CTRL(inst), ctrl.value);
+}
+
+void memdut_get_test_ctrl(test_ctrl_reg *ctrl, uint32_t inst)
+{
+ apb_read(MEMDUT_N_TEST_CTRL(inst), &(ctrl->value));
+}
+
+void memdut_get_test_cnt(memdut_test_cnt *cnt, uint32_t inst)
+{
+ apb_read(MEMDUT_N_RESP_CNT(inst), &(cnt->resp_cnt.value));
+ apb_read(MEMDUT_N_RRESP_CNT(inst), &(cnt->rresp_cnt.value));
+ apb_read(MEMDUT_N_RDATA_CNT(inst), &(cnt->rdata_cnt.value));
+ apb_read(MEMDUT_N_REQ_CNT(inst), &(cnt->req_cnt.value));
+ apb_read(MEMDUT_N_REQ_WR_CNT(inst), &(cnt->req_wr_cnt.value));
+ apb_read(MEMDUT_N_REQ_WD_CNT(inst), &(cnt->req_wd_cnt.value));
+}
+
+void memdut_get_test_status(test_status_reg *status, uint32_t inst)
+{
+ apb_read(MEMDUT_N_TEST_STATUS(inst), &(status->value));
+}
diff --git a/cl_memdut/verif/README.md b/cl_memdut/verif/README.md
new file mode 100644
index 0000000..d614749
--- /dev/null
+++ b/cl_memdut/verif/README.md
@@ -0,0 +1,14 @@
+# CL_MEMDUT Simulation
+
+The cl_memdut includes a basic test that exercises the BAR1, DDR_C, and interrupt.
+
+The test can be run from the [verif/scripts] (scripts) directory with one of three different simulators:
+
+```
+ $ make C_TEST=test_memdut
+ $ make C_TEST=test_memdut VCS=1
+ $ make C_TEST=test_memdut QUESTA=1
+```
+
+Note that the appropriate simulators must be installed.
+
diff --git a/cl_memdut/verif/scripts/Makefile b/cl_memdut/verif/scripts/Makefile
new file mode 100644
index 0000000..a51a004
--- /dev/null
+++ b/cl_memdut/verif/scripts/Makefile
@@ -0,0 +1,52 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+
+export TEST ?= test_null
+export C_TEST ?= test_null
+
+export CL_ROOT = $(PWD)/../..
+
+export CL_COMMON_ROOT = $(PWD)/../../../common
+
+export C_INC_DIR = $(CL_ROOT)/software/include
+export C_SRC_DIR = $(CL_ROOT)/software/src
+
+export TEST_NAME = $(CL_ROOT)/verif/tests/$(TEST).sv
+export C_TEST_NAME = $(C_SRC_DIR)/$(C_TEST).c $(C_SRC_DIR)/test_utils.c $(CL_COMMON_ROOT)/software/src/cl_common_utils.c $(CL_COMMON_ROOT)/software/src/sh_dpi_tasks.c
+
+export SIM_ROOT = $(CL_ROOT)/verif/sim
+
+ifeq ($(C_TEST),test_null)
+ export SIM_DIR = $(SIM_ROOT)/$(TEST)
+else
+ export SIM_DIR = $(SIM_ROOT)/$(C_TEST)
+endif
+
+export SCRIPTS_DIR = $(PWD)
+export XILINX_IP = $(HDK_SHELL_DESIGN_DIR)/ip
+export SH_LIB_DIR = $(HDK_SHELL_DESIGN_DIR)/lib
+export SH_INF_DIR = $(HDK_SHELL_DESIGN_DIR)/interfaces
+
+SV_TEST_LIST =
+C_TEST_LIST = test_memdut.c
+
+all: make_sim_dir compile run
+
+include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc
+
diff --git a/cl_memdut/verif/scripts/Makefile.vcs b/cl_memdut/verif/scripts/Makefile.vcs
new file mode 100644
index 0000000..2659ec5
--- /dev/null
+++ b/cl_memdut/verif/scripts/Makefile.vcs
@@ -0,0 +1,40 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+
+##################################################################
+## Makefile For VCS compiles and simulations
+## Step to run :
+## 1. make create_libs VCS=1 -> To generate xilinx compile
+## libraries. This is a one time step
+## 2. make all VCS=1 -> Runs the test
+##################################################################
+
+compile: $(COMPLIB_DIR)
+ mkdir -p $(SIM_DIR)
+ cd ${SIM_DIR} && ln -s -f ../vcs_complib/synopsys_sim.setup
+ cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) +lint=TFIPC-L
+ cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -DSV_TEST" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log
+
+run:
+ cd $(SIM_DIR) && ./simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd
+
+$(COMPLIB_DIR):
+ cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl
+ cd $(SIM_ROOT)/.. && vivado -mode batch -source create_libs.tcl
+ cd $(SIM_ROOT)/.. && rm -rf create_libs.tcl
diff --git a/cl_memdut/verif/scripts/top.vcs.f b/cl_memdut/verif/scripts/top.vcs.f
new file mode 100644
index 0000000..f33fa93
--- /dev/null
+++ b/cl_memdut/verif/scripts/top.vcs.f
@@ -0,0 +1,92 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
++define+VCS_SIM
+
++libext+.v
++libext+.sv
++libext+.svh
+
+-y ${CL_ROOT}/design
+-y ${SH_LIB_DIR}
+-y ${SH_INF_DIR}
+-y ${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim
+
++incdir+${CL_ROOT}/design
++incdir+${CL_ROOT}/verif/sv
++incdir+${CL_COMMON_ROOT}/verif/include
++incdir+${SH_LIB_DIR}
++incdir+${SH_INF_DIR}
++incdir+${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim
+
+${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_xbar_0/sim/cl_axi_interconnect_xbar_0.v
+${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_s00_regslice_0/sim/cl_axi_interconnect_s00_regslice_0.v
+${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/sim/cl_axi_interconnect_s01_regslice_0.v
+${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/sim/cl_axi_interconnect_m00_regslice_0.v
+${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/sim/cl_axi_interconnect_m01_regslice_0.v
+${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/sim/cl_axi_interconnect_m02_regslice_0.v
+${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_m03_regslice_0/sim/cl_axi_interconnect_m03_regslice_0.v
+${SH_LIB_DIR}/../ip/cl_axi_interconnect/hdl/cl_axi_interconnect.v
+${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
+${SH_LIB_DIR}/../ip/dest_register_slice/sim/dest_register_slice.v
+${SH_LIB_DIR}/../ip/src_register_slice/sim/src_register_slice.v
+${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v
+${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v
+
++define+DISABLE_VJTAG_DEBUG
+${CL_ROOT}/design/axil_slave.sv
+${CL_ROOT}/design/cl_memdut_defines.vh
+${CL_ROOT}/design/cl_memdut_pkg.sv
+${CL_ROOT}/design/cl_dma_pcis_slv.sv
+${CL_ROOT}/design/cl_ila.sv
+${CL_ROOT}/design/cl_vio.sv
+${CL_ROOT}/design/cl_memdut.sv
+${CL_ROOT}/design/cl_memdut_wrap.sv
+
+${CL_COMMON_ROOT}/design/xilinx_ip/axi_interconnect_nvdla_256b/axi_interconnect_nvdla_256b_sim_netlist.v
+${CL_COMMON_ROOT}/design/xilinx_ip/axi_apb_bridge_0/axi_apb_bridge_0_sim_netlist.v
+${CL_COMMON_ROOT}/design/transactors/irq/cl_irq_up.v
+${CL_COMMON_ROOT}/design/transactors/irq/cl_irq_up_bit.v
+${CL_COMMON_ROOT}/design/transactors/cfg/cl_cfgreg.sv
+
+-y ${CL_COMMON_ROOT}/design/vlibs
++incdir+${CL_COMMON_ROOT}/design/transactors/irq
+
++define+NO_PLI_OR_EMU
++define+VLIB_BYPASS_POWER_CG
++define+VERILINT
++define+PRAND_OFF
++define+SYNC_PL_NO_RANDOMIZATION
++define+NO_PERFMON_HISTOGRAM
+
+${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut.v
+${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_apb_slave.v
+${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_256_256.v
+${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_256.v
+${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256.v
+${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_resp_256.v
+${CL_ROOT}/design/simple_dut/nv_ram_rws_256x128.v
+${CL_ROOT}/design/simple_dut/nv_ram_rws_256x27.v
+${CL_ROOT}/design/simple_dut/nv_ram_rws_512x256.v
+${CL_ROOT}/design/simple_dut/nv_ram_rws_512x32.v
++define+NO_INIT_MEM_RANDOM_TASK
++define+NO_INIT_MEM_VAL_TASKS
+
+-f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f
+
+${TEST_NAME}
diff --git a/cl_memdut/verif/scripts/waves.tcl b/cl_memdut/verif/scripts/waves.tcl
new file mode 100644
index 0000000..4b14d0d
--- /dev/null
+++ b/cl_memdut/verif/scripts/waves.tcl
@@ -0,0 +1,27 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 200 us
+quit
diff --git a/cl_memdut/verif/tests/test_null.sv b/cl_memdut/verif/tests/test_null.sv
new file mode 100644
index 0000000..7b22606
--- /dev/null
+++ b/cl_memdut/verif/tests/test_null.sv
@@ -0,0 +1,37 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+module test_null();
+
+ initial begin
+ int exit_code;
+
+ tb.power_up();
+
+// tb.nsec_delay(500);
+// tb.poke_stat(.addr(8'h0c), .ddr_idx(0), .data(32'h0000_0000));
+// tb.poke_stat(.addr(8'h0c), .ddr_idx(1), .data(32'h0000_0000));
+// tb.poke_stat(.addr(8'h0c), .ddr_idx(2), .data(32'h0000_0000));
+//
+ tb.test_main(exit_code);
+
+ #50ns;
+
+ tb.power_down();
+
+ $finish;
+ end
+
+endmodule // test_null
diff --git a/cl_nvdla/build/README.md b/cl_nvdla/build/README.md
new file mode 100644
index 0000000..4a542c6
--- /dev/null
+++ b/cl_nvdla/build/README.md
@@ -0,0 +1,181 @@
+# How to build and submit your Custom Logic (CL) to AWS
+
+# Table of Contents
+
+1. [Overview of AFI Build process](#buildoverview)
+2. [Build procedure step by step](#stepbystep)
+3. [Build strategies and parallel builds](#strategies)
+4. [About Encryption during build process](#buildencryption)
+5. [Advanced Notes](#buildadvanced_notes)
+6. [Build Frequently Asked Questions](#buildfaq)
+
+
+
+## Overview
+
+Once the developer has a functional design, the next steps are to: synthesize the design into basic FPGA cells, perform place-and-route, and check that the design meets the timing/frequency constraints. This could be an iterative process. Upon success, the developer will need to pass the output of the flow to AWS for final AFI creation.
+
+The developer needs to transfer to AWS a tar file that includes the encrypted placed-and-routed design checkpoint (referred to as DCP throughout this document) and [manifest](./../../../../docs/AFI_Manifest.md). The DCP includes the complete developer design that meets timing/frequency constraints, placement boundaries within the allocated CL area on the FPGA, and the functional requirements laid out in the [Shell Interface Specification](./../../../../docs/AWS_Shell_Interface_Specification.md#overview). The [manifest.txt](./../../../../docs/AFI_Manifest.md) should include key parameters needed for registering and loading the AFI, such as target frequency.
+
+To assist in this process, AWS provides a reference DCP that includes the shell (SH) logic with a black-boxed CL under: `$HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp`
+
+AWS also provides an out-of-the-box generic script called `aws_build_dcp_from_cl.sh` that is used to test compile a few examples, such as the `cl_hello_world` design, as if they were developer code. These reference examples can serve as starting points for new designs. The output of the AWS-provided scripts will create a tar file, with both the encrypted placed-and-routed DCP and the corresponding `manifest.txt`, which AWS will use to generate the final bitstream.
+
+AWS provides multiple options to generate a DCP that meets placement and timing constraints. The `aws_build_dcp_from_cl.sh` provides multiple choices for implementation strategies, invoked by the `-strategy` option. For more details refer to [Build Strategies](#strategies) below or call `aws_build_dcp_from_cl.sh -help` for the list of supported capabilities.
+
+Advanced developers can use different scripts, tools, and techniques (e.g., regioning), with the condition that they submit both the `manifest.txt` and "encrypted placed-and-routed design checkpoint (DCP)" in a single tar file that passes final checks.
+
+
+## Build Procedure
+
+The following describes the step-by-step procedure to build developer CLs. Some of these steps can be modified or adjusted based on developer experience and design needs.
+
+A developer can execute `$HDK_SHELL_DIR/build/scripts/aws_build_dcp_from_cl.sh` to check the environment, setup the build directory, invoke Xilinx Vivado to create the encrypted placed-and-routed DCP (which include AWS Shell + Developer CL), create the [`manifest.txt`](./../../../../docs/AFI_Manifest.md) that AWS will ingest through the CreateFpgaImage EC2 API. Executing this script also entails encryption of developer-specified RTL files. Further details on invoking the script from Vivado are provided below.
+
+### 1) Pre-requisite: Environment Variables and Tools
+
+ 1. The environment variable `HDK_SHELL_DIR` should have been set. This is usually done by executing `source hdk_setup.sh` from the HDK root directory
+ 2. The environment variable `CL_DIR` should have been set pointing to the root directory where the CL exists. The CL root directory should have the `/build` and `/design` subdirectories. One way to make sure to have the right directory is to execute `source $(HDK_DIR)/cl/developer_designs/prepare_new_cl.sh`
+ 3. Developer have Xilinx Vivado tools installed, with the supported version by the HDK, and with proper license. If the developer is using AWS supplied [FPGA Development AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) from AWS marketplace, it includes the README.md how to setup up the tools and license.
+
+### 2) Encrypt Source Files
+
+CL Encryption is required and AFI creation will fail if your CL source files are not encrypted. As a pre-cursor to the build process, modify the `$CL_DIR/build/scripts/encrypt.tcl` script to include all the CL source files, so the script can encrypt and copy them to the `$CL_DIR/build/src_post_encryption` directory.
+
+### 3) Prepare for the CL Build
+
+Modify the `$CL_DIR/build/scripts/create_dcp_from_cl.tcl` script to include:
+ 1. The list of CL encrypted files in `$CL_DIR/build/src_post_encryption`.
+ 2. The list of CL specific timing and placement constraints in `$CL_DIR/build/constraints`.
+ 3. The specific constraints and design file for IP any included in your CL (e.g., DDR4).
+
+### 4) Build
+
+Run the build script, aws_build_dcp_from_cl.sh, from the `$CL_DIR/build/scripts` directory.
+
+The build script performs:
+ - Synthesis of CL.
+ - Implementation of CL with AWS Shell.
+ - Generation of Design Checkpoint (DCP) for AWS ingestion with the associated logs.
+ - Generation of the corresponding manifest.txt.
+
+
+#### Build Strategies
+In order to help developers close timing goals and successfully build their designs efficiently, the build script provides the means to synthesize with different strategies. The different strategies alter the directives used by the synthesis tool. For example, some directives might specify additional optimizations to close timing, while others may specify less effort to minimize synthesis time for designs that can more easily close timing and area goals. Since every design is different, some strategies may provide better results than another build strategies. If a developer has trouble successfully building their design with one strategy it is encouraged that they try a different strategy, or run a few strategies in parallel using the FPGA Developer AMI. The strategies are described in more detail below.
+
+Build script usage:
+
+ $ ./aws_build_dcp_from_cl.sh [ [-script ] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-uram_option 2 | 3 | 4] [-foreground] [-notify] | [-h] | [-H] | [-help] ]
+Options:
+
+* -script \
+ * Use the specified vivado script. The default script create_dcp_from_cl.tcl will be used if a script is not specified.
+
+* -h, -H, -help
+ * Print a usage message.
+
+* -strategy \
+ * Use the specified strategy to alter the directives used during synthesis. The DEFAULT strategy will be used if a strategy is not specified.
+
+* -clock_recipe_a \
+ * Use the Clock Group A clock frequencies defined for the specified Clock Group A recipe. This is an optional argument and the default value will be A0. Refer to the [Clock Group Recipes Table](./../../../../docs/clock_recipes.csv).
+
+* -clock_recipe_b \
+ * Use the Clock Group B clock frequencies defined for the specified Clock Group B recipe. This is an optional argument and the default value will be B0. Refer to the [Clock Group Recipes Table](./../../../../docs/clock_recipes.csv).
+
+* -clock_recipe_c \
+ * Use the Clock Group C clock frequencies defined for the specified Clock Group C recipe. This is an optional argument and the default value will be C0. Refer to the [Clock Group Recipes Table](./../../../../docs/clock_recipes.csv).
+
+* -uram_option \<2 | 3 | 4>
+ * Use the specified URAM option to define the percentage of URAM sites used for the design. A value of 2 indicates 50%, a value of 3 indicates 75%, and a value of 4 indicates 100%. This is an optional argument and the default value will be 2.
+
+* -foreground
+ * Run the build in the foreground such that all output will go to the terminal and the build may be terminated if the terminal is closed. This option is useful if you want to wait for the build to complete. This option is safe if the terminal is running on the AWS instance, for example on a GUI desktop on the instance.
+
+* -notify
+ * Send e-mail to notify user once the build is complete. Requires setup described in `$HDK_DIR/cl/examples/README.md`.
+
+Strategy descriptions:
+
+* BASIC
+ * This is the basic flow in Vivado and contains the mandatory steps to be able to build a design. It is designed to provide a good balance between runtime and Quality of Results (QOR).
+
+* EXPLORE
+ * This is a high-effort flow which is designed to give improved QOR results at the expense of runtime.
+
+* TIMING
+ * This flow is designed for more aggressive timing optimization at the expense of runtime and congestion.
+
+* CONGESTION
+ * This flow is designed to insert more aggressive whitespace to alleviate routing congestion.
+
+* DEFAULT
+ * This is an additional high-effort flow that results in improved QOR results for the example design at the expense of runtime.
+
+In addition, in order to aid developers with build verification, there is a final step in the build script that emulates the process that AWS uses to generate bitstreams from a developer DCP.
+
+The outputs of the build script are:
+ - `$CL_DIR/build/checkpoints/*`: Various checkpoints generated during the build process.
+ - `$CL_DIR/build/to_aws/SH_CL_routed.dcp`: Encrypted placed-and-routed design checkpoint for AWS ingestion.
+ - `$CL_DIR/build/reports/*`: Various build reports (generally, check_timing/report_timing).
+ - `$CL_DIR/build/src_post_encryption/*`: Encrypted developer source.
+ - `$CL_DIR/build/constraints/*`: Implementation constraints.
+
+A developer may need to iterate multiple times through this process until arriving upon an error-free run.
+
+### 5) Submit the final tar file to AWS to register the AFI
+
+To submit the DCP, create an S3 bucket for submitting the design and upload the tarball file into that bucket.
+You need to prepare the following information:
+
+1. Name of the logic design *(Optional)*.
+2. Generic description of the logic design *(Optional)*.
+3. PCI IDs: Device, Vendor, Subsystem, SubsystemVendor.
+4. Location of the tarball file object in S3.
+5. Location of an S3 directory where AWS would write back logs of the AFI creation.
+6. Version of the AWS Shell.
+
+**NOTE**: *The PCI IDs for the example CLs should be found in the README files in the respective CL example directory.
+If you are building a custom CL, then you need to incorporate these values in your design as shown in the [AWS Shell Interface Specifications](./../../../../docs/AWS_Shell_Interface_Specification.md#pcie-ids).*
+
+[Refer to step 3 for instructions on how to submit the Design Checkpoint to AWS](./../../../../cl/examples/README.md)
+
+
+## Build Strategies and Parallel Builds
+
+Developers may face challenges fitting the CL design into the FPGA due to routing congestion, placement congestion, or not being able to meet timing. These are typical challenges in FPGA and chip development.
+
+AWS script `./aws_build_dcp_from_cl.sh` offers an optional flag to set one of a few useful implementation strategies, which would automatically different directives to various build steps. You can learn about the various strategy options by running `$ ./aws_build_dcp_from_cl.sh -help`.
+
+If you are running on one of the EC2 compute instances with 31GiB DRAM or more, you could run multiple builds concurrently for the same CL, but calling the build script multiple times with different `-strategy` options, taking advantage of the large vCPU count typically available on EC2 instances, as each build would typically consume between 1 to 8 vCPUs throughout the entire run of a given build.
+
+
+## About Encryption
+
+Developer RTL is encrypted using IEEE 1735 V2 encryption. This level of encryption protects both the raw source files and the implemented design.
+
+
+## Advanced Notes
+
+* The included implementation flow is a baseline flow. It is possible to add advanced commands/constraints (e.g, rejoining) to the flow.
+* Developers are free to modify the flow, but the final output must be a tar file with manifest.txt and the combined (AWS Shell + CL), encrypted, placed-and-routed design checkpoint,.
+
+
+# Frequently Asked Questions
+
+
+**Q: What are the different files that a developer needs to provide to AWS?**
+The developer should submit a tar file that contains the placed-and-routed DCP along with the required manifest.txt file.
+
+**Q: What should I do my design is not meeting timing?**
+The developer should evaluate the timing path to identify a solution that may include design changes or additional constraints. Additionally, the developer can try using one of the different build strategies that may help resolve the timing violations.
+
+**Q: My design was meeting timing, but even without changes, subsequent builds are not meeting timing?**
+This may happen due to various reasons. The developer should investigate the timing violation regardless of the lack of design changes. Additionally, the developer can try using one of the different build strategies that may help resolve the timing violations.
+
+**Q: "pr_verify" is complaining that the design checkpoints are incompatible. What should I do?**
+The developer can double-check that the AWS Shell DCP, SH_CL_BB_routed.dcp, was downloaded properly from the S3 bucket to the `hdk/common/shell_stable/build/checkpoints/from_aws` directory during the [hdk_setup.sh](../../../../../hdk_setup.sh) step and that there aren't errors in the build log.
+
+**Q: What version of Vivado do I need to use?**
+The valid version of Vivado is verified during the [hdk_setup.sh](../../../../../hdk_setup.sh) step.
+
diff --git a/cl_nvdla/build/constraints/cl_pnr_user.xdc b/cl_nvdla/build/constraints/cl_pnr_user.xdc
new file mode 100644
index 0000000..12a9812
--- /dev/null
+++ b/cl_nvdla/build/constraints/cl_pnr_user.xdc
@@ -0,0 +1,26 @@
+# This contains the CL specific constraints for Top level PNR
+
+create_pblock pblock_CL_top
+resize_pblock [get_pblocks pblock_CL_top] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14}
+set_property PARENT pblock_CL [get_pblocks pblock_CL_top]
+
+create_pblock pblock_CL_mid
+add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ CL/CL_DMA_PCIS_SLV/AXI_CROSSBAR}]
+add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ CL/CL_PCIM_MSTR/CL_TST_PCI}] -clear_locs
+add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells [list CL/CL_PCIM_MSTR/PCI_AXI4_REG_SLC]]
+resize_pblock [get_pblocks pblock_CL_mid] -add {CLOCKREGION_X0Y5:CLOCKREGION_X3Y9}
+set_property PARENT pblock_CL [get_pblocks pblock_CL_mid]
+
+create_pblock pblock_CL_bot
+add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells [list CL/CL_DMA_PCIS_SLV/PCI_AXL_REG_SLC CL/CL_OCL_SLV/AXIL_OCL_REG_SLC CL/CL_SDA_SLV/AXIL_SDA_REG_SLC]]
+add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -hierarchical -filter { NAME =~ "*CL/CL_OCL_SLV/slv_tst_wdata_reg[*][*]*" && PRIMITIVE_TYPE =~ REGISTER.*.* }]
+#Reassign select cells to parent Pblock for better QoR
+add_cells_to_pblock [get_pblocks pblock_CL] $pblock_cells
+resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X3Y4}
+set_property PARENT pblock_CL [get_pblocks pblock_CL_bot]
+
+set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
+set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
+set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
+
+
diff --git a/cl_nvdla/build/constraints/cl_synth_user.xdc b/cl_nvdla/build/constraints/cl_synth_user.xdc
new file mode 100644
index 0000000..08b4712
--- /dev/null
+++ b/cl_nvdla/build/constraints/cl_synth_user.xdc
@@ -0,0 +1,3 @@
+# This contains the CL specific constraints for synthesis at the CL level
+
+
diff --git a/cl_nvdla/build/scripts/README.md b/cl_nvdla/build/scripts/README.md
new file mode 100644
index 0000000..ba52bce
--- /dev/null
+++ b/cl_nvdla/build/scripts/README.md
@@ -0,0 +1,13 @@
+# Step by step to build nvdla(small configuration) in AWS F1:
+1. Setup environment variables:
+ > export CL_DIR=/vp/fpga/aws-fpga/cl_nvdla
+ > export NV_HW_ROOT=
+2. Git clone aws-fpga from github:
+ > git clone https://github.com/aws/aws-fpga.git
+3. Souce aws-fpga hdk environment:
+ > source aws-fpga/hdk_setup.sh
+4. generate nvdla file list:
+ > ./filelist.sh
+4. Command line to build nvdla in aws fpga:
+ > $HDK_DIR/common/shell_stable/build/scripts/aws_build_dcp_from_cl.sh -foreground -clock_recipe_a A2
+
diff --git a/cl_nvdla/build/scripts/create_dcp_from_cl.tcl b/cl_nvdla/build/scripts/create_dcp_from_cl.tcl
new file mode 100755
index 0000000..b412255
--- /dev/null
+++ b/cl_nvdla/build/scripts/create_dcp_from_cl.tcl
@@ -0,0 +1,367 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+package require tar
+
+## Do not edit $TOP
+set TOP top_sp
+
+## Replace with the name of your module
+set CL_MODULE cl_nvdla
+
+#################################################
+## Command-line Arguments
+#################################################
+set timestamp [lindex $argv 0]
+set strategy [lindex $argv 1]
+set hdk_version [lindex $argv 2]
+set shell_version [lindex $argv 3]
+set device_id [lindex $argv 4]
+set vendor_id [lindex $argv 5]
+set subsystem_id [lindex $argv 6]
+set subsystem_vendor_id [lindex $argv 7]
+set clock_recipe_a [lindex $argv 8]
+set clock_recipe_b [lindex $argv 9]
+set clock_recipe_c [lindex $argv 10]
+set uram_option [lindex $argv 11]
+set notify_via_sns [lindex $argv 12]
+
+##################################################
+## Flow control variables
+##################################################
+set cl.synth 1
+set implement 1
+
+#################################################
+## Generate CL_routed.dcp (Done by User)
+#################################################
+puts "AWS FPGA Scripts";
+puts "Creating Design Checkpoint from Custom Logic source code";
+puts "HDK Version: $hdk_version";
+puts "Shell Version: $shell_version";
+puts "Vivado Script Name: $argv0";
+puts "Strategy: $strategy";
+puts "PCI Device ID $device_id";
+puts "PCI Vendor ID $vendor_id";
+puts "PCI Subsystem ID $subsystem_id";
+puts "PCI Subsystem Vendor ID $subsystem_vendor_id";
+puts "Clock Recipe A: $clock_recipe_a";
+puts "Clock Recipe B: $clock_recipe_b";
+puts "Clock Recipe C: $clock_recipe_c";
+puts "URAM option: $uram_option";
+puts "Notify when done: $notify_via_sns";
+
+#checking if CL_DIR env variable exists
+if { [info exists ::env(CL_DIR)] } {
+ set CL_DIR $::env(CL_DIR)
+ puts "Using CL directory $CL_DIR";
+} else {
+ puts "Error: CL_DIR environment variable not defined ! ";
+ puts "Use export CL_DIR=Your_Design_Root_Directory"
+ exit 2
+}
+
+#checking if HDK_SHELL_DIR env variable exists
+if { [info exists ::env(HDK_SHELL_DIR)] } {
+ set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
+ puts "Using Shell directory $HDK_SHELL_DIR";
+} else {
+ puts "Error: HDK_SHELL_DIR environment variable not defined ! ";
+ puts "Run the hdk_setup.sh script from the root directory of aws-fpga";
+ exit 2
+}
+
+#checking if HDK_SHELL_DESIGN_DIR env variable exists
+if { [info exists ::env(HDK_SHELL_DESIGN_DIR)] } {
+ set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
+ puts "Using Shell design directory $HDK_SHELL_DESIGN_DIR";
+} else {
+ puts "Error: HDK_SHELL_DESIGN_DIR environment variable not defined ! ";
+ puts "Run the hdk_setup.sh script from the root directory of aws-fpga";
+ exit 2
+}
+
+##################################################
+### Output Directories used by step_user.tcl
+##################################################
+set implDir $CL_DIR/build/checkpoints
+set rptDir $CL_DIR/build/reports
+set cacheDir $HDK_SHELL_DESIGN_DIR/cache/ddr4_phy
+
+puts "All reports and intermediate results will be time stamped with $timestamp";
+
+set_msg_config -id {Chipscope 16-3} -suppress
+set_msg_config -string {AXI_QUAD_SPI} -suppress
+
+# Suppress Warnings
+# These are to avoid warning messages that may not be real issues. A developer
+# may comment them out if they wish to see more information from warning
+# messages.
+set_msg_config -id {Common 17-55} -suppress
+set_msg_config -id {Designutils 20-1567} -suppress
+set_msg_config -id {IP_Flow 19-2162} -suppress
+set_msg_config -id {Project 1-498} -suppress
+set_msg_config -id {Route 35-328} -suppress
+set_msg_config -id {Vivado 12-508} -suppress
+set_msg_config -id {Constraints 18-4866} -suppress
+set_msg_config -id {filemgmt 56-12} -suppress
+set_msg_config -id {Constraints 18-4644} -suppress
+set_msg_config -id {Coretcl 2-64} -suppress
+set_msg_config -id {Vivado 12-4739} -suppress
+set_msg_config -id {Vivado 12-5201} -suppress
+set_msg_config -id {DRC CKLD-1} -suppress
+set_msg_config -id {IP_Flow 19-2248} -suppress
+set_msg_config -id {Opt 31-155} -suppress
+set_msg_config -id {Synth 8-115} -suppress
+set_msg_config -id {Synth 8-3936} -suppress
+set_msg_config -id {Vivado 12-1023} -suppress
+set_msg_config -id {Constraints 18-550} -suppress
+set_msg_config -id {Synth 8-3295} -suppress
+set_msg_config -id {Synth 8-3321} -suppress
+set_msg_config -id {Synth 8-3331} -suppress
+set_msg_config -id {Synth 8-3332} -suppress
+set_msg_config -id {Synth 8-350} -suppress
+set_msg_config -id {Synth 8-3848} -suppress
+set_msg_config -id {Synth 8-3917} -suppress
+set_msg_config -id {Synth 8-6014} -suppress
+set_msg_config -id {Vivado 12-1580} -suppress
+set_msg_config -id {Constraints 18-619} -suppress
+set_msg_config -id {DRC CKLD-2} -suppress
+set_msg_config -id {DRC REQP-1853} -suppress
+set_msg_config -id {Timing 38-436} -suppress
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
+
+# Check that an email address has been set, else unset notify_via_sns
+
+if {[string compare $notify_via_sns "1"] == 0} {
+ if {![info exists env(EMAIL)]} {
+ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL variable empty! Completition notification will *not* be sent!";
+ set notify_via_sns 0;
+ } else {
+ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL address for completion notification set to $env(EMAIL).";
+ }
+}
+
+##################################################
+### Strategy options
+##################################################
+switch $strategy {
+ "BASIC" {
+ puts "BASIC strategy."
+ source $HDK_SHELL_DIR/build/scripts/strategy_BASIC.tcl
+ }
+ "EXPLORE" {
+ puts "EXPLORE strategy."
+ source $HDK_SHELL_DIR/build/scripts/strategy_EXPLORE.tcl
+ }
+ "TIMING" {
+ puts "TIMING strategy."
+ source $HDK_SHELL_DIR/build/scripts/strategy_TIMING.tcl
+ }
+ "CONGESTION" {
+ puts "CONGESTION strategy."
+ source $HDK_SHELL_DIR/build/scripts/strategy_CONGESTION.tcl
+ }
+ "DEFAULT" {
+ puts "DEFAULT strategy."
+ source $HDK_SHELL_DIR/build/scripts/strategy_DEFAULT.tcl
+ }
+ default {
+ puts "$strategy is NOT a valid strategy. Defaulting to strategy DEFAULT."
+ source $HDK_SHELL_DIR/build/scripts/strategy_DEFAULT.tcl
+ }
+}
+
+#Encrypt source code
+source encrypt.tcl
+
+#Set the Device Type
+source $HDK_SHELL_DIR/build/scripts/device_type.tcl
+
+#Procedure for running various implementation steps (impl_step)
+source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
+
+########################################
+## Generate clocks based on Recipe
+########################################
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
+
+source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
+
+##################################################
+### CL XPR OOC Synthesis
+##################################################
+if {${cl.synth}} {
+ source -notrace ./synth_${CL_MODULE}.tcl
+}
+
+##################################################
+### Implementation
+##################################################
+if {$implement} {
+
+ ########################
+ # Link Design
+ ########################
+ if {$link} {
+ ####Create in-memory prjoect and setup IP cache location
+ create_project -part [DEVICE_TYPE] -in_memory
+ set_property IP_REPO_PATHS $cacheDir [current_project]
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Combining Shell and CL design checkpoints";
+ add_files $HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp
+ add_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
+ set_property SCOPED_TO_CELLS {CL} [get_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp]
+
+ #Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)
+ read_xdc [ list \
+ $CL_DIR/build/constraints/cl_pnr_user.xdc
+ ]
+ set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]
+
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running link_design";
+ link_design -top $TOP -part [DEVICE_TYPE] -reconfig_partitions {SH CL}
+
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - PLATFORM.IMPL==[get_property PLATFORM.IMPL [current_design]]";
+ ##################################################
+ # Apply Clock Properties for Clock Table Recipes
+ ##################################################
+ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
+
+ # Apply properties to clocks
+ source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
+
+ # Write post-link checkpoint
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Writing post-link_design checkpoint ${timestamp}.post_link.dcp";
+ write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.post_link.dcp
+ }
+
+ ########################
+ # CL Optimize
+ ########################
+ if {$opt} {
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running optimization";
+ impl_step opt_design $TOP $opt_options $opt_directive $opt_preHookTcl $opt_postHookTcl
+ if {$psip} {
+ impl_step opt_design $TOP "-merge_equivalent_drivers -sweep"
+ }
+ }
+
+ ########################
+ # CL Place
+ ########################
+ if {$place} {
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running placement";
+ if {$psip} {
+ append place_options " -fanout_opt"
+ }
+ impl_step place_design $TOP $place_options $place_directive $place_preHookTcl $place_postHookTcl
+ }
+
+ ##############################
+ # CL Post-Place Optimization
+ ##############################
+ if {$phys_opt} {
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-place optimization";
+ impl_step phys_opt_design $TOP $phys_options $phys_directive $phys_preHookTcl $phys_postHookTcl
+ }
+
+ ########################
+ # CL Route
+ ########################
+ if {$route} {
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Routing design";
+ impl_step route_design $TOP $route_options $route_directive $route_preHookTcl $route_postHookTcl
+ }
+
+ ##############################
+ # CL Post-Route Optimization
+ ##############################
+ set SLACK [get_property SLACK [get_timing_paths]]
+ #Post-route phys_opt will not be run if slack is positive or greater than -200ps.
+ if {$route_phys_opt && $SLACK > -0.400 && $SLACK < 0} {
+ puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-route optimization";
+ impl_step route_phys_opt_design $TOP $post_phys_options $post_phys_directive $post_phys_preHookTcl $post_phys_postHookTcl
+ }
+
+ ##############################
+ # Final Implmentation Steps
+ ##############################
+ # Report final timing
+ report_timing_summary -file $CL_DIR/build/reports/${timestamp}.SH_CL_final_timing_summary.rpt
+
+ # This is what will deliver to AWS
+ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Writing final DCP to to_aws directory.";
+
+ write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
+
+ # Generate debug probes file
+ write_debug_probes -force -no_partial_ltxfile -file $CL_DIR/build/checkpoints/${timestamp}.debug_probes.ltx
+
+ close_project
+}
+
+# ################################################
+# Create Manifest and Tarball for delivery
+# ################################################
+
+# Create a zipped tar file, that would be used for createFpgaImage EC2 API
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Compress files for sending to AWS. "
+
+# Create manifest file
+set manifest_file [open "$CL_DIR/build/checkpoints/to_aws/${timestamp}.manifest.txt" w]
+set hash [lindex [split [exec sha256sum $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp] ] 0]
+
+puts $manifest_file "manifest_format_version=1\n"
+puts $manifest_file "pci_vendor_id=$vendor_id\n"
+puts $manifest_file "pci_device_id=$device_id\n"
+puts $manifest_file "pci_subsystem_id=$subsystem_id\n"
+puts $manifest_file "pci_subsystem_vendor_id=$subsystem_vendor_id\n"
+puts $manifest_file "dcp_hash=$hash\n"
+puts $manifest_file "shell_version=$shell_version\n"
+puts $manifest_file "dcp_file_name=${timestamp}.SH_CL_routed.dcp\n"
+puts $manifest_file "hdk_version=$hdk_version\n"
+puts $manifest_file "date=$timestamp\n"
+puts $manifest_file "clock_recipe_a=$clock_recipe_a\n"
+puts $manifest_file "clock_recipe_b=$clock_recipe_b\n"
+puts $manifest_file "clock_recipe_c=$clock_recipe_c\n"
+
+close $manifest_file
+
+# Delete old tar file with same name
+if { [file exists $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar] } {
+ puts "Deleting old tar file with same name.";
+ file delete -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar
+}
+
+# Tar checkpoint to aws
+cd $CL_DIR/build/checkpoints
+tar::create to_aws/${timestamp}.Developer_CL.tar [glob to_aws/${timestamp}*]
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Finished creating final tar file in to_aws directory.";
+
+if {[string compare $notify_via_sns "1"] == 0} {
+ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Calling notification script to send e-mail to $env(EMAIL)";
+ exec $env(HDK_COMMON_DIR)/scripts/notify_via_sns.py
+}
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
+
+
diff --git a/cl_nvdla/build/scripts/download_f1 b/cl_nvdla/build/scripts/download_f1
new file mode 100755
index 0000000..eb4055a
--- /dev/null
+++ b/cl_nvdla/build/scripts/download_f1
@@ -0,0 +1,13 @@
+# ================================================================
+# NVDLA Open Source Project
+#
+# Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+# NVDLA Open Hardware License; Check \"LICENSE\" which comes with
+# this distribution for more information.
+# ================================================================
+
+sudo fpga-clear-local-image -S 0
+sudo fpga-describe-local-image -S 0 -H
+sudo fpga-load-local-image -S 0 -I "agfi-0f43c1ea1b624384e"
+sudo fpga-describe-local-image -S 0 -R -H
+sudo rmmod edma-drv && sudo insmod $SDK_DIR/linux_kernel_drivers/edma/edma-drv.ko
diff --git a/cl_nvdla/build/scripts/encrypt.tcl b/cl_nvdla/build/scripts/encrypt.tcl
new file mode 100644
index 0000000..534719b
--- /dev/null
+++ b/cl_nvdla/build/scripts/encrypt.tcl
@@ -0,0 +1,63 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+# TODO:
+# Add check if CL_DIR and HDK_SHELL_DIR directories exist
+# Add check if /build and /build/src_port_encryption directories exist
+# Add check if the vivado_keyfile exist
+
+set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
+set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
+set CL_DIR $::env(CL_DIR)
+set NV_HW_ROOT $::env(NV_HW_ROOT)
+
+set TARGET_DIR $CL_DIR/build/src_post_encryption
+set UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces
+
+
+# Remove any previously encrypted files, that may no longer be used
+exec rm -f $TARGET_DIR/*
+
+#---- Developr would replace this section with design files ----
+
+## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files.
+file copy -force $CL_DIR/design/cl_nvdla_defines.vh $TARGET_DIR
+file copy -force $CL_DIR/../common/design/transactors/cfg/cl_cfgreg.sv $TARGET_DIR
+file copy -force $CL_DIR/../common/design/transactors/irq/cl_irq_up.v $TARGET_DIR
+file copy -force $CL_DIR/../common/design/transactors/irq/cl_irq_up_bit.v $TARGET_DIR
+file copy -force $CL_DIR/../common/design/transactors/irq/simulate_x_tick.vh $TARGET_DIR
+file copy -force $CL_DIR/design/cl_dma_pcis_slv.sv $TARGET_DIR
+file copy -force $CL_DIR/design/cl_id_defines.vh $TARGET_DIR
+file copy -force $CL_DIR/design/cl_ila.sv $TARGET_DIR
+file copy -force $CL_DIR/design/cl_nvdla_pkg.sv $TARGET_DIR
+file copy -force $CL_DIR/design/cl_nvdla_wrap.sv $TARGET_DIR
+file copy -force $CL_DIR/design/cl_vio.sv $TARGET_DIR
+file copy -force $CL_DIR/design/cl_nvdla.sv $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_apppf_irq_template.inc $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_cl_sda_template.inc $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_a_b_d_template.inc $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_c_template.inc $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_dma_pcis_template.inc $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_pcim_template.inc $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR
+file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc $TARGET_DIR
+source ./nvdla_file.tcl
+
+#---- End of section replaced by Developr ---
+exec chmod +w {*}[glob $TARGET_DIR/*]
+#encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
diff --git a/cl_nvdla/build/scripts/filelist.sh b/cl_nvdla/build/scripts/filelist.sh
new file mode 100755
index 0000000..c3f72a7
--- /dev/null
+++ b/cl_nvdla/build/scripts/filelist.sh
@@ -0,0 +1,65 @@
+# ================================================================
+# NVDLA Open Source Project
+#
+# Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+# NVDLA Open Hardware License; Check \"LICENSE\" which comes with
+# this distribution for more information.
+# ================================================================
+
+rm -rf ./nvdla_file.tcl
+
+SelecSource(){
+local_folder=$1
+local_file_type=$2
+
+echo processing the folder: $local_folder
+file_list=`ls ${NV_HW_ROOT}/${local_folder}/*.${local_file_type}`
+#echo ${file_list}
+for file in ${file_list}
+do
+tmp_file=`basename $file`
+echo file copy -force \$NV_HW_ROOT/$local_folder/$tmp_file \$TARGET_DIR >> ./nvdla_file.tcl
+done
+}
+
+RemoveFile(){
+local_file=$1
+echo "remove file $local_file"
+sed '/'$local_file'/d' nvdla_file.tcl > nvdla_file.tcl_temp
+mv nvdla_file.tcl_temp nvdla_file.tcl
+}
+
+ip_path=outdir/nv_small/spec/manual
+file_type=v
+SelecSource $ip_path $file_type
+
+ip_path=outdir/nv_small/vmod/nvdla
+file_type=v
+folder_list=`ls ${NV_HW_ROOT}/${ip_path}`
+echo ${folder_list}
+for folder in ${folder_list}
+do
+SelecSource ${ip_path}/$folder $file_type
+done
+
+ip_path=outdir/nv_small/vmod/include
+file_type=vh
+SelecSource ${ip_path} $file_type
+
+ip_path=outdir/nv_small/vmod/vlibs
+file_type=v
+SelecSource ${ip_path} $file_type
+
+ip_path=outdir/nv_small/spec/defs
+file_type=vh
+SelecSource ${ip_path} $file_type
+
+ip_path=outdir/nv_small/vmod/rams/fpga/small_rams
+file_type=v
+SelecSource ${ip_path} $file_type
+
+file_remove_list="NV_NVDLA_SDP_CORE_Y_lut.v NV_NVDLA_SDP_HLS_Y_cvt_top.v NV_NVDLA_SDP_HLS_Y_idx_top.v NV_NVDLA_SDP_HLS_Y_inp_top.v NV_NVDLA_SDP_HLS_Y_int_core.v"
+for each_file in $file_remove_list
+do
+RemoveFile $each_file
+done
diff --git a/cl_nvdla/build/scripts/synth_cl_nvdla.tcl b/cl_nvdla/build/scripts/synth_cl_nvdla.tcl
new file mode 100644
index 0000000..0e4fe3c
--- /dev/null
+++ b/cl_nvdla/build/scripts/synth_cl_nvdla.tcl
@@ -0,0 +1,145 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+#Param needed to avoid clock name collisions
+set_param sta.enableAutoGenClkNamePersistence 0
+set CL_MODULE $CL_MODULE
+
+create_project -in_memory -part [DEVICE_TYPE] -force
+
+########################################
+## Generate clocks based on Recipe
+########################################
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
+
+source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
+
+#############################
+## Read design files
+#############################
+
+#Convenience to set the root of the RTL directory
+set ENC_SRC_DIR $CL_DIR/build/src_post_encryption
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's Custom Logic files post encryption.";
+
+#---- User would replace this section -----
+
+# Reading the .sv and .v files, as proper designs would not require
+# reading .v, .vh, nor .inc files
+
+read_verilog -sv [glob $ENC_SRC_DIR/*.v]
+read_verilog -sv [glob $ENC_SRC_DIR/*.vh]
+read_verilog -sv [glob $ENC_SRC_DIR/*.sv]
+
+#---- End of section replaced by User ----
+
+puts "AWS FPGA: Reading AWS Shell design";
+
+#Read AWS Design files
+read_verilog [ list \
+ $HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
+ $HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \
+ $HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_acc_axl.sv \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_gen_axl.sv \
+ $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sh_ddr.sv \
+ $HDK_SHELL_DESIGN_DIR/interfaces/cl_ports.vh
+]
+
+puts "AWS FPGA: Reading IP blocks";
+
+#Read DDR IP
+read_ip [ list \
+ $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci
+]
+
+#Read IP for axi register slices
+read_ip [ list \
+ $HDK_SHELL_DESIGN_DIR/ip/src_register_slice/src_register_slice.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/dest_register_slice/dest_register_slice.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/axi_clock_converter_0/axi_clock_converter_0.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/axi_register_slice/axi_register_slice.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/axi_register_slice_light/axi_register_slice_light.xci
+]
+
+#Read IP for virtual jtag / ILA/VIO
+read_ip [ list \
+ $HDK_SHELL_DESIGN_DIR/ip/cl_debug_bridge/cl_debug_bridge.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/ila_1/ila_1.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/ila_vio_counter/ila_vio_counter.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/vio_0/vio_0.xci
+]
+
+# Additional IP's that might be needed if using the DDR
+read_bd [ list \
+ $HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd
+]
+
+#Read Xilinx interconnection IP
+read_ip [ list \
+ $CL_DIR/../common/design/xilinx_ip/axi_interconnect_nvdla_64b/axi_interconnect_nvdla_64b.xci \
+ $CL_DIR/../common/design/xilinx_ip/axi_apb_bridge_0/axi_apb_bridge_0.xci
+]
+
+
+puts "AWS FPGA: Reading AWS constraints";
+
+#Read all the constraints
+#
+# cl_clocks_aws.xdc - AWS auto-generated clock constraint. ***DO NOT MODIFY***
+# cl_ddr.xdc - AWS provided DDR pin constraints. ***DO NOT MODIFY***
+# cl_synth_user.xdc - Developer synthesis constraints.
+read_xdc [ list \
+ $CL_DIR/build/constraints/cl_clocks_aws.xdc \
+ $HDK_SHELL_DIR/build/constraints/cl_ddr.xdc \
+ $HDK_SHELL_DIR/build/constraints/cl_synth_aws.xdc \
+ $CL_DIR/build/constraints/cl_synth_user.xdc
+]
+set_property file_type SystemVerilog [get_files *.v]
+set_property verilog_define {FPGA=1 SYNTHESIS=1 DESIGNWARE_NOEXIST=1 VLIB_BYPASS_POWER_CG=1 NV_FPGA_SYSTEM=1 NV_FPGA_UNIT=1} [current_fileset]
+
+#Do not propagate local clock constraints for clocks generated in the SH
+set_property USED_IN {synthesis implementation OUT_OF_CONTEXT} [get_files cl_clocks_aws.xdc]
+set_property PROCESSING_ORDER EARLY [get_files cl_clocks_aws.xdc]
+
+########################
+# CL Synthesis
+########################
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthesis.";
+
+update_compile_order -fileset sources_1
+puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
+eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -verilog_define FPGA -verilog_define SYNTHESIS -verilog_define DESIGNWARE_NOEXIST -verilog_define VLIB_BYPASS_POWER_CG -verilog_define NV_FPGA_SYSTEM -verilog_define NV_FPGA_FIFOGEN -verilog_define NV_FPGA_UNIT -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
+
+set failval [catch {exec grep "FAIL" failfast.csv}]
+if { $failval==0 } {
+ puts "AWS FPGA: FATAL ERROR--Resource utilization error; check failfast.csv for details"
+ exit 1
+}
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing post synth checkpoint.";
+write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
+
+close_project
+#Set param back to default value
+set_param sta.enableAutoGenClkNamePersistence 1
diff --git a/cl_nvdla/build/scripts/upload_f1 b/cl_nvdla/build/scripts/upload_f1
new file mode 100755
index 0000000..976b2b4
--- /dev/null
+++ b/cl_nvdla/build/scripts/upload_f1
@@ -0,0 +1,15 @@
+# ================================================================
+# NVDLA Open Source Project
+#
+# Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+# NVDLA Open Hardware License; Check \"LICENSE\" which comes with
+# this distribution for more information.
+# ================================================================
+
+aws s3 mb s3://sqi
+aws s3 mb s3://sqi/nv_small_64/
+aws s3 cp $CL_DIR/build/checkpoints/to_aws/18_04_16-221842.Developer_CL.tar s3://sqi/nv_small_64/
+aws s3 mb s3://sqi/nv_small_64_log/
+touch LOGS_FILES_GO_HERE.txt
+aws s3 cp LOGS_FILES_GO_HERE.txt s3://sqi/nv_small_64_log/
+aws ec2 create-fpga-image --name nvdla_small_64_18_04_16_221842 --description nvdla_small_18_04_16_221842 --input-storage-location Bucket=sqi,Key=nv_small_64/18_04_16-221842.Developer_CL.tar --logs-storage-location Bucket=sqi,Key=nv_small_64_log
diff --git a/cl_nvdla/design/cl_dma_pcis_slv.sv b/cl_nvdla/design/cl_dma_pcis_slv.sv
new file mode 100644
index 0000000..c5ff1c6
--- /dev/null
+++ b/cl_nvdla/design/cl_dma_pcis_slv.sv
@@ -0,0 +1,428 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+module cl_dma_pcis_slv #(parameter SCRB_MAX_ADDR = 64'h3FFFFFFFF, parameter SCRB_BURST_LEN_MINUS1 = 15, parameter NO_SCRB_INST = 1)
+
+(
+ input aclk,
+ input aresetn,
+
+ axi_bus_t.master sh_cl_dma_pcis_bus,
+ axi_bus_t.master nvdla_dbb_axi_bus,
+`ifdef NVDLA_CVSRAM_PRESENT
+ axi_bus_t.master nvdla_cvsram_axi_bus,
+`endif
+
+ axi_bus_t sh_cl_dma_pcis_q,
+
+ axi_bus_t.slave cl_sh_ddr_bus
+
+
+);
+localparam NUM_CFG_STGS_CL_DDR_ATG = 4;
+localparam NUM_CFG_STGS_SH_DDR_ATG = 4;
+
+//----------------------------
+// Internal signals
+//----------------------------
+axi_bus_t cl_sh_ddr_q();
+axi_bus_t cl_sh_ddr_q2();
+axi_bus_t sh_cl_pcis();
+
+//----------------------------
+// End Internal signals
+//----------------------------
+
+
+//reset synchronizers
+(* dont_touch = "true" *) logic slr0_sync_aresetn;
+(* dont_touch = "true" *) logic slr1_sync_aresetn;
+(* dont_touch = "true" *) logic slr2_sync_aresetn;
+lib_pipe #(.WIDTH(1), .STAGES(4)) SLR0_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in_bus(aresetn), .out_bus(slr0_sync_aresetn));
+lib_pipe #(.WIDTH(1), .STAGES(4)) SLR1_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in_bus(aresetn), .out_bus(slr1_sync_aresetn));
+lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in_bus(aresetn), .out_bus(slr2_sync_aresetn));
+
+//----------------------------
+// flop the dma_pcis interface input of CL
+//----------------------------
+
+ // AXI4 Register Slice for dma_pcis interface
+ axi_register_slice PCI_AXL_REG_SLC (
+ .aclk (aclk),
+ .aresetn (slr0_sync_aresetn),
+ .s_axi_awid (sh_cl_dma_pcis_bus.awid),
+ .s_axi_awaddr (sh_cl_dma_pcis_bus.awaddr),
+ .s_axi_awlen (sh_cl_dma_pcis_bus.awlen),
+ .s_axi_awvalid (sh_cl_dma_pcis_bus.awvalid),
+ .s_axi_awsize (sh_cl_dma_pcis_bus.awsize),
+ .s_axi_awready (sh_cl_dma_pcis_bus.awready),
+ .s_axi_wdata (sh_cl_dma_pcis_bus.wdata),
+ .s_axi_wstrb (sh_cl_dma_pcis_bus.wstrb),
+ .s_axi_wlast (sh_cl_dma_pcis_bus.wlast),
+ .s_axi_wvalid (sh_cl_dma_pcis_bus.wvalid),
+ .s_axi_wready (sh_cl_dma_pcis_bus.wready),
+ .s_axi_bid (sh_cl_dma_pcis_bus.bid),
+ .s_axi_bresp (sh_cl_dma_pcis_bus.bresp),
+ .s_axi_bvalid (sh_cl_dma_pcis_bus.bvalid),
+ .s_axi_bready (sh_cl_dma_pcis_bus.bready),
+ .s_axi_arid (sh_cl_dma_pcis_bus.arid),
+ .s_axi_araddr (sh_cl_dma_pcis_bus.araddr),
+ .s_axi_arlen (sh_cl_dma_pcis_bus.arlen),
+ .s_axi_arvalid (sh_cl_dma_pcis_bus.arvalid),
+ .s_axi_arsize (sh_cl_dma_pcis_bus.arsize),
+ .s_axi_arready (sh_cl_dma_pcis_bus.arready),
+ .s_axi_rid (sh_cl_dma_pcis_bus.rid),
+ .s_axi_rdata (sh_cl_dma_pcis_bus.rdata),
+ .s_axi_rresp (sh_cl_dma_pcis_bus.rresp),
+ .s_axi_rlast (sh_cl_dma_pcis_bus.rlast),
+ .s_axi_rvalid (sh_cl_dma_pcis_bus.rvalid),
+ .s_axi_rready (sh_cl_dma_pcis_bus.rready),
+
+ .m_axi_awid (sh_cl_dma_pcis_q.awid),
+ .m_axi_awaddr (sh_cl_dma_pcis_q.awaddr),
+ .m_axi_awlen (sh_cl_dma_pcis_q.awlen),
+ .m_axi_awvalid (sh_cl_dma_pcis_q.awvalid),
+ .m_axi_awsize (sh_cl_dma_pcis_q.awsize),
+ .m_axi_awready (sh_cl_dma_pcis_q.awready),
+ .m_axi_wdata (sh_cl_dma_pcis_q.wdata),
+ .m_axi_wstrb (sh_cl_dma_pcis_q.wstrb),
+ .m_axi_wvalid (sh_cl_dma_pcis_q.wvalid),
+ .m_axi_wlast (sh_cl_dma_pcis_q.wlast),
+ .m_axi_wready (sh_cl_dma_pcis_q.wready),
+ .m_axi_bresp (sh_cl_dma_pcis_q.bresp),
+ .m_axi_bvalid (sh_cl_dma_pcis_q.bvalid),
+ .m_axi_bid (sh_cl_dma_pcis_q.bid),
+ .m_axi_bready (sh_cl_dma_pcis_q.bready),
+ .m_axi_arid (sh_cl_dma_pcis_q.arid),
+ .m_axi_araddr (sh_cl_dma_pcis_q.araddr),
+ .m_axi_arlen (sh_cl_dma_pcis_q.arlen),
+ .m_axi_arsize (sh_cl_dma_pcis_q.arsize),
+ .m_axi_arvalid (sh_cl_dma_pcis_q.arvalid),
+ .m_axi_arready (sh_cl_dma_pcis_q.arready),
+ .m_axi_rid (sh_cl_dma_pcis_q.rid),
+ .m_axi_rdata (sh_cl_dma_pcis_q.rdata),
+ .m_axi_rresp (sh_cl_dma_pcis_q.rresp),
+ .m_axi_rlast (sh_cl_dma_pcis_q.rlast),
+ .m_axi_rvalid (sh_cl_dma_pcis_q.rvalid),
+ .m_axi_rready (sh_cl_dma_pcis_q.rready)
+ );
+
+
+//----------------------------
+// axi interconnect for DDR address decodes
+//----------------------------
+`ifdef NVDLA_CVSRAM_PRESENT
+(* dont_touch = "true" *) axi_interconnect_nvdla_512b AXI_INTERCONNECT (
+`else
+(* dont_touch = "true" *) axi_interconnect_nvdla_64b AXI_INTERCONNECT (
+`endif
+ .INTERCONNECT_ACLK (aclk)
+ ,.INTERCONNECT_ARESETN (slr1_sync_aresetn)
+ ,.S00_AXI_ARESET_OUT_N ()
+ ,.S00_AXI_ACLK (aclk)
+ ,.S00_AXI_AWID ({2'b0, sh_cl_dma_pcis_q.awid[5:0]})
+ ,.S00_AXI_AWADDR ({sh_cl_dma_pcis_q.awaddr[63:37], 1'b0, sh_cl_dma_pcis_q.awaddr[35:0]})
+ ,.S00_AXI_AWLEN (sh_cl_dma_pcis_q.awlen)
+ ,.S00_AXI_AWSIZE (sh_cl_dma_pcis_q.awsize)
+ ,.S00_AXI_AWBURST (2'b01)
+ ,.S00_AXI_AWLOCK (1'b0)
+ ,.S00_AXI_AWCACHE (4'b11)
+ ,.S00_AXI_AWPROT (3'b010)
+ ,.S00_AXI_AWQOS (4'b0)
+ ,.S00_AXI_AWVALID (sh_cl_dma_pcis_q.awvalid)
+ ,.S00_AXI_AWREADY (sh_cl_dma_pcis_q.awready)
+ ,.S00_AXI_WDATA (sh_cl_dma_pcis_q.wdata)
+ ,.S00_AXI_WSTRB (sh_cl_dma_pcis_q.wstrb)
+ ,.S00_AXI_WLAST (sh_cl_dma_pcis_q.wlast)
+ ,.S00_AXI_WVALID (sh_cl_dma_pcis_q.wvalid)
+ ,.S00_AXI_WREADY (sh_cl_dma_pcis_q.wready)
+ ,.S00_AXI_BID (sh_cl_dma_pcis_q.bid[5:0])
+ ,.S00_AXI_BRESP (sh_cl_dma_pcis_q.bresp)
+ ,.S00_AXI_BVALID (sh_cl_dma_pcis_q.bvalid)
+ ,.S00_AXI_BREADY (sh_cl_dma_pcis_q.bready)
+ ,.S00_AXI_ARID ({2'b0, sh_cl_dma_pcis_q.arid[5:0]})
+ ,.S00_AXI_ARADDR (sh_cl_dma_pcis_q.araddr)
+ ,.S00_AXI_ARLEN (sh_cl_dma_pcis_q.arlen)
+ ,.S00_AXI_ARSIZE (sh_cl_dma_pcis_q.arsize)
+ ,.S00_AXI_ARBURST (2'b01)
+ ,.S00_AXI_ARLOCK (1'b0)
+ ,.S00_AXI_ARCACHE (4'b11)
+ ,.S00_AXI_ARPROT (3'b010)
+ ,.S00_AXI_ARQOS (4'b0)
+ ,.S00_AXI_ARVALID (sh_cl_dma_pcis_q.arvalid)
+ ,.S00_AXI_ARREADY (sh_cl_dma_pcis_q.arready)
+ ,.S00_AXI_RID (sh_cl_dma_pcis_q.rid[5:0])
+ ,.S00_AXI_RDATA (sh_cl_dma_pcis_q.rdata)
+ ,.S00_AXI_RRESP (sh_cl_dma_pcis_q.rresp)
+ ,.S00_AXI_RLAST (sh_cl_dma_pcis_q.rlast)
+ ,.S00_AXI_RVALID (sh_cl_dma_pcis_q.rvalid)
+ ,.S00_AXI_RREADY (sh_cl_dma_pcis_q.rready)
+ ,.S01_AXI_ARESET_OUT_N ()
+ ,.S01_AXI_ACLK (aclk)
+ ,.S01_AXI_AWID (nvdla_dbb_axi_bus.awid)
+ ,.S01_AXI_AWADDR (nvdla_dbb_axi_bus.awaddr)
+ ,.S01_AXI_AWLEN ({4'b0, nvdla_dbb_axi_bus.awlen})
+ ,.S01_AXI_AWSIZE (nvdla_dbb_axi_bus.awsize)
+ ,.S01_AXI_AWBURST (2'b01)
+ ,.S01_AXI_AWLOCK (1'b0)
+ ,.S01_AXI_AWCACHE (4'b11)
+ ,.S01_AXI_AWPROT (3'b010)
+ ,.S01_AXI_AWQOS (4'b0)
+ ,.S01_AXI_AWVALID (nvdla_dbb_axi_bus.awvalid)
+ ,.S01_AXI_AWREADY (nvdla_dbb_axi_bus.awready)
+ ,.S01_AXI_WDATA (nvdla_dbb_axi_bus.wdata)
+ ,.S01_AXI_WSTRB (nvdla_dbb_axi_bus.wstrb)
+ ,.S01_AXI_WLAST (nvdla_dbb_axi_bus.wlast)
+ ,.S01_AXI_WVALID (nvdla_dbb_axi_bus.wvalid)
+ ,.S01_AXI_WREADY (nvdla_dbb_axi_bus.wready)
+ ,.S01_AXI_BID (nvdla_dbb_axi_bus.bid)
+ ,.S01_AXI_BRESP (nvdla_dbb_axi_bus.bresp)
+ ,.S01_AXI_BVALID (nvdla_dbb_axi_bus.bvalid)
+ ,.S01_AXI_BREADY (nvdla_dbb_axi_bus.bready)
+ ,.S01_AXI_ARID (nvdla_dbb_axi_bus.arid)
+ ,.S01_AXI_ARADDR (nvdla_dbb_axi_bus.araddr)
+ ,.S01_AXI_ARLEN ({4'b0, nvdla_dbb_axi_bus.arlen})
+ ,.S01_AXI_ARSIZE (nvdla_dbb_axi_bus.arsize)
+ ,.S01_AXI_ARBURST (2'b01)
+ ,.S01_AXI_ARLOCK (1'b0)
+ ,.S01_AXI_ARCACHE (4'b11)
+ ,.S01_AXI_ARPROT (3'b10)
+ ,.S01_AXI_ARQOS (4'b0)
+ ,.S01_AXI_ARVALID (nvdla_dbb_axi_bus.arvalid)
+ ,.S01_AXI_ARREADY (nvdla_dbb_axi_bus.arready)
+ ,.S01_AXI_RID (nvdla_dbb_axi_bus.rid)
+ ,.S01_AXI_RDATA (nvdla_dbb_axi_bus.rdata)
+ ,.S01_AXI_RRESP (nvdla_dbb_axi_bus.rresp)
+ ,.S01_AXI_RLAST (nvdla_dbb_axi_bus.rlast)
+ ,.S01_AXI_RVALID (nvdla_dbb_axi_bus.rvalid)
+ ,.S01_AXI_RREADY (nvdla_dbb_axi_bus.rready)
+`ifdef NVDLA_CVSRAM_PRESENT
+ ,.S02_AXI_ARESET_OUT_N ()
+ ,.S02_AXI_ACLK (aclk)
+ ,.S02_AXI_AWID (nvdla_cvsram_axi_bus.awid)
+ ,.S02_AXI_AWADDR (nvdla_cvsram_axi_bus.awaddr)
+ ,.S02_AXI_AWLEN ({4'b0, nvdla_cvsram_axi_bus.awlen})
+ ,.S02_AXI_AWSIZE (nvdla_cvsram_axi_bus.awsize)
+ ,.S02_AXI_AWBURST (2'b01)
+ ,.S02_AXI_AWLOCK (1'b0)
+ ,.S02_AXI_AWCACHE (4'b11)
+ ,.S02_AXI_AWPROT (3'b10)
+ ,.S02_AXI_AWQOS (4'b0)
+ ,.S02_AXI_AWVALID (nvdla_cvsram_axi_bus.awvalid)
+ ,.S02_AXI_AWREADY (nvdla_cvsram_axi_bus.awready)
+ ,.S02_AXI_WDATA (nvdla_cvsram_axi_bus.wdata)
+ ,.S02_AXI_WSTRB (nvdla_cvsram_axi_bus.wstrb)
+ ,.S02_AXI_WLAST (nvdla_cvsram_axi_bus.wlast)
+ ,.S02_AXI_WVALID (nvdla_cvsram_axi_bus.wvalid)
+ ,.S02_AXI_WREADY (nvdla_cvsram_axi_bus.wready)
+ ,.S02_AXI_BID (nvdla_cvsram_axi_bus.bid)
+ ,.S02_AXI_BRESP (nvdla_cvsram_axi_bus.bresp)
+ ,.S02_AXI_BVALID (nvdla_cvsram_axi_bus.bvalid)
+ ,.S02_AXI_BREADY (nvdla_cvsram_axi_bus.bready)
+ ,.S02_AXI_ARID (nvdla_cvsram_axi_bus.arid)
+ ,.S02_AXI_ARADDR (nvdla_cvsram_axi_bus.araddr)
+ ,.S02_AXI_ARLEN ({4'b0, nvdla_cvsram_axi_bus.arlen})
+ ,.S02_AXI_ARSIZE (nvdla_cvsram_axi_bus.arsize)
+ ,.S02_AXI_ARBURST (2'b01)
+ ,.S02_AXI_ARLOCK (1'b0)
+ ,.S02_AXI_ARCACHE (4'b11)
+ ,.S02_AXI_ARPROT (3'b10)
+ ,.S02_AXI_ARQOS (4'b0)
+ ,.S02_AXI_ARVALID (nvdla_cvsram_axi_bus.arvalid)
+ ,.S02_AXI_ARREADY (nvdla_cvsram_axi_bus.arready)
+ ,.S02_AXI_RID (nvdla_cvsram_axi_bus.rid)
+ ,.S02_AXI_RDATA (nvdla_cvsram_axi_bus.rdata)
+ ,.S02_AXI_RRESP (nvdla_cvsram_axi_bus.rresp)
+ ,.S02_AXI_RLAST (nvdla_cvsram_axi_bus.rlast)
+ ,.S02_AXI_RVALID (nvdla_cvsram_axi_bus.rvalid)
+ ,.S02_AXI_RREADY (nvdla_cvsram_axi_bus.rready)
+`endif
+ ,.M00_AXI_ARESET_OUT_N ()
+ ,.M00_AXI_ACLK (aclk)
+ ,.M00_AXI_AWID (cl_sh_ddr_q.awid[11:0])
+ ,.M00_AXI_AWADDR (cl_sh_ddr_q.awaddr)
+ ,.M00_AXI_AWLEN (cl_sh_ddr_q.awlen)
+ ,.M00_AXI_AWSIZE (cl_sh_ddr_q.awsize)
+ ,.M00_AXI_AWBURST ()
+ ,.M00_AXI_AWLOCK ()
+ ,.M00_AXI_AWCACHE ()
+ ,.M00_AXI_AWPROT ()
+ ,.M00_AXI_AWQOS ()
+ ,.M00_AXI_AWVALID (cl_sh_ddr_q.awvalid)
+ ,.M00_AXI_AWREADY (cl_sh_ddr_q.awready)
+ ,.M00_AXI_WDATA (cl_sh_ddr_q.wdata)
+ ,.M00_AXI_WSTRB (cl_sh_ddr_q.wstrb)
+ ,.M00_AXI_WLAST (cl_sh_ddr_q.wlast)
+ ,.M00_AXI_WVALID (cl_sh_ddr_q.wvalid)
+ ,.M00_AXI_WREADY (cl_sh_ddr_q.wready)
+ ,.M00_AXI_BID (cl_sh_ddr_q.bid[11:0])
+ ,.M00_AXI_BRESP (cl_sh_ddr_q.bresp)
+ ,.M00_AXI_BVALID (cl_sh_ddr_q.bvalid)
+ ,.M00_AXI_BREADY (cl_sh_ddr_q.bready)
+ ,.M00_AXI_ARID (cl_sh_ddr_q.arid[11:0])
+ ,.M00_AXI_ARADDR (cl_sh_ddr_q.araddr)
+ ,.M00_AXI_ARLEN (cl_sh_ddr_q.arlen)
+ ,.M00_AXI_ARSIZE (cl_sh_ddr_q.arsize)
+ ,.M00_AXI_ARBURST ()
+ ,.M00_AXI_ARLOCK ()
+ ,.M00_AXI_ARCACHE ()
+ ,.M00_AXI_ARPROT ()
+ ,.M00_AXI_ARQOS ()
+ ,.M00_AXI_ARVALID (cl_sh_ddr_q.arvalid)
+ ,.M00_AXI_ARREADY (cl_sh_ddr_q.arready)
+ ,.M00_AXI_RID (cl_sh_ddr_q.rid[11:0])
+ ,.M00_AXI_RDATA (cl_sh_ddr_q.rdata)
+ ,.M00_AXI_RRESP (cl_sh_ddr_q.rresp)
+ ,.M00_AXI_RLAST (cl_sh_ddr_q.rlast)
+ ,.M00_AXI_RVALID (cl_sh_ddr_q.rvalid)
+ ,.M00_AXI_RREADY (cl_sh_ddr_q.rready));
+
+assign cl_sh_ddr_q.arid[15:12] = 4'b0;
+assign cl_sh_ddr_q.awid[15:12] = 4'b0;
+
+//----------------------------
+// flop the output of interconnect for DDRC
+//----------------------------
+ axi_register_slice DDR_C_TST_AXI4_REG_SLC (
+ .aclk (aclk),
+ .aresetn (slr1_sync_aresetn),
+
+ .s_axi_awid (cl_sh_ddr_q.awid),
+ .s_axi_awaddr ({cl_sh_ddr_q.awaddr[63:36], 2'b0, cl_sh_ddr_q.awaddr[33:0]}),
+ .s_axi_awlen (cl_sh_ddr_q.awlen),
+ .s_axi_awsize (cl_sh_ddr_q.awsize),
+ .s_axi_awvalid (cl_sh_ddr_q.awvalid),
+ .s_axi_awready (cl_sh_ddr_q.awready),
+ .s_axi_wdata (cl_sh_ddr_q.wdata),
+ .s_axi_wstrb (cl_sh_ddr_q.wstrb),
+ .s_axi_wlast (cl_sh_ddr_q.wlast),
+ .s_axi_wvalid (cl_sh_ddr_q.wvalid),
+ .s_axi_wready (cl_sh_ddr_q.wready),
+ .s_axi_bid (cl_sh_ddr_q.bid),
+ .s_axi_bresp (cl_sh_ddr_q.bresp),
+ .s_axi_bvalid (cl_sh_ddr_q.bvalid),
+ .s_axi_bready (cl_sh_ddr_q.bready),
+ .s_axi_arid (cl_sh_ddr_q.arid),
+ .s_axi_araddr ({cl_sh_ddr_q.araddr[63:36], 2'b0, cl_sh_ddr_q.araddr[33:0]}),
+ .s_axi_arlen (cl_sh_ddr_q.arlen),
+ .s_axi_arsize (cl_sh_ddr_q.arsize),
+ .s_axi_arvalid (cl_sh_ddr_q.arvalid),
+ .s_axi_arready (cl_sh_ddr_q.arready),
+ .s_axi_rid (cl_sh_ddr_q.rid),
+ .s_axi_rdata (cl_sh_ddr_q.rdata),
+ .s_axi_rresp (cl_sh_ddr_q.rresp),
+ .s_axi_rlast (cl_sh_ddr_q.rlast),
+ .s_axi_rvalid (cl_sh_ddr_q.rvalid),
+ .s_axi_rready (cl_sh_ddr_q.rready),
+ .m_axi_awid (cl_sh_ddr_q2.awid),
+ .m_axi_awaddr (cl_sh_ddr_q2.awaddr),
+ .m_axi_awlen (cl_sh_ddr_q2.awlen),
+ .m_axi_awsize (cl_sh_ddr_q2.awsize),
+ .m_axi_awvalid (cl_sh_ddr_q2.awvalid),
+ .m_axi_awready (cl_sh_ddr_q2.awready),
+ .m_axi_wdata (cl_sh_ddr_q2.wdata),
+ .m_axi_wstrb (cl_sh_ddr_q2.wstrb),
+ .m_axi_wlast (cl_sh_ddr_q2.wlast),
+ .m_axi_wvalid (cl_sh_ddr_q2.wvalid),
+ .m_axi_wready (cl_sh_ddr_q2.wready),
+ .m_axi_bid (cl_sh_ddr_q2.bid),
+ .m_axi_bresp (cl_sh_ddr_q2.bresp),
+ .m_axi_bvalid (cl_sh_ddr_q2.bvalid),
+ .m_axi_bready (cl_sh_ddr_q2.bready),
+ .m_axi_arid (cl_sh_ddr_q2.arid),
+ .m_axi_araddr (cl_sh_ddr_q2.araddr),
+ .m_axi_arlen (cl_sh_ddr_q2.arlen),
+ .m_axi_arsize (cl_sh_ddr_q2.arsize),
+ .m_axi_arvalid (cl_sh_ddr_q2.arvalid),
+ .m_axi_arready (cl_sh_ddr_q2.arready),
+ .m_axi_rid (cl_sh_ddr_q2.rid),
+ .m_axi_rdata (cl_sh_ddr_q2.rdata),
+ .m_axi_rresp (cl_sh_ddr_q2.rresp),
+ .m_axi_rlast (cl_sh_ddr_q2.rlast),
+ .m_axi_rvalid (cl_sh_ddr_q2.rvalid),
+ .m_axi_rready (cl_sh_ddr_q2.rready)
+ );
+
+
+//----------------------------
+// flop the output of ATG/Scrubber for DDRC
+//----------------------------
+
+ axi_register_slice DDR_C_TST_AXI4_REG_SLC_1 (
+ .aclk (aclk),
+ .aresetn (slr1_sync_aresetn),
+
+ .s_axi_awid (cl_sh_ddr_q2.awid),
+ .s_axi_awaddr ({cl_sh_ddr_q2.awaddr}),
+ .s_axi_awlen (cl_sh_ddr_q2.awlen),
+ .s_axi_awsize (cl_sh_ddr_q2.awsize),
+ .s_axi_awvalid (cl_sh_ddr_q2.awvalid),
+ .s_axi_awready (cl_sh_ddr_q2.awready),
+ .s_axi_wdata (cl_sh_ddr_q2.wdata),
+ .s_axi_wstrb (cl_sh_ddr_q2.wstrb),
+ .s_axi_wlast (cl_sh_ddr_q2.wlast),
+ .s_axi_wvalid (cl_sh_ddr_q2.wvalid),
+ .s_axi_wready (cl_sh_ddr_q2.wready),
+ .s_axi_bid (cl_sh_ddr_q2.bid),
+ .s_axi_bresp (cl_sh_ddr_q2.bresp),
+ .s_axi_bvalid (cl_sh_ddr_q2.bvalid),
+ .s_axi_bready (cl_sh_ddr_q2.bready),
+ .s_axi_arid (cl_sh_ddr_q2.arid),
+ .s_axi_araddr (cl_sh_ddr_q2.araddr),
+ .s_axi_arlen (cl_sh_ddr_q2.arlen),
+ .s_axi_arsize (cl_sh_ddr_q2.arsize),
+ .s_axi_arvalid (cl_sh_ddr_q2.arvalid),
+ .s_axi_arready (cl_sh_ddr_q2.arready),
+ .s_axi_rid (cl_sh_ddr_q2.rid),
+ .s_axi_rdata (cl_sh_ddr_q2.rdata),
+ .s_axi_rresp (cl_sh_ddr_q2.rresp),
+ .s_axi_rlast (cl_sh_ddr_q2.rlast),
+ .s_axi_rvalid (cl_sh_ddr_q2.rvalid),
+ .s_axi_rready (cl_sh_ddr_q2.rready),
+
+ .m_axi_awid (cl_sh_ddr_bus.awid),
+ .m_axi_awaddr (cl_sh_ddr_bus.awaddr),
+ .m_axi_awlen (cl_sh_ddr_bus.awlen),
+ .m_axi_awsize (cl_sh_ddr_bus.awsize),
+ .m_axi_awvalid (cl_sh_ddr_bus.awvalid),
+ .m_axi_awready (cl_sh_ddr_bus.awready),
+ .m_axi_wdata (cl_sh_ddr_bus.wdata),
+ .m_axi_wstrb (cl_sh_ddr_bus.wstrb),
+ .m_axi_wlast (cl_sh_ddr_bus.wlast),
+ .m_axi_wvalid (cl_sh_ddr_bus.wvalid),
+ .m_axi_wready (cl_sh_ddr_bus.wready),
+ .m_axi_bid (cl_sh_ddr_bus.bid),
+ .m_axi_bresp (cl_sh_ddr_bus.bresp),
+ .m_axi_bvalid (cl_sh_ddr_bus.bvalid),
+ .m_axi_bready (cl_sh_ddr_bus.bready),
+ .m_axi_arid (cl_sh_ddr_bus.arid),
+ .m_axi_araddr (cl_sh_ddr_bus.araddr),
+ .m_axi_arlen (cl_sh_ddr_bus.arlen),
+ .m_axi_arsize (cl_sh_ddr_bus.arsize),
+ .m_axi_arvalid (cl_sh_ddr_bus.arvalid),
+ .m_axi_arready (cl_sh_ddr_bus.arready),
+ .m_axi_rid (cl_sh_ddr_bus.rid),
+ .m_axi_rdata (cl_sh_ddr_bus.rdata),
+ .m_axi_rresp (cl_sh_ddr_bus.rresp),
+ .m_axi_rlast (cl_sh_ddr_bus.rlast),
+ .m_axi_rvalid (cl_sh_ddr_bus.rvalid),
+ .m_axi_rready (cl_sh_ddr_bus.rready)
+ );
+
+endmodule
+
diff --git a/cl_nvdla/design/cl_id_defines.vh b/cl_nvdla/design/cl_id_defines.vh
new file mode 100644
index 0000000..d957c70
--- /dev/null
+++ b/cl_nvdla/design/cl_id_defines.vh
@@ -0,0 +1,33 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// CL_SH_ID0
+// - PCIe Vendor/Device ID Values
+// 31:16: PCIe Device ID
+// 15: 0: PCIe Vendor ID
+// - A Vendor ID value of 0x8086 is not valid.
+// - If using a Vendor ID value of 0x1D0F (Amazon) then valid
+// values for Device ID's are in the range of 0xF000 - 0xF0FF.
+// - A Vendor/Device ID of 0 (zero) is not valid.
+`define CL_SH_ID0 32'hF001_1D0F
+
+// CL_SH_ID1
+// - PCIe Subsystem/Subsystem Vendor ID Values
+// 31:16: PCIe Subsystem ID
+// 15: 0: PCIe Subsystem Vendor ID
+// - A PCIe Subsystem/Subsystem Vendor ID of 0 (zero) is not valid
+`define CL_SH_ID1 32'h1D51_FEDC
+
+
diff --git a/cl_nvdla/design/cl_ila.sv b/cl_nvdla/design/cl_ila.sv
new file mode 100644
index 0000000..df0a565
--- /dev/null
+++ b/cl_nvdla/design/cl_ila.sv
@@ -0,0 +1,161 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+module cl_ila (
+
+ input aclk,
+
+ input drck,
+ input shift,
+ input tdi,
+ input update,
+ input sel,
+ output logic tdo,
+ input tms,
+ input tck,
+ input runtest,
+ input reset,
+ input capture,
+ input bscanid_en,
+
+ axi_bus_t sh_cl_dma_pcis_q,
+ axi_bus_t cl_sh_ddr_bus
+
+);
+
+//----------------------------
+// Debug bridge
+//----------------------------
+ cl_debug_bridge CL_DEBUG_BRIDGE (
+ .clk(aclk),
+ .S_BSCAN_drck(drck),
+ .S_BSCAN_shift(shift),
+ .S_BSCAN_tdi(tdi),
+ .S_BSCAN_update(update),
+ .S_BSCAN_sel(sel),
+ .S_BSCAN_tdo(tdo),
+ .S_BSCAN_tms(tms),
+ .S_BSCAN_tck(tck),
+ .S_BSCAN_runtest(runtest),
+ .S_BSCAN_reset(reset),
+ .S_BSCAN_capture(capture),
+ .S_BSCAN_bscanid_en(bscanid_en)
+ );
+
+
+//----------------------------
+// Debug Core ILA for dmm pcis AXI4 interface
+//----------------------------
+ ila_1 CL_DMA_ILA_0 (
+ .clk (aclk),
+ .probe0 (sh_cl_dma_pcis_q.awvalid),
+ .probe1 (sh_cl_dma_pcis_q.awaddr),
+ .probe2 (2'b0),
+ .probe3 (sh_cl_dma_pcis_q.awready),
+ .probe4 (sh_cl_dma_pcis_q.wvalid),
+ .probe5 (sh_cl_dma_pcis_q.wstrb),
+ .probe6 (sh_cl_dma_pcis_q.wlast),
+ .probe7 (sh_cl_dma_pcis_q.wready),
+ .probe8 (1'b0),
+ .probe9 (1'b0),
+ .probe10 (sh_cl_dma_pcis_q.wdata),
+ .probe11 (1'b0),
+ .probe12 (sh_cl_dma_pcis_q.arready),
+ .probe13 (2'b0),
+ .probe14 (sh_cl_dma_pcis_q.rdata),
+ .probe15 (sh_cl_dma_pcis_q.araddr),
+ .probe16 (sh_cl_dma_pcis_q.arvalid),
+ .probe17 (3'b0),
+ .probe18 (3'b0),
+ .probe19 (sh_cl_dma_pcis_q.awid),
+ .probe20 (sh_cl_dma_pcis_q.arid),
+ .probe21 (sh_cl_dma_pcis_q.awlen),
+ .probe22 (sh_cl_dma_pcis_q.rlast),
+ .probe23 (3'b0),
+ .probe24 (sh_cl_dma_pcis_q.rresp),
+ .probe25 (sh_cl_dma_pcis_q.rid),
+ .probe26 (sh_cl_dma_pcis_q.rvalid),
+ .probe27 (sh_cl_dma_pcis_q.arlen),
+ .probe28 (3'b0),
+ .probe29 (sh_cl_dma_pcis_q.bresp),
+ .probe30 (sh_cl_dma_pcis_q.rready),
+ .probe31 (4'b0),
+ .probe32 (4'b0),
+ .probe33 (4'b0),
+ .probe34 (4'b0),
+ .probe35 (sh_cl_dma_pcis_q.bvalid),
+ .probe36 (4'b0),
+ .probe37 (4'b0),
+ .probe38 (sh_cl_dma_pcis_q.bid),
+ .probe39 (sh_cl_dma_pcis_q.bready),
+ .probe40 (1'b0),
+ .probe41 (1'b0),
+ .probe42 (1'b0),
+ .probe43 (1'b0)
+ );
+//----------------------------
+// Debug Core ILA for DDRA AXI4 interface monitoring
+//----------------------------
+ ila_1 CL_DDRA_ILA_0 (
+ .clk (aclk),
+ .probe0 (cl_sh_ddr_bus.awvalid),
+ .probe1 (cl_sh_ddr_bus.awaddr),
+ .probe2 (2'b0),
+ .probe3 (cl_sh_ddr_bus.awready),
+ .probe4 (cl_sh_ddr_bus.wvalid),
+ .probe5 (cl_sh_ddr_bus.wstrb),
+ .probe6 (cl_sh_ddr_bus.wlast),
+ .probe7 (cl_sh_ddr_bus.wready),
+ .probe8 (1'b0),
+ .probe9 (1'b0),
+ .probe10 (cl_sh_ddr_bus.wdata),
+ .probe11 (1'b0),
+ .probe12 (cl_sh_ddr_bus.arready),
+ .probe13 (2'b0),
+ .probe14 (cl_sh_ddr_bus.rdata),
+ .probe15 (cl_sh_ddr_bus.araddr),
+ .probe16 (cl_sh_ddr_bus.arvalid),
+ .probe17 (3'b0),
+ .probe18 (3'b0),
+ .probe19 (cl_sh_ddr_bus.awid[4:0]),
+ .probe20 (cl_sh_ddr_bus.arid[4:0]),
+ .probe21 (cl_sh_ddr_bus.awlen),
+ .probe22 (cl_sh_ddr_bus.rlast),
+ .probe23 (3'b0),
+ .probe24 (cl_sh_ddr_bus.rresp),
+ .probe25 (cl_sh_ddr_bus.rid[4:0]),
+ .probe26 (cl_sh_ddr_bus.rvalid),
+ .probe27 (cl_sh_ddr_bus.arlen),
+ .probe28 (3'b0),
+ .probe29 (cl_sh_ddr_bus.bresp),
+ .probe30 (cl_sh_ddr_bus.rready),
+ .probe31 (4'b0),
+ .probe32 (4'b0),
+ .probe33 (4'b0),
+ .probe34 (4'b0),
+ .probe35 (cl_sh_ddr_bus.bvalid),
+ .probe36 (4'b0),
+ .probe37 (4'b0),
+ .probe38 (cl_sh_ddr_bus.bid[4:0]),
+ .probe39 (cl_sh_ddr_bus.bready),
+ .probe40 (1'b0),
+ .probe41 (1'b0),
+ .probe42 (1'b0),
+ .probe43 (1'b0)
+ );
+
+
+endmodule
+
diff --git a/cl_nvdla/design/cl_nvdla.sv b/cl_nvdla/design/cl_nvdla.sv
new file mode 100644
index 0000000..baa2906
--- /dev/null
+++ b/cl_nvdla/design/cl_nvdla.sv
@@ -0,0 +1,448 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+module cl_nvdla #(parameter NUM_DDR=4)
+
+(
+ `include "cl_ports.vh"
+
+);
+
+//`include "cl_common_defines.vh" // CL Defines for all examples
+`include "cl_id_defines.vh" // Defines for ID0 and ID1 (PCI ID's)
+`include "cl_nvdla_defines.vh"
+
+// TIE OFF ALL UNUSED INTERFACES
+// Including all the unused interface to tie off
+// This list is put in the top of the fie to remind
+// developers to remve the specific interfaces
+// that the CL will use
+
+`include "unused_ddr_a_b_d_template.inc"
+`include "unused_pcim_template.inc"
+`include "unused_cl_sda_template.inc"
+
+// Define the addition pipeline stag
+// needed to close timing for the various
+// place where ATG (Automatic Test Generator)
+// is defined
+
+ localparam NUM_CFG_STGS_CL_DDR_ATG = 8;
+ localparam NUM_CFG_STGS_SH_DDR_ATG = 4;
+ localparam NUM_CFG_STGS_PCIE_ATG = 4;
+
+// To reduce RTL simulation time, only 8KiB of
+// each external DRAM is scrubbed in simulations
+
+`ifdef SIM
+ localparam DDR_SCRB_MAX_ADDR = 64'h1FFF;
+`else
+ localparam DDR_SCRB_MAX_ADDR = 64'h3FFFFFFFF; //16GB
+`endif
+ localparam DDR_SCRB_BURST_LEN_MINUS1 = 15;
+
+`ifdef NO_CL_TST_SCRUBBER
+ localparam NO_SCRB_INST = 1;
+`else
+ localparam NO_SCRB_INST = 0;
+`endif
+
+//----------------------------
+// Internal signals
+//----------------------------
+axi_bus_t sh_cl_dma_pcis_bus();
+axi_bus_t sh_cl_dma_pcis_q();
+// keep below nvdla_axi_0/1 i/f same as nvdla configuration. Note: nvdla, axi_data_width=512,axi_len_width=4
+`ifdef NVDLA_CVSRAM_PRESENT
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(512), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(64), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_dbb_axi_bus();
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(512), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(64), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_cvsram_axi_bus();
+`else
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(64), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(64), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_dbb_axi_bus();
+`endif
+
+axi_bus_t cl_sh_ddr_bus();
+`ifdef SIM_BACKDOOR_MEM
+axi_bus_t cl_sh_ddr_bus_sim();
+`endif
+
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(32), .AWS_FPGA_AXI_BUS_ID_WIDTH(1), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(32), .AWS_FPGA_AXI_BUS_LEN_WIDTH(1)) sh_ocl_bus();
+
+axi_bus_t sh_bar1_bus();
+
+cfg_bus_t int_tst_cfg_bus();
+
+logic clk;
+(* dont_touch = "true" *) logic pipe_rst_n;
+logic pre_sync_rst_n;
+(* dont_touch = "true" *) logic sync_rst_n;
+logic sh_cl_flr_assert_q;
+
+//----------------------------
+// End Internal signals
+//----------------------------
+
+assign clk = clk_main_a0;
+
+//reset synchronizer
+lib_pipe #(.WIDTH(1), .STAGES(4)) PIPE_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(rst_main_n), .out_bus(pipe_rst_n));
+
+always_ff @(negedge pipe_rst_n or posedge clk)
+ if (!pipe_rst_n)
+ begin
+ pre_sync_rst_n <= 0;
+ sync_rst_n <= 0;
+ end
+ else
+ begin
+ pre_sync_rst_n <= 1;
+ sync_rst_n <= pre_sync_rst_n;
+ end
+
+//FLR response
+always_ff @(negedge sync_rst_n or posedge clk)
+ if (!sync_rst_n)
+ begin
+ sh_cl_flr_assert_q <= 0;
+ cl_sh_flr_done <= 0;
+ end
+ else
+ begin
+ sh_cl_flr_assert_q <= sh_cl_flr_assert;
+ cl_sh_flr_done <= sh_cl_flr_assert_q && !cl_sh_flr_done;
+ end
+
+//-------------------------------------------
+// Tie-Off Global Signals
+//-------------------------------------------
+`ifndef CL_VERSION
+ `define CL_VERSION 32'hee_ee_ee_00
+`endif
+
+
+ assign cl_sh_status0[31:0] = 32'h0000_0FF0;
+ assign cl_sh_status1[31:0] = `CL_VERSION;
+
+//-------------------------------------------------
+// ID Values
+//-------------------------------------------------
+ assign cl_sh_id0[31:0] = `CL_SH_ID0;
+ assign cl_sh_id1[31:0] = `CL_SH_ID1;
+
+
+///////////////////////////////////////////////////////////////////////
+///////////////// DMA PCIS SLAVE module ///////////////////////////////
+///////////////////////////////////////////////////////////////////////
+
+assign sh_cl_dma_pcis_bus.awvalid = sh_cl_dma_pcis_awvalid;
+assign sh_cl_dma_pcis_bus.awaddr = sh_cl_dma_pcis_awaddr;
+assign sh_cl_dma_pcis_bus.awid[5:0] = sh_cl_dma_pcis_awid;
+assign sh_cl_dma_pcis_bus.awlen = sh_cl_dma_pcis_awlen;
+assign sh_cl_dma_pcis_bus.awsize = sh_cl_dma_pcis_awsize;
+assign cl_sh_dma_pcis_awready = sh_cl_dma_pcis_bus.awready;
+assign sh_cl_dma_pcis_bus.wvalid = sh_cl_dma_pcis_wvalid;
+assign sh_cl_dma_pcis_bus.wdata = sh_cl_dma_pcis_wdata;
+assign sh_cl_dma_pcis_bus.wstrb = sh_cl_dma_pcis_wstrb;
+assign sh_cl_dma_pcis_bus.wlast = sh_cl_dma_pcis_wlast;
+assign cl_sh_dma_pcis_wready = sh_cl_dma_pcis_bus.wready;
+assign cl_sh_dma_pcis_bvalid = sh_cl_dma_pcis_bus.bvalid;
+assign cl_sh_dma_pcis_bresp = sh_cl_dma_pcis_bus.bresp;
+assign sh_cl_dma_pcis_bus.bready = sh_cl_dma_pcis_bready;
+assign cl_sh_dma_pcis_bid = sh_cl_dma_pcis_bus.bid[5:0];
+assign sh_cl_dma_pcis_bus.arvalid = sh_cl_dma_pcis_arvalid;
+assign sh_cl_dma_pcis_bus.araddr = sh_cl_dma_pcis_araddr;
+assign sh_cl_dma_pcis_bus.arid[5:0] = sh_cl_dma_pcis_arid;
+assign sh_cl_dma_pcis_bus.arlen = sh_cl_dma_pcis_arlen;
+assign sh_cl_dma_pcis_bus.arsize = sh_cl_dma_pcis_arsize;
+assign cl_sh_dma_pcis_arready = sh_cl_dma_pcis_bus.arready;
+assign cl_sh_dma_pcis_rvalid = sh_cl_dma_pcis_bus.rvalid;
+assign cl_sh_dma_pcis_rid = sh_cl_dma_pcis_bus.rid[5:0];
+assign cl_sh_dma_pcis_rlast = sh_cl_dma_pcis_bus.rlast;
+assign cl_sh_dma_pcis_rresp = sh_cl_dma_pcis_bus.rresp;
+assign cl_sh_dma_pcis_rdata = sh_cl_dma_pcis_bus.rdata;
+assign sh_cl_dma_pcis_bus.rready = sh_cl_dma_pcis_rready;
+
+assign cl_sh_ddr_awid = cl_sh_ddr_bus.awid;
+assign cl_sh_ddr_awaddr = cl_sh_ddr_bus.awaddr;
+assign cl_sh_ddr_awlen = cl_sh_ddr_bus.awlen;
+assign cl_sh_ddr_awsize = cl_sh_ddr_bus.awsize;
+assign cl_sh_ddr_awvalid = cl_sh_ddr_bus.awvalid;
+assign cl_sh_ddr_bus.awready = sh_cl_ddr_awready;
+assign cl_sh_ddr_wid = 16'b0;
+assign cl_sh_ddr_wdata = cl_sh_ddr_bus.wdata;
+assign cl_sh_ddr_wstrb = cl_sh_ddr_bus.wstrb;
+assign cl_sh_ddr_wlast = cl_sh_ddr_bus.wlast;
+assign cl_sh_ddr_wvalid = cl_sh_ddr_bus.wvalid;
+assign cl_sh_ddr_bus.wready = sh_cl_ddr_wready;
+assign cl_sh_ddr_bus.bid = sh_cl_ddr_bid;
+assign cl_sh_ddr_bus.bresp = sh_cl_ddr_bresp;
+assign cl_sh_ddr_bus.bvalid = sh_cl_ddr_bvalid;
+assign cl_sh_ddr_bready = cl_sh_ddr_bus.bready;
+assign cl_sh_ddr_arid = cl_sh_ddr_bus.arid;
+assign cl_sh_ddr_araddr = cl_sh_ddr_bus.araddr;
+assign cl_sh_ddr_arlen = cl_sh_ddr_bus.arlen;
+assign cl_sh_ddr_arsize = cl_sh_ddr_bus.arsize;
+assign cl_sh_ddr_arvalid = cl_sh_ddr_bus.arvalid;
+assign cl_sh_ddr_bus.arready = sh_cl_ddr_arready;
+assign cl_sh_ddr_bus.rid = sh_cl_ddr_rid;
+assign cl_sh_ddr_bus.rresp = sh_cl_ddr_rresp;
+assign cl_sh_ddr_bus.rvalid = sh_cl_ddr_rvalid;
+assign cl_sh_ddr_bus.rdata = sh_cl_ddr_rdata;
+assign cl_sh_ddr_bus.rlast = sh_cl_ddr_rlast;
+assign cl_sh_ddr_rready = cl_sh_ddr_bus.rready;
+
+(* dont_touch = "true" *) logic dma_pcis_slv_sync_rst_n;
+lib_pipe #(.WIDTH(1), .STAGES(4)) DMA_PCIS_SLV_SLC_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(sync_rst_n), .out_bus(dma_pcis_slv_sync_rst_n));
+cl_dma_pcis_slv #(.SCRB_BURST_LEN_MINUS1(DDR_SCRB_BURST_LEN_MINUS1),
+ .SCRB_MAX_ADDR(DDR_SCRB_MAX_ADDR),
+ .NO_SCRB_INST(NO_SCRB_INST)) CL_DMA_PCIS_SLV (
+ .aclk(clk),
+ .aresetn(dma_pcis_slv_sync_rst_n),
+
+ .sh_cl_dma_pcis_bus(sh_cl_dma_pcis_bus),
+ .nvdla_dbb_axi_bus(nvdla_dbb_axi_bus),
+`ifdef NVDLA_CVSRAM_PRESENT
+ .nvdla_cvsram_axi_bus(nvdla_cvsram_axi_bus),
+`endif
+
+ .sh_cl_dma_pcis_q(sh_cl_dma_pcis_q),
+
+`ifdef SIM_BACKDOOR_MEM
+ .cl_sh_ddr_bus (cl_sh_ddr_bus_sim)
+`else
+ .cl_sh_ddr_bus (cl_sh_ddr_bus)
+`endif
+ );
+
+`ifdef SIM_BACKDOOR_MEM
+cl_sim_mem_wrap CL_SIM_MEM_WRAP (
+ .aclk(clk),
+ .aresetn(dma_pcis_slv_sync_rst_n),
+ .mem_bus_in(cl_sh_ddr_bus_sim),
+ .mem_bus_out(cl_sh_ddr_bus)
+);
+`endif
+
+///////////////////////////////////////////////////////////////////////
+///////////////// DMA PCIS SLAVE module ///////////////////////////////
+///////////////////////////////////////////////////////////////////////
+
+
+///////////////////////////////////////////////////////////////////////
+///////////////// OCL SLAVE module ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////
+
+assign sh_ocl_bus.awvalid = sh_ocl_awvalid;
+assign sh_ocl_bus.awaddr[31:0] = sh_ocl_awaddr;
+assign ocl_sh_awready = sh_ocl_bus.awready;
+assign sh_ocl_bus.wvalid = sh_ocl_wvalid;
+assign sh_ocl_bus.wdata[31:0] = sh_ocl_wdata;
+assign sh_ocl_bus.wstrb[3:0] = sh_ocl_wstrb;
+assign ocl_sh_wready = sh_ocl_bus.wready;
+assign ocl_sh_bvalid = sh_ocl_bus.bvalid;
+assign ocl_sh_bresp = sh_ocl_bus.bresp;
+assign sh_ocl_bus.bready = sh_ocl_bready;
+assign sh_ocl_bus.arvalid = sh_ocl_arvalid;
+assign sh_ocl_bus.araddr[31:0] = sh_ocl_araddr;
+assign ocl_sh_arready = sh_ocl_bus.arready;
+assign ocl_sh_rvalid = sh_ocl_bus.rvalid;
+assign ocl_sh_rresp = sh_ocl_bus.rresp;
+assign ocl_sh_rdata = sh_ocl_bus.rdata[31:0];
+assign sh_ocl_bus.rready = sh_ocl_rready;
+
+(* dont_touch = "true" *) logic ocl_slv_sync_rst_n;
+lib_pipe #(.WIDTH(1), .STAGES(4)) OCL_SLV_SLC_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(sync_rst_n), .out_bus(ocl_slv_sync_rst_n));
+//cl_ocl_slv CL_OCL_SLV (
+//
+// .clk(clk),
+// .sync_rst_n(ocl_slv_sync_rst_n),
+//
+// .sh_cl_flr_assert_q(sh_cl_flr_assert_q),
+//
+// .sh_ocl_bus (sh_ocl_bus),
+//
+// .int_tst_cfg_bus(int_tst_cfg_bus)
+//
+//);
+
+///////////////////////////////////////////////////////////////////////
+///////////////// OCL SLAVE module ////////////////////////////////////
+///////////////////////////////////////////////////////////////////////
+
+
+//-----------------------------------------
+// Interrrupt example
+//-----------------------------------------
+
+(* dont_touch = "true" *) logic int_slv_sync_rst_n;
+lib_pipe #(.WIDTH(1), .STAGES(4)) INT_SLV_SLC_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(sync_rst_n), .out_bus(int_slv_sync_rst_n));
+
+//-----------------------------------------
+// Interrrupt example
+//-----------------------------------------
+
+//-----------------------------------------
+// BAR1 SLAVE module
+//-----------------------------------------
+
+assign sh_bar1_bus.awvalid = sh_bar1_awvalid;
+assign sh_bar1_bus.awaddr[31:0] = sh_bar1_awaddr;
+assign bar1_sh_awready = sh_bar1_bus.awready;
+assign sh_bar1_bus.wvalid = sh_bar1_wvalid;
+assign sh_bar1_bus.wdata[31:0] = sh_bar1_wdata;
+assign sh_bar1_bus.wstrb[3:0] = sh_bar1_wstrb;
+assign bar1_sh_wready = sh_bar1_bus.wready;
+assign bar1_sh_bvalid = sh_bar1_bus.bvalid;
+assign bar1_sh_bresp = sh_bar1_bus.bresp;
+assign sh_bar1_bus.bready = sh_bar1_bready;
+assign sh_bar1_bus.arvalid = sh_bar1_arvalid;
+assign sh_bar1_bus.araddr[31:0] = sh_bar1_araddr;
+assign bar1_sh_arready = sh_bar1_bus.arready;
+assign bar1_sh_rvalid = sh_bar1_bus.rvalid;
+assign bar1_sh_rresp = sh_bar1_bus.rresp;
+assign bar1_sh_rdata = sh_bar1_bus.rdata[31:0];
+assign sh_bar1_bus.rready = sh_bar1_rready;
+
+(* dont_touch = "true" *) logic bar1_slv_sync_rst_n;
+lib_pipe #(.WIDTH(1), .STAGES(4)) BAR1_SLV_SLC_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(sync_rst_n), .out_bus(bar1_slv_sync_rst_n));
+
+//-----------------------------------------
+// BAR1 SLAVE module
+//-----------------------------------------
+
+//-----------------------------------------
+// Virtual JTAG ILA Debug core example
+//-----------------------------------------
+
+
+`ifndef DISABLE_VJTAG_DEBUG
+
+cl_ila CL_ILA (
+
+ .aclk(clk),
+
+ .drck(drck),
+ .shift(shift),
+ .tdi(tdi),
+ .update(update),
+ .sel(sel),
+ .tdo(tdo),
+ .tms(tms),
+ .tck(tck),
+ .runtest(runtest),
+ .reset(reset),
+ .capture(capture),
+ .bscanid_en(bscanid_en),
+
+ .sh_cl_dma_pcis_q(sh_cl_dma_pcis_q),
+ .cl_sh_ddr_bus(cl_sh_ddr_bus)
+
+);
+
+cl_vio CL_VIO (
+
+ .clk_extra_a1(clk_extra_a1)
+
+);
+
+
+`endif // `ifndef DISABLE_VJTAG_DEBUG
+
+//-----------------------------------------
+// Virtual JATG ILA Debug core example
+//-----------------------------------------
+
+//-----------------------------------------
+// NVDLA DUT
+//-----------------------------------------
+wire nvdla_rst_n; // using cfgreg module to control nvdla_rst to avoid regression test hang, added by allan
+wire nvdla_intr;
+wire [63:0] base_addr0;
+wire [63:0] base_addr1;
+
+wire nvdla_rst;
+
+assign nvdla_rst = ~nvdla_rst_n;
+
+cl_nvdla_wrap CL_nvdla_WRAP (
+ .clk(clk),
+ .rstn(nvdla_rst & rst_main_n),
+
+ .dla_intr(nvdla_intr),
+ .base_addr0(base_addr0[63:0]),
+`ifdef NVDLA_CVSRAM_PRESENT
+ .base_addr1(base_addr1[63:0]),
+`endif
+
+ .cl_dut_axi_0(nvdla_dbb_axi_bus),
+`ifdef NVDLA_CVSRAM_PRESENT
+ .cl_dut_axi_1(nvdla_cvsram_axi_bus),
+`endif
+
+ .cl_dut_axi_cfg(sh_ocl_bus)
+);
+
+//-----------------------------------------
+// NVDLA DUT
+//-----------------------------------------
+
+
+
+//-----------------------------------------
+// misc_control ( bit0 : reset ; )
+//-----------------------------------------
+wire [15:0] misc_control;
+
+//-----------------------------------------
+// interrupt upstream
+//-----------------------------------------
+wire [15:0] irq_status;
+wire [15:0] irq_pop;
+
+cl_irq_up CL_IRQ_UP(
+ .clk (clk),
+ .reset_ (int_slv_sync_rst_n),
+ .irq ({15'b0, nvdla_intr}),
+ .irq_status (irq_status[15:0]),
+ .irq_pop (irq_pop[15:0]),
+ .irq_req (cl_sh_apppf_irq_req[15:0]),
+ .irq_ack (sh_cl_apppf_irq_ack[15:0])
+);
+
+
+//-----------------------------------------
+// interrupt upstream
+//-----------------------------------------
+
+//-----------------------------------------
+//custom configure registers
+//-----------------------------------------
+
+cl_cfgreg CL_CFGREG (
+ .clk(clk),
+ .rstn(bar1_slv_sync_rst_n),
+ .irq_status(irq_status[15:0]),
+ .irq_pop(irq_pop[15:0]),
+ .base_addr0(base_addr0[63:0]),
+ .base_addr1(base_addr1[63:0]),
+ .misc_control(nvdla_rst_n),
+ .cfg_axi_bus(sh_bar1_bus)
+
+);
+
+
+endmodule
diff --git a/cl_nvdla/design/cl_nvdla_defines.vh b/cl_nvdla/design/cl_nvdla_defines.vh
new file mode 100644
index 0000000..51f7585
--- /dev/null
+++ b/cl_nvdla/design/cl_nvdla_defines.vh
@@ -0,0 +1,42 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+`ifndef CL_NVDLA_DEFINES
+`define CL_NVDLA_DEFINES
+
+//Put module name of the CL design here. This is used to instantiate in top.sv
+`define CL_NAME cl_nvdla
+
+//Highly recommeneded. For lib FIFO block, uses less async reset (take advantage of
+// FPGA flop init capability). This will help with routing resources.
+`define FPGA_LESS_RST
+
+`define SH_SDA
+//uncomment below to make SH and CL async
+`define SH_CL_ASYNC
+
+// Uncomment to disable Virtual JTAG
+`define DISABLE_VJTAG_DEBUG
+`define FPGA
+`define SYNTHESIS
+`define DESIGNWARE_NOEXIST
+`define VLIB_BYPASS_POWER_CG
+`define NV_FPGA_UNIT
+`define NV_FPGA_FIFOGEN
+`endif
+
diff --git a/cl_nvdla/design/cl_nvdla_pkg.sv b/cl_nvdla/design/cl_nvdla_pkg.sv
new file mode 100644
index 0000000..4ed98c1
--- /dev/null
+++ b/cl_nvdla/design/cl_nvdla_pkg.sv
@@ -0,0 +1,98 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+`ifndef CL_NVDLA_PKG
+`define CL_NVDLA_PKG
+
+ interface axi_bus_t;
+ parameter AWS_FPGA_AXI_BUS_DATA_WIDTH = 512;
+ parameter AWS_FPGA_AXI_BUS_ID_WIDTH = 16;
+ parameter AWS_FPGA_AXI_BUS_ADDR_WIDTH = 64;
+ parameter AWS_FPGA_AXI_BUS_LEN_WIDTH = 8;
+ logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] awid;
+ logic[AWS_FPGA_AXI_BUS_ADDR_WIDTH-1:0] awaddr;
+ logic[AWS_FPGA_AXI_BUS_LEN_WIDTH-1:0] awlen;
+ logic [2:0] awsize;
+ logic awvalid;
+ logic awready;
+
+ logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] wid;
+ logic[AWS_FPGA_AXI_BUS_DATA_WIDTH-1:0] wdata;
+ logic[AWS_FPGA_AXI_BUS_DATA_WIDTH/8-1:0] wstrb;
+ logic wlast;
+ logic wvalid;
+ logic wready;
+
+ logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] bid;
+ logic[1:0] bresp;
+ logic bvalid;
+ logic bready;
+
+ logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] arid;
+ logic[AWS_FPGA_AXI_BUS_ADDR_WIDTH-1:0] araddr;
+ logic[AWS_FPGA_AXI_BUS_LEN_WIDTH-1:0] arlen;
+ logic [2:0] arsize;
+ logic arvalid;
+ logic arready;
+
+ logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] rid;
+ logic[AWS_FPGA_AXI_BUS_DATA_WIDTH-1:0] rdata;
+ logic[1:0] rresp;
+ logic rlast;
+ logic rvalid;
+ logic rready;
+
+ modport master (input awid, awaddr, awlen, awsize, awvalid, output awready,
+ input wid, wdata, wstrb, wlast, wvalid, output wready,
+ output bid, bresp, bvalid, input bready,
+ input arid, araddr, arlen, arsize, arvalid, output arready,
+ output rid, rdata, rresp, rlast, rvalid, input rready);
+
+ modport slave (output awid, awaddr, awlen, awsize, awvalid, input awready,
+ output wid, wdata, wstrb, wlast, wvalid, input wready,
+ input bid, bresp, bvalid, output bready,
+ output arid, araddr, arlen, arsize, arvalid, input arready,
+ input rid, rdata, rresp, rlast, rvalid, output rready);
+ endinterface
+
+
+ interface cfg_bus_t;
+ logic [31:0] addr;
+ logic [31:0] wdata;
+ logic wr;
+ logic rd;
+ logic ack;
+ logic[31:0] rdata;
+
+ modport master (input addr, wdata, wr, rd, output ack, rdata);
+
+ modport slave (output addr, wdata, wr, rd, input ack, rdata);
+ endinterface
+
+ interface scrb_bus_t;
+ logic [63:0] addr;
+ logic [2:0] state;
+ logic enable;
+ logic done;
+
+ modport master (input enable, output addr, state, done);
+
+ modport slave (output enable, input addr, state, done);
+ endinterface
+
+`endif //CL_NVDLA_PKG
diff --git a/cl_nvdla/design/cl_nvdla_wrap.sv b/cl_nvdla/design/cl_nvdla_wrap.sv
new file mode 100644
index 0000000..4f55129
--- /dev/null
+++ b/cl_nvdla/design/cl_nvdla_wrap.sv
@@ -0,0 +1,203 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: cl_nvdla_wrap.sv
+
+module cl_nvdla_wrap
+(
+ input clk,
+ input rstn,
+
+ output dla_intr,
+ input [63:0] base_addr0,
+`ifdef NVDLA_CVSRAM_PRESENT
+ input [63:0] base_addr1,
+`endif
+
+ axi_bus_t.slave cl_dut_axi_0,
+`ifdef NVDLA_CVSRAM_PRESENT
+ axi_bus_t.slave cl_dut_axi_1,
+`endif
+
+ axi_bus_t.master cl_dut_axi_cfg
+);
+
+wire [23:0] m_apb_paddr;
+wire m_apb_penable;
+wire m_apb_pns = 1'b0; // FIXME
+wire m_apb_psel;
+wire [12:0] m_apb_puser = 13'b0; // FIXME
+wire [31:0] m_apb_pwdata;
+wire m_apb_pwrite;
+wire [3:0] m_apb_pwstrb = 4'b1111; // FIXME
+wire [31:0] m_apb_prdata;
+wire m_apb_pready;
+wire m_apb_pslverr;
+
+wire m_csb2nvdla_valid;
+wire m_csb2nvdla_ready;
+wire [15:0] m_csb2nvdla_addr;
+wire [31:0] m_csb2nvdla_wdat;
+wire m_csb2nvdla_write;
+wire m_csb2nvdla_nposted;
+wire m_nvdla2csb_valid;
+wire [31:0] m_nvdla2csb_data;
+
+wire [63:0] axi_0_awaddr;
+wire [63:0] axi_1_awaddr;
+wire [63:0] axi_0_araddr;
+wire [63:0] axi_1_araddr;
+
+assign cl_dut_axi_0.awaddr = axi_0_awaddr - base_addr0;
+assign cl_dut_axi_0.araddr = axi_0_araddr - base_addr0;
+`ifdef NVDLA_CVSRAM_PRESENT
+assign cl_dut_axi_1.awaddr = axi_1_awaddr - base_addr1;
+assign cl_dut_axi_1.araddr = axi_1_araddr - base_addr1;
+`endif
+
+axi_apb_bridge_0 axi2apb (
+ .s_axi_aclk (clk)
+ ,.s_axi_aresetn (rstn)
+ ,.s_axi_awaddr (cl_dut_axi_cfg.awaddr[31:0])
+ ,.s_axi_awvalid (cl_dut_axi_cfg.awvalid)
+ ,.s_axi_awready (cl_dut_axi_cfg.awready)
+ ,.s_axi_wdata (cl_dut_axi_cfg.wdata[31:0])
+ ,.s_axi_wvalid (cl_dut_axi_cfg.wvalid)
+ ,.s_axi_wready (cl_dut_axi_cfg.wready)
+ ,.s_axi_bresp (cl_dut_axi_cfg.bresp)
+ ,.s_axi_bvalid (cl_dut_axi_cfg.bvalid)
+ ,.s_axi_bready (cl_dut_axi_cfg.bready)
+ ,.s_axi_araddr (cl_dut_axi_cfg.araddr)
+ ,.s_axi_arvalid (cl_dut_axi_cfg.arvalid)
+ ,.s_axi_arready (cl_dut_axi_cfg.arready)
+ ,.s_axi_rdata (cl_dut_axi_cfg.rdata)
+ ,.s_axi_rresp (cl_dut_axi_cfg.rresp)
+ ,.s_axi_rvalid (cl_dut_axi_cfg.rvalid)
+ ,.s_axi_rready (cl_dut_axi_cfg.rready)
+ ,.m_apb_paddr (m_apb_paddr)
+ ,.m_apb_psel (m_apb_psel)
+ ,.m_apb_penable (m_apb_penable)
+ ,.m_apb_pwrite (m_apb_pwrite)
+ ,.m_apb_pwdata (m_apb_pwdata)
+ ,.m_apb_pready (m_apb_pready)
+ ,.m_apb_prdata (m_apb_prdata)
+ ,.m_apb_pslverr (m_apb_pslverr)
+);
+assign m_apb_pslverr = 1'b0;
+
+
+NV_NVDLA_apb2csb apb2csb (
+ .pclk (clk)
+ ,.prstn (rstn)
+ ,.csb2nvdla_ready (m_csb2nvdla_ready)
+ ,.nvdla2csb_data (m_nvdla2csb_data)
+ ,.nvdla2csb_valid (m_nvdla2csb_valid)
+ ,.paddr (m_apb_paddr)
+ ,.penable (m_apb_penable)
+ ,.psel (m_apb_psel)
+ ,.pwdata (m_apb_pwdata)
+ ,.pwrite (m_apb_pwrite)
+ ,.csb2nvdla_addr (m_csb2nvdla_addr)
+ ,.csb2nvdla_nposted (m_csb2nvdla_nposted)
+ ,.csb2nvdla_valid (m_csb2nvdla_valid)
+ ,.csb2nvdla_wdat (m_csb2nvdla_wdat)
+ ,.csb2nvdla_write (m_csb2nvdla_write)
+ ,.prdata (m_apb_prdata)
+ ,.pready (m_apb_pready)
+);
+
+
+NV_nvdla nvdla_top (
+ .dla_core_clk (clk)
+ ,.dla_csb_clk (clk)
+ ,.global_clk_ovr_on (1'b0)
+ ,.tmc2slcg_disable_clock_gating (1'b0)
+ ,.dla_reset_rstn (rstn)
+ ,.direct_reset_ (rstn)
+ ,.test_mode (1'b0)
+ ,.csb2nvdla_valid (m_csb2nvdla_valid)
+ ,.csb2nvdla_ready (m_csb2nvdla_ready)
+ ,.csb2nvdla_addr (m_csb2nvdla_addr)
+ ,.csb2nvdla_wdat (m_csb2nvdla_wdat)
+ ,.csb2nvdla_write (m_csb2nvdla_write)
+ ,.csb2nvdla_nposted (m_csb2nvdla_nposted)
+ ,.nvdla2csb_valid (m_nvdla2csb_valid)
+ ,.nvdla2csb_data (m_nvdla2csb_data)
+ ,.nvdla2csb_wr_complete () //FIXME: no such port in apb2csb
+ ,.nvdla_core2dbb_aw_awvalid (cl_dut_axi_0.awvalid)
+ ,.nvdla_core2dbb_aw_awready (cl_dut_axi_0.awready)
+ ,.nvdla_core2dbb_aw_awaddr (axi_0_awaddr)
+ ,.nvdla_core2dbb_aw_awid (cl_dut_axi_0.awid)
+ ,.nvdla_core2dbb_aw_awlen (cl_dut_axi_0.awlen)
+ ,.nvdla_core2dbb_w_wvalid (cl_dut_axi_0.wvalid)
+ ,.nvdla_core2dbb_w_wready (cl_dut_axi_0.wready)
+ ,.nvdla_core2dbb_w_wdata (cl_dut_axi_0.wdata)
+ ,.nvdla_core2dbb_w_wstrb (cl_dut_axi_0.wstrb)
+ ,.nvdla_core2dbb_w_wlast (cl_dut_axi_0.wlast)
+ ,.nvdla_core2dbb_b_bvalid (cl_dut_axi_0.bvalid)
+ ,.nvdla_core2dbb_b_bready (cl_dut_axi_0.bready)
+ ,.nvdla_core2dbb_b_bid (cl_dut_axi_0.bid)
+ ,.nvdla_core2dbb_ar_arvalid (cl_dut_axi_0.arvalid)
+ ,.nvdla_core2dbb_ar_arready (cl_dut_axi_0.arready)
+ ,.nvdla_core2dbb_ar_araddr (axi_0_araddr)
+ ,.nvdla_core2dbb_ar_arid (cl_dut_axi_0.arid)
+ ,.nvdla_core2dbb_ar_arlen (cl_dut_axi_0.arlen)
+ ,.nvdla_core2dbb_r_rvalid (cl_dut_axi_0.rvalid)
+ ,.nvdla_core2dbb_r_rready (cl_dut_axi_0.rready)
+ ,.nvdla_core2dbb_r_rid (cl_dut_axi_0.rid)
+ ,.nvdla_core2dbb_r_rlast (cl_dut_axi_0.rlast)
+ ,.nvdla_core2dbb_r_rdata (cl_dut_axi_0.rdata)
+`ifdef NVDLA_CVSRAM_PRESENT
+ ,.nvdla_core2cvsram_aw_awvalid (cl_dut_axi_1.awvalid)
+ ,.nvdla_core2cvsram_aw_awready (cl_dut_axi_1.awready)
+ ,.nvdla_core2cvsram_aw_awaddr (axi_1_awaddr)
+ ,.nvdla_core2cvsram_aw_awid (cl_dut_axi_1.awid)
+ ,.nvdla_core2cvsram_aw_awlen (cl_dut_axi_1.awlen)
+ ,.nvdla_core2cvsram_w_wvalid (cl_dut_axi_1.wvalid)
+ ,.nvdla_core2cvsram_w_wready (cl_dut_axi_1.wready)
+ ,.nvdla_core2cvsram_w_wdata (cl_dut_axi_1.wdata)
+ ,.nvdla_core2cvsram_w_wstrb (cl_dut_axi_1.wstrb)
+ ,.nvdla_core2cvsram_w_wlast (cl_dut_axi_1.wlast)
+ ,.nvdla_core2cvsram_b_bvalid (cl_dut_axi_1.bvalid)
+ ,.nvdla_core2cvsram_b_bready (cl_dut_axi_1.bready)
+ ,.nvdla_core2cvsram_b_bid (cl_dut_axi_1.bid)
+ ,.nvdla_core2cvsram_ar_arvalid (cl_dut_axi_1.arvalid)
+ ,.nvdla_core2cvsram_ar_arready (cl_dut_axi_1.arready)
+ ,.nvdla_core2cvsram_ar_araddr (axi_1_araddr)
+ ,.nvdla_core2cvsram_ar_arid (cl_dut_axi_1.arid)
+ ,.nvdla_core2cvsram_ar_arlen (cl_dut_axi_1.arlen)
+ ,.nvdla_core2cvsram_r_rvalid (cl_dut_axi_1.rvalid)
+ ,.nvdla_core2cvsram_r_rready (cl_dut_axi_1.rready)
+ ,.nvdla_core2cvsram_r_rid (cl_dut_axi_1.rid)
+ ,.nvdla_core2cvsram_r_rlast (cl_dut_axi_1.rlast)
+ ,.nvdla_core2cvsram_r_rdata (cl_dut_axi_1.rdata)
+`endif
+ ,.dla_intr (dla_intr)
+ ,.nvdla_pwrbus_ram_c_pd (32'b0)
+ ,.nvdla_pwrbus_ram_ma_pd (32'b0)
+ ,.nvdla_pwrbus_ram_mb_pd (32'b0)
+ ,.nvdla_pwrbus_ram_p_pd (32'b0)
+ ,.nvdla_pwrbus_ram_o_pd (32'b0)
+ ,.nvdla_pwrbus_ram_a_pd (32'b0)
+); // nvdla_top
+
+`ifdef NVDLA_CVSRAM_PRESENT
+assign cl_dut_axi_0.awsize = 3'b110;
+assign cl_dut_axi_0.arsize = 3'b110;
+`else
+assign cl_dut_axi_0.awsize = 3'b011;
+assign cl_dut_axi_0.arsize = 3'b011;
+`endif
+
+`ifdef NVDLA_CVSRAM_PRESENT
+assign cl_dut_axi_1.awsize = 3'b110;
+assign cl_dut_axi_1.arsize = 3'b110;
+`endif
+
+
+endmodule
diff --git a/cl_nvdla/design/cl_sim_mem.sv b/cl_nvdla/design/cl_sim_mem.sv
new file mode 100644
index 0000000..0754768
--- /dev/null
+++ b/cl_nvdla/design/cl_sim_mem.sv
@@ -0,0 +1,132 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: cl_sim_mem.sv
+
+module cl_sim_mem (
+ input clk,
+ input rstn,
+input mem_axi_awvalid,
+output mem_axi_awready,
+input [63:0] mem_axi_awaddr,
+
+input mem_axi_wvalid,
+output reg mem_axi_wready,
+input [63:0] mem_axi_wdata,
+input [7:0] mem_axi_wstrb,
+
+output reg mem_axi_bvalid,
+input mem_axi_bready,
+output reg [1:0] mem_axi_bresp,
+
+input mem_axi_arvalid,
+output reg mem_axi_arready,
+input [63:0] mem_axi_araddr,
+
+output reg mem_axi_rvalid,
+input mem_axi_rready,
+output reg [1:0] mem_axi_rresp,
+output reg [63:0] mem_axi_rdata
+);
+
+
+// internal signals
+wire [63:0] mem_axi_awaddr_t;
+reg [63:0] mem_axi_awaddr_reg;
+reg mem_axi_write_pend;
+reg mem_axi_write_pend_reg;
+
+wire [63:0] mem_axi_araddr_t;
+reg [63:0] mem_axi_araddr_reg;
+reg mem_axi_read_pend;
+
+// write channel
+
+assign mem_axi_awaddr_t = (mem_axi_awvalid & mem_axi_awready) ? mem_axi_awaddr : mem_axi_awaddr_reg;
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ mem_axi_awaddr_reg <= 64'b0;
+ else if(mem_axi_awvalid & mem_axi_awready)
+ mem_axi_awaddr_reg <= mem_axi_awaddr;
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ mem_axi_write_pend <= 1'b0;
+ else if(mem_axi_awvalid & mem_axi_awready)
+ mem_axi_write_pend <= 1'b1;
+ else if(mem_axi_bvalid & mem_axi_bready)
+ mem_axi_write_pend <= 1'b0;
+assign mem_axi_awready = !mem_axi_write_pend;
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ mem_axi_write_pend_reg <= 1'b0;
+ else
+ mem_axi_write_pend_reg <= mem_axi_write_pend;
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ mem_axi_wready <= 1'b0;
+ else if(mem_axi_wvalid & mem_axi_wready)
+ mem_axi_wready <= 1'b0;
+ else if(mem_axi_write_pend & !mem_axi_write_pend_reg)
+ mem_axi_wready <= 1'b1;
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ mem_axi_bvalid <= 1'b0;
+ else if(mem_axi_bvalid & mem_axi_bready)
+ mem_axi_bvalid <= 1'b0;
+ else if(mem_axi_wvalid & mem_axi_wready)
+ mem_axi_bvalid <= 1'b1;
+
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn) begin
+ mem_axi_bresp <= 2'b0;
+ end
+ else begin
+ if(mem_axi_wvalid & mem_axi_wready) begin
+ tb.backdoor_mem_write({mem_axi_awaddr_t[63:3],3'b0}, mem_axi_wdata, 8, mem_axi_wstrb);
+ end
+ end
+
+// read channel
+
+assign mem_axi_araddr_t = (mem_axi_arvalid & mem_axi_arready) ? mem_axi_araddr : mem_axi_araddr_reg;
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ mem_axi_araddr_reg <= 32'b0;
+ else if(mem_axi_arvalid & mem_axi_arready)
+ mem_axi_araddr_reg <= mem_axi_araddr;
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ mem_axi_read_pend <= 1'b0;
+ else if(mem_axi_arvalid & mem_axi_arready)
+ mem_axi_read_pend <= 1'b1;
+ else if(mem_axi_rvalid & mem_axi_rready)
+ mem_axi_read_pend <= 1'b0;
+assign mem_axi_arready = !mem_axi_read_pend;
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ mem_axi_rvalid <= 1'b0;
+ else if(mem_axi_rvalid & mem_axi_rready)
+ mem_axi_rvalid <= 1'b0;
+ else if(mem_axi_arvalid & mem_axi_arready)
+ mem_axi_rvalid <= 1'b1;
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ mem_axi_rresp <= 2'b00;
+ else if(mem_axi_arvalid & mem_axi_arready) begin
+ mem_axi_rdata <= tb.backdoor_mem_read({mem_axi_araddr[63:3],3'b0}, 8);
+ end
+
+endmodule
diff --git a/cl_nvdla/design/cl_sim_mem_wrap.sv b/cl_nvdla/design/cl_sim_mem_wrap.sv
new file mode 100644
index 0000000..02918d8
--- /dev/null
+++ b/cl_nvdla/design/cl_sim_mem_wrap.sv
@@ -0,0 +1,352 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+`ifndef SYNTHESIS
+
+module cl_sim_mem_wrap
+(
+ input aclk,
+ input aresetn,
+
+ axi_bus_t.master mem_bus_in,
+ axi_bus_t.slave mem_bus_out
+);
+
+logic[15:0] mem_axi_512_bus_awid;
+logic[63:0] mem_axi_512_bus_awaddr;
+logic[7:0] mem_axi_512_bus_awlen;
+logic [2:0] mem_axi_512_bus_awsize;
+logic mem_axi_512_bus_awvalid;
+logic mem_axi_512_bus_awready;
+
+logic[15:0] mem_axi_512_bus_wid;
+logic[511:0] mem_axi_512_bus_wdata;
+logic[63:0] mem_axi_512_bus_wstrb;
+logic mem_axi_512_bus_wlast;
+logic mem_axi_512_bus_wvalid;
+logic mem_axi_512_bus_wready;
+
+logic[15:0] mem_axi_512_bus_bid;
+logic[1:0] mem_axi_512_bus_bresp;
+logic mem_axi_512_bus_bvalid;
+logic mem_axi_512_bus_bready;
+
+logic[15:0] mem_axi_512_bus_arid;
+logic[63:0] mem_axi_512_bus_araddr;
+logic[7:0] mem_axi_512_bus_arlen;
+logic [2:0] mem_axi_512_bus_arsize;
+logic mem_axi_512_bus_arvalid;
+logic mem_axi_512_bus_arready;
+
+logic[15:0] mem_axi_512_bus_rid;
+logic[511:0] mem_axi_512_bus_rdata;
+logic[1:0] mem_axi_512_bus_rresp;
+logic mem_axi_512_bus_rlast;
+logic mem_axi_512_bus_rvalid;
+logic mem_axi_512_bus_rready;
+
+logic[63:0] mem_axi_64_bus_awaddr;
+logic[7:0] mem_axi_64_bus_awlen;
+logic [2:0] mem_axi_64_bus_awsize;
+logic mem_axi_64_bus_awvalid;
+logic mem_axi_64_bus_awready;
+
+logic[63:0] mem_axi_64_bus_wdata;
+logic[7:0] mem_axi_64_bus_wstrb;
+logic mem_axi_64_bus_wlast;
+logic mem_axi_64_bus_wvalid;
+logic mem_axi_64_bus_wready;
+
+logic[1:0] mem_axi_64_bus_bresp;
+logic mem_axi_64_bus_bvalid;
+logic mem_axi_64_bus_bready;
+
+logic[63:0] mem_axi_64_bus_araddr;
+logic[7:0] mem_axi_64_bus_arlen;
+logic [2:0] mem_axi_64_bus_arsize;
+logic mem_axi_64_bus_arvalid;
+logic mem_axi_64_bus_arready;
+
+logic[63:0] mem_axi_64_bus_rdata;
+logic[1:0] mem_axi_64_bus_rresp;
+logic mem_axi_64_bus_rlast;
+logic mem_axi_64_bus_rvalid;
+logic mem_axi_64_bus_rready;
+
+logic[63:0] mem_axil_64_bus_awaddr;
+logic[7:0] mem_axil_64_bus_awlen;
+logic [2:0] mem_axil_64_bus_awsize;
+logic mem_axil_64_bus_awvalid;
+logic mem_axil_64_bus_awready;
+
+logic[63:0] mem_axil_64_bus_wdata;
+logic[7:0] mem_axil_64_bus_wstrb;
+logic mem_axil_64_bus_wlast;
+logic mem_axil_64_bus_wvalid;
+logic mem_axil_64_bus_wready;
+
+logic[1:0] mem_axil_64_bus_bresp;
+logic mem_axil_64_bus_bvalid;
+logic mem_axil_64_bus_bready;
+
+logic[63:0] mem_axil_64_bus_araddr;
+logic[7:0] mem_axil_64_bus_arlen;
+logic [2:0] mem_axil_64_bus_arsize;
+logic mem_axil_64_bus_arvalid;
+logic mem_axil_64_bus_arready;
+
+logic[63:0] mem_axil_64_bus_rdata;
+logic[1:0] mem_axil_64_bus_rresp;
+logic mem_axil_64_bus_rlast;
+logic mem_axil_64_bus_rvalid;
+logic mem_axil_64_bus_rready;
+
+logic enable_sim_mem;
+initial
+begin
+ if ($test$plusargs("enable_sim_mem"))
+ begin
+ $display("Enable simulation memory!");
+ enable_sim_mem = 1;
+ end
+ else
+ begin
+ $display("Disable simulation memory!");
+ enable_sim_mem = 0;
+ end
+end
+
+assign mem_bus_out.awid = enable_sim_mem ? 0 : mem_bus_in.awid;
+assign mem_bus_out.awaddr = enable_sim_mem ? 0 : mem_bus_in.awaddr;
+assign mem_bus_out.awlen = enable_sim_mem ? 0 : mem_bus_in.awlen;
+assign mem_bus_out.awsize = enable_sim_mem ? 0 : mem_bus_in.awsize;
+assign mem_bus_out.awvalid = enable_sim_mem ? 0 : mem_bus_in.awvalid;
+assign mem_bus_out.wdata = enable_sim_mem ? 0 : mem_bus_in.wdata;
+assign mem_bus_out.wstrb = enable_sim_mem ? 0 : mem_bus_in.wstrb;
+assign mem_bus_out.wlast = enable_sim_mem ? 0 : mem_bus_in.wlast;
+assign mem_bus_out.wvalid = enable_sim_mem ? 0 : mem_bus_in.wvalid;
+assign mem_bus_out.bready = enable_sim_mem ? 0 : mem_bus_in.bready;
+assign mem_bus_out.arid = enable_sim_mem ? 0 : mem_bus_in.arid;
+assign mem_bus_out.araddr = enable_sim_mem ? 0 : mem_bus_in.araddr;
+assign mem_bus_out.arlen = enable_sim_mem ? 0 : mem_bus_in.arlen;
+assign mem_bus_out.arsize = enable_sim_mem ? 0 : mem_bus_in.arsize;
+assign mem_bus_out.arvalid = enable_sim_mem ? 0 : mem_bus_in.arvalid;
+assign mem_bus_out.rready = enable_sim_mem ? 0 : mem_bus_in.rready;
+
+assign mem_axi_512_bus_awid = enable_sim_mem ? mem_bus_in.awid : 0;
+assign mem_axi_512_bus_awaddr = enable_sim_mem ? mem_bus_in.awaddr : 0;
+assign mem_axi_512_bus_awlen = enable_sim_mem ? mem_bus_in.awlen : 0;
+assign mem_axi_512_bus_awsize = enable_sim_mem ? mem_bus_in.awsize : 0;
+assign mem_axi_512_bus_awvalid = enable_sim_mem ? mem_bus_in.awvalid : 0;
+assign mem_axi_512_bus_wdata = enable_sim_mem ? mem_bus_in.wdata : 0;
+assign mem_axi_512_bus_wstrb = enable_sim_mem ? mem_bus_in.wstrb : 0;
+assign mem_axi_512_bus_wlast = enable_sim_mem ? mem_bus_in.wlast : 0;
+assign mem_axi_512_bus_wvalid = enable_sim_mem ? mem_bus_in.wvalid : 0;
+assign mem_axi_512_bus_bready = enable_sim_mem ? mem_bus_in.bready : 0;
+assign mem_axi_512_bus_arid = enable_sim_mem ? mem_bus_in.arid : 0;
+assign mem_axi_512_bus_araddr = enable_sim_mem ? mem_bus_in.araddr : 0;
+assign mem_axi_512_bus_arlen = enable_sim_mem ? mem_bus_in.arlen : 0;
+assign mem_axi_512_bus_arsize = enable_sim_mem ? mem_bus_in.arsize : 0;
+assign mem_axi_512_bus_arvalid = enable_sim_mem ? mem_bus_in.arvalid : 0;
+assign mem_axi_512_bus_rready = enable_sim_mem ? mem_bus_in.rready : 0;
+
+assign mem_bus_in.awready = enable_sim_mem ? mem_axi_512_bus_awready : mem_bus_out.awready;
+assign mem_bus_in.wready = enable_sim_mem ? mem_axi_512_bus_wready : mem_bus_out.wready;
+assign mem_bus_in.bid = enable_sim_mem ? mem_axi_512_bus_bid : mem_bus_out.bid;
+assign mem_bus_in.bresp = enable_sim_mem ? mem_axi_512_bus_bresp : mem_bus_out.bresp;
+assign mem_bus_in.bvalid = enable_sim_mem ? mem_axi_512_bus_bvalid : mem_bus_out.bvalid;
+assign mem_bus_in.arready = enable_sim_mem ? mem_axi_512_bus_arready : mem_bus_out.arready;
+assign mem_bus_in.rid = enable_sim_mem ? mem_axi_512_bus_rid : mem_bus_out.rid;
+assign mem_bus_in.rresp = enable_sim_mem ? mem_axi_512_bus_rresp : mem_bus_out.rresp;
+assign mem_bus_in.rvalid = enable_sim_mem ? mem_axi_512_bus_rvalid : mem_bus_out.rvalid;
+assign mem_bus_in.rdata = enable_sim_mem ? mem_axi_512_bus_rdata : mem_bus_out.rdata;
+assign mem_bus_in.rlast = enable_sim_mem ? mem_axi_512_bus_rlast : mem_bus_out.rlast;
+
+axi_dwidth_converter_512b_to_64b AXI_DWIDTH_CONVERTER_512B_TO_64B (
+ .s_axi_aclk(aclk),
+ .s_axi_aresetn(aresetn),
+ .s_axi_awid(mem_axi_512_bus_awid),
+ .s_axi_awaddr(mem_axi_512_bus_awaddr),
+ .s_axi_awlen(mem_axi_512_bus_awlen),
+ .s_axi_awsize(mem_axi_512_bus_awsize),
+ .s_axi_awburst(2'b01),
+ .s_axi_awlock(1'b0),
+ .s_axi_awcache(4'b11),
+ .s_axi_awprot(3'b010),
+ .s_axi_awregion(4'b0),
+ .s_axi_awqos(4'b0),
+ .s_axi_awvalid(mem_axi_512_bus_awvalid),
+ .s_axi_awready(mem_axi_512_bus_awready),
+ .s_axi_wdata(mem_axi_512_bus_wdata),
+ .s_axi_wstrb(mem_axi_512_bus_wstrb),
+ .s_axi_wlast(mem_axi_512_bus_wlast),
+ .s_axi_wvalid(mem_axi_512_bus_wvalid),
+ .s_axi_wready(mem_axi_512_bus_wready),
+ .s_axi_bid(mem_axi_512_bus_bid),
+ .s_axi_bresp(mem_axi_512_bus_bresp),
+ .s_axi_bvalid(mem_axi_512_bus_bvalid),
+ .s_axi_bready(mem_axi_512_bus_bready),
+ .s_axi_arid(mem_axi_512_bus_arid),
+ .s_axi_araddr(mem_axi_512_bus_araddr),
+ .s_axi_arlen(mem_axi_512_bus_arlen),
+ .s_axi_arsize(mem_axi_512_bus_arsize),
+ .s_axi_arburst(2'b01),
+ .s_axi_arlock(1'b0),
+ .s_axi_arcache(4'b11),
+ .s_axi_arprot(3'b010),
+ .s_axi_arregion(4'b0),
+ .s_axi_arqos(4'b0),
+ .s_axi_arvalid(mem_axi_512_bus_arvalid),
+ .s_axi_arready(mem_axi_512_bus_arready),
+ .s_axi_rid(mem_axi_512_bus_rid),
+ .s_axi_rdata(mem_axi_512_bus_rdata),
+ .s_axi_rresp(mem_axi_512_bus_rresp),
+ .s_axi_rlast(mem_axi_512_bus_rlast),
+ .s_axi_rvalid(mem_axi_512_bus_rvalid),
+ .s_axi_rready(mem_axi_512_bus_rready),
+ .m_axi_awaddr(mem_axi_64_bus_awaddr),
+ .m_axi_awlen(mem_axi_64_bus_awlen),
+ .m_axi_awsize(mem_axi_64_bus_awsize),
+ .m_axi_awburst(),
+ .m_axi_awlock(),
+ .m_axi_awcache(),
+ .m_axi_awprot(),
+ .m_axi_awregion(),
+ .m_axi_awqos(),
+ .m_axi_awvalid(mem_axi_64_bus_awvalid),
+ .m_axi_awready(mem_axi_64_bus_awready),
+ .m_axi_wdata(mem_axi_64_bus_wdata),
+ .m_axi_wstrb(mem_axi_64_bus_wstrb),
+ .m_axi_wlast(mem_axi_64_bus_wlast),
+ .m_axi_wvalid(mem_axi_64_bus_wvalid),
+ .m_axi_wready(mem_axi_64_bus_wready),
+ .m_axi_bresp(mem_axi_64_bus_bresp),
+ .m_axi_bvalid(mem_axi_64_bus_bvalid),
+ .m_axi_bready(mem_axi_64_bus_bready),
+ .m_axi_araddr(mem_axi_64_bus_araddr),
+ .m_axi_arlen(mem_axi_64_bus_arlen),
+ .m_axi_arsize(mem_axi_64_bus_arsize),
+ .m_axi_arburst(),
+ .m_axi_arlock(),
+ .m_axi_arcache(),
+ .m_axi_arprot(),
+ .m_axi_arregion(),
+ .m_axi_arqos(),
+ .m_axi_arvalid(mem_axi_64_bus_arvalid),
+ .m_axi_arready(mem_axi_64_bus_arready),
+ .m_axi_rdata(mem_axi_64_bus_rdata),
+ .m_axi_rresp(mem_axi_64_bus_rresp),
+ .m_axi_rlast(mem_axi_64_bus_rlast),
+ .m_axi_rvalid(mem_axi_64_bus_rvalid),
+ .m_axi_rready(mem_axi_64_bus_rready)
+);
+
+axi_protocol_converter_axi_to_axil AXI_PROTOCOL_CONVERTER_AXI_TO_AXIL (
+ .aclk(aclk),
+ .aresetn(aresetn),
+ .s_axi_awaddr(mem_axi_64_bus_awaddr),
+ .s_axi_awlen(mem_axi_64_bus_awlen),
+ .s_axi_awsize(mem_axi_64_bus_awsize),
+ .s_axi_awburst(2'b01),
+ .s_axi_awlock(1'b0),
+ .s_axi_awcache(4'b11),
+ .s_axi_awprot(3'b010),
+ .s_axi_awregion(4'b0),
+ .s_axi_awqos(4'b0),
+ .s_axi_awvalid(mem_axi_64_bus_awvalid),
+ .s_axi_awready(mem_axi_64_bus_awready),
+ .s_axi_wdata(mem_axi_64_bus_wdata),
+ .s_axi_wstrb(mem_axi_64_bus_wstrb),
+ .s_axi_wlast(mem_axi_64_bus_wlast),
+ .s_axi_wvalid(mem_axi_64_bus_wvalid),
+ .s_axi_wready(mem_axi_64_bus_wready),
+ .s_axi_bresp(mem_axi_64_bus_bresp),
+ .s_axi_bvalid(mem_axi_64_bus_bvalid),
+ .s_axi_bready(mem_axi_64_bus_bready),
+ .s_axi_araddr(mem_axi_64_bus_araddr),
+ .s_axi_arlen(mem_axi_64_bus_arlen),
+ .s_axi_arsize(mem_axi_64_bus_arsize),
+ .s_axi_arburst(2'b01),
+ .s_axi_arlock(1'b0),
+ .s_axi_arcache(4'b11),
+ .s_axi_arprot(3'b010),
+ .s_axi_arregion(4'b0),
+ .s_axi_arqos(4'b0),
+ .s_axi_arvalid(mem_axi_64_bus_arvalid),
+ .s_axi_arready(mem_axi_64_bus_arready),
+ .s_axi_rdata(mem_axi_64_bus_rdata),
+ .s_axi_rresp(mem_axi_64_bus_rresp),
+ .s_axi_rlast(mem_axi_64_bus_rlast),
+ .s_axi_rvalid(mem_axi_64_bus_rvalid),
+ .s_axi_rready(mem_axi_64_bus_rready),
+ .m_axi_awaddr(mem_axil_64_bus_awaddr),
+ .m_axi_awprot(),
+ .m_axi_awvalid(mem_axil_64_bus_awvalid),
+ .m_axi_awready(mem_axil_64_bus_awready),
+ .m_axi_wdata(mem_axil_64_bus_wdata),
+ .m_axi_wstrb(mem_axil_64_bus_wstrb),
+ .m_axi_wvalid(mem_axil_64_bus_wvalid),
+ .m_axi_wready(mem_axil_64_bus_wready),
+ .m_axi_bresp(mem_axil_64_bus_bresp),
+ .m_axi_bvalid(mem_axil_64_bus_bvalid),
+ .m_axi_bready(mem_axil_64_bus_bready),
+ .m_axi_araddr(mem_axil_64_bus_araddr),
+ .m_axi_arprot(),
+ .m_axi_arvalid(mem_axil_64_bus_arvalid),
+ .m_axi_arready(mem_axil_64_bus_arready),
+ .m_axi_rdata(mem_axil_64_bus_rdata),
+ .m_axi_rresp(mem_axil_64_bus_rresp),
+ .m_axi_rvalid(mem_axil_64_bus_rvalid),
+ .m_axi_rready(mem_axil_64_bus_rready)
+);
+
+cl_sim_mem CL_SIM_MEM(
+ .clk(aclk),
+ .rstn(aresetn),
+
+ .mem_axi_awvalid(mem_axil_64_bus_awvalid),
+ .mem_axi_awaddr(mem_axil_64_bus_awaddr),
+ .mem_axi_awready(mem_axil_64_bus_awready),
+
+ //Write data
+ .mem_axi_wvalid(mem_axil_64_bus_wvalid),
+ .mem_axi_wdata(mem_axil_64_bus_wdata),
+ .mem_axi_wstrb(mem_axil_64_bus_wstrb),
+ .mem_axi_wready(mem_axil_64_bus_wready),
+
+ //Write response
+ .mem_axi_bvalid(mem_axil_64_bus_bvalid),
+ .mem_axi_bresp(mem_axil_64_bus_bresp),
+ .mem_axi_bready(mem_axil_64_bus_bready),
+
+ //Read address
+ .mem_axi_arvalid(mem_axil_64_bus_arvalid),
+ .mem_axi_araddr(mem_axil_64_bus_araddr),
+ .mem_axi_arready(mem_axil_64_bus_arready),
+
+ //Read data/response
+ .mem_axi_rvalid(mem_axil_64_bus_rvalid),
+ .mem_axi_rdata(mem_axil_64_bus_rdata),
+ .mem_axi_rresp(mem_axil_64_bus_rresp),
+
+ .mem_axi_rready(mem_axil_64_bus_rready)
+);
+
+endmodule
+
+`endif
diff --git a/cl_nvdla/design/cl_vio.sv b/cl_nvdla/design/cl_vio.sv
new file mode 100644
index 0000000..6605093
--- /dev/null
+++ b/cl_nvdla/design/cl_vio.sv
@@ -0,0 +1,105 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+module cl_vio (
+ input clk_extra_a1
+
+);
+
+ // Counter running at 125MHz
+
+ logic vo_cnt_enable;
+ logic vo_cnt_load;
+ logic vo_cnt_clear;
+ logic vo_cnt_oneshot;
+ logic [7:0] vo_tick_value;
+ logic [15:0] vo_cnt_load_value;
+ logic [15:0] vo_cnt_watermark;
+
+ logic vo_cnt_enable_q = 0;
+ logic vo_cnt_load_q = 0;
+ logic vo_cnt_clear_q = 0;
+ logic vo_cnt_oneshot_q = 0;
+ logic [7:0] vo_tick_value_q = 0;
+ logic [15:0] vo_cnt_load_value_q = 0;
+ logic [15:0] vo_cnt_watermark_q = 0;
+
+ logic vi_tick;
+ logic vi_cnt_ge_watermark;
+ logic [7:0] vi_tick_cnt = 0;
+ logic [15:0] vi_cnt = 0;
+
+ // Tick counter and main counter
+ always @(posedge clk_extra_a1) begin
+
+ vo_cnt_enable_q <= vo_cnt_enable ;
+ vo_cnt_load_q <= vo_cnt_load ;
+ vo_cnt_clear_q <= vo_cnt_clear ;
+ vo_cnt_oneshot_q <= vo_cnt_oneshot ;
+ vo_tick_value_q <= vo_tick_value ;
+ vo_cnt_load_value_q <= vo_cnt_load_value;
+ vo_cnt_watermark_q <= vo_cnt_watermark ;
+
+ vi_tick_cnt = vo_cnt_clear_q ? 0 :
+ ~vo_cnt_enable_q ? vi_tick_cnt :
+ (vi_tick_cnt >= vo_tick_value_q) ? 0 :
+ vi_tick_cnt + 1;
+
+ vi_cnt = vo_cnt_clear_q ? 0 :
+ vo_cnt_load_q ? vo_cnt_load_value_q :
+ ~vo_cnt_enable_q ? vi_cnt :
+ (vi_tick_cnt >= vo_tick_value_q) && (~vo_cnt_oneshot_q || (vi_cnt <= 16'hFFFF)) ? vi_cnt + 1 :
+ vi_cnt;
+
+ vi_tick = (vi_tick_cnt >= vo_tick_value_q);
+
+ vi_cnt_ge_watermark = (vi_cnt >= vo_cnt_watermark_q);
+
+ end // always @ (posedge clk_extra_a1)
+
+
+ vio_0 CL_VIO_0 (
+ .clk (clk_extra_a1),
+ .probe_in0 (vi_tick),
+ .probe_in1 (vi_cnt_ge_watermark),
+ .probe_in2 (vi_tick_cnt),
+ .probe_in3 (vi_cnt),
+ .probe_out0 (vo_cnt_enable),
+ .probe_out1 (vo_cnt_load),
+ .probe_out2 (vo_cnt_clear),
+ .probe_out3 (vo_cnt_oneshot),
+ .probe_out4 (vo_tick_value),
+ .probe_out5 (vo_cnt_load_value),
+ .probe_out6 (vo_cnt_watermark)
+ );
+
+ ila_vio_counter CL_VIO_ILA (
+ .clk (clk_extra_a1),
+ .probe0 (vi_tick),
+ .probe1 (vi_cnt_ge_watermark),
+ .probe2 (vi_tick_cnt),
+ .probe3 (vi_cnt),
+ .probe4 (vo_cnt_enable_q),
+ .probe5 (vo_cnt_load_q),
+ .probe6 (vo_cnt_clear_q),
+ .probe7 (vo_cnt_oneshot_q),
+ .probe8 (vo_tick_value_q),
+ .probe9 (vo_cnt_load_value_q),
+ .probe10 (vo_cnt_watermark_q)
+ );
+
+
+endmodule
+
diff --git a/cl_nvdla/design/rams/nv_ram_model b/cl_nvdla/design/rams/nv_ram_model
new file mode 100644
index 0000000..9bd9036
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_model
@@ -0,0 +1,44 @@
+nv_ram_rws_128x18.v
+nv_ram_rws_16x256.v
+nv_ram_rws_16x272.v
+nv_ram_rws_16x64.v
+nv_ram_rws_256x3.v
+nv_ram_rws_256x512.v
+nv_ram_rws_256x7.v
+nv_ram_rws_32x16.v
+nv_ram_rws_32x512.v
+nv_ram_rws_32x544.v
+nv_ram_rws_32x768.v
+nv_ram_rws_512x512.v
+nv_ram_rws_512x64.v
+nv_ram_rws_64x10.v
+nv_ram_rws_64x1024.v
+nv_ram_rws_64x1088.v
+nv_ram_rws_64x116.v
+nv_ram_rws_64x18.v
+nv_ram_rwsp_128x11.v
+nv_ram_rwsp_128x6.v
+nv_ram_rwsp_160x16.v
+nv_ram_rwsp_160x514.v
+nv_ram_rwsp_160x65.v
+nv_ram_rwsp_20x289.v
+nv_ram_rwsp_245x514.v
+nv_ram_rwsp_256x11.v
+nv_ram_rwsp_32x32.v
+nv_ram_rwsp_61x514.v
+nv_ram_rwsp_61x64.v
+nv_ram_rwsp_61x65.v
+nv_ram_rwsp_80x14.v
+nv_ram_rwsp_80x16.v
+nv_ram_rwsp_80x256.v
+nv_ram_rwsp_80x514.v
+nv_ram_rwsp_80x65.v
+nv_ram_rwst_256x8.v
+nv_ram_rwsthp_19x32.v
+nv_ram_rwsthp_19x4.v
+nv_ram_rwsthp_19x80.v
+nv_ram_rwsthp_60x168.v
+nv_ram_rwsthp_60x21.v
+nv_ram_rwsthp_80x15.v
+nv_ram_rwsthp_80x72.v
+nv_ram_rwsthp_80x9.v
diff --git a/cl_nvdla/design/rams/nv_ram_rws_128x18.v b/cl_nvdla/design/rams/nv_ram_rws_128x18.v
new file mode 100644
index 0000000..f61e0a5
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_128x18.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_128x18.v
+
+module nv_ram_rws_128x18 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+output [17:0] dout;
+input [6:0] wa;
+input we;
+input [17:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [17:0] dout;
+reg [17:0] M [127:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_16x256.v b/cl_nvdla/design/rams/nv_ram_rws_16x256.v
new file mode 100644
index 0000000..1bf6643
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_16x256.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_16x256.v
+
+module nv_ram_rws_16x256 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [3:0] ra;
+input re;
+output [255:0] dout;
+input [3:0] wa;
+input we;
+input [255:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [3:0] ra_d;
+wire [255:0] dout;
+reg [255:0] M [15:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_16x272.v b/cl_nvdla/design/rams/nv_ram_rws_16x272.v
new file mode 100644
index 0000000..392d0f1
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_16x272.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_16x272.v
+
+module nv_ram_rws_16x272 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [3:0] ra;
+input re;
+output [271:0] dout;
+input [3:0] wa;
+input we;
+input [271:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [3:0] ra_d;
+wire [271:0] dout;
+reg [271:0] M [15:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_16x64.v b/cl_nvdla/design/rams/nv_ram_rws_16x64.v
new file mode 100644
index 0000000..fef328c
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_16x64.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_16x64.v
+
+module nv_ram_rws_16x64 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [3:0] ra;
+input re;
+output [63:0] dout;
+input [3:0] wa;
+input we;
+input [63:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [3:0] ra_d;
+wire [63:0] dout;
+reg [63:0] M [15:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_256x3.v b/cl_nvdla/design/rams/nv_ram_rws_256x3.v
new file mode 100644
index 0000000..3e6e5d8
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_256x3.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_256x3.v
+
+module nv_ram_rws_256x3 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [7:0] ra;
+input re;
+output [2:0] dout;
+input [7:0] wa;
+input we;
+input [2:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [7:0] ra_d;
+wire [2:0] dout;
+reg [2:0] M [255:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_256x512.v b/cl_nvdla/design/rams/nv_ram_rws_256x512.v
new file mode 100644
index 0000000..7bc7ab6
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_256x512.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_256x512.v
+
+module nv_ram_rws_256x512 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [7:0] ra;
+input re;
+output [511:0] dout;
+input [7:0] wa;
+input we;
+input [511:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [7:0] ra_d;
+wire [511:0] dout;
+reg [511:0] M [255:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_256x7.v b/cl_nvdla/design/rams/nv_ram_rws_256x7.v
new file mode 100644
index 0000000..6ddc2d3
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_256x7.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_256x7.v
+
+module nv_ram_rws_256x7 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [7:0] ra;
+input re;
+output [6:0] dout;
+input [7:0] wa;
+input we;
+input [6:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [7:0] ra_d;
+wire [6:0] dout;
+reg [6:0] M [255:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_32x16.v b/cl_nvdla/design/rams/nv_ram_rws_32x16.v
new file mode 100644
index 0000000..2724ac1
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_32x16.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_32x16.v
+
+module nv_ram_rws_32x16 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [4:0] ra;
+input re;
+output [15:0] dout;
+input [4:0] wa;
+input we;
+input [15:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [4:0] ra_d;
+wire [15:0] dout;
+reg [15:0] M [31:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_32x512.v b/cl_nvdla/design/rams/nv_ram_rws_32x512.v
new file mode 100644
index 0000000..7f9e2e0
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_32x512.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_32x512.v
+
+module nv_ram_rws_32x512 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [4:0] ra;
+input re;
+output [511:0] dout;
+input [4:0] wa;
+input we;
+input [511:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [4:0] ra_d;
+wire [511:0] dout;
+reg [511:0] M [31:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_32x544.v b/cl_nvdla/design/rams/nv_ram_rws_32x544.v
new file mode 100644
index 0000000..8ea6518
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_32x544.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_32x544.v
+
+module nv_ram_rws_32x544 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [4:0] ra;
+input re;
+output [543:0] dout;
+input [4:0] wa;
+input we;
+input [543:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [4:0] ra_d;
+wire [543:0] dout;
+reg [543:0] M [31:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_32x768.v b/cl_nvdla/design/rams/nv_ram_rws_32x768.v
new file mode 100644
index 0000000..9c28c88
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_32x768.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_32x768.v
+
+module nv_ram_rws_32x768 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [4:0] ra;
+input re;
+output [767:0] dout;
+input [4:0] wa;
+input we;
+input [767:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [4:0] ra_d;
+wire [767:0] dout;
+reg [767:0] M [31:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_512x512.v b/cl_nvdla/design/rams/nv_ram_rws_512x512.v
new file mode 100644
index 0000000..53d9c0e
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_512x512.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_512x512.v
+
+module nv_ram_rws_512x512 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [8:0] ra;
+input re;
+output [511:0] dout;
+input [8:0] wa;
+input we;
+input [511:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [8:0] ra_d;
+wire [511:0] dout;
+reg [511:0] M [511:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_512x64.v b/cl_nvdla/design/rams/nv_ram_rws_512x64.v
new file mode 100644
index 0000000..542791d
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_512x64.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_512x64.v
+
+module nv_ram_rws_512x64 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [8:0] ra;
+input re;
+output [63:0] dout;
+input [8:0] wa;
+input we;
+input [63:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [8:0] ra_d;
+wire [63:0] dout;
+reg [63:0] M [511:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_64x10.v b/cl_nvdla/design/rams/nv_ram_rws_64x10.v
new file mode 100644
index 0000000..22c31d4
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_64x10.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_64x10.v
+
+module nv_ram_rws_64x10 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [5:0] ra;
+input re;
+output [9:0] dout;
+input [5:0] wa;
+input we;
+input [9:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [5:0] ra_d;
+wire [9:0] dout;
+reg [9:0] M [63:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_64x1024.v b/cl_nvdla/design/rams/nv_ram_rws_64x1024.v
new file mode 100644
index 0000000..9200795
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_64x1024.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_64x1024.v
+
+module nv_ram_rws_64x1024 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [5:0] ra;
+input re;
+output [1023:0] dout;
+input [5:0] wa;
+input we;
+input [1023:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [5:0] ra_d;
+wire [1023:0] dout;
+reg [1023:0] M [63:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_64x1088.v b/cl_nvdla/design/rams/nv_ram_rws_64x1088.v
new file mode 100644
index 0000000..d142f58
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_64x1088.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_64x1088.v
+
+module nv_ram_rws_64x1088 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [5:0] ra;
+input re;
+output [1087:0] dout;
+input [5:0] wa;
+input we;
+input [1087:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [5:0] ra_d;
+wire [1087:0] dout;
+reg [1087:0] M [63:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_64x116.v b/cl_nvdla/design/rams/nv_ram_rws_64x116.v
new file mode 100644
index 0000000..a334784
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_64x116.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_64x116.v
+
+module nv_ram_rws_64x116 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [5:0] ra;
+input re;
+output [115:0] dout;
+input [5:0] wa;
+input we;
+input [115:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [5:0] ra_d;
+wire [115:0] dout;
+reg [115:0] M [63:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rws_64x18.v b/cl_nvdla/design/rams/nv_ram_rws_64x18.v
new file mode 100644
index 0000000..5370bc3
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rws_64x18.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rws_64x18.v
+
+module nv_ram_rws_64x18 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [5:0] ra;
+input re;
+output [17:0] dout;
+input [5:0] wa;
+input we;
+input [17:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [5:0] ra_d;
+wire [17:0] dout;
+reg [17:0] M [63:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_128x11.v b/cl_nvdla/design/rams/nv_ram_rwsp_128x11.v
new file mode 100644
index 0000000..11c7565
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_128x11.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_128x11.v
+
+module nv_ram_rwsp_128x11 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+input ore;
+output [10:0] dout;
+input [6:0] wa;
+input we;
+input [10:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [10:0] dout;
+reg [10:0] M [127:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [10:0] dout_ram = M[ra_d];
+
+reg [10:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_128x6.v b/cl_nvdla/design/rams/nv_ram_rwsp_128x6.v
new file mode 100644
index 0000000..881a428
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_128x6.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_128x6.v
+
+module nv_ram_rwsp_128x6 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+input ore;
+output [5:0] dout;
+input [6:0] wa;
+input we;
+input [5:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [5:0] dout;
+reg [5:0] M [127:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [5:0] dout_ram = M[ra_d];
+
+reg [5:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_160x16.v b/cl_nvdla/design/rams/nv_ram_rwsp_160x16.v
new file mode 100644
index 0000000..e168693
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_160x16.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_160x16.v
+
+module nv_ram_rwsp_160x16 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [7:0] ra;
+input re;
+input ore;
+output [15:0] dout;
+input [7:0] wa;
+input we;
+input [15:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [7:0] ra_d;
+wire [15:0] dout;
+reg [15:0] M [159:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [15:0] dout_ram = M[ra_d];
+
+reg [15:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_160x514.v b/cl_nvdla/design/rams/nv_ram_rwsp_160x514.v
new file mode 100644
index 0000000..8885d08
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_160x514.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_160x514.v
+
+module nv_ram_rwsp_160x514 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [7:0] ra;
+input re;
+input ore;
+output [513:0] dout;
+input [7:0] wa;
+input we;
+input [513:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [7:0] ra_d;
+wire [513:0] dout;
+reg [513:0] M [159:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [513:0] dout_ram = M[ra_d];
+
+reg [513:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_160x65.v b/cl_nvdla/design/rams/nv_ram_rwsp_160x65.v
new file mode 100644
index 0000000..684f71b
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_160x65.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_160x65.v
+
+module nv_ram_rwsp_160x65 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [7:0] ra;
+input re;
+input ore;
+output [64:0] dout;
+input [7:0] wa;
+input we;
+input [64:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [7:0] ra_d;
+wire [64:0] dout;
+reg [64:0] M [159:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [64:0] dout_ram = M[ra_d];
+
+reg [64:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_20x289.v b/cl_nvdla/design/rams/nv_ram_rwsp_20x289.v
new file mode 100644
index 0000000..07e1677
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_20x289.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_20x289.v
+
+module nv_ram_rwsp_20x289 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [4:0] ra;
+input re;
+input ore;
+output [288:0] dout;
+input [4:0] wa;
+input we;
+input [288:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [4:0] ra_d;
+wire [288:0] dout;
+reg [288:0] M [19:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [288:0] dout_ram = M[ra_d];
+
+reg [288:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_245x514.v b/cl_nvdla/design/rams/nv_ram_rwsp_245x514.v
new file mode 100644
index 0000000..902a8be
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_245x514.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_245x514.v
+
+module nv_ram_rwsp_245x514 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [7:0] ra;
+input re;
+input ore;
+output [513:0] dout;
+input [7:0] wa;
+input we;
+input [513:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [7:0] ra_d;
+wire [513:0] dout;
+reg [513:0] M [244:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [513:0] dout_ram = M[ra_d];
+
+reg [513:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_256x11.v b/cl_nvdla/design/rams/nv_ram_rwsp_256x11.v
new file mode 100644
index 0000000..a58b5fb
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_256x11.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_256x11.v
+
+module nv_ram_rwsp_256x11 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [7:0] ra;
+input re;
+input ore;
+output [10:0] dout;
+input [7:0] wa;
+input we;
+input [10:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [7:0] ra_d;
+wire [10:0] dout;
+reg [10:0] M [255:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [10:0] dout_ram = M[ra_d];
+
+reg [10:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_32x32.v b/cl_nvdla/design/rams/nv_ram_rwsp_32x32.v
new file mode 100644
index 0000000..ed7ff68
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_32x32.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_32x32.v
+
+module nv_ram_rwsp_32x32 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [4:0] ra;
+input re;
+input ore;
+output [31:0] dout;
+input [4:0] wa;
+input we;
+input [31:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [4:0] ra_d;
+wire [31:0] dout;
+reg [31:0] M [31:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [31:0] dout_ram = M[ra_d];
+
+reg [31:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_61x514.v b/cl_nvdla/design/rams/nv_ram_rwsp_61x514.v
new file mode 100644
index 0000000..d4f8437
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_61x514.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_61x514.v
+
+module nv_ram_rwsp_61x514 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [5:0] ra;
+input re;
+input ore;
+output [513:0] dout;
+input [5:0] wa;
+input we;
+input [513:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [5:0] ra_d;
+wire [513:0] dout;
+reg [513:0] M [60:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [513:0] dout_ram = M[ra_d];
+
+reg [513:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_61x64.v b/cl_nvdla/design/rams/nv_ram_rwsp_61x64.v
new file mode 100644
index 0000000..8c5160e
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_61x64.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_61x64.v
+
+module nv_ram_rwsp_61x64 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [5:0] ra;
+input re;
+input ore;
+output [63:0] dout;
+input [5:0] wa;
+input we;
+input [63:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [5:0] ra_d;
+wire [63:0] dout;
+reg [63:0] M [60:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [63:0] dout_ram = M[ra_d];
+
+reg [63:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_61x65.v b/cl_nvdla/design/rams/nv_ram_rwsp_61x65.v
new file mode 100644
index 0000000..62cc7fd
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_61x65.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_61x65.v
+
+module nv_ram_rwsp_61x65 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [5:0] ra;
+input re;
+input ore;
+output [64:0] dout;
+input [5:0] wa;
+input we;
+input [64:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [5:0] ra_d;
+wire [64:0] dout;
+reg [64:0] M [60:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [64:0] dout_ram = M[ra_d];
+
+reg [64:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_80x14.v b/cl_nvdla/design/rams/nv_ram_rwsp_80x14.v
new file mode 100644
index 0000000..0841e6f
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_80x14.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_80x14.v
+
+module nv_ram_rwsp_80x14 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+input ore;
+output [13:0] dout;
+input [6:0] wa;
+input we;
+input [13:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [13:0] dout;
+reg [13:0] M [79:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [13:0] dout_ram = M[ra_d];
+
+reg [13:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_80x16.v b/cl_nvdla/design/rams/nv_ram_rwsp_80x16.v
new file mode 100644
index 0000000..937507c
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_80x16.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_80x16.v
+
+module nv_ram_rwsp_80x16 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+input ore;
+output [15:0] dout;
+input [6:0] wa;
+input we;
+input [15:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [15:0] dout;
+reg [15:0] M [79:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [15:0] dout_ram = M[ra_d];
+
+reg [15:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_80x256.v b/cl_nvdla/design/rams/nv_ram_rwsp_80x256.v
new file mode 100644
index 0000000..64645ae
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_80x256.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_80x256.v
+
+module nv_ram_rwsp_80x256 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+input ore;
+output [255:0] dout;
+input [6:0] wa;
+input we;
+input [255:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [255:0] dout;
+reg [255:0] M [79:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [255:0] dout_ram = M[ra_d];
+
+reg [255:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_80x514.v b/cl_nvdla/design/rams/nv_ram_rwsp_80x514.v
new file mode 100644
index 0000000..62186a9
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_80x514.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_80x514.v
+
+module nv_ram_rwsp_80x514 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+input ore;
+output [513:0] dout;
+input [6:0] wa;
+input we;
+input [513:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [513:0] dout;
+reg [513:0] M [79:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [513:0] dout_ram = M[ra_d];
+
+reg [513:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsp_80x65.v b/cl_nvdla/design/rams/nv_ram_rwsp_80x65.v
new file mode 100644
index 0000000..dc355ad
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsp_80x65.v
@@ -0,0 +1,62 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsp_80x65.v
+
+module nv_ram_rwsp_80x65 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+input ore;
+output [64:0] dout;
+input [6:0] wa;
+input we;
+input [64:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [64:0] dout;
+reg [64:0] M [79:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [64:0] dout_ram = M[ra_d];
+
+reg [64:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwst_256x8.v b/cl_nvdla/design/rams/nv_ram_rwst_256x8.v
new file mode 100644
index 0000000..2e74db0
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwst_256x8.v
@@ -0,0 +1,50 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwst_256x8.v
+
+module nv_ram_rwst_256x8 (
+ clk,
+ ra,
+ re,
+ dout,
+ wa,
+ we,
+ di,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [7:0] ra;
+input re;
+output [7:0] dout;
+input [7:0] wa;
+input we;
+input [7:0] di;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [7:0] ra_d;
+wire [7:0] dout;
+reg [7:0] M [255:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+assign dout = M[ra_d];
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsthp_19x32.v b/cl_nvdla/design/rams/nv_ram_rwsthp_19x32.v
new file mode 100644
index 0000000..dd5900d
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsthp_19x32.v
@@ -0,0 +1,68 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsthp_19x32.v
+
+module nv_ram_rwsthp_19x32 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ byp_sel,
+ dbyp,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [4:0] ra;
+input re;
+input ore;
+output [31:0] dout;
+input [4:0] wa;
+input we;
+input [31:0] di;
+input byp_sel;
+input [31:0] dbyp;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [4:0] ra_d;
+wire [31:0] dout;
+reg [31:0] M [18:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [31:0] dout_ram = M[ra_d];
+
+wire [31:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram);
+
+reg [31:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= fbypass_dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsthp_19x4.v b/cl_nvdla/design/rams/nv_ram_rwsthp_19x4.v
new file mode 100644
index 0000000..3f8c93c
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsthp_19x4.v
@@ -0,0 +1,68 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsthp_19x4.v
+
+module nv_ram_rwsthp_19x4 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ byp_sel,
+ dbyp,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [4:0] ra;
+input re;
+input ore;
+output [3:0] dout;
+input [4:0] wa;
+input we;
+input [3:0] di;
+input byp_sel;
+input [3:0] dbyp;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [4:0] ra_d;
+wire [3:0] dout;
+reg [3:0] M [18:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [3:0] dout_ram = M[ra_d];
+
+wire [3:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram);
+
+reg [3:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= fbypass_dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsthp_19x80.v b/cl_nvdla/design/rams/nv_ram_rwsthp_19x80.v
new file mode 100644
index 0000000..aa89fda
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsthp_19x80.v
@@ -0,0 +1,68 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsthp_19x80.v
+
+module nv_ram_rwsthp_19x80 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ byp_sel,
+ dbyp,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [4:0] ra;
+input re;
+input ore;
+output [79:0] dout;
+input [4:0] wa;
+input we;
+input [79:0] di;
+input byp_sel;
+input [79:0] dbyp;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [4:0] ra_d;
+wire [79:0] dout;
+reg [79:0] M [18:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [79:0] dout_ram = M[ra_d];
+
+wire [79:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram);
+
+reg [79:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= fbypass_dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsthp_60x168.v b/cl_nvdla/design/rams/nv_ram_rwsthp_60x168.v
new file mode 100644
index 0000000..9f9f54c
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsthp_60x168.v
@@ -0,0 +1,68 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsthp_60x168.v
+
+module nv_ram_rwsthp_60x168 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ byp_sel,
+ dbyp,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [5:0] ra;
+input re;
+input ore;
+output [167:0] dout;
+input [5:0] wa;
+input we;
+input [167:0] di;
+input byp_sel;
+input [167:0] dbyp;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [5:0] ra_d;
+wire [167:0] dout;
+reg [167:0] M [59:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [167:0] dout_ram = M[ra_d];
+
+wire [167:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram);
+
+reg [167:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= fbypass_dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsthp_60x21.v b/cl_nvdla/design/rams/nv_ram_rwsthp_60x21.v
new file mode 100644
index 0000000..2412074
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsthp_60x21.v
@@ -0,0 +1,68 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsthp_60x21.v
+
+module nv_ram_rwsthp_60x21 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ byp_sel,
+ dbyp,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [5:0] ra;
+input re;
+input ore;
+output [20:0] dout;
+input [5:0] wa;
+input we;
+input [20:0] di;
+input byp_sel;
+input [20:0] dbyp;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [5:0] ra_d;
+wire [20:0] dout;
+reg [20:0] M [59:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [20:0] dout_ram = M[ra_d];
+
+wire [20:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram);
+
+reg [20:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= fbypass_dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsthp_80x15.v b/cl_nvdla/design/rams/nv_ram_rwsthp_80x15.v
new file mode 100644
index 0000000..9ff1d5a
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsthp_80x15.v
@@ -0,0 +1,68 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsthp_80x15.v
+
+module nv_ram_rwsthp_80x15 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ byp_sel,
+ dbyp,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+input ore;
+output [14:0] dout;
+input [6:0] wa;
+input we;
+input [14:0] di;
+input byp_sel;
+input [14:0] dbyp;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [14:0] dout;
+reg [14:0] M [79:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [14:0] dout_ram = M[ra_d];
+
+wire [14:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram);
+
+reg [14:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= fbypass_dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsthp_80x72.v b/cl_nvdla/design/rams/nv_ram_rwsthp_80x72.v
new file mode 100644
index 0000000..efa3016
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsthp_80x72.v
@@ -0,0 +1,68 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsthp_80x72.v
+
+module nv_ram_rwsthp_80x72 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ byp_sel,
+ dbyp,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+input ore;
+output [71:0] dout;
+input [6:0] wa;
+input we;
+input [71:0] di;
+input byp_sel;
+input [71:0] dbyp;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [71:0] dout;
+reg [71:0] M [79:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [71:0] dout_ram = M[ra_d];
+
+wire [71:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram);
+
+reg [71:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= fbypass_dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/design/rams/nv_ram_rwsthp_80x9.v b/cl_nvdla/design/rams/nv_ram_rwsthp_80x9.v
new file mode 100644
index 0000000..04d5e6a
--- /dev/null
+++ b/cl_nvdla/design/rams/nv_ram_rwsthp_80x9.v
@@ -0,0 +1,68 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: nv_ram_rwsthp_80x9.v
+
+module nv_ram_rwsthp_80x9 (
+ clk,
+ ra,
+ re,
+ ore,
+ dout,
+ wa,
+ we,
+ di,
+ byp_sel,
+ dbyp,
+ pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input clk;
+input [6:0] ra;
+input re;
+input ore;
+output [8:0] dout;
+input [6:0] wa;
+input we;
+input [8:0] di;
+input byp_sel;
+input [8:0] dbyp;
+input [31:0] pwrbus_ram_pd;
+
+//reg and wire list
+reg [6:0] ra_d;
+wire [8:0] dout;
+reg [8:0] M [79:0];
+
+always @( posedge clk ) begin
+ if (we)
+ M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+ if (re)
+ ra_d <= ra;
+end
+
+wire [8:0] dout_ram = M[ra_d];
+
+wire [8:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram);
+
+reg [8:0] dout_r;
+always @( posedge clk ) begin
+ if (ore)
+ dout_r <= fbypass_dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule
diff --git a/cl_nvdla/software/src/Makefile b/cl_nvdla/software/src/Makefile
new file mode 100644
index 0000000..9c1d692
--- /dev/null
+++ b/cl_nvdla/software/src/Makefile
@@ -0,0 +1,83 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+#VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include
+
+.PHONY: default
+default: all
+
+NVDLA_HW_ROOT ?= $(abspath ../../../../../../hw)
+NVDLA_HW_PROJECT ?= nv_small
+
+NVDLA_TRACE_PLAYER_ROOT ?= $(abspath ../../../common/trace_player)
+NVDLA_TRACE_PLAYER_CFLAGS = "-DDEBUG -g"
+NVDLA_REGISTER_HEADER_DIR ?= $(NVDLA_HW_ROOT)/outdir/$(NVDLA_HW_PROJECT)/spec/manual
+NVDLA_TRACE ?= ../test_bdma/test_bdma.cfg
+
+include $(NVDLA_TRACE_PLAYER_ROOT)/Makefile.inc
+
+VPATH = src:../../../common/software/src:$(NVDLA_TRACE_PLAYER_SRC_DIR)
+INCLUDES = -I../../../common/software/include -I../include -I$(NVDLA_REGISTER_HEADER_DIR) -I$(NVDLA_TRACE_PLAYER_INCLUDES)
+ifndef VP_TEST
+INCLUDES += -I$(SDK_DIR)/userspace/include
+endif
+
+ifdef VP_TEST
+CC = aarch64-linux-gnu-gcc
+else
+CC = gcc
+endif
+CFLAGS = -DCONFIG_LOGLEVEL=4 -g -Wall $(INCLUDES)
+ifdef VP_TEST
+CFLAGS += -DVP_TEST
+else
+CFLAGS += -L$(SDK_DIR)/userspace/lib/so
+endif
+
+LDFLAGS = -Wl,-rpath $(NVDLA_TRACE_PLAYER_LIB_DIR) -L$(NVDLA_TRACE_PLAYER_LIB_DIR)
+LDLIBS = -l$(NVDLA_TRACE_PLAYER_LIB)
+ifndef VP_TEST
+LDLIBS += -lfpga_mgmt -lrt -lpthread
+endif
+
+SRC = trace_test.c trace_test_impl.c cl_common_utils.c
+OBJ = $(SRC:.c=.o)
+ifdef VP_TEST
+BIN = aarch64_trace_test
+else
+BIN = trace_test
+endif
+
+ifdef VP_TEST
+all: $(NVDLA_TRACE_PARSER_COMMAND_LIB) $(NVDLA_TRACE_PLAYER_LIB_DIR)/$(NVDLA_TRACE_PLAYER_LIB) $(BIN)
+else
+all: $(NVDLA_TRACE_PARSER_COMMAND_LIB) $(NVDLA_TRACE_PLAYER_LIB_DIR)/$(NVDLA_TRACE_PLAYER_LIB) $(BIN) check_env
+endif
+
+$(BIN): $(OBJ)
+ $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LDLIBS)
+
+clean:
+ rm -f *.o $(BIN) $(NVDLA_TRACE_PARSER_COMMAND_SRC) $(NVDLA_TRACE_PARSER_COMMAND_OBJ) $(NVDLA_TRACE_PARSER_COMMAND_LIB) *.dat *.log
+
+ifndef VP_TEST
+check_env:
+ifndef SDK_DIR
+ $(error SDK_DIR is undefined. Try "source sdk_setup.sh" to set the software environment)
+endif
+endif
diff --git a/cl_nvdla/software/src/test_null.c b/cl_nvdla/software/src/test_null.c
new file mode 100644
index 0000000..4b11367
--- /dev/null
+++ b/cl_nvdla/software/src/test_null.c
@@ -0,0 +1,34 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include
+#include
+#include
+
+// Vivado does not support svGetScopeFromName
+#ifdef INCLUDE_DPI_CALLS
+#ifndef VIVADO_SIM
+#include "svdpi.h"
+#endif
+#endif
+
+#include "sh_dpi_tasks.h"
+
+void test_main(uint32_t *exit_code) {
+
+ // NULL Test
+
+ *exit_code = 0;
+}
diff --git a/cl_nvdla/software/src/trace_test.c b/cl_nvdla/software/src/trace_test.c
new file mode 100644
index 0000000..32f2769
--- /dev/null
+++ b/cl_nvdla/software/src/trace_test.c
@@ -0,0 +1,215 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_test.c
+
+#include
+#include
+#include
+#include
+#include
+
+#include "opendla.h"
+
+#include "cl_common_utils.h"
+
+#include "trace_player.h"
+#include "trace_player_intr.h"
+
+/*
+ * Platform Specific Params
+ */
+#define CFG_INT_STATUS_ADDR (0x0)
+
+/*
+ * pci_vendor_id and pci_device_id values below are Amazon's and avaliable to use for a given FPGA slot.
+ * Users may replace these with their own if allocated to them by PCI SIG
+ */
+static uint16_t pci_vendor_id = 0x1D0F; /* Amazon PCI Vendor ID */
+static uint16_t pci_device_id = 0xF001; /* PCI Device ID preassigned by Amazon for F1 applications */
+static uint32_t int_mask = 0x1;
+
+typedef enum { INT_INIT, INT_ASSERT, INT_DEASSERT } IRQ_STATE_t;
+
+static IRQ_STATE_t irq_state = INT_INIT;
+
+uint32_t trace_player_pending_intr = 0;
+
+#ifdef SV_TEST
+void set_enable_sim_mem(int val);
+#endif
+
+/*
+ * Interrupt handler
+ */
+void cl_int_handler(uint32_t int_num);
+void wait_irq_done(void);
+void cl_check_and_clear_intr(void);
+
+#ifdef SV_TEST
+void trace_test_main(uint32_t *exit_code, const char *trace_file, int enable_sim_mem)
+#else
+int main(int argc, char **argv)
+#endif
+{
+ int rc = 0;
+
+#ifdef SV_TEST
+#else
+ assert(argc == 2);
+ char *trace_file = argv[1];
+#endif
+
+ if (cl_common_init(pci_vendor_id, pci_device_id, int_mask)) {
+ log_printf("Errors on initialization!\n");
+ assert(0);
+ }
+#ifndef VP_TEST
+ cl_common_reset();
+#endif
+
+#ifdef SV_TEST
+ set_enable_sim_mem(enable_sim_mem);
+#endif
+
+ rc = trace_player_run(trace_file);
+
+ /* wait for irq handling done */
+ wait_irq_done();
+
+ /* cleanup */
+ if (cl_common_cleanup()) {
+ rc = 1;
+ }
+
+ switch(rc){
+ case 0:
+ log_printf("Test PASSED\n");
+ break;
+ case 1:
+ log_printf("Test FAILED\n");
+ break;
+ case 2:
+ log_printf("Test TIMEOUT\n");
+ break;
+ }
+
+#ifdef SV_TEST
+ *exit_code = rc;
+#else
+ return rc;
+#endif
+}
+
+void cl_int_handler(uint32_t int_num)
+{
+ log_printf("CL_INT_HANDLER: enter cl_int_handler, int_num=%d\n", int_num);
+
+ if (int_num != 0) {
+ log_printf("CL_INT_HANDLER: ERROR! int_num should always be 0!\n");
+ return;
+ }
+
+ uint32_t status;
+ static uint32_t last_status = 0;
+
+ cfg_read(CFG_INT_STATUS_ADDR, &status);
+
+ log_printf("CL_INT_HANDLER: int_status=0x%x, last_status=0x%x\n", status, last_status);
+
+ if (status == last_status) {
+ log_printf("CL_INT_HANDLER: ERROR! status should never be the same as last_status!\n");
+ return;
+ }
+
+ if (status & (0x1< 0) {
+ if (cl_msi_is_active(0)) {
+ cl_int_handler(0);
+ } else {
+ log_printf("Error! interrupt %d is not active\n", 0);
+ assert(0);
+ }
+ }
+}
+#endif
+#endif
diff --git a/cl_nvdla/software/src/trace_test_impl.c b/cl_nvdla/software/src/trace_test_impl.c
new file mode 100644
index 0000000..926f43a
--- /dev/null
+++ b/cl_nvdla/software/src/trace_test_impl.c
@@ -0,0 +1,201 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_test_impl.c
+
+#include
+#include
+#include
+
+#include "cl_common_utils.h"
+
+#define CHAR2UINT64(array, index) \
+ (((uint64_t)(array[index])) \
+ | (((uint64_t)(array[index+1]))<<8) \
+ | (((uint64_t)(array[index+2]))<<16) \
+ | (((uint64_t)(array[index+3]))<<24) \
+ | (((uint64_t)(array[index+4]))<<32) \
+ | (((uint64_t)(array[index+5]))<<40) \
+ | (((uint64_t)(array[index+6]))<<48) \
+ | (((uint64_t)(array[index+7]))<<56))
+#define CHAR2UINT32(array, index) \
+ (((uint32_t)(array[index])) \
+ | (((uint32_t)(array[index+1]))<<8) \
+ | (((uint32_t)(array[index+2]))<<16) \
+ | (((uint32_t)(array[index+3]))<<24))
+#define CHAR2UINT16(array, index) \
+ (((uint16_t)(array[index])) \
+ | (((uint16_t)(array[index+1]))<<8))
+
+#define DDR_C_BASE_ADDR 0xC0000000
+
+static int enable_sim_mem = 0;
+void set_enable_sim_mem(int val)
+{
+ enable_sim_mem = val;
+}
+
+void reg_write(uint64_t offset, uint32_t val)
+{
+ apb_write(offset, val);
+}
+
+void reg_read(uint64_t offset, uint32_t *val)
+{
+ apb_read(offset, val);
+}
+
+void mem_write64(const char *mem_type, uint64_t offset, uint64_t val)
+{
+ if (enable_sim_mem) {
+#ifdef SV_TEST
+ backdoor_mem_write(offset, val, 8, 0xFF);
+#endif
+ } else {
+#ifdef VP_TEST
+ ddr_write(offset-DDR_C_BASE_ADDR, val, 3);
+#else
+ ddr_write(offset, val, 3);
+#endif
+ }
+}
+
+void mem_write32(const char *mem_type, uint64_t offset, uint32_t val)
+{
+ if (enable_sim_mem) {
+#ifdef SV_TEST
+ backdoor_mem_write(offset, val, 4, 0xF);
+#endif
+ } else {
+#ifdef VP_TEST
+ ddr_write(offset-DDR_C_BASE_ADDR, val, 2);
+#else
+ ddr_write(offset, val, 2);
+#endif
+ }
+}
+
+void mem_write16(const char *mem_type, uint64_t offset, uint16_t val)
+{
+ if (enable_sim_mem) {
+#ifdef SV_TEST
+ backdoor_mem_write(offset, val, 2, 0x3);
+#endif
+ } else {
+#ifdef VP_TEST
+ ddr_write(offset-DDR_C_BASE_ADDR, val, 1);
+#else
+ ddr_write(offset, val, 1);
+#endif
+ }
+}
+
+void mem_write8(const char *mem_type, uint64_t offset, uint8_t val)
+{
+ if (enable_sim_mem) {
+#ifdef SV_TEST
+ backdoor_mem_write(offset, val, 1, 0x1);
+#endif
+ } else {
+#ifdef VP_TEST
+ ddr_write(offset-DDR_C_BASE_ADDR, val, 0);
+#else
+ ddr_write(offset, val, 0);
+#endif
+ }
+}
+
+void mem_read64(const char *mem_type, uint64_t offset, uint64_t *val)
+{
+ if (enable_sim_mem) {
+#ifdef SV_TEST
+ *val = backdoor_mem_read(offset, 8);
+#endif
+ } else {
+#ifdef VP_TEST
+ ddr_read(offset-DDR_C_BASE_ADDR, val, 3);
+#else
+ ddr_read(offset, val, 3);
+#endif
+ }
+}
+
+void mem_read32(const char *mem_type, uint64_t offset, uint32_t *val)
+{
+ uint64_t rdata;
+ if (enable_sim_mem) {
+#ifdef SV_TEST
+ rdata = backdoor_mem_read(offset, 4);
+#endif
+ } else {
+#ifdef VP_TEST
+ ddr_read(offset-DDR_C_BASE_ADDR, &rdata, 2);
+#else
+ ddr_read(offset, &rdata, 2);
+#endif
+ }
+ *val = rdata;
+}
+
+void mem_read16(const char *mem_type, uint64_t offset, uint16_t *val)
+{
+ uint64_t rdata;
+ if (enable_sim_mem) {
+#ifdef SV_TEST
+ rdata = backdoor_mem_read(offset, 2);
+#endif
+ } else {
+#ifdef VP_TEST
+ ddr_read(offset-DDR_C_BASE_ADDR, &rdata, 1);
+#else
+ ddr_read(offset, &rdata, 1);
+#endif
+ }
+ *val = rdata;
+}
+
+void mem_read8(const char *mem_type, uint64_t offset, uint8_t *val)
+{
+ uint64_t rdata;
+ if (enable_sim_mem) {
+#ifdef SV_TEST
+ rdata = backdoor_mem_read(offset, 1);
+#endif
+ } else {
+ ddr_read(offset, &rdata, 0);
+#ifdef VP_TEST
+ ddr_read(offset-DDR_C_BASE_ADDR, &rdata, 0);
+#else
+ ddr_read(offset, &rdata, 0);
+#endif
+ }
+ *val = rdata;
+}
+
+void trace_player_wait(uint32_t num)
+{
+#ifdef SV_TEST
+ sv_pause(num);
+#endif
+}
+
+#ifndef SV_TEST
+extern void cl_check_and_clear_intr(void);
+#endif
+
+uint32_t trace_player_check_and_clear_pending_intr(void)
+{
+#ifndef SV_TEST
+ cl_check_and_clear_intr();
+#endif
+ extern uint32_t trace_player_pending_intr;
+ uint32_t rc = trace_player_pending_intr;
+ /* clear pending intr */
+ trace_player_pending_intr = 0;
+ return rc;
+}
diff --git a/cl_nvdla/software/traces/bdma_sanity/bdma_sanity.cfg b/cl_nvdla/software/traces/bdma_sanity/bdma_sanity.cfg
new file mode 100644
index 0000000..da66c17
--- /dev/null
+++ b/cl_nvdla/software/traces/bdma_sanity/bdma_sanity.cfg
@@ -0,0 +1,17 @@
+mem_load(pri_mem, 0xC0000000, "bdma_sanity_input.dat");
+reg_write(NVDLA_BDMA.CFG_SRC_ADDR_HIGH_0, 0);
+reg_write(NVDLA_BDMA.CFG_SRC_ADDR_LOW_0, 0xC0000000);
+reg_write(NVDLA_BDMA.CFG_DST_ADDR_HIGH_0, 0);
+reg_write(NVDLA_BDMA.CFG_DST_ADDR_LOW_0 , 0xC00017C0);
+reg_write(NVDLA_BDMA.CFG_DST_SURF_0, 0x800);
+reg_write(NVDLA_BDMA.CFG_DST_LINE_0, 0x100);
+reg_write(NVDLA_BDMA.CFG_SRC_SURF_0, 0x800);
+reg_write(NVDLA_BDMA.CFG_SRC_LINE_0, 0x100);
+reg_write(NVDLA_BDMA.CFG_SURF_REPEAT_0, 0);
+reg_write(NVDLA_BDMA.CFG_LINE_REPEAT_0, 7);
+reg_write(NVDLA_BDMA.CFG_LINE_0, 7);
+reg_write(NVDLA_BDMA.CFG_CMD_0, 3);
+reg_write(NVDLA_BDMA.CFG_OP_0, 1);
+reg_write(NVDLA_BDMA.CFG_LAUNCH0_0, 1);
+intr_notify(BDMA_0, BDMA_0_BDMA_0_interrupt);
+check_file(BDMA_0_BDMA_0_interrupt, pri_mem, 0xC00017C0, 0x800, "bdma_sanity_output.dat");
diff --git a/cl_nvdla/software/traces/bdma_sanity/bdma_sanity_input.dat b/cl_nvdla/software/traces/bdma_sanity/bdma_sanity_input.dat
new file mode 100644
index 0000000..938100e
--- /dev/null
+++ b/cl_nvdla/software/traces/bdma_sanity/bdma_sanity_input.dat
@@ -0,0 +1,64 @@
+{offset:0x0, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x20, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x40, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x60, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x80, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0xa0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0xc0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0xe0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x100, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x120, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x140, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x160, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x180, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x1a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x1c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x1e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x200, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x220, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x240, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x260, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x280, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x2a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x2c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x2e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x300, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x320, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x340, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x360, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x380, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x3a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x3c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x3e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x400, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x420, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x440, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x460, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x480, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x4a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x4c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x4e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x500, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x520, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x540, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x560, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x580, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x5a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x5c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x5e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x600, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x620, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x640, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x660, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x680, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x6a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x6c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x6e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x700, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x720, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x740, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x760, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x780, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x7a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x7c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x7e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
\ No newline at end of file
diff --git a/cl_nvdla/software/traces/bdma_sanity/bdma_sanity_output.dat b/cl_nvdla/software/traces/bdma_sanity/bdma_sanity_output.dat
new file mode 100644
index 0000000..938100e
--- /dev/null
+++ b/cl_nvdla/software/traces/bdma_sanity/bdma_sanity_output.dat
@@ -0,0 +1,64 @@
+{offset:0x0, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x20, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x40, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x60, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x80, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0xa0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0xc0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0xe0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x100, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x120, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x140, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x160, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x180, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x1a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x1c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x1e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x200, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x220, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x240, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x260, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x280, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x2a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x2c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x2e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x300, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x320, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x340, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x360, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x380, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x3a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x3c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x3e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x400, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x420, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x440, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x460, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x480, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x4a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x4c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x4e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x500, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x520, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x540, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x560, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x580, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x5a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x5c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x5e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x600, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x620, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x640, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x660, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x680, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x6a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x6c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x6e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x700, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x720, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x740, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x760, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x780, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x7a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x7c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x7e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
\ No newline at end of file
diff --git a/cl_nvdla/software/traces/cdp_8x8x32_lrn3_int8_1/CDP_0_input.dat b/cl_nvdla/software/traces/cdp_8x8x32_lrn3_int8_1/CDP_0_input.dat
new file mode 100644
index 0000000..938100e
--- /dev/null
+++ b/cl_nvdla/software/traces/cdp_8x8x32_lrn3_int8_1/CDP_0_input.dat
@@ -0,0 +1,64 @@
+{offset:0x0, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x20, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x40, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x60, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x80, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0xa0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0xc0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0xe0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x100, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x120, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x140, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x160, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x180, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x1a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x1c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x1e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x200, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x220, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x240, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x260, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x280, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x2a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x2c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x2e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x300, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x320, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x340, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x360, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x380, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x3a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x3c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x3e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x400, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x420, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x440, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x460, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x480, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x4a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x4c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x4e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x500, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x520, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x540, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x560, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x580, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x5a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x5c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x5e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x600, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x620, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x640, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x660, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x680, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x6a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x6c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x6e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x700, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x720, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x740, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x760, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x780, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x7a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x7c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x7e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
\ No newline at end of file
diff --git a/cl_nvdla/software/traces/cdp_8x8x32_lrn3_int8_1/CDP_0_output.dat b/cl_nvdla/software/traces/cdp_8x8x32_lrn3_int8_1/CDP_0_output.dat
new file mode 100644
index 0000000..b76a57c
--- /dev/null
+++ b/cl_nvdla/software/traces/cdp_8x8x32_lrn3_int8_1/CDP_0_output.dat
@@ -0,0 +1,64 @@
+{offset:0x0, size:32, payload:0xA7 0x21 0x6D 0xF1 0xDB 0x15 0xFB 0x83 0x83 0x00 0x58 0x8F 0xEB 0x6E 0x48 0x0B 0x0E 0x7E 0x26 0x54 0x8A 0x18 0xFF 0xCA 0xD2 0x53 0x02 0x24 0x89 0x03 0x23 0x22},
+{offset:0x20, size:32, payload:0x7E 0xF6 0x9A 0xC4 0x49 0xEE 0x70 0x6B 0x6F 0xFC 0xA2 0xB9 0x54 0xD6 0xB4 0x77 0xE5 0xB7 0x47 0x77 0x72 0x03 0xCB 0x29 0x05 0x30 0xF9 0x08 0x25 0x7E 0x22 0x3D},
+{offset:0x40, size:32, payload:0xED 0xB5 0x86 0x08 0x5E 0x92 0xB8 0xE1 0x04 0x9B 0xB9 0x8B 0xD0 0x8A 0x18 0xD1 0x62 0x7B 0xB9 0x9B 0x3D 0xC7 0xAF 0x85 0x50 0x30 0x0B 0xE9 0x09 0xE7 0x56 0x85},
+{offset:0x60, size:32, payload:0x9C 0x91 0xAA 0xCD 0x26 0xEE 0xE3 0x6E 0xB0 0x58 0x02 0x0D 0x64 0xE0 0xB5 0xA5 0xEB 0x3D 0x19 0x0E 0x03 0xB5 0x41 0x38 0x35 0x61 0x5F 0xF8 0xDD 0xE8 0xFD 0xF1},
+{offset:0x80, size:32, payload:0x55 0xFA 0x9E 0xE4 0xC1 0xC4 0x87 0x46 0xFF 0xE6 0x55 0x03 0x9C 0x68 0x9C 0x43 0x03 0xD4 0x76 0x43 0x7A 0xBC 0x2C 0xBF 0x6B 0xF2 0x09 0x81 0x60 0x28 0xD7 0x17},
+{offset:0xa0, size:32, payload:0x42 0x25 0x44 0xDB 0x92 0x36 0x21 0x7A 0x01 0x52 0x52 0x35 0x81 0xB9 0x96 0xE8 0xE9 0x0C 0x21 0x5F 0x50 0x15 0x6A 0x80 0x0F 0xCE 0x12 0x65 0x15 0x6D 0x7F 0x2D},
+{offset:0xc0, size:32, payload:0x58 0x13 0xE7 0xA4 0x55 0x80 0x3C 0x47 0x98 0x53 0xF0 0xF4 0x17 0x22 0x5A 0x9C 0xF3 0x8C 0xB1 0x8A 0xEF 0xE9 0x89 0x4D 0x58 0x2C 0xEC 0x3F 0xBE 0x22 0xF6 0xDC},
+{offset:0xe0, size:32, payload:0xE9 0x02 0x4B 0x12 0x34 0x47 0xA8 0xE5 0x96 0x11 0x41 0x38 0x3E 0xCC 0x41 0x6F 0x47 0x3D 0xA9 0xE7 0x32 0xB6 0xAD 0xDA 0xCB 0x2F 0xEA 0xC8 0xF9 0x13 0x33 0xCA},
+{offset:0x100, size:32, payload:0x26 0x1D 0x2C 0x12 0xE0 0x36 0x37 0x32 0x9C 0x98 0xBE 0x9E 0x8B 0x9F 0x54 0x00 0xD2 0x14 0x16 0x1E 0x25 0x6E 0x27 0xAE 0x6C 0xE1 0xE4 0xEA 0x11 0x5A 0x79 0x91},
+{offset:0x120, size:32, payload:0x48 0xF1 0x66 0xDF 0xE9 0xFC 0x2D 0xBB 0x24 0x34 0xBD 0xCA 0x29 0xE4 0xEF 0x27 0x69 0x7A 0x6A 0x90 0x49 0x00 0x4D 0xE2 0x20 0xC1 0xF6 0x17 0x1B 0x07 0xC0 0x6E},
+{offset:0x140, size:32, payload:0x36 0x14 0x7C 0x5F 0x2A 0x63 0x22 0xB3 0x35 0x69 0x99 0xBF 0x4F 0x28 0x8F 0x52 0x40 0x08 0x88 0x12 0x77 0xC2 0xE1 0x10 0x0D 0x96 0x03 0xE8 0x1A 0x14 0xE6 0x2C},
+{offset:0x160, size:32, payload:0x48 0x6E 0xF6 0x13 0xA6 0x5D 0x60 0x76 0xAA 0x2A 0x12 0x0E 0xF9 0x5A 0x7E 0xFC 0x29 0x8F 0xCE 0x2E 0x7F 0x38 0xEE 0x9D 0x03 0x1B 0x99 0x0B 0x47 0x41 0xC8 0xBA},
+{offset:0x180, size:32, payload:0x83 0x47 0x28 0x56 0x33 0xE7 0xB9 0x11 0x34 0xA3 0x04 0xBD 0x7A 0xB5 0x7A 0xA4 0xA2 0x68 0xC7 0x21 0x42 0xDA 0x10 0xCB 0x0C 0x94 0xDC 0x35 0x6A 0x64 0x7B 0x12},
+{offset:0x1a0, size:32, payload:0xAA 0x55 0x07 0x76 0xBF 0xB3 0x03 0xE3 0xE3 0xD2 0xFC 0xCD 0x35 0xAE 0xC5 0xC5 0x6C 0xCF 0x79 0x12 0xA9 0x35 0x3E 0xDD 0xE9 0x73 0xA0 0xF8 0xC0 0x13 0x99 0x90},
+{offset:0x1c0, size:32, payload:0x4D 0x1D 0x9B 0xB0 0xDD 0x72 0x59 0x3F 0x93 0x41 0xB4 0x72 0xF4 0x1E 0xF9 0x0D 0x38 0xB7 0x53 0x23 0xD8 0x59 0xCA 0x27 0x5A 0x50 0xF1 0x09 0xFB 0xD5 0x5C 0xCD},
+{offset:0x1e0, size:32, payload:0x13 0x2C 0xEC 0x4D 0x76 0x0D 0xDA 0xAF 0x93 0x6A 0x83 0x6A 0x6B 0x5F 0x75 0x92 0x08 0x39 0x1A 0xC3 0x14 0x08 0x77 0x47 0x0F 0x1F 0xA3 0x31 0xDC 0x98 0x51 0xA7},
+{offset:0x200, size:32, payload:0x1E 0x70 0x7D 0x3E 0x99 0xB0 0xFF 0x11 0x35 0x61 0xF3 0x3F 0x60 0x38 0x66 0x36 0xB6 0x44 0xA3 0x97 0x7C 0xDC 0x9D 0x17 0xF6 0x2D 0xE8 0x15 0x4D 0x49 0x4E 0x49},
+{offset:0x220, size:32, payload:0xDA 0x8F 0x24 0x99 0x0E 0x42 0x9D 0xC2 0x91 0xCF 0xA4 0x60 0xF2 0x4A 0x8B 0x62 0xA6 0xF6 0x0A 0x71 0x41 0x22 0x95 0xA6 0xCD 0xD9 0x56 0xC5 0xE2 0xE8 0xDD 0x0B},
+{offset:0x240, size:32, payload:0x32 0xEF 0xC4 0xBB 0xAE 0x64 0xBF 0x30 0x05 0xB4 0x43 0x3E 0xC5 0xD6 0xF6 0x89 0xF8 0x86 0xE7 0x49 0x15 0xA7 0x3B 0xA1 0xF7 0x86 0x4B 0xF2 0x10 0xE9 0xCE 0xCF},
+{offset:0x260, size:32, payload:0xEC 0x6E 0x67 0x6D 0xC2 0xB5 0xE7 0x93 0x1C 0xE8 0x33 0x97 0x5D 0x86 0xA2 0xE1 0xD1 0xA7 0x22 0x82 0x32 0xC0 0xA2 0xFE 0x04 0xFA 0xB2 0xF9 0xBC 0x95 0x95 0xA4},
+{offset:0x280, size:32, payload:0x20 0xDB 0x6C 0x53 0x93 0x80 0x62 0x5B 0x9A 0x59 0x9D 0x55 0xD6 0x71 0xC4 0x9E 0x27 0x1D 0x9E 0x66 0x97 0x6E 0xFE 0x31 0xA3 0xEE 0xD8 0x00 0x68 0xBD 0x79 0x93},
+{offset:0x2a0, size:32, payload:0x47 0xBB 0x18 0x4D 0x17 0xBC 0x36 0xFD 0xD4 0xB8 0xC4 0x6E 0xD6 0x7C 0xAC 0xA2 0xC2 0x3E 0xF7 0x7C 0x44 0x66 0xD9 0x31 0xE5 0x8F 0x25 0x6C 0xB8 0xB2 0xBC 0xC1},
+{offset:0x2c0, size:32, payload:0x4E 0xC8 0xB6 0x45 0x54 0xD4 0xA7 0xF3 0x50 0x7A 0x8B 0x38 0xE3 0xA3 0x23 0xEC 0x0F 0x72 0x56 0x5E 0xF9 0x45 0x6D 0x38 0x8C 0xD5 0xFA 0x6B 0xE1 0xD7 0x84 0x74},
+{offset:0x2e0, size:32, payload:0xD3 0x94 0xE1 0x4A 0xF9 0x02 0x7A 0x38 0xBE 0x93 0x91 0x30 0x4D 0xB0 0x50 0xDA 0xF0 0x0E 0x22 0x1C 0x74 0x01 0xAE 0x28 0x38 0xA2 0x9F 0x7C 0xC6 0x99 0x0A 0xF9},
+{offset:0x300, size:32, payload:0x83 0x01 0x6E 0xE9 0x01 0x93 0xF5 0x12 0x32 0xD5 0xEA 0xEA 0x80 0xCD 0xFF 0xB8 0xF6 0x41 0x65 0x13 0xDA 0xC5 0x31 0xF5 0x4E 0xFD 0x6C 0x84 0x9D 0xB4 0xF5 0xB4},
+{offset:0x320, size:32, payload:0x96 0x9B 0x27 0x7F 0xC3 0xB2 0xFB 0x1F 0x1F 0xF3 0xEC 0x31 0x11 0x0B 0xD7 0xB4 0xB1 0xCC 0x7E 0x02 0x4A 0xFE 0xA0 0xC2 0x3A 0xBA 0x38 0xF6 0xE2 0x29 0x28 0xDB},
+{offset:0x340, size:32, payload:0xB9 0xD0 0x82 0xA9 0x47 0x31 0x65 0xE0 0xCC 0x56 0x82 0x42 0xAE 0x00 0xAA 0x15 0x15 0x55 0x65 0x7B 0xDC 0xA4 0xB0 0x2F 0x5C 0x9E 0x2C 0xAF 0x5D 0x93 0xD7 0xC9},
+{offset:0x360, size:32, payload:0xC9 0x30 0x06 0x69 0x1C 0x85 0x7E 0x4A 0x28 0xC2 0x27 0x49 0x19 0x3B 0x05 0x0B 0x5B 0xC0 0x76 0xE5 0x81 0xCD 0x4E 0xCA 0xD0 0xFC 0x86 0xE6 0x9C 0x00 0x14 0x75},
+{offset:0x380, size:32, payload:0xE6 0x4B 0x8E 0x32 0x32 0x44 0x46 0x18 0xA4 0x50 0x77 0x5B 0xC0 0xBD 0x85 0x4B 0x63 0x8D 0xA3 0x2F 0x32 0xC6 0xB3 0xA6 0xEB 0x63 0x2C 0x05 0x64 0xF8 0x35 0x52},
+{offset:0x3a0, size:32, payload:0x45 0x8B 0xA6 0xCE 0x1A 0x76 0x91 0xF5 0x43 0x5F 0x34 0xB4 0x61 0xAF 0xF4 0x63 0x38 0xAE 0xB3 0xC3 0x41 0x29 0xA1 0xB3 0xD4 0x0C 0xC1 0xB6 0x45 0x44 0x15 0x39},
+{offset:0x3c0, size:32, payload:0x87 0xA6 0x2D 0xFE 0xDC 0xF3 0x9A 0xEB 0x6C 0x08 0xAD 0x13 0xED 0xAD 0x6D 0x10 0xFE 0x2A 0xEF 0xD5 0x83 0x81 0x8B 0x02 0x28 0xB7 0x28 0x7C 0xBD 0xA7 0x8E 0x01},
+{offset:0x3e0, size:32, payload:0x12 0x08 0xB0 0x83 0x89 0xF4 0xCC 0x8D 0xB3 0x83 0xC7 0xBD 0x67 0xE6 0x90 0x9D 0x2A 0x2C 0x74 0xBE 0x5F 0x5C 0x2E 0x8B 0x36 0xC9 0x72 0x11 0xE3 0x5C 0x56 0xBC},
+{offset:0x400, size:32, payload:0xDE 0xA0 0x66 0x41 0x1F 0x85 0x59 0xA3 0x1F 0xA3 0x26 0xFF 0xC2 0xC6 0xB4 0x1E 0xE3 0x3F 0x42 0x1F 0x9A 0x7B 0x83 0xB6 0x0B 0xB2 0x5E 0xBC 0x3E 0x93 0xDA 0x62},
+{offset:0x420, size:32, payload:0xE5 0xF5 0xE3 0x0C 0xF7 0x1E 0x14 0xA5 0x25 0x95 0x81 0x10 0x1A 0x46 0xB1 0x82 0xF7 0x3A 0x39 0x81 0x6F 0x40 0x1A 0x40 0x2F 0xD2 0x7F 0x53 0x51 0x17 0x12 0xBD},
+{offset:0x440, size:32, payload:0x00 0xD8 0xB1 0x38 0x2D 0x6F 0x0A 0xEC 0x6D 0xF6 0xE6 0x0F 0xC4 0xD0 0x90 0x5B 0xF1 0xE0 0x55 0x82 0xAA 0xD9 0xD0 0x66 0xE4 0x86 0x03 0x18 0xA4 0xE1 0xD6 0xAD},
+{offset:0x460, size:32, payload:0xCD 0xD7 0x66 0x31 0xE1 0x6C 0x27 0x3D 0x52 0xB0 0x2E 0x1F 0xFB 0xAB 0x00 0x59 0x3E 0x0C 0x72 0x10 0x60 0xB4 0xBB 0x37 0xF3 0x45 0x85 0x4E 0x43 0x39 0xDC 0x39},
+{offset:0x480, size:32, payload:0xF3 0x8F 0x96 0x86 0x49 0x30 0xDD 0xF4 0xA4 0xEC 0x02 0x86 0xE3 0x88 0x22 0x5B 0xF1 0x67 0x7D 0x28 0x8F 0xAA 0xF1 0x0E 0x7F 0x7C 0x43 0x0D 0xFE 0xFB 0x29 0x97},
+{offset:0x4a0, size:32, payload:0x55 0x2E 0x9A 0xF4 0x10 0xC7 0xD2 0x18 0xEE 0x5B 0x1B 0x16 0xCF 0xCE 0xC3 0x24 0xEF 0x2C 0x06 0x65 0x2D 0x7A 0x9D 0xA4 0x79 0x82 0x39 0x2E 0x42 0xA2 0xEF 0xCC},
+{offset:0x4c0, size:32, payload:0xCD 0x87 0x0A 0x64 0x8B 0x04 0xC4 0xD5 0x05 0xFF 0xCD 0x0C 0xC4 0x7D 0x76 0x3C 0xE3 0x94 0x74 0xB0 0x36 0xAF 0xBD 0x5E 0x45 0x67 0x58 0x1F 0xF8 0xA8 0x2F 0xB0},
+{offset:0x4e0, size:32, payload:0x5C 0x70 0x31 0xB2 0xF4 0x42 0xEC 0x79 0x7B 0x4B 0x16 0x9C 0x49 0x56 0x85 0x54 0x65 0xD6 0x37 0xC0 0x8D 0xDA 0xEF 0xD7 0xFA 0xA3 0x35 0xEE 0x12 0x65 0xCC 0x12},
+{offset:0x500, size:32, payload:0xE5 0xC3 0xD8 0xCD 0x31 0xE5 0xCA 0xF4 0x55 0x00 0x32 0x6E 0xD6 0x4D 0x01 0x60 0x2A 0x05 0x14 0x2C 0x8A 0xAF 0x91 0x64 0x37 0x3D 0x78 0xF8 0x29 0x42 0x1A 0x5D},
+{offset:0x520, size:32, payload:0x74 0x54 0x44 0x1F 0x58 0x47 0x26 0xBB 0xBA 0xCF 0x59 0xE7 0x9A 0x27 0xB2 0xC6 0xC4 0x23 0xD7 0xA7 0x3B 0x6E 0xD7 0xDF 0x34 0x7D 0xDC 0xAF 0xA5 0x24 0xDC 0xA2},
+{offset:0x540, size:32, payload:0x07 0x0F 0x7D 0x61 0xAA 0x7D 0x13 0xCD 0x2E 0xD5 0x29 0xDA 0x20 0xE2 0xF6 0xDB 0x4F 0x92 0xF4 0x8C 0x48 0xF8 0x02 0x5C 0xAD 0xAB 0xE4 0xB4 0x8D 0x8B 0x84 0x2D},
+{offset:0x560, size:32, payload:0x5A 0xAE 0x8C 0x38 0xAF 0xCD 0x38 0x95 0x18 0x63 0x4F 0x94 0x39 0x07 0xC8 0x85 0x42 0x33 0xC9 0x2E 0xB0 0xF6 0x5A 0xB4 0xA7 0xB9 0xE1 0xE4 0xC7 0xB5 0x1D 0x4F},
+{offset:0x580, size:32, payload:0x46 0x8A 0xB6 0xFF 0xB7 0xBB 0xF0 0xB1 0xC6 0xAC 0x9E 0xD1 0x5D 0x8A 0x7D 0xCF 0x07 0x22 0x5B 0x10 0x99 0xC7 0xB2 0xA3 0x7A 0xFA 0xC3 0xED 0x9E 0xEA 0x18 0xFF},
+{offset:0x5a0, size:32, payload:0x3E 0xD4 0xB9 0x40 0xFA 0x55 0x21 0xB4 0xEA 0x26 0xF9 0xF5 0x5D 0x48 0x93 0x67 0x7D 0x55 0x6A 0x5A 0xA9 0x05 0x02 0x01 0x07 0xEF 0xB3 0x82 0x49 0xD9 0x44 0x6C},
+{offset:0x5c0, size:32, payload:0xC4 0x35 0xDB 0x5D 0xCD 0x1D 0x62 0xCF 0x8C 0xAA 0xEC 0x7E 0x4E 0xAF 0x9E 0xEC 0x3E 0x27 0xFB 0xF3 0x1E 0x83 0xC2 0xE9 0x5A 0x40 0xCB 0x8B 0x97 0x86 0x3A 0x9F},
+{offset:0x5e0, size:32, payload:0xD5 0x08 0x4C 0xD7 0xFE 0x4E 0x5F 0x4B 0x61 0x8A 0xE4 0x69 0x8A 0xE3 0x3A 0x43 0x45 0x9B 0xEC 0x2D 0xDB 0x20 0xB2 0x67 0xBB 0x3E 0xBD 0x66 0x2F 0x41 0x8B 0xC0},
+{offset:0x600, size:32, payload:0x4C 0xDC 0xAF 0x6B 0x6E 0xA2 0x32 0xC3 0x05 0x69 0x6F 0x62 0xFA 0x4F 0x09 0x7B 0xB9 0x91 0x4E 0x23 0x3F 0x4D 0x2D 0x8A 0x58 0x9A 0x8E 0x86 0xE8 0x6B 0x52 0xA7},
+{offset:0x620, size:32, payload:0x1E 0x0C 0x1F 0xC6 0xCA 0x8C 0xC0 0x0F 0x2B 0xE9 0x3D 0x98 0x16 0x91 0x1F 0x40 0x94 0xE2 0x4A 0xB5 0xEB 0x67 0xA5 0xFA 0xAD 0x9A 0x72 0xE2 0x60 0xDC 0x6D 0xA8},
+{offset:0x640, size:32, payload:0x8F 0xA0 0xDE 0x6B 0x4D 0xCF 0x93 0xE7 0xEF 0xD1 0x46 0x0F 0xE6 0xEE 0x72 0x2E 0xA9 0x8B 0xE0 0xB6 0xFA 0x0E 0x08 0x5D 0xA8 0x71 0x24 0x30 0x31 0xD3 0x73 0x5E},
+{offset:0x660, size:32, payload:0x06 0x04 0x9F 0x1D 0x35 0xD5 0x44 0x11 0x60 0x8C 0x2C 0xD9 0x16 0xAE 0x48 0xE1 0x54 0x80 0x28 0x33 0x22 0xED 0x7E 0x3D 0xFD 0x22 0x88 0xC2 0x4D 0x85 0x5C 0xCE},
+{offset:0x680, size:32, payload:0xC6 0x66 0x9A 0x30 0xA7 0x9E 0xE8 0x29 0xBF 0x78 0xF7 0x32 0xF5 0x63 0x80 0xC7 0x0B 0xA8 0x1E 0x79 0x7A 0x65 0x80 0x52 0x19 0xDC 0x0E 0x04 0x4F 0xEE 0x8D 0x52},
+{offset:0x6a0, size:32, payload:0x30 0x92 0xA9 0x65 0x29 0x78 0xF3 0x87 0xAC 0xD3 0x7C 0xEC 0x57 0x5E 0x7A 0x05 0x41 0xFF 0x98 0x76 0xAC 0x83 0x98 0xC8 0xA6 0xF0 0x04 0x60 0x17 0x16 0x04 0x1C},
+{offset:0x6c0, size:32, payload:0x44 0xD8 0xFA 0xA4 0xD2 0xED 0x3D 0xF7 0xF4 0x31 0x9D 0x4B 0x1F 0xD6 0xC2 0x0D 0x2C 0xD8 0x6D 0xFA 0x9F 0x02 0x5F 0xA0 0xD5 0x20 0x74 0xF5 0x91 0xB9 0xE7 0x1A},
+{offset:0x6e0, size:32, payload:0xA3 0x0D 0x35 0x48 0x43 0x32 0xA8 0xA6 0x3B 0xE3 0xB0 0xB0 0x5E 0x44 0x3C 0x28 0x3C 0x1E 0xDD 0xA6 0x75 0x2D 0x57 0x69 0xD1 0x23 0x31 0x08 0xB2 0x8B 0xB6 0xAB},
+{offset:0x700, size:32, payload:0x47 0x62 0x6E 0x05 0x09 0x9A 0xB3 0xF3 0xAE 0x72 0x87 0xD7 0x72 0x0C 0xB5 0xEC 0xD3 0x10 0x00 0x69 0x72 0xF8 0xDE 0x1A 0x73 0xD8 0x7E 0x7A 0x29 0xBC 0x3C 0xBD},
+{offset:0x720, size:32, payload:0x76 0xD4 0x2B 0x60 0x1F 0xE4 0x74 0xA3 0x1C 0x32 0xA7 0x99 0x4B 0x64 0x57 0x6C 0x03 0x6F 0xC4 0xBD 0xC9 0xAD 0xF1 0x36 0x4B 0xA6 0x20 0xB7 0x30 0xC7 0x7D 0xD3},
+{offset:0x740, size:32, payload:0xD4 0x0A 0x32 0xD5 0x0F 0x47 0xE4 0x9B 0x47 0x7A 0x3A 0x11 0x8A 0x50 0x82 0x3D 0x25 0xE6 0x33 0x23 0x11 0xA4 0x2A 0x65 0x03 0x2C 0x5C 0x3B 0xF9 0xB8 0x7E 0xDF},
+{offset:0x760, size:32, payload:0x62 0x3D 0x31 0xC9 0x88 0x16 0xBC 0xC0 0xA5 0xE5 0x26 0x60 0x54 0xCE 0xF4 0x20 0x01 0xEB 0x08 0x16 0x04 0x2C 0x70 0x4D 0x14 0x9C 0x5E 0xDD 0xBB 0xAF 0x23 0xDA},
+{offset:0x780, size:32, payload:0xD7 0xF1 0xF2 0xC1 0x40 0xDE 0x43 0x2C 0xC6 0x1A 0xF6 0x67 0xBF 0x0C 0x90 0xD0 0xC5 0x12 0x6A 0xBA 0x56 0x07 0x58 0x2A 0xDA 0x9E 0x4D 0xB0 0xC8 0x9B 0x2E 0x2F},
+{offset:0x7a0, size:32, payload:0xBE 0x10 0xDD 0x03 0x8E 0x7C 0x9A 0x2E 0x61 0x25 0x44 0xC0 0xA0 0xE0 0x68 0xD4 0xD6 0x2C 0xFB 0x99 0x98 0xD9 0x12 0x86 0x04 0x33 0xC7 0x2E 0x72 0xD2 0x13 0x53},
+{offset:0x7c0, size:32, payload:0x71 0xCA 0x54 0xC4 0x5B 0x35 0x75 0xCE 0xFD 0xB0 0x57 0x90 0x7B 0x8C 0xE2 0x1D 0xB6 0xC7 0xF0 0xBF 0xA2 0x9F 0xAB 0x4E 0xD7 0xEC 0xA0 0xC4 0x47 0x0E 0xE8 0x62},
+{offset:0x7e0, size:32, payload:0x5D 0x1D 0x4D 0xD8 0x67 0x5E 0x77 0xD7 0x5F 0x77 0xA6 0x5F 0x67 0x94 0x48 0x51 0xB5 0x96 0x91 0x53 0x13 0xED 0xA4 0xE2 0x51 0x66 0xDD 0xD6 0x6F 0x37 0x3C 0x31},
\ No newline at end of file
diff --git a/cl_nvdla/software/traces/cdp_8x8x32_lrn3_int8_1/cdp_8x8x32_lrn3_int8_1.cfg b/cl_nvdla/software/traces/cdp_8x8x32_lrn3_int8_1/cdp_8x8x32_lrn3_int8_1.cfg
new file mode 100644
index 0000000..46641d5
--- /dev/null
+++ b/cl_nvdla/software/traces/cdp_8x8x32_lrn3_int8_1/cdp_8x8x32_lrn3_int8_1.cfg
@@ -0,0 +1,455 @@
+// NVDLA TRACE config: cdp_passthrough_8x8x32_pack_inc
+//---------- Layer:CDP_0, scenario:CDP----------
+//----------## Layer:CDP_0: memory preparation, begin----------
+mem_load(pri_mem, 0xC0080000, "CDP_0_output.dat");
+mem_load(pri_mem, 0xC0000000, "CDP_0_input.dat");
+//----------## Layer:CDP_0: memory preparation, end----------
+//----------## Layer:CDP_0: cross layer dependency, begin----------
+//----------## Layer:CDP_0: cross layer dependency, end----------
+//----------## Layer:CDP_0: set producer pointer, begin----------
+reg_write(NVDLA_CDP.S_POINTER_0, 0);
+reg_write(NVDLA_CDP_RDMA.S_POINTER_0, 0);
+//----------## Layer:CDP_0: set producer pointer, end----------
+//----------## Layer:CDP_0: LUT programming, begin----------
+reg_write(NVDLA_CDP.S_LUT_ACCESS_CFG_0, 0x30000);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x0);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x4);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x5);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x6);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x7);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x8);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x9);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x10);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x11);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x12);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x13);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x14);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x15);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x16);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x17);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x18);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x19);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x20);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x21);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x22);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x23);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x24);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x25);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x26);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x27);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x28);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x29);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x30);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x31);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x32);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x33);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x34);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x35);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x36);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x37);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x38);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x39);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x40);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x41);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x42);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x43);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x44);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x45);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x46);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x47);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x48);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x49);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x4a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x4b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x4c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x4d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x4e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x4f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x50);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x51);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x52);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x53);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x54);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x55);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x56);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x57);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x58);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x59);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x5a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x5b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x5c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x5d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x5e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x5f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x60);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x61);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x62);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x63);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x64);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x65);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x66);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x67);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x68);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x69);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x6a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x6b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x6c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x6d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x6e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x6f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x70);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x71);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x72);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x73);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x74);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x75);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x76);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x77);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x78);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x79);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x7a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x7b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x7c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x7d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x7e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x7f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x80);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x81);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x82);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x83);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x84);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x85);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x86);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x87);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x88);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x89);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x8a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x8b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x8c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x8d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x8e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x8f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x90);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x91);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x92);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x93);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x94);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x95);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x96);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x97);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x98);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x99);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x9a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x9b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x9c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x9d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x9e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x9f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa0);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa1);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa2);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa3);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa4);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa5);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa6);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa7);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa8);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa9);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xaa);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xab);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xac);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xad);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xae);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xaf);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb0);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb1);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb2);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb3);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb4);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb5);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb6);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb7);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb8);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb9);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xba);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xbb);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xbc);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xbd);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xbe);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xbf);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc0);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc1);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc2);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc3);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc4);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc5);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc6);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc7);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc8);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc9);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xca);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xcb);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xcc);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xcd);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xce);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xcf);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd0);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd1);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd2);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd3);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd4);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd5);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd6);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd7);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd8);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd9);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xda);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xdb);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xdc);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xdd);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xde);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xdf);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe0);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe1);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe2);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe3);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe4);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe5);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe6);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe7);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe8);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe9);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xea);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xeb);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xec);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xed);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xee);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xef);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf0);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf1);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf2);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf3);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf4);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf5);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf6);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf7);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf8);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf9);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xfa);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xfb);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xfc);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xfd);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xfe);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xff);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x100);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_CFG_0, 0x20000);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x0);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x4);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x5);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x6);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x7);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x8);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x9);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xa);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xb);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xc);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xd);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xe);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0xf);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x10);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x11);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x12);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x13);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x14);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x15);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x16);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x17);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x18);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x19);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x1f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x20);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x21);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x22);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x23);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x24);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x25);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x26);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x27);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x28);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x29);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x2f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x30);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x31);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x32);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x33);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x34);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x35);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x36);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x37);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x38);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x39);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3a);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3b);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3c);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3d);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3e);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x3f);
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x40);
+reg_write(NVDLA_CDP.S_LUT_LE_START_LOW_0, 0x0);
+// NVDLA_CDP.S_LUT_LE_START_LOW_0.LUT_LE_START_LOW:0x0
+reg_write(NVDLA_CDP.S_LUT_LO_END_LOW_0, 0x100);
+// NVDLA_CDP.S_LUT_LO_END_LOW_0.LUT_LO_END_LOW:0x100
+reg_write(NVDLA_CDP.S_LUT_ACCESS_CFG_0, 0x0);
+// NVDLA_CDP.S_LUT_ACCESS_CFG_0.LUT_ACCESS_TYPE:READ : 0x0
+// NVDLA_CDP.S_LUT_ACCESS_CFG_0.LUT_TABLE_ID:LE : 0x0
+// NVDLA_CDP.S_LUT_ACCESS_CFG_0.LUT_ADDR:0x0
+reg_write(NVDLA_CDP.S_LUT_ACCESS_DATA_0, 0x0);
+// NVDLA_CDP.S_LUT_ACCESS_DATA_0.LUT_DATA:0x0
+reg_write(NVDLA_CDP.S_LUT_LE_START_HIGH_0, 0x0);
+// NVDLA_CDP.S_LUT_LE_START_HIGH_0.LUT_LE_START_HIGH:0x0
+reg_write(NVDLA_CDP.S_LUT_LO_END_HIGH_0, 0x0);
+// NVDLA_CDP.S_LUT_LO_END_HIGH_0.LUT_LO_END_HIGH:0x0
+reg_write(NVDLA_CDP.S_LUT_CFG_0, 0x1);
+// NVDLA_CDP.S_LUT_CFG_0.LUT_UFLOW_PRIORITY:LE : 0x0
+// NVDLA_CDP.S_LUT_CFG_0.LUT_OFLOW_PRIORITY:LE : 0x0
+// NVDLA_CDP.S_LUT_CFG_0.LUT_HYBRID_PRIORITY:LE : 0x0
+// NVDLA_CDP.S_LUT_CFG_0.LUT_LE_FUNCTION:LINEAR : 0x1
+reg_write(NVDLA_CDP.S_LUT_LE_SLOPE_SHIFT_0, 0x0);
+// NVDLA_CDP.S_LUT_LE_SLOPE_SHIFT_0.LUT_LE_SLOPE_OFLOW_SHIFT:0x0
+// NVDLA_CDP.S_LUT_LE_SLOPE_SHIFT_0.LUT_LE_SLOPE_UFLOW_SHIFT:0x0
+reg_write(NVDLA_CDP.S_LUT_LE_SLOPE_SCALE_0, 0x0);
+// NVDLA_CDP.S_LUT_LE_SLOPE_SCALE_0.LUT_LE_SLOPE_UFLOW_SCALE:0x0
+// NVDLA_CDP.S_LUT_LE_SLOPE_SCALE_0.LUT_LE_SLOPE_OFLOW_SCALE:0x0
+reg_write(NVDLA_CDP.S_LUT_INFO_0, 0x0);
+// NVDLA_CDP.S_LUT_INFO_0.LUT_LE_INDEX_SELECT:0x0
+// NVDLA_CDP.S_LUT_INFO_0.LUT_LE_INDEX_OFFSET:0x0
+// NVDLA_CDP.S_LUT_INFO_0.LUT_LO_INDEX_SELECT:0x0
+reg_write(NVDLA_CDP.S_LUT_LE_END_LOW_0, 0x40);
+// NVDLA_CDP.S_LUT_LE_END_LOW_0.LUT_LE_END_LOW:0x40
+reg_write(NVDLA_CDP.S_LUT_LO_SLOPE_SCALE_0, 0x0);
+// NVDLA_CDP.S_LUT_LO_SLOPE_SCALE_0.LUT_LO_SLOPE_OFLOW_SCALE:0x0
+// NVDLA_CDP.S_LUT_LO_SLOPE_SCALE_0.LUT_LO_SLOPE_UFLOW_SCALE:0x0
+reg_write(NVDLA_CDP.S_LUT_LE_END_HIGH_0, 0x0);
+// NVDLA_CDP.S_LUT_LE_END_HIGH_0.LUT_LE_END_HIGH:0x0
+reg_write(NVDLA_CDP.S_LUT_LO_START_HIGH_0, 0x0);
+// NVDLA_CDP.S_LUT_LO_START_HIGH_0.LUT_LO_START_HIGH:0x0
+reg_write(NVDLA_CDP.S_LUT_LO_START_LOW_0, 0x0);
+// NVDLA_CDP.S_LUT_LO_START_LOW_0.LUT_LO_START_LOW:0x0
+reg_write(NVDLA_CDP.S_LUT_LO_SLOPE_SHIFT_0, 0x0);
+// NVDLA_CDP.S_LUT_LO_SLOPE_SHIFT_0.LUT_LO_SLOPE_UFLOW_SHIFT:0x0
+// NVDLA_CDP.S_LUT_LO_SLOPE_SHIFT_0.LUT_LO_SLOPE_OFLOW_SHIFT:0x0
+//----------## Layer:CDP_0: LUT programming, end----------
+//----------## Layer:CDP_0: configuraion, begin----------
+reg_write(NVDLA_CDP.D_DATOUT_OFFSET_0, 0x80);
+// NVDLA_CDP.D_DATOUT_OFFSET_0.DATOUT_OFFSET:0x80
+reg_write(NVDLA_CDP.D_DST_SURFACE_STRIDE_0, 0x200);
+// NVDLA_CDP.D_DST_SURFACE_STRIDE_0.DST_SURFACE_STRIDE:0x40
+reg_write(NVDLA_CDP_RDMA.D_SRC_BASE_ADDR_LOW_0, 0xC0000000);
+// NVDLA_CDP_RDMA.D_SRC_BASE_ADDR_LOW_0.SRC_BASE_ADDR_LOW:0x4000000
+reg_write(NVDLA_CDP.D_DST_DMA_CFG_0, 0x1);
+// NVDLA_CDP.D_DST_DMA_CFG_0.DST_RAM_TYPE:MC : 0x1
+reg_write(NVDLA_CDP_RDMA.D_DATA_CUBE_WIDTH_0, 0x7);
+// NVDLA_CDP_RDMA.D_DATA_CUBE_WIDTH_0.WIDTH:0x7
+reg_write(NVDLA_CDP_RDMA.D_DATA_FORMAT_0, 0x0);
+// NVDLA_CDP_RDMA.D_DATA_FORMAT_0.INPUT_DATA:INT8 : 0x0
+reg_write(NVDLA_CDP.D_DATIN_SCALE_0, 0x1);
+// NVDLA_CDP.D_DATIN_SCALE_0.DATIN_SCALE:0x1
+reg_write(NVDLA_CDP.D_DATOUT_SHIFTER_0, 0x0);
+// NVDLA_CDP.D_DATOUT_SHIFTER_0.DATOUT_SHIFTER:0x0
+reg_write(NVDLA_CDP.D_CYA_0, 0x0);
+// NVDLA_CDP.D_CYA_0.CYA:0x0
+reg_write(NVDLA_CDP_RDMA.D_PERF_ENABLE_0, 0x0);
+// NVDLA_CDP_RDMA.D_PERF_ENABLE_0.DMA_EN:DISABLE : 0x0
+reg_write(NVDLA_CDP.D_LRN_CFG_0, 0x0);
+// NVDLA_CDP.D_LRN_CFG_0.NORMALZ_LEN:LEN3 : 0x0
+reg_write(NVDLA_CDP_RDMA.D_DATA_CUBE_CHANNEL_0, 0x1f);
+// NVDLA_CDP_RDMA.D_DATA_CUBE_CHANNEL_0.CHANNEL:0x1f
+reg_write(NVDLA_CDP.D_DATA_FORMAT_0, 0x0);
+// NVDLA_CDP.D_DATA_FORMAT_0.INPUT_DATA_TYPE:INT8 : 0x0
+reg_write(NVDLA_CDP.D_DATIN_SHIFTER_0, 0x0);
+// NVDLA_CDP.D_DATIN_SHIFTER_0.DATIN_SHIFTER:0x0
+reg_write(NVDLA_CDP.D_PERF_ENABLE_0, 0x0);
+// NVDLA_CDP.D_PERF_ENABLE_0.LUT_EN:DISABLE : 0x0
+// NVDLA_CDP.D_PERF_ENABLE_0.DMA_EN:DISABLE : 0x0
+reg_write(NVDLA_CDP_RDMA.D_SRC_BASE_ADDR_HIGH_0, 0x0);
+// NVDLA_CDP_RDMA.D_SRC_BASE_ADDR_HIGH_0.SRC_BASE_ADDR_HIGH:0x0
+reg_write(NVDLA_CDP.D_DST_BASE_ADDR_HIGH_0, 0x0);
+// NVDLA_CDP.D_DST_BASE_ADDR_HIGH_0.DST_BASE_ADDR_HIGH:0x0
+reg_write(NVDLA_CDP_RDMA.D_SRC_DMA_CFG_0, 0x1);
+// NVDLA_CDP_RDMA.D_SRC_DMA_CFG_0.SRC_RAM_TYPE:MC : 0x1
+reg_write(NVDLA_CDP.D_DATOUT_SCALE_0, 0x1);
+// NVDLA_CDP.D_DATOUT_SCALE_0.DATOUT_SCALE:0x1
+reg_write(NVDLA_CDP.D_DATIN_OFFSET_0, 0x80);
+// NVDLA_CDP.D_DATIN_OFFSET_0.DATIN_OFFSET:0x80
+reg_write(NVDLA_CDP.D_NAN_FLUSH_TO_ZERO_0, 0x0);
+// NVDLA_CDP.D_NAN_FLUSH_TO_ZERO_0.NAN_TO_ZERO:DISABLE : 0x0
+reg_write(NVDLA_CDP.D_FUNC_BYPASS_0, 0x3);
+// NVDLA_CDP.D_FUNC_BYPASS_0.SQSUM_BYPASS:ENABLE : 0x1
+// NVDLA_CDP.D_FUNC_BYPASS_0.MUL_BYPASS:ENABLE : 0x1
+reg_write(NVDLA_CDP.D_DST_BASE_ADDR_LOW_0, 0xC0080000);
+// NVDLA_CDP.D_DST_BASE_ADDR_LOW_0.DST_BASE_ADDR_LOW:0x4004000
+reg_write(NVDLA_CDP_RDMA.D_CYA_0, 0x0);
+// NVDLA_CDP_RDMA.D_CYA_0.CYA:0x0
+reg_write(NVDLA_CDP_RDMA.D_SRC_SURFACE_STRIDE_0, 0x200);
+// NVDLA_CDP_RDMA.D_SRC_SURFACE_STRIDE_0.SRC_SURFACE_STRIDE:0x40
+reg_write(NVDLA_CDP.D_DST_LINE_STRIDE_0, 0x40);
+// NVDLA_CDP.D_DST_LINE_STRIDE_0.DST_LINE_STRIDE:0x8
+reg_write(NVDLA_CDP_RDMA.D_SRC_LINE_STRIDE_0, 0x40);
+// NVDLA_CDP_RDMA.D_SRC_LINE_STRIDE_0.SRC_LINE_STRIDE:0x8
+reg_write(NVDLA_CDP_RDMA.D_DATA_CUBE_HEIGHT_0, 0x7);
+// NVDLA_CDP_RDMA.D_DATA_CUBE_HEIGHT_0.HEIGHT:0x7
+//----------## Layer:CDP_0: configuraion, end----------
+//----------## Layer:CDP_0: operation enable, begin----------
+//----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP_RDMA, begin --
+reg_write(NVDLA_CDP_RDMA.D_OP_ENABLE_0,0x1);
+//----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP_RDMA, end --
+//----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP, begin --
+reg_write(NVDLA_CDP.D_OP_ENABLE_0,0x1);
+//----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP, end --
+//----------## Layer:CDP_0: operation enable, end----------
+//----------## Layer:CDP_0: interrupt handling, begin----------
+intr_notify(CDP_0, CDP_0_CDP_0_interrupt);
+//----------## Layer:CDP_0: interrupt handling, end----------
+//----------## Layer:CDP_0: result checker, begin----------
+check_crc(CDP_0_CDP_0_interrupt, pri_mem, 0xC0080000, 0x800, 0x9f5edd58);
+//----------## Layer:CDP_0: result checker, end----------
diff --git a/cl_nvdla/verif/README.md b/cl_nvdla/verif/README.md
new file mode 100644
index 0000000..99c411d
--- /dev/null
+++ b/cl_nvdla/verif/README.md
@@ -0,0 +1,14 @@
+# CL_NVDLA Simulation
+
+The cl_nvdla includes a basic test that exercises the BAR1, DDR_C, and interrupt.
+
+The test can be run from the [verif/scripts] (scripts) directory with one of three different simulators:
+
+```
+ $ make C_TEST=test_nvdla
+ $ make C_TEST=test_nvdla VCS=1
+ $ make C_TEST=test_nvdla QUESTA=1
+```
+
+Note that the appropriate simulators must be installed.
+
diff --git a/cl_nvdla/verif/regression/Makefile b/cl_nvdla/verif/regression/Makefile
new file mode 100644
index 0000000..9d317ff
--- /dev/null
+++ b/cl_nvdla/verif/regression/Makefile
@@ -0,0 +1,121 @@
+# ================================================================
+# NVDLA Open Source Project
+#
+# Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+# NVDLA Open Hardware License; Check \"LICENSE\" which comes with
+# this distribution for more information.
+# ================================================================
+
+RUN_TEST_MAKEFILE_DIR = $(abspath ../scripts)
+CL_ROOT = $(abspath ../..)
+
+NVDLA_HW_ROOT ?= ../../../../../../hw
+NVDLA_HW_ROOT_FULL_PATH = $(abspath $(NVDLA_HW_ROOT))
+NVDLA_HW_PROJECT ?= nv_small
+
+NVDLA_HW_TRACE_LIST ?= nv_small_sanity
+
+NVDLA_HW_TRACE_DIR ?= $(shell cat $(NVDLA_HW_TRACE_LIST))
+
+NVDLA_HW_TRACE_ROOT ?= $(NVDLA_HW_ROOT_FULL_PATH)/verif/tests/trace_tests/$(NVDLA_HW_PROJECT)
+
+TIMESTAMP := $(shell /bin/date "+%Y-%m-%d_%H-%M-%S")
+
+ifdef AWS_FPGA
+OUT_DIR ?= $(PWD)/regression_$(NVDLA_HW_PROJECT)_$(NVDLA_HW_TRACE_LIST)_$(TIMESTAMP)_AWS_FPGA
+else
+OUT_DIR ?= $(PWD)/regression_$(NVDLA_HW_PROJECT)_$(NVDLA_HW_TRACE_LIST)_$(TIMESTAMP)
+endif
+LSF_GROUP = /regression_$(NVDLA_HW_PROJECT)_$(NVDLA_HW_TRACE_LIST)_$(TIMESTAMP)
+
+CHECK_OUT_DIR ?= $(shell ls -rtd -- regression_* | tail -1)
+
+NVDLA_HW_TRACE_LST_1 = $(wordlist 1,40,$(NVDLA_HW_TRACE_DIR))
+NVDLA_HW_TRACE_LST_2 = $(wordlist 41,81,$(NVDLA_HW_TRACE_DIR))
+
+ifdef AWS_FPGA
+CL_ROOT ?= $(PWD)/../..
+CL_TRACE_TEST_BUILD = $(CL_ROOT)/software/src
+CL_TRACE_TEST_BIN ?= $(OUT_DIR)/$(trace)/test
+RUN_OUT_DIR ?= $(shell ls -rtd -- regression_* | tail -1)
+NVDLA_HW_TRACE_LST_1 = $(wordlist 1,100,$(NVDLA_HW_TRACE_DIR))
+NVDLA_HW_TRACE_LST_2 = $(wordlist 101,200,$(NVDLA_HW_TRACE_DIR))
+endif
+
+.PHONY: all
+all: compile run
+
+compile:
+
+ifdef AWS_FPGA
+ifdef RANDOM_TEST
+ $(foreach trace, $(NVDLA_HW_TRACE_LST_1), \
+ $(eval trace_base := $(shell echo $(trace) | sed 's/_[0-9]//g')) \
+ mkdir -p $(CL_TRACE_TEST_BIN); \
+ make -C $(CL_TRACE_TEST_BUILD) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace_base)/$(trace_base).cfg; \
+ cp $(CL_TRACE_TEST_BUILD)/trace_test $(CL_TRACE_TEST_BIN); \
+ cp $(CL_TRACE_TEST_BUILD)/libtrace_parser_command.so $(CL_TRACE_TEST_BIN); \
+ make -C $(CL_TRACE_TEST_BUILD) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace_base)/$(trace_base).cfg clean;)
+ $(foreach trace, $(NVDLA_HW_TRACE_LST_2), \
+ $(eval trace_base := $(shell echo $(trace) | sed 's/_[0-9]//g')) \
+ mkdir -p $(CL_TRACE_TEST_BIN); \
+ make -C $(CL_TRACE_TEST_BUILD) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace_base)/$(trace_base).cfg; \
+ cp $(CL_TRACE_TEST_BUILD)/trace_test $(CL_TRACE_TEST_BIN); \
+ cp $(CL_TRACE_TEST_BUILD)/libtrace_parser_command.so $(CL_TRACE_TEST_BIN); \
+ make -C $(CL_TRACE_TEST_BUILD) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace_base)/$(trace_base).cfg clean;)
+else
+ $(foreach trace, $(NVDLA_HW_TRACE_LST_1), mkdir -p $(CL_TRACE_TEST_BIN) && make -C $(CL_TRACE_TEST_BUILD) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg && cp $(CL_TRACE_TEST_BUILD)/trace_test $(CL_TRACE_TEST_BIN) && cp $(CL_TRACE_TEST_BUILD)/libtrace_parser_command.so $(CL_TRACE_TEST_BIN) && make -C $(CL_TRACE_TEST_BUILD) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg clean;)
+ $(foreach trace, $(NVDLA_HW_TRACE_LST_2), mkdir -p $(CL_TRACE_TEST_BIN) && make -C $(CL_TRACE_TEST_BUILD) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg && cp $(CL_TRACE_TEST_BUILD)/trace_test $(CL_TRACE_TEST_BIN) && cp $(CL_TRACE_TEST_BUILD)/libtrace_parser_command.so $(CL_TRACE_TEST_BIN) && make -C $(CL_TRACE_TEST_BUILD) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg clean;)
+endif
+else
+ifdef LSF_CMD
+ cd $(RUN_TEST_MAKEFILE_DIR) && $(LSF_CMD) -Is make CL_ROOT=$(CL_ROOT) VCS=1 NVDLA_HW_ROOT=$(NVDLA_HW_ROOT_FULL_PATH) NVDLA_HW_PROJECT=$(NVDLA_HW_PROJECT) TRACE_TEST=1 SIM_BACKDOOR_MEM=1 make_sim_dir compile
+else
+ cd $(RUN_TEST_MAKEFILE_DIR) && make -C $(RUN_TEST_MAKEFILE_DIR) CL_ROOT=$(CL_ROOT) VCS=1 NVDLA_HW_ROOT=$(NVDLA_HW_ROOT_FULL_PATH) NVDLA_HW_PROJECT=$(NVDLA_HW_PROJECT) TRACE_TEST=1 SIM_BACKDOOR_MEM=1 make_sim_dir compile
+endif
+endif
+
+run:
+ifdef AWS_FPGA
+ cd $(RUN_OUT_DIR) && $(foreach trace, $(NVDLA_HW_TRACE_DIR), cd $(trace)/test && echo 'sudo ./trace_test ./libtrace_parser_command.so' > $(trace).sh && chmod +x *.sh && sudo ./trace_test ./libtrace_parser_command.so | tee ../trace_test.log && cd ../..;)
+else
+ mkdir -p $(OUT_DIR)
+ifdef LSF_CMD
+ cd $(OUT_DIR) && echo "bkill -g $(LSF_GROUP) 0" > kill.sh && chmod +x kill.sh && $(foreach trace, $(NVDLA_HW_TRACE_LST_1), mkdir -p $(OUT_DIR)/$(trace) && cd $(OUT_DIR)/$(trace) && cp -r $(NVDLA_HW_TRACE_ROOT)/$(trace) ./ && echo '$(LSF_CMD) -g $(LSF_GROUP) -eo $(trace).log2 -oo $(trace).log make -C $(RUN_TEST_MAKEFILE_DIR) TRACE_TEST=1 RUN_DIR="$(OUT_DIR)/$(trace)" CL_ROOT=$(CL_ROOT) VCS=1 NVDLA_HW_ROOT=$(NVDLA_HW_ROOT_FULL_PATH) NVDLA_HW_PROJECT=$(NVDLA_HW_PROJECT) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg run' > $(trace).cmd.sh && echo 'make -C $(RUN_TEST_MAKEFILE_DIR) TRACE_TEST=1 RUN_DIR="$(OUT_DIR)/$(trace)" CL_ROOT=$(CL_ROOT) VCS=1 NVDLA_HW_ROOT=$(NVDLA_HW_ROOT_FULL_PATH) NVDLA_HW_PROJECT=$(NVDLA_HW_PROJECT) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg run' > $(trace).sh && chmod +x *.sh && $(LSF_CMD) -g $(LSF_GROUP) -eo $(trace).log2 -oo $(trace).log make -C $(RUN_TEST_MAKEFILE_DIR) TRACE_TEST=1 RUN_DIR="$(OUT_DIR)/$(trace)" CL_ROOT=$(CL_ROOT) VCS=1 NVDLA_HW_ROOT=$(NVDLA_HW_ROOT_FULL_PATH) NVDLA_HW_PROJECT=$(NVDLA_HW_PROJECT) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg run;)
+ cd $(OUT_DIR) && echo "bkill -g $(LSF_GROUP) 0" > kill.sh && chmod +x kill.sh && $(foreach trace, $(NVDLA_HW_TRACE_LST_2), mkdir -p $(OUT_DIR)/$(trace) && cd $(OUT_DIR)/$(trace) && cp -r $(NVDLA_HW_TRACE_ROOT)/$(trace) ./ && echo '$(LSF_CMD) -g $(LSF_GROUP) -eo $(trace).log2 -oo $(trace).log make -C $(RUN_TEST_MAKEFILE_DIR) TRACE_TEST=1 RUN_DIR="$(OUT_DIR)/$(trace)" CL_ROOT=$(CL_ROOT) VCS=1 NVDLA_HW_ROOT=$(NVDLA_HW_ROOT_FULL_PATH) NVDLA_HW_PROJECT=$(NVDLA_HW_PROJECT) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg run' > $(trace).cmd.sh && echo 'make -C $(RUN_TEST_MAKEFILE_DIR) TRACE_TEST=1 RUN_DIR="$(OUT_DIR)/$(trace)" CL_ROOT=$(CL_ROOT) VCS=1 NVDLA_HW_ROOT=$(NVDLA_HW_ROOT_FULL_PATH) NVDLA_HW_PROJECT=$(NVDLA_HW_PROJECT) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg run' > $(trace).sh && chmod +x *.sh && $(LSF_CMD) -g $(LSF_GROUP) -eo $(trace).log2 -oo $(trace).log make -C $(RUN_TEST_MAKEFILE_DIR) TRACE_TEST=1 RUN_DIR="$(OUT_DIR)/$(trace)" CL_ROOT=$(CL_ROOT) VCS=1 NVDLA_HW_ROOT=$(NVDLA_HW_ROOT_FULL_PATH) NVDLA_HW_PROJECT=$(NVDLA_HW_PROJECT) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg run;)
+else
+ cd $(OUT_DIR) && $(foreach trace, $(NVDLA_HW_TRACE_DIR), mkdir -p $(OUT_DIR)/$(trace) && cd $(OUT_DIR)/$(trace) && echo 'make -C $(RUN_TEST_MAKEFILE_DIR) TRACE_TEST=1 RUN_DIR="$(OUT_DIR)/$(trace)" CL_ROOT=$(CL_ROOT) VCS=1 NVDLA_HW_ROOT=$(NVDLA_HW_ROOT_FULL_PATH) NVDLA_HW_PROJECT=$(NVDLA_HW_PROJECT) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg run' > $(trace).sh && chmod +x *.sh && make -C $(RUN_TEST_MAKEFILE_DIR) TRACE_TEST=1 RUN_DIR="$(OUT_DIR)/$(trace)" CL_ROOT=$(CL_ROOT) VCS=1 NVDLA_HW_ROOT=$(NVDLA_HW_ROOT_FULL_PATH) NVDLA_HW_PROJECT=$(NVDLA_HW_PROJECT) NVDLA_TRACE=$(NVDLA_HW_TRACE_ROOT)/$(trace)/$(trace).cfg run |& tee $(trace).log;)
+endif
+endif
+
+check:
+ @echo "Regression status: $(CHECK_OUT_DIR)" && cd $(CHECK_OUT_DIR) && $(foreach trace, $(NVDLA_HW_TRACE_DIR), test -f $(trace)/trace_test.log && (grep -sqF -- "Test PASS" $(trace)/trace_test.log && echo -e "\033[0;32mPASS\033[0m: $(trace)" || (grep -sqF -- "Test FAIL" $(trace)/trace_test.log && echo -e "\033[0;31mFAIL\033[0m: $(trace)" || (grep -sqF -- "Test TIMEOUT" $(trace)/trace_test.log && echo -e "\033[0;31mTIMEOUT\033[0m: $(trace)" || echo -e "\033[0;33mINCOMPLETE\033[0m: $(trace)"))) || echo -e "NOTRUN: $(trace)" ;)
+
+kill:
+ @echo "Kill regression: $(CHECK_OUT_DIR)" && $(CHECK_OUT_DIR)/kill.sh
+
+clean:
+ rm -rf regression_*
+
+help:
+ @echo "Running NVDLA-AWS-FPGA trace test regression"
+ @echo ""
+ @echo "Examples:"
+ @echo " make LSF_CMD='' all # compile design and running regression nv_small_sanity"
+ @echo " make LSF_CMD='' run # running regression nv_small_sanity"
+ @echo " make check # check last regression status"
+ @echo " make kill # kill last regression lsf jobs"
+ @echo " make AWS_FPGA=1 all # compile design and running regression with AWS FPGA nv_small_sanity"
+ @echo ""
+ @echo "Options:"
+ @echo " LSF_CMD= # Specify the lsf command"
+ @echo " # Default: empty, meaning all the tests will be running in local host sequentially"
+ @echo " NVDLA_HW_ROOT= # Specify NVDLA HW repository location"
+ @echo " # Default: ../../../../../../hw"
+ @echo " NVDLA_HW_PROJECT= # Specify NVDLA HW project"
+ @echo " # Default: nv_small"
+ @echo " NVDLA_HW_TRACE_LIST= # Specify the testlist to run"
+ @echo " # Default: nv_small_sanity"
+ @echo " CHECK_OUT_DIR= # Specify regression directory that you want to check status"
+ @echo " RUN_OUT_DIR= # Specify regression directory that you want to run"
+ @echo " # Default: the latest regression run directory"
diff --git a/cl_nvdla/verif/regression/nv_small_random b/cl_nvdla/verif/regression/nv_small_random
new file mode 100644
index 0000000..4162701
--- /dev/null
+++ b/cl_nvdla/verif/regression/nv_small_random
@@ -0,0 +1,200 @@
+cc_feature_data_full_reuse_rtest_0
+cc_feature_data_full_reuse_rtest_1
+cc_feature_data_full_reuse_rtest_2
+cc_feature_data_full_reuse_rtest_3
+cc_feature_data_full_reuse_rtest_4
+cc_feature_data_full_reuse_rtest_5
+cc_feature_data_full_reuse_rtest_6
+cc_feature_data_full_reuse_rtest_7
+cc_feature_data_full_reuse_rtest_8
+cc_feature_data_full_reuse_rtest_9
+cc_feature_rtest_0
+cc_feature_rtest_1
+cc_feature_rtest_2
+cc_feature_rtest_3
+cc_feature_rtest_4
+cc_feature_rtest_5
+cc_feature_rtest_6
+cc_feature_rtest_7
+cc_feature_rtest_8
+cc_feature_rtest_9
+cc_feature_weight_full_reuse_rtest_0
+cc_feature_weight_full_reuse_rtest_1
+cc_feature_weight_full_reuse_rtest_2
+cc_feature_weight_full_reuse_rtest_3
+cc_feature_weight_full_reuse_rtest_4
+cc_feature_weight_full_reuse_rtest_5
+cc_feature_weight_full_reuse_rtest_6
+cc_feature_weight_full_reuse_rtest_7
+cc_feature_weight_full_reuse_rtest_8
+cc_feature_weight_full_reuse_rtest_9
+cc_image_data_full_reuse_rtest_0
+cc_image_data_full_reuse_rtest_1
+cc_image_data_full_reuse_rtest_2
+cc_image_data_full_reuse_rtest_3
+cc_image_data_full_reuse_rtest_4
+cc_image_data_full_reuse_rtest_5
+cc_image_data_full_reuse_rtest_6
+cc_image_data_full_reuse_rtest_7
+cc_image_data_full_reuse_rtest_8
+cc_image_data_full_reuse_rtest_9
+cc_pitch_rtest_0
+cc_pitch_rtest_1
+cc_pitch_rtest_2
+cc_pitch_rtest_3
+cc_pitch_rtest_4
+cc_pitch_rtest_5
+cc_pitch_rtest_6
+cc_pitch_rtest_7
+cc_pitch_rtest_8
+cc_pitch_rtest_9
+cc_rtest_0
+cc_rtest_1
+cc_rtest_2
+cc_rtest_3
+cc_rtest_4
+cc_rtest_5
+cc_rtest_6
+cc_rtest_7
+cc_rtest_8
+cc_rtest_9
+cc_sdp_pdp_rtest_0
+cc_sdp_pdp_rtest_1
+cc_sdp_pdp_rtest_2
+cc_sdp_pdp_rtest_3
+cc_sdp_pdp_rtest_4
+cc_sdp_pdp_rtest_5
+cc_sdp_pdp_rtest_6
+cc_sdp_pdp_rtest_7
+cc_sdp_pdp_rtest_8
+cc_sdp_pdp_rtest_9
+cc_sdprdma_sdp_pdp_rtest_0
+cc_sdprdma_sdp_pdp_rtest_1
+cc_sdprdma_sdp_pdp_rtest_2
+cc_sdprdma_sdp_pdp_rtest_3
+cc_sdprdma_sdp_pdp_rtest_4
+cc_sdprdma_sdp_pdp_rtest_5
+cc_sdprdma_sdp_pdp_rtest_6
+cc_sdprdma_sdp_pdp_rtest_7
+cc_sdprdma_sdp_pdp_rtest_8
+cc_sdprdma_sdp_pdp_rtest_9
+cc_sdprdma_sdp_rtest_0
+cc_sdprdma_sdp_rtest_1
+cc_sdprdma_sdp_rtest_2
+cc_sdprdma_sdp_rtest_3
+cc_sdprdma_sdp_rtest_4
+cc_sdprdma_sdp_rtest_5
+cc_sdprdma_sdp_rtest_6
+cc_sdprdma_sdp_rtest_7
+cc_sdprdma_sdp_rtest_8
+cc_sdprdma_sdp_rtest_9
+cdp_exp_rtest_0
+cdp_exp_rtest_1
+cdp_exp_rtest_2
+cdp_exp_rtest_3
+cdp_exp_rtest_4
+cdp_exp_rtest_5
+cdp_exp_rtest_6
+cdp_exp_rtest_7
+cdp_exp_rtest_8
+cdp_exp_rtest_9
+cdp_lin_rtest_0
+cdp_lin_rtest_1
+cdp_lin_rtest_2
+cdp_lin_rtest_3
+cdp_lin_rtest_4
+cdp_lin_rtest_5
+cdp_lin_rtest_6
+cdp_lin_rtest_7
+cdp_lin_rtest_8
+cdp_lin_rtest_9
+cdp_rtest_0
+cdp_rtest_1
+cdp_rtest_2
+cdp_rtest_3
+cdp_rtest_4
+cdp_rtest_5
+cdp_rtest_6
+cdp_rtest_7
+cdp_rtest_8
+cdp_rtest_9
+multi_scenario_rtest_0
+multi_scenario_rtest_1
+multi_scenario_rtest_2
+multi_scenario_rtest_3
+multi_scenario_rtest_4
+multi_scenario_rtest_5
+multi_scenario_rtest_6
+multi_scenario_rtest_7
+multi_scenario_rtest_8
+multi_scenario_rtest_9
+pdp_non_split_rtest_0
+pdp_non_split_rtest_1
+pdp_non_split_rtest_2
+pdp_non_split_rtest_3
+pdp_non_split_rtest_4
+pdp_non_split_rtest_5
+pdp_non_split_rtest_6
+pdp_non_split_rtest_7
+pdp_non_split_rtest_8
+pdp_non_split_rtest_9
+pdp_rtest_0
+pdp_rtest_1
+pdp_rtest_2
+pdp_rtest_3
+pdp_rtest_4
+pdp_rtest_5
+pdp_rtest_6
+pdp_rtest_7
+pdp_rtest_8
+pdp_rtest_9
+pdp_split_rtest_0
+pdp_split_rtest_1
+pdp_split_rtest_2
+pdp_split_rtest_3
+pdp_split_rtest_4
+pdp_split_rtest_5
+pdp_split_rtest_6
+pdp_split_rtest_7
+pdp_split_rtest_8
+pdp_split_rtest_9
+sdp_bn_rtest_0
+sdp_bn_rtest_1
+sdp_bn_rtest_2
+sdp_bn_rtest_3
+sdp_bn_rtest_4
+sdp_bn_rtest_5
+sdp_bn_rtest_6
+sdp_bn_rtest_7
+sdp_bn_rtest_8
+sdp_bn_rtest_9
+sdp_bs_rtest_0
+sdp_bs_rtest_1
+sdp_bs_rtest_2
+sdp_bs_rtest_3
+sdp_bs_rtest_4
+sdp_bs_rtest_5
+sdp_bs_rtest_6
+sdp_bs_rtest_7
+sdp_bs_rtest_8
+sdp_bs_rtest_9
+sdp_rtest_0
+sdp_rtest_1
+sdp_rtest_2
+sdp_rtest_3
+sdp_rtest_4
+sdp_rtest_5
+sdp_rtest_6
+sdp_rtest_7
+sdp_rtest_8
+sdp_rtest_9
+sdprdma_sdp_pdp_rtest_0
+sdprdma_sdp_pdp_rtest_1
+sdprdma_sdp_pdp_rtest_2
+sdprdma_sdp_pdp_rtest_3
+sdprdma_sdp_pdp_rtest_4
+sdprdma_sdp_pdp_rtest_5
+sdprdma_sdp_pdp_rtest_6
+sdprdma_sdp_pdp_rtest_7
+sdprdma_sdp_pdp_rtest_8
+sdprdma_sdp_pdp_rtest_9
\ No newline at end of file
diff --git a/cl_nvdla/verif/regression/nv_small_sanity b/cl_nvdla/verif/regression/nv_small_sanity
new file mode 100644
index 0000000..9304e4d
--- /dev/null
+++ b/cl_nvdla/verif/regression/nv_small_sanity
@@ -0,0 +1,81 @@
+cdp_1x1x1_lrn3_int8_0
+cdp_1x1x31_lrn3_int8_0
+cdp_33x17x34_lrn5_int8_0
+cdp_8x8x32_lrn3_int8_0
+cdp_8x8x32_lrn3_int8_1
+cdp_8x8x32_lrn3_int8_2
+cdp_8x8x32_lrn5_int8_0
+cdp_8x8x32_lrn7_int8_0
+cdp_8x8x32_lrn9_int8_0
+cdp_8x8x64_lrn3_int8_0
+cdp_8x8x64_lrn3_int8_1
+cdp_8x8x64_lrn3_int8_10
+cdp_8x8x64_lrn3_int8_11
+cdp_8x8x64_lrn3_int8_12
+cdp_8x8x64_lrn3_int8_2
+cdp_8x8x64_lrn3_int8_3
+cdp_8x8x64_lrn3_int8_4
+cdp_8x8x64_lrn3_int8_5
+cdp_8x8x64_lrn3_int8_6
+cdp_8x8x64_lrn3_int8_7
+cdp_8x8x64_lrn3_int8_8
+cdp_8x8x64_lrn3_int8_9
+cdp_8x8x64_lrn9_int8
+dc_13x15x64_5x3x64x16_int8_0
+dc_14x7x49_3x4x49x32_int8_0
+dc_1x1x8_1x1x8x1_int8_0
+dc_24x33x55_5x5x55x25_int8_0
+dc_24x44x14_5x3x14x41_int8_0
+dc_32x26x76_6x3x76x16_int8_0
+dc_32x26x76_6x3x76x270_int8_0
+dc_35x22x54_6x8x54x29_int8_0
+dc_4x1x8192_1x1x8192x1_int8_0
+dc_6x8x192_3x3x192x32_int8_0
+dc_8192x1x1_2x3x1x41_int8_0
+dc_8x16x128_3x3x128x32_int8
+dc_8x8x36_4x4x36x16_dilation_int8_0
+img_51x96x4_1x10x4x32_A8B8G8R8_int8_0
+img_51x96x4_1x10x4x32_A8R8G8B8_int8_0
+img_51x96x4_1x10x4x32_A8Y8U8V8_int8_0
+img_51x96x4_1x10x4x32_B8G8R8A8_int8_0
+img_51x96x4_1x10x4x32_B8G8R8X8_int8_0
+img_51x96x4_1x10x4x32_R8G8B8A8_int8_0
+img_51x96x4_1x10x4x32_R8G8B8X8_int8_0
+img_51x96x4_1x10x4x32_V8U8Y8A8_int8_0
+img_51x96x4_1x10x4x32_X8B8G8R8_int8_0
+img_51x96x4_1x10x4x32_X8R8G8B8_int8_0
+pdp_12x9x19_8x3_ave_int8_0
+pdp_16x6x16_4x2_split_max_int8_0
+pdp_1x1x1_3x3_ave_int8_0
+pdp_1x3x8_8x8_ave_int8_0
+pdp_24x16x1_8x8_ave_int8_0
+pdp_28x28x8_2x2_max_int8_0
+pdp_5x7x8_4x1_split_max_int8_0
+pdp_7x9x10_3x3_int8
+pdp_8x8x32_1x1_int8_0
+pdp_8x8x32_1x1_int8_1
+pdp_8x8x64_2x2_ave_int8_0
+pdp_8x8x64_2x2_int8
+pdp_8x8x64_2x2_min_int8_0
+pdp_8x9x19_3x3_ave_int8_0
+pdp_8x9x19_3x3_ave_int8_1
+sdp_1x1x1_pass_through_int8
+sdp_1x1x8_pass_through_int8_0
+sdp_1x8192x1_pass_through_int8_0
+sdp_23x13x42_bs_int8_mem_0
+sdp_3x3x33_bn_int8_mem_0
+sdp_3x3x33_bn_int8_reg_0
+sdp_3x3x33_bn_int8_reg_1
+sdp_3x3x33_bn_int8_reg_2
+sdp_3x3x33_bn_int8_reg_3
+sdp_3x3x33_bs_bn_int8_0
+sdp_3x3x33_bs_bn_int8_1
+sdp_3x3x33_bs_int8_reg_0
+sdp_3x3x33_bs_int8_reg_1
+sdp_4x1x8192_pass_through_int8_0
+sdp_4x22x42_bypass_int8
+sdp_5x24x18_bs_int8_mem_0
+sdp_8192x1x1_pass_through_int8_0
+sdp_8x8x32_bypass_int8_0
+sdp_8x8x32_bypass_int8_1
+sdp_pdp_32x16x32_pass_through_int8_0
\ No newline at end of file
diff --git a/cl_nvdla/verif/scripts/Makefile b/cl_nvdla/verif/scripts/Makefile
new file mode 100644
index 0000000..565d54e
--- /dev/null
+++ b/cl_nvdla/verif/scripts/Makefile
@@ -0,0 +1,101 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+.PHONY: default
+default: all
+
+export TRACE_TEST ?= 0
+
+ifeq ($(TRACE_TEST),1)
+export TEST ?= trace_test
+export C_TEST ?= trace_test
+export NVDLA_ENABLE_SIM_MEM ?= "+enable_sim_mem"
+else
+export TEST ?= test_null
+export C_TEST ?= test_null
+endif
+
+export CL_ROOT ?= $(PWD)/../..
+
+export CL_COMMON_ROOT = $(CL_ROOT)/../common
+
+export VP_ROOT = $(PWD)/../../../../..
+
+export C_INC_DIR = -I${CL_COMMON_ROOT}/software/include
+export C_SRC_DIR = $(CL_ROOT)/software/src
+
+export TEST_NAME = $(CL_ROOT)/verif/tests/$(TEST).sv
+ifeq ($(TRACE_TEST),1)
+export C_TEST_NAME = $(CL_ROOT)/software/src/$(C_TEST).c $(CL_ROOT)/software/src/trace_test_impl.c $(CL_COMMON_ROOT)/software/src/cl_common_utils.c $(CL_COMMON_ROOT)/software/src/sh_dpi_tasks.c
+else
+ifeq ($(COSIM), 1)
+export C_TEST_NAME = $(CL_ROOT)/software/src/$(C_TEST).c
+else
+export C_TEST_NAME = $(CL_ROOT)/software/src/$(C_TEST).c $(CL_COMMON_ROOT)/software/src/cl_common_utils.c $(CL_COMMON_ROOT)/software/src/sh_dpi_tasks.c
+endif
+endif
+
+export SIM_ROOT = $(CL_ROOT)/verif/sim
+
+export NVDLA_TRACE ?= $(CL_ROOT)/software/test_bdma/test_bdma.cfg
+
+ifeq ($(C_TEST),test_null)
+ export SIM_DIR = $(SIM_ROOT)/$(TEST)
+ export RUN_DIR = $(SIM_ROOT)/$(TEST)
+else
+ifeq ($(C_TEST),trace_test)
+ export SIM_DIR = $(SIM_ROOT)/$(C_TEST)
+ export RUN_DIR ?= $(SIM_ROOT)/$(notdir $(NVDLA_TRACE))
+else
+ export SIM_DIR = $(SIM_ROOT)/$(C_TEST)
+ export RUN_DIR = $(SIM_ROOT)/$(C_TEST)
+endif
+endif
+
+export SCRIPTS_DIR = $(CL_ROOT)/verif/scripts
+export XILINX_IP = $(HDK_SHELL_DESIGN_DIR)/ip
+export SH_LIB_DIR = $(HDK_SHELL_DESIGN_DIR)/lib
+export SH_INF_DIR = $(HDK_SHELL_DESIGN_DIR)/interfaces
+
+export NVDLA_HW_ROOT ?= $(VP_ROOT)/../hw
+export NVDLA_HW_PROJECT ?= nv_small
+
+ifneq ($(NVDLA_HW_PROJECT),nv_small)
+export NVDLA_HW_DEFINES ?= +define+NVDLA_CVSRAM_PRESENT
+endif
+
+export NVDLA_REGISTER_HEADER_DIR ?= $(NVDLA_HW_ROOT)/outdir/$(NVDLA_HW_PROJECT)/spec/manual
+
+SV_TEST_LIST =
+C_TEST_LIST = trace_test.c test_null.c
+
+ifeq ($(TRACE_TEST),1)
+export NVDLA_TRACE_PLAYER_CFLAGS ?= "-g -DDEBUG"
+export NVDLA_TRACE_PLAYER_ROOT ?= $(CL_COMMON_ROOT)/trace_player
+
+include $(NVDLA_TRACE_PLAYER_ROOT)/Makefile.inc
+endif
+
+export SIM_BACKDOOR_MEM ?= 1
+ifeq ($(SIM_BACKDOOR_MEM),1)
+export NVDLA_HW_DEFINES += +define+SIM_BACKDOOR_MEM
+endif
+
+all: make_sim_dir compile run
+
+include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc
diff --git a/cl_nvdla/verif/scripts/Makefile.vcs b/cl_nvdla/verif/scripts/Makefile.vcs
new file mode 100644
index 0000000..69c934b
--- /dev/null
+++ b/cl_nvdla/verif/scripts/Makefile.vcs
@@ -0,0 +1,62 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
+
+##################################################################
+## Makefile For VCS compiles and simulations
+## Step to run :
+## 1. make create_libs VCS=1 -> To generate xilinx compile
+## libraries. This is a one time step
+## 2. make all VCS=1 -> Runs the test
+##################################################################
+
+ifeq ($(COSIM), 1)
+export DPI_FUNCTIONS = set_apb_rd set_apb_wr set_irq_rd set_irq_wr set_ram_rd set_ram_wr set_ev_trigger sv_int_ack sv_printf apb_read_ack ram_read_ack irq_read_ack
+compile: $(COMPLIB_DIR)
+ mkdir -p $(SIM_DIR)
+ cd ${SIM_DIR} && rm -rf csrc AN.DB simv* *.log DEFAULT.DB DVEfiles/ *.vpd && syscan -export_DPI $(DPI_FUNCTIONS) && syscan -full64 -sysc=230 -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -std=c++11 -DSV_TEST" $(CL_COMMON_ROOT)/software/src/cosim_top.cpp:cosim_top -l compile.sysc.log
+ cd ${SIM_DIR} && ln -s -f ../vcs/vcs_complib/synopsys_sim.setup
+ cd ${SIM_DIR} && rm -rf csrc AN.DB simv* *.log DEFAULT.DB DVEfiles/ *.vpd && syscan -export_DPI $(DPI_FUNCTIONS) && syscan -full64 -sysc=230 -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -std=c++11 -DSV_TEST" $(CL_COMMON_ROOT)/software/src/cosim_top.cpp:cosim_top -l compile.sysc.log
+ cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS +define+COSIM_TOP $(DEFINES) $(NVDLA_HW_DEFINES) +lint=TFIPC-L
+ cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -I$(NVDLA_REGISTER_HEADER_DIR) -I$(SIM_DIR) -DSV_TEST -DDEBUG -DCONFIG_LOGLEVEL=4 -std=c++11" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -sysc=230 -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log
+else
+compile: $(COMPLIB_DIR)
+ mkdir -p $(SIM_DIR)
+ cd ${SIM_DIR} && ln -s -f ../vcs/vcs_complib/synopsys_sim.setup
+ cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -kdb -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) $(NVDLA_HW_DEFINES) +lint=TFIPC-L
+ifeq ($(TRACE_TEST), 1)
+ cd $(NVDLA_TRACE_PLAYER_ROOT)/build && make NVDLA_TRACE_PLAYER_CFLAGS=$(NVDLA_TRACE_PLAYER_CFLAGS)
+ cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -I$(NVDLA_REGISTER_HEADER_DIR) -I$(NVDLA_TRACE_PLAYER_INCLUDES) -I$(SIM_DIR) -DSV_TEST -DDEBUG -DCONFIG_LOGLEVEL=4" -LDFLAGS "-Wl,-rpath=$(NVDLA_TRACE_PLAYER_LIB_DIR) -L$(NVDLA_TRACE_PLAYER_LIB_DIR) -l$(NVDLA_TRACE_PLAYER_LIB)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -kdb -lca -v2005 -l compile.vcs.log
+else
+ cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -I$(NVDLA_REGISTER_HEADER_DIR) -I$(SIM_DIR) -DSV_TEST -DDEBUG -DCONFIG_LOGLEVEL=4" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log
+endif
+endif
+
+run:
+ mkdir -p $(RUN_DIR)
+ifeq ($(TRACE_TEST), 1)
+ cd $(RUN_DIR) && $(NVDLA_TRACE_PARSER) -f $(NVDLA_TRACE)
+ cd $(RUN_DIR) && gcc -fPIC -c $(NVDLA_TRACE_PARSER_COMMAND_SRC) -o $(NVDLA_TRACE_PARSER_COMMAND_OBJ) -I$(NVDLA_REGISTER_HEADER_DIR) -I$(NVDLA_TRACE_PLAYER_INCLUDES)
+ cd $(RUN_DIR) && gcc -fPIC -shared -o $(NVDLA_TRACE_PARSER_COMMAND_LIB) $(NVDLA_TRACE_PARSER_COMMAND_OBJ)
+endif
+ cd $(RUN_DIR) && $(SIM_DIR)/simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd +trace_output_lib=$(NVDLA_TRACE_PARSER_COMMAND_LIB) $(NVDLA_ENABLE_SIM_MEM)
+
+$(COMPLIB_DIR):
+ cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl
+ cd $(SIM_ROOT)/.. && vivado -mode batch -source create_libs.tcl
+ cd $(SIM_ROOT)/.. && rm -rf create_libs.tcl
diff --git a/cl_nvdla/verif/scripts/top.vcs.f b/cl_nvdla/verif/scripts/top.vcs.f
new file mode 100644
index 0000000..e6d119c
--- /dev/null
+++ b/cl_nvdla/verif/scripts/top.vcs.f
@@ -0,0 +1,116 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+# NVIDIA’s contributions are offered under the Amazon Software License
+
++define+VCS_SIM
+
++libext+.v
++libext+.sv
++libext+.svh
+
+-y ${CL_ROOT}/design
+-y ${SH_LIB_DIR}
+-y ${SH_INF_DIR}
+-y ${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim
+
++incdir+${CL_ROOT}/design
++incdir+${CL_ROOT}/verif/sv
++incdir+${CL_COMMON_ROOT}/verif/include
++incdir+${SH_LIB_DIR}
++incdir+${SH_INF_DIR}
++incdir+${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim
+
+${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
+${SH_LIB_DIR}/../ip/dest_register_slice/sim/dest_register_slice.v
+${SH_LIB_DIR}/../ip/src_register_slice/sim/src_register_slice.v
+${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v
+${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v
+
++define+DISABLE_VJTAG_DEBUG
+${CL_ROOT}/design/cl_sim_mem.sv
+${CL_ROOT}/design/cl_sim_mem_wrap.sv
+${CL_ROOT}/design/cl_nvdla_defines.vh
+${CL_ROOT}/design/cl_nvdla_pkg.sv
+${CL_ROOT}/design/cl_dma_pcis_slv.sv
+${CL_ROOT}/design/cl_ila.sv
+${CL_ROOT}/design/cl_vio.sv
+${CL_ROOT}/design/cl_nvdla.sv
+${CL_ROOT}/design/cl_nvdla_wrap.sv
+
+${CL_COMMON_ROOT}/design/xilinx_ip/axi_interconnect_nvdla_64b/axi_interconnect_nvdla_64b_sim_netlist.v
+${CL_COMMON_ROOT}/design/xilinx_ip/axi_apb_bridge_0/axi_apb_bridge_0_sim_netlist.v
+${CL_COMMON_ROOT}/design/xilinx_ip/axi_dwidth_converter_512b_to_64b/axi_dwidth_converter_512b_to_64b_sim_netlist.v
+${CL_COMMON_ROOT}/design/xilinx_ip/axi_protocol_converter_axi_to_axil/axi_protocol_converter_axi_to_axil_sim_netlist.v
+${CL_COMMON_ROOT}/design/transactors/irq/cl_irq_up.v
+${CL_COMMON_ROOT}/design/transactors/irq/cl_irq_up_bit.v
+${CL_COMMON_ROOT}/design/transactors/cfg/cl_cfgreg.sv
+
+-y ${CL_COMMON_ROOT}/design/vlibs
++incdir+${CL_COMMON_ROOT}/design/transactors/irq
+
++define+NO_PLI_OR_EMU
++define+VLIB_BYPASS_POWER_CG
++define+VERILINT
++define+SYNC_PL_NO_RANDOMIZATION
+
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/cdma
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/cbuf
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/csc
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/cmac
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/cacc
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/sdp
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/pdp
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/cdp
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/bdma
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/rubik
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/car
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/glb
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/csb_master
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/nocif
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/retiming
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/top
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/apb2csb
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/cfgrom
+
+-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/vlibs
+
+#-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/rams
+#-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/rams/model
+#-y ${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/rams/synth
+-y ${NVDLA_HW_ROOT}/vmod/rams/fpga/small_rams
+
+${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/vlibs/nv_assert_no_x.vlib
+${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/vlibs/NV_DW02_tree.v
+${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/vlibs/NV_DW_lsd.v
+${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/vlibs/NV_DW_minmax.v
+${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v
+
++incdir+${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/include
++incdir+${NVDLA_HW_ROOT}/outdir/${NVDLA_HW_PROJECT}/vmod/vlibs
+
++define+NVTOOLS_SYNC2D_GENERIC_CELL
++define+DESIGNWARE_NOEXIST
++define+PRAND_OFF
++define+NO_PERFMON_HISTOGRAM
++define+NO_INIT_MEM_RANDOM_TASK
++define+NO_INIT_MEM_VAL_TASKS
++define+NV_FPGA_FIFOGEN
+
+-f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f
+
+${TEST_NAME}
diff --git a/cl_nvdla/verif/scripts/waves.tcl b/cl_nvdla/verif/scripts/waves.tcl
new file mode 100644
index 0000000..4b14d0d
--- /dev/null
+++ b/cl_nvdla/verif/scripts/waves.tcl
@@ -0,0 +1,27 @@
+# Amazon FPGA Hardware Development Kit
+#
+# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+#
+# Licensed under the Amazon Software License (the "License"). You may not use
+# this file except in compliance with the License. A copy of the License is
+# located at
+#
+# http://aws.amazon.com/asl/
+#
+# or in the "license" file accompanying this file. This file is distributed on
+# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+# implied. See the License for the specific language governing permissions and
+# limitations under the License.
+
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 200 us
+quit
diff --git a/cl_nvdla/verif/tests/cosim_test.sv b/cl_nvdla/verif/tests/cosim_test.sv
new file mode 100644
index 0000000..bc3e450
--- /dev/null
+++ b/cl_nvdla/verif/tests/cosim_test.sv
@@ -0,0 +1,263 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+
+module cosim_test();
+`ifdef COSIM_TOP
+import "DPI-C" context function void sv_done_notify(input longint unsigned ev_idx);
+ cosim_top cosim_top();
+ event ev_apb_wr;
+ event ev_ram_wr;
+ event ev_irq_wr;
+ event ev_apb_rd;
+ event ev_ram_rd;
+ event ev_irq_rd;
+ event ev_tb_power_on;
+
+ longint unsigned apb_addr_rd;
+ longint unsigned apb_addr_wr;
+ int unsigned apb_data_rd;
+ int unsigned apb_data_wr;
+
+ longint unsigned ram_addr_rd;
+ longint unsigned ram_addr_wr;
+ longint unsigned ram_data_rd;
+ longint unsigned ram_data_wr;
+ int unsigned ram_size_rd;
+ int unsigned ram_size_wr;
+
+ int unsigned irq_wr;
+ int unsigned irq_rd;
+
+ export "DPI-C" function set_apb_wr;
+ export "DPI-C" function set_apb_rd;
+ export "DPI-C" function set_ram_wr;
+ export "DPI-C" function set_ram_rd;
+ export "DPI-C" function set_irq_wr;
+ export "DPI-C" function set_irq_rd;
+ export "DPI-C" function set_ev_trigger;
+ export "DPI-C" function apb_read_ack;
+ export "DPI-C" function ram_read_ack;
+ export "DPI-C" function irq_read_ack;
+
+ function set_apb_wr(input longint unsigned addr, input int unsigned data);
+ apb_addr_wr = addr;
+ apb_data_wr = data;
+ endfunction
+
+ function set_apb_rd(input longint unsigned addr, input int unsigned data);
+ apb_addr_rd = addr;
+ apb_data_rd = data;
+ endfunction
+
+ function set_ram_wr(input longint unsigned addr, input longint unsigned data, input int unsigned size);
+ ram_addr_wr = addr;
+ ram_data_wr = data;
+ ram_size_wr = size;
+ endfunction
+
+ function set_ram_rd(input longint unsigned addr, input longint unsigned data, input int unsigned size);
+ ram_addr_rd = addr;
+ ram_data_rd = data;
+ ram_size_rd = size;
+ endfunction
+
+ function set_irq_wr(input int unsigned data);
+ irq_wr = data;
+ endfunction
+
+ function set_irq_rd(input int unsigned data);
+ irq_rd = data;
+ endfunction
+
+ function int unsigned apb_read_ack();
+ return apb_data_rd;
+ endfunction
+
+ function longint unsigned ram_read_ack();
+ return ram_data_rd;
+ endfunction
+
+ function int unsigned irq_read_ack();
+ return irq_rd;
+ endfunction
+
+ function set_ev_trigger(input int unsigned ev_idx);
+`ifdef COSIM_LOG
+ $display( "Set event trigger index: %H", ev_idx);
+`endif
+ case (ev_idx)
+ 0 : begin
+ ->ev_apb_wr;
+`ifdef COSIM_LOG
+ $display( "Set event trigger ev_apb_wr");
+`endif
+ end
+ 1 : begin
+ ->ev_ram_wr;
+`ifdef COSIM_LOG
+ $display( "Set event trigger ev_ram_wr");
+`endif
+ end
+ 2 : begin
+ ->ev_irq_wr;
+`ifdef COSIM_LOG
+ $display( "Set event trigger ev_irq_wr");
+`endif
+ end
+ 3 : begin
+ ->ev_apb_rd;
+`ifdef COSIM_LOG
+ $display( "Set event trigger ev_apb_rd");
+`endif
+ end
+ 4 : begin
+ ->ev_ram_rd;
+`ifdef COSIM_LOG
+ $display( "Set event trigger ev_ram_rd");
+`endif
+ end
+ 5 : begin
+ ->ev_irq_rd;
+`ifdef COSIM_LOG
+ $display( "Set event trigger ev_irq_rd");
+`endif
+ end
+ default: begin
+ $display("Error: Invlid event ID!");
+ end
+ endcase
+ endfunction
+
+ initial begin
+ @(ev_tb_power_on);
+`ifdef COSIM_LOG
+ $display("ev_apb_wr");
+`endif
+ forever begin
+ @(ev_apb_wr)
+`ifdef COSIM_LOG
+ $display( "Before Get APB write event Address: %H Data: %H", apb_addr_wr, apb_data_wr);
+`endif
+ tb.cl_poke_ocl(apb_addr_wr, apb_data_wr);
+`ifdef COSIM_LOG
+ $display( "Get APB write event Address: %H Data: %H", apb_addr_wr, apb_data_wr);
+`endif
+ sv_done_notify(32'h0000_0000);
+ end
+ end
+
+ initial begin
+ @(ev_tb_power_on);
+`ifdef COSIM_LOG
+ $display("ev_ram_wr");
+`endif
+ forever begin
+ @(ev_ram_wr)
+`ifdef COSIM_LOG
+ $display( " Before Get RAM write event Address: %H Data: %H", ram_addr_wr, ram_data_wr);
+`endif
+ tb.cl_poke_pcis(ram_addr_wr, ram_data_wr, ram_size_wr);
+`ifdef COSIM_LOG
+ $display( "Get RAM write event Address: %H Data: %H", ram_addr_wr, ram_data_wr);
+`endif
+ sv_done_notify(32'h0000_0001);
+ end
+ end
+
+ initial begin
+ @(ev_tb_power_on);
+`ifdef COSIM_LOG
+ $display("ev_irq_wr");
+`endif
+ forever begin
+ @(ev_irq_wr)
+`ifdef COSIM_LOG
+ $display( "Before Get INT write event Value: %H", irq_wr);
+`endif
+ tb.cl_poke_bar1(32'h0000_0000, irq_wr);
+`ifdef COSIM_LOG
+ $display( "Get INT write event Value: %H", irq_wr);
+`endif
+ sv_done_notify(32'h0000_0002);
+ end
+ end
+
+ initial begin
+ @(ev_tb_power_on);
+`ifdef COSIM_LOG
+ $display("ev_apb_rd");
+`endif
+ forever begin
+ @(ev_apb_rd)
+`ifdef COSIM_LOG
+ $display( "Before Get APB read event Address: %H Data: %H", apb_addr_rd, apb_data_rd);
+`endif
+ tb.cl_peek_ocl(apb_addr_rd, apb_data_rd);
+`ifdef COSIM_LOG
+ $display( "Get APB read event Address: %H Data: %H", apb_addr_rd, apb_data_rd);
+`endif
+ sv_done_notify(32'h0000_0003);
+ end
+ end
+
+ initial begin
+ @(ev_tb_power_on);
+`ifdef COSIM_LOG
+ $display("ev_ram_rd");
+`endif
+ forever begin
+ @(ev_ram_rd);
+`ifdef COSIM_LOG
+ $display( "Before Get RAM read event Address: %H Data: %H", ram_addr_rd, ram_data_rd);
+`endif
+ tb.cl_peek_pcis(ram_addr_rd, ram_data_rd, ram_size_rd);
+`ifdef COSIM_LOG
+ $display( "Get RAM read event Address: %H Data: %H", ram_addr_rd, ram_data_rd);
+`endif
+ sv_done_notify(32'h0000_0004);
+ end
+ end
+
+ initial begin
+ @(ev_tb_power_on);
+`ifdef COSIM_LOG
+ $display("ev_irq_rd");
+`endif
+ forever begin
+ @(ev_irq_rd)
+`ifdef COSIM_LOG
+ $display( "Before Get INT read event Value: %H", irq_rd);
+`endif
+ tb.cl_peek_bar1(32'h0000_0000, irq_rd);
+`ifdef COSIM_LOG
+ $display( "Get INT read event Value: %H", irq_rd);
+`endif
+ sv_done_notify(32'h0000_0005);
+ end
+ end
+`endif
+ initial begin
+ int exit_code;
+ tb.power_up();
+ tb.nsec_delay(500);
+ ->ev_tb_power_on;
+ sv_done_notify(32'h0000_0006);
+ end
+
+endmodule // cosim_test
diff --git a/cl_nvdla/verif/tests/test_null.sv b/cl_nvdla/verif/tests/test_null.sv
new file mode 100644
index 0000000..7b22606
--- /dev/null
+++ b/cl_nvdla/verif/tests/test_null.sv
@@ -0,0 +1,37 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+module test_null();
+
+ initial begin
+ int exit_code;
+
+ tb.power_up();
+
+// tb.nsec_delay(500);
+// tb.poke_stat(.addr(8'h0c), .ddr_idx(0), .data(32'h0000_0000));
+// tb.poke_stat(.addr(8'h0c), .ddr_idx(1), .data(32'h0000_0000));
+// tb.poke_stat(.addr(8'h0c), .ddr_idx(2), .data(32'h0000_0000));
+//
+ tb.test_main(exit_code);
+
+ #50ns;
+
+ tb.power_down();
+
+ $finish;
+ end
+
+endmodule // test_null
diff --git a/cl_nvdla/verif/tests/trace_test.sv b/cl_nvdla/verif/tests/trace_test.sv
new file mode 100644
index 0000000..e107684
--- /dev/null
+++ b/cl_nvdla/verif/tests/trace_test.sv
@@ -0,0 +1,59 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+module trace_test();
+
+ initial begin
+ int exit_code;
+ string trace_output_lib;
+ int enable_sim_mem = 0;
+
+ tb.power_up();
+
+// tb.nsec_delay(500);
+// tb.poke_stat(.addr(8'h0c), .ddr_idx(0), .data(32'h0000_0000));
+// tb.poke_stat(.addr(8'h0c), .ddr_idx(1), .data(32'h0000_0000));
+// tb.poke_stat(.addr(8'h0c), .ddr_idx(2), .data(32'h0000_0000));
+//
+
+ $value$plusargs("trace_output_lib=%s", trace_output_lib);
+
+`ifdef SIM_BACKDOOR_MEM
+ if ($test$plusargs("enable_sim_mem"))
+ enable_sim_mem = 1;
+`endif
+
+ if ($test$plusargs("enable_mem_log"))
+ tb.enable_backdoor_mem_log(1);
+ else
+ tb.enable_backdoor_mem_log(0);
+
+ @(tb.card.fpga.CL.bar1_slv_sync_rst_n === 1'b1);
+
+ #50ns;
+
+ tb.trace_test_main(exit_code, trace_output_lib, enable_sim_mem);
+
+ #50ns;
+
+ tb.power_down();
+
+ $finish;
+ end
+
+endmodule // trace_test
diff --git a/common/design/transactors/cfg/cl_cfgreg.sv b/common/design/transactors/cfg/cl_cfgreg.sv
new file mode 100644
index 0000000..bb90bfb
--- /dev/null
+++ b/common/design/transactors/cfg/cl_cfgreg.sv
@@ -0,0 +1,239 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: cl_cfgreg.sv
+
+module cl_cfgreg (
+ input clk,
+ input rstn,
+ input [15:0] irq_status,
+ output [15:0] irq_pop,
+ output [63:0] base_addr0,
+ output [63:0] base_addr1,
+ output [31:0] misc_control,
+ axi_bus_t.master cfg_axi_bus
+);
+
+wire cfg_axi_awvalid;
+wire cfg_axi_awready;
+wire [31:0] cfg_axi_awaddr;
+
+wire cfg_axi_wvalid;
+reg cfg_axi_wready;
+wire [31:0] cfg_axi_wdata;
+wire [3:0] cfg_axi_wstrb;
+
+reg cfg_axi_bvalid;
+wire cfg_axi_bready;
+reg [1:0] cfg_axi_bresp;
+
+wire cfg_axi_arvalid;
+reg cfg_axi_arready;
+wire [31:0] cfg_axi_araddr;
+
+reg cfg_axi_rvalid;
+wire cfg_axi_rready;
+reg [1:0] cfg_axi_rresp;
+reg [31:0] cfg_axi_rdata;
+
+reg [15:0] irq_pop;
+reg [31:0] misc_control;
+
+// internal signals
+reg [2:0] cfg_axi_wr_state;
+reg [31:0] cfg_axi_awaddr_reg;
+reg [31:0] base_addr0_hi;
+reg [31:0] base_addr0_lo;
+reg [31:0] base_addr1_hi;
+reg [31:0] base_addr1_lo;
+
+reg [1:0] cfg_axi_rd_state;
+reg [31:0] cfg_axi_araddr_reg;
+
+
+assign cfg_axi_awvalid = cfg_axi_bus.awvalid;
+assign cfg_axi_awaddr = cfg_axi_bus.awaddr;
+assign cfg_axi_bus.awready = cfg_axi_awready;
+
+assign cfg_axi_wvalid = cfg_axi_bus.wvalid;
+assign cfg_axi_wdata = cfg_axi_bus.wdata;
+assign cfg_axi_wstrb = cfg_axi_bus.wstrb;
+assign cfg_axi_bus.wready = cfg_axi_wready;
+
+assign cfg_axi_bus.bvalid = cfg_axi_bvalid;
+assign cfg_axi_bus.bresp = cfg_axi_bresp;
+assign cfg_axi_bready = cfg_axi_bus.bready;
+
+assign cfg_axi_arvalid = cfg_axi_bus.arvalid;
+assign cfg_axi_araddr = cfg_axi_bus.araddr;
+assign cfg_axi_bus.arready = cfg_axi_arready;
+
+assign cfg_axi_bus.rvalid = cfg_axi_rvalid;
+assign cfg_axi_bus.rresp = cfg_axi_rresp;
+assign cfg_axi_bus.rdata = cfg_axi_rdata;
+assign cfg_axi_rready = cfg_axi_bus.rready;
+
+assign base_addr0 = {base_addr0_hi, base_addr0_lo};
+assign base_addr1 = {base_addr1_hi, base_addr1_lo};
+
+///////////////////////////////////////////////////////////
+// write channel
+
+// axi write cmd flow control
+`define CFG_AXI_WR_IDLE 0
+`define CFG_AXI_WR_DATA 1
+`define CFG_AXI_WR_RESP 2
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ cfg_axi_wr_state <= 1<<`CFG_AXI_WR_IDLE;
+ else
+ case (1)
+ cfg_axi_wr_state[`CFG_AXI_WR_IDLE] :
+ // awready asserted, wait awvalid to jump out
+ if(cfg_axi_awvalid)
+ cfg_axi_wr_state <= 1<<`CFG_AXI_WR_DATA;
+ cfg_axi_wr_state[`CFG_AXI_WR_DATA] :
+ // wready asserted, wait wvalid to jump out. only support 1 beat.
+ if(cfg_axi_wvalid)
+ cfg_axi_wr_state <= 1<<`CFG_AXI_WR_RESP;
+ cfg_axi_wr_state[`CFG_AXI_WR_RESP] :
+ // bvalid asserted, wait bready to jump out.
+ if(cfg_axi_bready)
+ cfg_axi_wr_state <= 1<<`CFG_AXI_WR_IDLE;
+ endcase
+
+assign cfg_axi_awready = cfg_axi_wr_state[`CFG_AXI_WR_IDLE];
+assign cfg_axi_wready = cfg_axi_wr_state[`CFG_AXI_WR_DATA];
+assign cfg_axi_bvalid = cfg_axi_wr_state[`CFG_AXI_WR_RESP];
+
+// latch awaddr for address decoding
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ cfg_axi_awaddr_reg <= 32'b0;
+ else if(cfg_axi_awvalid & cfg_axi_awready)
+ cfg_axi_awaddr_reg <= cfg_axi_awaddr;
+
+// write data to registers
+`define CFGREG_IRQUP 32'h00000000
+`define CFGREG_BASE0_LO 32'h00000004
+`define CFGREG_BASE0_HI 32'h00000008
+`define CFGREG_BASE1_LO 32'h0000000C
+`define CFGREG_BASE1_HI 32'h00000010
+`define CFGREG_BASE1_HI 32'h00000010
+`define CFGREG_MISC_CTRL 32'h00000014
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn) begin
+ base_addr0_hi <= 32'b0;
+ base_addr0_lo <= 32'b0;
+ base_addr1_hi <= 32'b0;
+ base_addr1_lo <= 32'b0;
+ irq_pop <= 16'b0;
+ cfg_axi_bresp <= 2'b0;
+ misc_control <= 32'b0;
+ end
+ else begin
+ irq_pop <= 16'b0;
+ cfg_axi_bresp[1:0] <= 2'b0;
+ if(cfg_axi_wvalid & cfg_axi_wready) begin
+ case (cfg_axi_awaddr_reg)
+ `CFGREG_IRQUP : begin
+ irq_pop[7:0] <= {8{cfg_axi_wstrb[0]}} & cfg_axi_wdata[7:0];
+ irq_pop[15:8] <= {8{cfg_axi_wstrb[1]}} & cfg_axi_wdata[15:8];
+ end
+ `CFGREG_BASE0_LO : begin
+ base_addr0_lo[7:0] <= {8{cfg_axi_wstrb[0]}} & cfg_axi_wdata[7:0];
+ base_addr0_lo[15:8] <= {8{cfg_axi_wstrb[1]}} & cfg_axi_wdata[15:8];
+ base_addr0_lo[23:16]<= {8{cfg_axi_wstrb[2]}} & cfg_axi_wdata[23:16];
+ base_addr0_lo[31:24]<= {8{cfg_axi_wstrb[3]}} & cfg_axi_wdata[31:24];
+ end
+ `CFGREG_BASE0_HI : begin
+ base_addr0_hi[7:0] <= {8{cfg_axi_wstrb[0]}} & cfg_axi_wdata[7:0];
+ base_addr0_hi[15:8] <= {8{cfg_axi_wstrb[1]}} & cfg_axi_wdata[15:8];
+ base_addr0_hi[23:16]<= {8{cfg_axi_wstrb[2]}} & cfg_axi_wdata[23:16];
+ base_addr0_hi[31:24]<= {8{cfg_axi_wstrb[3]}} & cfg_axi_wdata[31:24];
+ end
+ `CFGREG_BASE1_LO : begin
+ base_addr1_lo[7:0] <= {8{cfg_axi_wstrb[0]}} & cfg_axi_wdata[7:0];
+ base_addr1_lo[15:8] <= {8{cfg_axi_wstrb[1]}} & cfg_axi_wdata[15:8];
+ base_addr1_lo[23:16]<= {8{cfg_axi_wstrb[2]}} & cfg_axi_wdata[23:16];
+ base_addr1_lo[31:24]<= {8{cfg_axi_wstrb[3]}} & cfg_axi_wdata[31:24];
+ end
+ `CFGREG_BASE1_HI : begin
+ base_addr1_hi[7:0] <= {8{cfg_axi_wstrb[0]}} & cfg_axi_wdata[7:0];
+ base_addr1_hi[15:8] <= {8{cfg_axi_wstrb[1]}} & cfg_axi_wdata[15:8];
+ base_addr1_hi[23:16]<= {8{cfg_axi_wstrb[2]}} & cfg_axi_wdata[23:16];
+ base_addr1_hi[31:24]<= {8{cfg_axi_wstrb[3]}} & cfg_axi_wdata[31:24];
+ end
+ `CFGREG_MISC_CTRL : begin
+ misc_control[7:0] <= {8{cfg_axi_wstrb[0]}} & cfg_axi_wdata[7:0];
+ misc_control[15:8] <= {8{cfg_axi_wstrb[1]}} & cfg_axi_wdata[15:8];
+ misc_control[23:16] <= {8{cfg_axi_wstrb[2]}} & cfg_axi_wdata[23:16];
+ misc_control[31:24] <= {8{cfg_axi_wstrb[3]}} & cfg_axi_wdata[31:24];
+ end
+ default : begin
+ cfg_axi_bresp[1:0] <= 2'b11; // return error code for non existing address
+ end
+ endcase
+ end
+ end
+
+
+///////////////////////////////////////////////////////////
+// read channel
+
+// axi write cmd flow control
+`define CFG_AXI_RD_IDLE 0
+`define CFG_AXI_RD_DATA 1
+
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ cfg_axi_rd_state <= 1<<`CFG_AXI_RD_IDLE;
+ else
+ case (1)
+ cfg_axi_rd_state[`CFG_AXI_RD_IDLE] :
+ // arready asserted, wait awvalid to jump out
+ if(cfg_axi_arvalid)
+ cfg_axi_rd_state <= 1<<`CFG_AXI_RD_DATA;
+ cfg_axi_rd_state[`CFG_AXI_RD_DATA] :
+ // rvalid asserted, wait bready to jump out. only support 1 beat
+ if(cfg_axi_rready)
+ cfg_axi_rd_state <= 1<<`CFG_AXI_RD_IDLE;
+ endcase
+
+assign cfg_axi_arready = cfg_axi_rd_state[`CFG_AXI_RD_IDLE];
+assign cfg_axi_rvalid = cfg_axi_rd_state[`CFG_AXI_RD_DATA];
+
+// latch araddr for address decoding
+always @ (posedge clk or negedge rstn)
+ if(!rstn)
+ cfg_axi_araddr_reg <= 32'b0;
+ else if(cfg_axi_arvalid & cfg_axi_arready)
+ cfg_axi_araddr_reg <= cfg_axi_araddr;
+
+// mux register data out
+always @ (*) begin
+ cfg_axi_rresp = 2'b00;
+
+ case (cfg_axi_araddr_reg)
+ `CFGREG_IRQUP : cfg_axi_rdata = {16'b0, irq_status};
+ `CFGREG_BASE0_LO : cfg_axi_rdata = base_addr0_lo;
+ `CFGREG_BASE0_HI : cfg_axi_rdata = base_addr0_hi;
+ `CFGREG_BASE1_LO : cfg_axi_rdata = base_addr1_lo;
+ `CFGREG_BASE1_HI : cfg_axi_rdata = base_addr1_hi;
+ `CFGREG_MISC_CTRL : cfg_axi_rdata = misc_control;
+ default : begin
+ cfg_axi_rdata[31:0] = 32'b0;
+ cfg_axi_rresp[1:0] = 2'b11; // return error code for non existing address
+ end
+ endcase
+end
+
+
+endmodule
diff --git a/common/design/transactors/irq/cl_irq_up.v b/common/design/transactors/irq/cl_irq_up.v
new file mode 100644
index 0000000..1fabf16
--- /dev/null
+++ b/common/design/transactors/irq/cl_irq_up.v
@@ -0,0 +1,678 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: cl_irq_up.v
+
+`timescale 100ps/10ps
+`include "simulate_x_tick.vh"
+`timescale 100ps/10ps
+`include "simulate_x_tick.vh"
+module cl_irq_up (
+ clk //|< i
+ ,irq //|< i
+ ,irq_ack //|< i
+ ,irq_pop //|< i
+ ,reset_ //|< i
+ ,irq_req //|> o
+ ,irq_status //|> o
+ );
+
+input clk;
+input [15:0] irq;
+input [15:0] irq_ack;
+input [15:0] irq_pop;
+input reset_;
+output [15:0] irq_req;
+output [15:0] irq_status;
+wire [15:0] irq_sync;
+
+
+
+//// generated by ::sync -type 3D -inst irq_sync -input irq -output irq_sync -clock clk -reset reset_ -width 16
+
+wire [15:0] sync_ibus_0;
+wire [15:0] sync_rbus_0;
+wire [15:0] sync_bbus_0;
+wire [15:0] sync_sbus_0;
+
+`undef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS
+`ifndef SYNC_PL_NO_RANDOMIZATION
+`ifndef SYNTH_LEVEL1_COMPILE
+`ifndef SYNTHESIS
+ `define SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS
+`endif
+`endif
+`endif
+
+// VCS coverage off
+
+`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS
+reg [15:0] RandSyncBusPipe_0 [0:1];
+reg [15:0] RandSyncBusCurr_0;
+reg [15:0] RandSyncBusNext_0;
+reg [15:0] RandSyncBusRand_0;
+reg [15:0] RandSyncBusPick_0;
+reg [1:1] RandSyncBusKnown_0;
+reg [1:1] RandSyncBusDelta_0;
+reg RandSyncEnable_0;
+reg RandSyncBusEnable_0;
+reg RandSyncBitEnable_0;
+reg RandSyncDiff_0;
+reg RandSyncDone_0;
+reg RandSyncSnap_0;
+`endif
+// VCS coverage on
+
+// input bus
+
+assign sync_ibus_0 = irq[15:0];
+
+// random bus
+
+`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS
+ assign sync_rbus_0 = RandSyncBusRand_0;
+`else
+ assign sync_rbus_0 = sync_ibus_0;
+`endif
+
+// buffer bus
+
+assign sync_bbus_0 = sync_rbus_0;
+
+ // sync bus
+
+
+sync3d_c_ppp irq_sync_0 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[0]),
+ .q(sync_sbus_0[0])
+ );
+
+sync3d_c_ppp irq_sync_1 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[1]),
+ .q(sync_sbus_0[1])
+ );
+
+sync3d_c_ppp irq_sync_2 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[2]),
+ .q(sync_sbus_0[2])
+ );
+
+sync3d_c_ppp irq_sync_3 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[3]),
+ .q(sync_sbus_0[3])
+ );
+
+sync3d_c_ppp irq_sync_4 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[4]),
+ .q(sync_sbus_0[4])
+ );
+
+sync3d_c_ppp irq_sync_5 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[5]),
+ .q(sync_sbus_0[5])
+ );
+
+sync3d_c_ppp irq_sync_6 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[6]),
+ .q(sync_sbus_0[6])
+ );
+
+sync3d_c_ppp irq_sync_7 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[7]),
+ .q(sync_sbus_0[7])
+ );
+
+sync3d_c_ppp irq_sync_8 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[8]),
+ .q(sync_sbus_0[8])
+ );
+
+sync3d_c_ppp irq_sync_9 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[9]),
+ .q(sync_sbus_0[9])
+ );
+
+sync3d_c_ppp irq_sync_10 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[10]),
+ .q(sync_sbus_0[10])
+ );
+
+sync3d_c_ppp irq_sync_11 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[11]),
+ .q(sync_sbus_0[11])
+ );
+
+sync3d_c_ppp irq_sync_12 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[12]),
+ .q(sync_sbus_0[12])
+ );
+
+sync3d_c_ppp irq_sync_13 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[13]),
+ .q(sync_sbus_0[13])
+ );
+
+sync3d_c_ppp irq_sync_14 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[14]),
+ .q(sync_sbus_0[14])
+ );
+
+sync3d_c_ppp irq_sync_15 (
+ .clk(clk),
+ .clr_(reset_),
+ .d(sync_bbus_0[15]),
+ .q(sync_sbus_0[15])
+ );
+
+// defeating sync randomizer
+`ifndef NO_PLI_OR_EMU
+`ifndef GATES
+`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_0.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_0.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_1.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_1.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_2.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_2.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_3.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_3.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_4.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_4.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_5.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_5.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_6.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_6.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_7.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_7.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_8.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_8.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_9.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_9.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_10.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_10.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_11.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_11.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_12.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_12.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_13.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_13.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_14.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_14.first_stage_of_sync.mode = 0;
+`endif
+
+`ifdef NVTOOLS_SYNC2D_GENERIC_CELL
+ defparam irq_sync_15.NV_GENERIC_CELL.first_stage_of_sync.mode = 0;
+`else
+ defparam irq_sync_15.first_stage_of_sync.mode = 0;
+`endif
+
+`endif
+`endif
+`endif
+
+// output bus
+
+assign irq_sync = sync_sbus_0;
+
+// VCS coverage off
+`ifndef NO_PLI_OR_EMU
+`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS
+
+initial begin
+ if ($test$plusargs("RandSyncInfo")) $display ("INFO: RandSync: @ %m");
+end
+
+initial begin
+ RandSyncEnable_0 = 1'b1;
+ if ($test$plusargs("RandSyncGlobalDisable")) RandSyncEnable_0 = 1'b0;
+ if ($test$plusargs("RandSyncLocalDisable")) RandSyncEnable_0 = 1'b0;
+end
+
+// SRC before DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized.
+// SRC equals DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized.
+// SRC after DSTCLK: old SRC is sampled again to CUR (NOP), CUR is sampled to PRE, CUR == PRE.
+
+// curr (glitch filter)
+always @(sync_ibus_0) begin
+ RandSyncBusCurr_0 <= sync_ibus_0;
+end
+
+// snap
+initial RandSyncSnap_0 = 1'b0;
+always @(posedge clk) begin
+ RandSyncSnap_0 <= (RandSyncSnap_0 === 1'bx)? 1'b0 : !RandSyncSnap_0;
+end
+
+// eval
+always @(RandSyncBusCurr_0 or RandSyncSnap_0 or negedge reset_) begin : rand_sync_block_0
+ integer i, j;
+
+ // bump
+ for (i=1; i>=1; i=i-1) begin
+ RandSyncBusPipe_0[i] = RandSyncBusPipe_0[i-1];
+ end
+ RandSyncBusPipe_0[0] = RandSyncBusCurr_0;
+
+ // next
+ RandSyncBusNext_0 = RandSyncBusPipe_0[0];
+
+ // rand
+ if (RandSyncEnable_0 && reset_) begin
+ // known
+ for (i=1; i>=1; i=i-1) begin
+ RandSyncBusKnown_0[i] = |RandSyncBusPipe_0[i] !== 1'bx;
+ end
+ // delta
+ for (i=1; i>=1; i=i-1) begin
+ RandSyncBusDelta_0[i] = |(RandSyncBusPipe_0[i] ^ RandSyncBusPipe_0[i-1]);
+ end
+ if (&RandSyncBusKnown_0 && |RandSyncBusDelta_0) begin
+ RandSyncBusNext_0 = RandSyncBusPipe_0[1];
+ RandSyncBusEnable_0 = prand_inst0(1, 100) > (100 - 50);
+ if (RandSyncBusEnable_0) begin
+ RandSyncDone_0 = 1'b0;
+ for (i=1; i>=1; i=i-1) begin
+ RandSyncDiff_0 = RandSyncBusPipe_0[i] !== RandSyncBusPipe_0[i-1];
+ if (RandSyncDiff_0 && !RandSyncDone_0) begin
+ RandSyncBusPickTask_0 (RandSyncBusPipe_0[i], RandSyncBusPipe_0[i-1]);
+ if (RandSyncBusNext_0 !== RandSyncBusPick_0) begin
+ RandSyncBusNext_0 = RandSyncBusPick_0;
+ RandSyncDone_0 = 1'b1;
+ end
+ end
+ end
+ end
+ end
+ end
+ RandSyncBusRand_0 = RandSyncBusNext_0;
+end
+
+// task
+task RandSyncBusPickTask_0; // rand value = mixture
+ input [15:0] RandSyncTaskBusPrev_0;
+ input [15:0] RandSyncTaskBusCurr_0;
+ integer i;
+ for (i=0; i<=15; i=i+1) begin
+ if (RandSyncTaskBusCurr_0[i] === RandSyncTaskBusPrev_0[i]) begin
+ RandSyncBusPick_0[i] = RandSyncTaskBusCurr_0[i];
+ end else begin
+ RandSyncBitEnable_0 = prand_inst1(1, 100) > (100 - 50);
+ RandSyncBusPick_0[i] = (RandSyncBitEnable_0)? RandSyncTaskBusCurr_0[i] : RandSyncTaskBusPrev_0[i];
+ end
+ end
+endtask
+
+
+`ifdef SYNTH_LEVEL1_COMPILE
+`else
+`ifdef SYNTHESIS
+`else
+`ifdef PRAND_VERILOG
+// Only verilog needs any local variables
+reg [47:0] prand_local_seed0;
+reg prand_initialized0;
+reg prand_no_rollpli0;
+`endif
+`endif
+`endif
+
+function [31:0] prand_inst0;
+//VCS coverage off
+ input [31:0] min;
+ input [31:0] max;
+ reg [32:0] diff;
+
+ begin
+`ifdef SYNTH_LEVEL1_COMPILE
+ prand_inst0 = min;
+`else
+`ifdef SYNTHESIS
+ prand_inst0 = min;
+`else
+`ifdef PRAND_VERILOG
+ if (prand_initialized0 !== 1'b1) begin
+ prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI");
+ if (!prand_no_rollpli0)
+ prand_local_seed0 = {$prand_get_seed(0), 16'b0};
+ prand_initialized0 = 1'b1;
+ end
+ if (prand_no_rollpli0) begin
+ prand_inst0 = min;
+ end else begin
+ diff = max - min + 1;
+ prand_inst0 = min + prand_local_seed0[47:16] % diff;
+ // magic numbers taken from Java's random class (same as lrand48)
+ prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11;
+ end
+`else
+`ifdef PRAND_OFF
+ prand_inst0 = min;
+`else
+ prand_inst0 = $RollPLI(min, max, "auto");
+`endif
+`endif
+`endif
+`endif
+ end
+//VCS coverage on
+endfunction
+
+
+`ifdef SYNTH_LEVEL1_COMPILE
+`else
+`ifdef SYNTHESIS
+`else
+`ifdef PRAND_VERILOG
+// Only verilog needs any local variables
+reg [47:0] prand_local_seed1;
+reg prand_initialized1;
+reg prand_no_rollpli1;
+`endif
+`endif
+`endif
+
+function [31:0] prand_inst1;
+//VCS coverage off
+ input [31:0] min;
+ input [31:0] max;
+ reg [32:0] diff;
+
+ begin
+`ifdef SYNTH_LEVEL1_COMPILE
+ prand_inst1 = min;
+`else
+`ifdef SYNTHESIS
+ prand_inst1 = min;
+`else
+`ifdef PRAND_VERILOG
+ if (prand_initialized1 !== 1'b1) begin
+ prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI");
+ if (!prand_no_rollpli1)
+ prand_local_seed1 = {$prand_get_seed(1), 16'b0};
+ prand_initialized1 = 1'b1;
+ end
+ if (prand_no_rollpli1) begin
+ prand_inst1 = min;
+ end else begin
+ diff = max - min + 1;
+ prand_inst1 = min + prand_local_seed1[47:16] % diff;
+ // magic numbers taken from Java's random class (same as lrand48)
+ prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11;
+ end
+`else
+`ifdef PRAND_OFF
+ prand_inst1 = min;
+`else
+ prand_inst1 = $RollPLI(min, max, "auto");
+`endif
+`endif
+`endif
+`endif
+ end
+//VCS coverage on
+endfunction
+
+
+`endif
+`endif
+// VCS coverage on
+
+
+cl_irq_up_bit CL_IRQ_UP_BIT0 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[0]) //|< i
+ ,.irq_in (irq_sync[0]) //|< w
+ ,.irq_pop (irq_pop[0]) //|< i
+ ,.irq_req (irq_req[0]) //|> o
+ ,.irq_status (irq_status[0]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT1 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[1]) //|< i
+ ,.irq_in (irq_sync[1]) //|< w
+ ,.irq_pop (irq_pop[1]) //|< i
+ ,.irq_req (irq_req[1]) //|> o
+ ,.irq_status (irq_status[1]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT2 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[2]) //|< i
+ ,.irq_in (irq_sync[2]) //|< w
+ ,.irq_pop (irq_pop[2]) //|< i
+ ,.irq_req (irq_req[2]) //|> o
+ ,.irq_status (irq_status[2]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT3 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[3]) //|< i
+ ,.irq_in (irq_sync[3]) //|< w
+ ,.irq_pop (irq_pop[3]) //|< i
+ ,.irq_req (irq_req[3]) //|> o
+ ,.irq_status (irq_status[3]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT4 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[4]) //|< i
+ ,.irq_in (irq_sync[4]) //|< w
+ ,.irq_pop (irq_pop[4]) //|< i
+ ,.irq_req (irq_req[4]) //|> o
+ ,.irq_status (irq_status[4]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT5 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[5]) //|< i
+ ,.irq_in (irq_sync[5]) //|< w
+ ,.irq_pop (irq_pop[5]) //|< i
+ ,.irq_req (irq_req[5]) //|> o
+ ,.irq_status (irq_status[5]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT6 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[6]) //|< i
+ ,.irq_in (irq_sync[6]) //|< w
+ ,.irq_pop (irq_pop[6]) //|< i
+ ,.irq_req (irq_req[6]) //|> o
+ ,.irq_status (irq_status[6]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT7 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[7]) //|< i
+ ,.irq_in (irq_sync[7]) //|< w
+ ,.irq_pop (irq_pop[7]) //|< i
+ ,.irq_req (irq_req[7]) //|> o
+ ,.irq_status (irq_status[7]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT8 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[8]) //|< i
+ ,.irq_in (irq_sync[8]) //|< w
+ ,.irq_pop (irq_pop[8]) //|< i
+ ,.irq_req (irq_req[8]) //|> o
+ ,.irq_status (irq_status[8]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT9 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[9]) //|< i
+ ,.irq_in (irq_sync[9]) //|< w
+ ,.irq_pop (irq_pop[9]) //|< i
+ ,.irq_req (irq_req[9]) //|> o
+ ,.irq_status (irq_status[9]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT10 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[10]) //|< i
+ ,.irq_in (irq_sync[10]) //|< w
+ ,.irq_pop (irq_pop[10]) //|< i
+ ,.irq_req (irq_req[10]) //|> o
+ ,.irq_status (irq_status[10]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT11 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[11]) //|< i
+ ,.irq_in (irq_sync[11]) //|< w
+ ,.irq_pop (irq_pop[11]) //|< i
+ ,.irq_req (irq_req[11]) //|> o
+ ,.irq_status (irq_status[11]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT12 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[12]) //|< i
+ ,.irq_in (irq_sync[12]) //|< w
+ ,.irq_pop (irq_pop[12]) //|< i
+ ,.irq_req (irq_req[12]) //|> o
+ ,.irq_status (irq_status[12]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT13 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[13]) //|< i
+ ,.irq_in (irq_sync[13]) //|< w
+ ,.irq_pop (irq_pop[13]) //|< i
+ ,.irq_req (irq_req[13]) //|> o
+ ,.irq_status (irq_status[13]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT14 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[14]) //|< i
+ ,.irq_in (irq_sync[14]) //|< w
+ ,.irq_pop (irq_pop[14]) //|< i
+ ,.irq_req (irq_req[14]) //|> o
+ ,.irq_status (irq_status[14]) //|> o
+ );
+
+cl_irq_up_bit CL_IRQ_UP_BIT15 (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.irq_ack (irq_ack[15]) //|< i
+ ,.irq_in (irq_sync[15]) //|< w
+ ,.irq_pop (irq_pop[15]) //|< i
+ ,.irq_req (irq_req[15]) //|> o
+ ,.irq_status (irq_status[15]) //|> o
+ );
+
+
+endmodule // cl_irq_up
+
+
diff --git a/common/design/transactors/irq/cl_irq_up_bit.v b/common/design/transactors/irq/cl_irq_up_bit.v
new file mode 100644
index 0000000..ae59f1e
--- /dev/null
+++ b/common/design/transactors/irq/cl_irq_up_bit.v
@@ -0,0 +1,1916 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: cl_irq_up_bit.v
+
+`timescale 100ps/10ps
+`include "simulate_x_tick.vh"
+module cl_irq_up_bit (
+ clk //|< i
+ ,reset_ //|< i
+ ,irq_ack //|< i *
+ ,irq_in //|< i
+ ,irq_pop //|< i
+ ,irq_req //|> o
+ ,irq_status //|> o
+ );
+
+input clk;
+input reset_;
+input [15:0] irq_ack;
+input irq_in;
+input irq_pop;
+output irq_req;
+output irq_status;
+wire irq_in_change;
+wire rd_data;
+wire rd_req;
+wire wr_busy;
+reg irq_in_d;
+reg irq_req;
+reg irq_status;
+reg rd_busy;
+
+always @(posedge clk) begin
+ if (!reset_) begin
+ irq_in_d <= 1'b0;
+ end else begin
+ irq_in_d <= irq_in;
+ end
+end
+
+assign irq_in_change = irq_in ^ irq_in_d;
+
+irq_upstream_reqfifo u_irq_upstream_reqfifo (
+ .clk (clk) //|< i
+ ,.reset_ (reset_) //|< i
+ ,.wr_busy (wr_busy) //|> w
+ ,.wr_idle () //|> ?
+ ,.wr_req ((irq_in_change & !wr_busy)) //|< ?
+ ,.wr_data (irq_in) //|< i
+ ,.rd_busy (rd_busy) //|< r
+ ,.rd_req (rd_req) //|> w
+ ,.rd_data (rd_data) //|> w
+ ,.pwrbus_ram_pd ({32{1'b0}}) //|< ?
+ );
+
+
+always @(posedge clk) begin
+ if (!reset_) begin
+ irq_req <= 1'b0;
+ rd_busy <= 1'b0;
+ irq_status <= 1'b0;
+ end else begin
+ if(irq_req)
+ irq_req <= 1'b0;
+ else if(rd_busy)
+ rd_busy <= !irq_pop;
+ else if(rd_req) begin
+ irq_req <= 1'b1;
+ rd_busy <= 1'b1;
+ irq_status <= rd_data;
+ end
+ end
+end
+
+`ifdef SPYGLASS_ASSERT_ON
+`else
+// spyglass disable_block NoWidthInBasedNum-ML
+// spyglass disable_block STARC-2.10.3.2a
+// spyglass disable_block STARC05-2.1.3.1
+// spyglass disable_block STARC-2.1.4.6
+// spyglass disable_block W116
+// spyglass disable_block W154
+// spyglass disable_block W239
+// spyglass disable_block W362
+// spyglass disable_block WRN_58
+// spyglass disable_block WRN_61
+`endif // SPYGLASS_ASSERT_ON
+`ifdef ASSERT_ON
+`ifdef FV_ASSERT_ON
+`define ASSERT_RESET reset_
+`else
+`ifdef SYNTHESIS
+`define ASSERT_RESET reset_
+`else
+`ifdef ASSERT_OFF_RESET_IS_X
+`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_)
+`else
+`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_)
+`endif // ASSERT_OFF_RESET_IS_X
+`endif // SYNTHESIS
+`endif // FV_ASSERT_ON
+ // VCS coverage off
+ nv_assert_never #(0,0,"error: irq fifo full!") zzz_assert_never_1x (clk, `ASSERT_RESET, (irq_in_change & wr_busy)); // spyglass disable W504 SelfDeterminedExpr-ML
+ // VCS coverage on
+`undef ASSERT_RESET
+`endif // ASSERT_ON
+`ifdef SPYGLASS_ASSERT_ON
+`else
+// spyglass enable_block NoWidthInBasedNum-ML
+// spyglass enable_block STARC-2.10.3.2a
+// spyglass enable_block STARC05-2.1.3.1
+// spyglass enable_block STARC-2.1.4.6
+// spyglass enable_block W116
+// spyglass enable_block W154
+// spyglass enable_block W239
+// spyglass enable_block W362
+// spyglass enable_block WRN_58
+// spyglass enable_block WRN_61
+`endif // SPYGLASS_ASSERT_ON
+
+endmodule // cl_irq_up_bit
+
+//
+// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN
+//
+// /home/nvtools/engr/2017/10/24_05_01_31/nvtools/scripts/fifogen
+// fifogen -no_make_ram -input_config_yaml /home/ip/shared/inf/fullchip_cfg/nvgpu/falcon6.0/39727485/config_yamls/fifogen/tulit2/fifogen.yml -stdout -m irq_upstream_reqfifo -d 64 -w 1 -ram ra2 -wr_reg -rd_reg -wr_idle [Chosen ram type (forced to -ram auto): ff - fifogen_flops (la2 was allowed but not chosen; ra2 was allowed but not chosen)]
+// chip config vars: strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 uses_prand=1 perfmon_histogram_defined=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 remove_unused_ports=1 viva_parsed=1 ram_variant_all=1 requires_full_throughput=1 rollpli_seedset="auto" force_first_ram_auto=1 force_first_ram_auto_no_latency_change=0 ram_auto_ff_bits_cutoff=96 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=256 ram_auto_ff_depth_cutoff=3 ram_auto_ff_no_la2_depth_cutoff=6 ram_auto_la2_width_cutoff=16 ram_auto_la2_width_cutoff_max_depth=64 ram_auto_la2_depth_cutoff=23 flopram_emu_model=1 reinit=0 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 allow_mt_rttrb_wr_reg=0
+//
+// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment
+// leda B_1405 OFF -- 2 asynchronous resets in this unit detected
+
+
+`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1
+
+`ifndef SYNTHESIS
+ `define FIFOGEN_KEEP_ASSERTION_VERIF_CODE
+`else
+ `ifdef FV_ASSERT_ON
+ `define FIFOGEN_KEEP_ASSERTION_VERIF_CODE
+ `endif
+`endif
+
+`include "simulate_x_tick.vh"
+
+
+module irq_upstream_reqfifo (
+ clk
+ , reset_
+ , wr_busy
+ , wr_idle
+ , wr_req
+`ifdef FV_RAND_WR_PAUSE
+ , wr_pause
+`endif
+ , wr_data
+ , rd_busy
+ , rd_req
+ , rd_data
+ , pwrbus_ram_pd
+ );
+
+// spyglass disable_block W401 -- clock is not input to module
+input clk;
+input reset_;
+output wr_busy;
+output wr_idle;
+input wr_req;
+`ifdef FV_RAND_WR_PAUSE
+input wr_pause;
+`endif
+input wr_data;
+input rd_busy;
+output rd_req;
+output rd_data;
+input [31:0] pwrbus_ram_pd;
+
+
+
+`ifdef FV_RAND_WR_PAUSE
+// FV forces this signal to trigger random stalling
+wire wr_pause = 0;
+`endif
+
+// Master Clock Gating (SLCG)
+//
+// We gate the clock(s) when idle or stalled.
+// This allows us to turn off numerous miscellaneous flops
+// that don't get gated during synthesis for one reason or another.
+//
+// We gate write side and read side separately.
+// If the fifo is synchronous, we also gate the ram separately, but if
+// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified,
+// then we use one clk gate for write, ram, and read.
+//
+wire clk_mgated_enable; // assigned by code at end of this module
+wire clk_mgated; // used only in synchronous fifos
+NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) );
+
+//
+// WRITE SIDE
+//
+// VCS coverage off
+`ifndef SYNTH_LEVEL1_COMPILE
+`ifndef SYNTHESIS
+wire wr_pause_rand; // random stalling
+reg wr_pause_rand_in;
+`endif
+`endif
+// VCS coverage on
+wire wr_reserving;
+reg wr_req_in; // registered wr_req
+reg wr_busy_in; // inputs being held this cycle?
+assign wr_busy = wr_busy_in;
+wire wr_busy_next; // fwd: fifo busy next?
+
+// factor for better timing with distant wr_req signal
+wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next;
+wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving;
+`ifdef FV_RAND_WR_PAUSE
+wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0)
+ || wr_pause ;
+`else
+wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0)
+
+ // VCS coverage off
+ `ifndef SYNTH_LEVEL1_COMPILE
+ `ifndef SYNTHESIS
+ || wr_pause_rand
+ `endif
+ `endif
+ // VCS coverage on
+
+ ;
+`endif
+wire wr_busy_in_int;
+always @( posedge clk or negedge reset_ ) begin
+ if ( !reset_ ) begin
+ wr_req_in <= 1'b0;
+ wr_busy_in <= 1'b0;
+ end else begin
+ wr_busy_in <= wr_busy_in_next;
+ if ( !wr_busy_in_int ) begin
+ wr_req_in <= wr_req && !wr_busy_in;
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if ( wr_busy_in_int ) begin
+ end else begin
+ wr_req_in <= `x_or_0;
+ end
+ // VCS coverage on
+ `endif // SYNTHESIS
+ end
+end
+
+reg wr_busy_int; // copy for internal use
+assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space?
+
+
+
+wire wr_popping; // fwd: write side sees pop?
+
+
+reg [6:0] wr_count; // write-side count
+
+wire [6:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484
+wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484
+wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
+ wr_count_next_no_wr_popping;
+
+wire wr_count_next_no_wr_popping_is_64 = ( wr_count_next_no_wr_popping == 7'd64 );
+wire wr_count_next_is_64 = wr_popping ? 1'b0 :
+ wr_count_next_no_wr_popping_is_64;
+wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides
+wire [6:0] wr_limit_reg = wr_limit_muxed;
+ // VCS coverage off
+assign wr_busy_next = wr_count_next_is_64 || // busy next cycle?
+ (wr_limit_reg != 7'd0 && // check wr_limit if != 0
+ wr_count_next >= wr_limit_reg) ;
+ // VCS coverage on
+assign wr_busy_in_int = wr_req_in && wr_busy_int;
+always @( posedge clk_mgated or negedge reset_ ) begin
+ if ( !reset_ ) begin
+ wr_busy_int <= 1'b0;
+ wr_count <= 7'd0;
+ end else begin
+ wr_busy_int <= wr_busy_next;
+ if ( wr_reserving ^ wr_popping ) begin
+ wr_count <= wr_count_next;
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if ( !(wr_reserving ^ wr_popping) ) begin
+ end else begin
+ wr_count <= {7{`x_or_0}};
+ end
+ // VCS coverage on
+ `endif // SYNTHESIS
+ end
+end
+
+wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in
+
+//
+// RAM
+//
+
+reg [5:0] wr_adr; // current write address
+
+// spyglass disable_block W484
+// next wr_adr if wr_pushing=1
+wire [5:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484
+always @( posedge clk_mgated or negedge reset_ ) begin
+ if ( !reset_ ) begin
+ wr_adr <= 6'd0;
+ end else begin
+ if ( wr_pushing ) begin
+ wr_adr <= wr_adr_next;
+ end
+ end
+end
+// spyglass enable_block W484
+
+wire rd_popping;
+
+reg [5:0] rd_adr; // read address this cycle
+wire ram_we = wr_pushing && (wr_count > 7'd0 || !rd_popping); // note: write occurs next cycle
+wire ram_iwe = !wr_busy_in && wr_req;
+wire rd_data_p; // read data out of ram
+
+wire [31 : 0] pwrbus_ram_pd;
+
+// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen.
+// Fifogen handles this by ignoring the data on the ram data out for that cycle.
+
+
+irq_upstream_reqfifo_flopram_rwsa_64x1 ram (
+ .clk( clk )
+ , .clk_mgated( clk_mgated )
+ , .pwrbus_ram_pd ( pwrbus_ram_pd )
+ , .di ( wr_data )
+ , .iwe ( ram_iwe )
+ , .we ( ram_we )
+ , .wa ( wr_adr )
+ , .ra ( (wr_count == 0) ? 7'd64 : {1'b0,rd_adr} )
+ , .dout ( rd_data_p )
+ );
+
+
+wire [5:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484
+always @( posedge clk_mgated or negedge reset_ ) begin
+ if ( !reset_ ) begin
+ rd_adr <= 6'd0;
+ end else begin
+ if ( rd_popping ) begin
+ rd_adr <= rd_adr_next_popping;
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if ( !rd_popping ) begin
+ end else begin
+ rd_adr <= {6{`x_or_0}};
+ end
+ // VCS coverage on
+ `endif // SYNTHESIS
+ end
+end
+
+//
+// SYNCHRONOUS BOUNDARY
+//
+
+
+assign wr_popping = rd_popping; // let it be seen immediately
+
+
+wire rd_pushing = wr_pushing; // let it be seen immediately
+
+//
+// READ SIDE
+//
+
+wire rd_req_p; // data out of fifo is valid
+
+reg rd_req_int; // internal copy of rd_req
+assign rd_req = rd_req_int;
+assign rd_popping = rd_req_p && !(rd_req_int && rd_busy);
+
+reg [6:0] rd_count_p; // read-side fifo count
+// spyglass disable_block W164a W484
+wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p :
+ (rd_count_p - 1'd1);
+wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) :
+ rd_count_p;
+// spyglass enable_block W164a W484
+wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
+ rd_count_p_next_no_rd_popping;
+assign rd_req_p = rd_count_p != 0 || rd_pushing;
+always @( posedge clk_mgated or negedge reset_ ) begin
+ if ( !reset_ ) begin
+ rd_count_p <= 7'd0;
+ end else begin
+ if ( rd_pushing || rd_popping ) begin
+ rd_count_p <= rd_count_p_next;
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if ( !(rd_pushing || rd_popping ) ) begin
+ end else begin
+ rd_count_p <= {7{`x_or_0}};
+ end
+ // VCS coverage on
+ `endif // SYNTHESIS
+ end
+end
+reg rd_data; // output data register
+wire rd_req_next = (rd_req_p || (rd_req_int && rd_busy)) ;
+
+always @( posedge clk_mgated or negedge reset_ ) begin
+ if ( !reset_ ) begin
+ rd_req_int <= 1'b0;
+ end else begin
+ rd_req_int <= rd_req_next;
+ end
+end
+always @( posedge clk_mgated ) begin
+ if ( (rd_popping) ) begin
+ rd_data <= rd_data_p;
+ end
+ `ifndef SYNTHESIS
+ // VCS coverage off
+ else if ( !((rd_popping)) ) begin
+ end else begin
+ rd_data <= {1{`x_or_0}};
+ end
+ // VCS coverage on
+ `endif // SYNTHESIS
+end
+//
+// Read-side Idle Calculation
+//
+wire rd_idle = !rd_req_int && !rd_pushing && rd_count_p == 0;
+
+
+//
+// Write-Side Idle Calculation
+//
+wire wr_idle_d0 = !wr_req_in && rd_idle && !wr_pushing && wr_count == 0
+// VCS coverage off
+`ifndef SYNTH_LEVEL1_COMPILE
+`ifndef SYNTHESIS
+ && !wr_pause_rand_in
+`endif
+`endif
+// VCS coverage on
+;
+wire wr_idle = wr_idle_d0;
+
+
+// Master Clock Gating (SLCG) Enables
+//
+
+// plusarg for disabling this stuff:
+
+// VCS coverage off
+`ifndef SYNTH_LEVEL1_COMPILE
+`ifndef SYNTHESIS
+reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
+`endif
+`endif
+// VCS coverage on
+
+// VCS coverage off
+`ifndef SYNTH_LEVEL1_COMPILE
+`ifndef SYNTHESIS
+reg wr_pause_rand_dly;
+always @( posedge clk or negedge reset_ ) begin
+ if ( !reset_ ) begin
+ wr_pause_rand_dly <= 1'b0;
+ end else begin
+ wr_pause_rand_dly <= wr_pause_rand;
+ end
+end
+`endif
+`endif
+// VCS coverage on
+assign clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && !rd_busy)) || (wr_pushing))
+ `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
+ || 1'b1
+ `endif
+ // VCS coverage off
+ `ifndef SYNTH_LEVEL1_COMPILE
+ `ifndef SYNTHESIS
+ || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly)
+ `endif
+ `endif
+ // VCS coverage on
+;
+
+
+// Simulation and Emulation Overrides of wr_limit(s)
+//
+
+`ifdef EMU
+
+`ifdef EMU_FIFO_CFG
+// Emulation Global Config Override
+//
+assign wr_limit_muxed = `EMU_FIFO_CFG.irq_upstream_reqfifo_wr_limit_override ? `EMU_FIFO_CFG.irq_upstream_reqfifo_wr_limit : 7'd0;
+`else
+// No Global Override for Emulation
+//
+assign wr_limit_muxed = 7'd0;
+`endif // EMU_FIFO_CFG
+
+`else // !EMU
+`ifdef SYNTH_LEVEL1_COMPILE
+
+// No Override for GCS Compiles
+//
+assign wr_limit_muxed = 7'd0;
+`else
+`ifdef SYNTHESIS
+
+// No Override for RTL Synthesis
+//
+
+assign wr_limit_muxed = 7'd0;
+
+`else
+
+// RTL Simulation Plusarg Override
+
+
+// VCS coverage off
+
+reg wr_limit_override;
+reg [6:0] wr_limit_override_value;
+assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0;
+initial begin
+ wr_limit_override = 0;
+ wr_limit_override_value = 0; // to keep viva happy with dangles
+ if ( $test$plusargs( "irq_upstream_reqfifo_wr_limit" ) ) begin
+ wr_limit_override = 1;
+ $value$plusargs( "irq_upstream_reqfifo_wr_limit=%d", wr_limit_override_value);
+ end
+end
+
+// VCS coverage on
+
+
+`endif
+`endif
+`endif
+
+
+// Random Write-Side Stalling
+// VCS coverage off
+`ifndef SYNTH_LEVEL1_COMPILE
+`ifndef SYNTHESIS
+// VCS coverage off
+
+// leda W339 OFF -- Non synthesizable operator
+// leda W372 OFF -- Undefined PLI task
+// leda W373 OFF -- Undefined PLI function
+// leda W599 OFF -- This construct is not supported by Synopsys
+// leda W430 OFF -- Initial statement is not synthesizable
+// leda W182 OFF -- Illegal statement for synthesis
+// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants
+// leda DCVER_274_NV OFF -- This system task is not supported by DC
+
+integer stall_probability; // prob of stalling
+integer stall_cycles_min; // min cycles to stall
+integer stall_cycles_max; // max cycles to stall
+integer stall_cycles_left; // stall cycles left
+initial begin
+ stall_probability = 0; // no stalling by default
+ stall_cycles_min = 1;
+ stall_cycles_max = 10;
+
+ if ( $test$plusargs( "irq_upstream_reqfifo_fifo_stall_probability" ) ) begin
+ $value$plusargs( "irq_upstream_reqfifo_fifo_stall_probability=%d", stall_probability);
+ end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin
+ $value$plusargs( "default_fifo_stall_probability=%d", stall_probability);
+ end
+
+ if ( $test$plusargs( "irq_upstream_reqfifo_fifo_stall_cycles_min" ) ) begin
+ $value$plusargs( "irq_upstream_reqfifo_fifo_stall_cycles_min=%d", stall_cycles_min);
+ end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin
+ $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min);
+ end
+
+ if ( $test$plusargs( "irq_upstream_reqfifo_fifo_stall_cycles_max" ) ) begin
+ $value$plusargs( "irq_upstream_reqfifo_fifo_stall_cycles_max=%d", stall_cycles_max);
+ end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin
+ $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max);
+ end
+
+ if ( stall_cycles_min < 1 ) begin
+ stall_cycles_min = 1;
+ end
+
+ if ( stall_cycles_min > stall_cycles_max ) begin
+ stall_cycles_max = stall_cycles_min;
+ end
+
+end
+
+// randomization globals
+`ifdef SIMTOP_RANDOMIZE_STALLS
+ always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin
+ if ( ! $test$plusargs( "irq_upstream_reqfifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability;
+ if ( ! $test$plusargs( "irq_upstream_reqfifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min;
+ if ( ! $test$plusargs( "irq_upstream_reqfifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max;
+ end
+`endif
+
+
+always @( negedge clk or negedge reset_ ) begin
+ if ( !reset_ ) begin
+ stall_cycles_left <= 0;
+ end else begin
+ if ( wr_req && !(wr_busy)
+ && stall_probability != 0 ) begin
+ if ( prand_inst0(1, 100) <= stall_probability ) begin
+ stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max);
+ end else if ( stall_cycles_left !== 0 ) begin
+ stall_cycles_left <= stall_cycles_left - 1;
+ end
+ end else if ( stall_cycles_left !== 0 ) begin
+ stall_cycles_left <= stall_cycles_left - 1;
+ end
+ end
+end
+
+assign wr_pause_rand = (stall_cycles_left !== 0) ;
+always @( posedge clk or negedge reset_ ) begin
+ if ( !reset_ ) begin
+ wr_pause_rand_in <= 1'b0;
+ end else begin
+ wr_pause_rand_in <= wr_pause_rand;
+ end
+end
+
+// VCS coverage on
+`endif
+`endif
+// VCS coverage on
+
+// leda W339 ON
+// leda W372 ON
+// leda W373 ON
+// leda W599 ON
+// leda W430 ON
+// leda W182 ON
+// leda W639 ON
+// leda DCVER_274_NV ON
+
+
+//
+// Histogram of fifo depth (from write side's perspective)
+//
+// NOTE: it will reference `SIMTOP.perfmon_enabled, so that
+// has to at least be defined, though not initialized.
+// tbgen testbenches have it already and various
+// ways to turn it on and off.
+//
+`ifdef NO_PERFMON_HISTOGRAM
+`else
+// VCS coverage off
+`ifndef SYNTH_LEVEL1_COMPILE
+`ifndef SYNTHESIS
+perfmon_histogram perfmon (
+ .clk ( clk )
+ , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd64 : wr_limit_reg} )
+ , .curr ( {25'd0, wr_count} )
+ );
+`endif
+`endif
+// VCS coverage on
+`endif
+
+// spyglass disable_block W164a W164b W116 W484 W504
+
+`ifdef SPYGLASS
+`else
+
+`ifdef FIFOGEN_KEEP_ASSERTION_VERIF_CODE
+// VCS coverage off
+`ifdef ASSERT_ON
+
+
+
+`ifdef SPYGLASS
+wire disable_assert_plusarg = 1'b0;
+`else
+
+`ifdef FV_ASSERT_ON
+wire disable_assert_plusarg = 1'b0;
+`else
+wire disable_assert_plusarg = |($test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"));
+`endif // ifdef FV_ASSERT_ON
+
+`endif // ifdef SPYGLASS
+
+
+wire assert_enabled = 1'b1 && !disable_assert_plusarg;
+
+
+`endif // ifdef ASSERT_ON
+// VCS coverage on
+`endif // ifdef FIFOGEN_KEEP_ASSERTION_VERIF_CODE
+
+
+`ifdef ASSERT_ON
+
+// VCS coverage off
+`ifndef SYNTH_LEVEL1_COMPILE
+`ifndef SYNTHESIS
+always @(assert_enabled) begin
+ if ( assert_enabled === 1'b0 ) begin
+ $display("Asserts are disabled for %m");
+ end
+end
+`endif
+`endif
+// VCS coverage on
+
+`endif
+
+`endif
+
+// spyglass enable_block W164a W164b W116 W484 W504
+
+
+
+`ifdef COVER
+
+wire wr_testpoint_reset_ = ( reset_ === 1'bx ? 1'b0 : reset_ );
+
+
+
+`ifndef DISABLE_TESTPOINTS
+ `ifdef COVER
+ `define COVER_OR_TP__Fifo_Full_OR_COVER
+ `endif // COVER
+
+ `ifdef COVER
+ `define COVER_OR_TP__Fifo_Full_OR_COVER
+ `endif // COVER
+
+ `ifdef TP__Fifo_Full
+ `define COVER_OR_TP__Fifo_Full_OR_COVER
+ `endif // TP__Fifo_Full
+
+`ifdef COVER_OR_TP__Fifo_Full_OR_COVER
+
+
+//VCS coverage off
+ // TESTPOINT_START
+ // NAME="Fifo Full"
+ // TYPE=OCCURRENCE
+ // AUTOGEN=true
+ // COUNT=1
+ // GROUP="DEFAULT"
+ // INFO=""
+ // RANDOM_COVER=true
+ // ASYNC_RESET=0
+ // ACTIVE_HIGH_RESET=0
+wire testpoint_0_internal_clk = clk;
+wire testpoint_0_internal_wr_testpoint_reset_ = wr_testpoint_reset_;
+
+`ifdef FV_COVER_ON
+ // Synthesizable code for SFV.
+ wire testpoint_got_reset_testpoint_0_internal_wr_testpoint_reset__with_clock_testpoint_0_internal_clk = 1'b1;
+`else
+ // Must be clocked with reset active before we start gathering
+ // coverage.
+ // Reset signal: testpoint_0_internal_wr_testpoint_reset_
+ // Clock signal: testpoint_0_internal_clk
+ reg testpoint_got_reset_testpoint_0_internal_wr_testpoint_reset__with_clock_testpoint_0_internal_clk;
+
+ initial
+ testpoint_got_reset_testpoint_0_internal_wr_testpoint_reset__with_clock_testpoint_0_internal_clk <= 1'b0;
+
+ always @(posedge testpoint_0_internal_clk) begin: HAS_RETENTION_TESTPOINT_RESET_0
+ if (~testpoint_0_internal_wr_testpoint_reset_)
+ testpoint_got_reset_testpoint_0_internal_wr_testpoint_reset__with_clock_testpoint_0_internal_clk <= 1'b1;
+ end
+`endif
+
+`ifndef LINE_TESTPOINTS_OFF
+ reg testpoint_0_count_0;
+
+ reg testpoint_0_goal_0;
+ initial testpoint_0_goal_0 = 0;
+ initial testpoint_0_count_0 = 0;
+ always@(testpoint_0_count_0) begin
+ if(testpoint_0_count_0 >= 1)
+ begin
+ `ifdef COVER_PRINT_TESTPOINT_HITS
+ if (testpoint_0_goal_0 != 1'b1)
+ $display("TESTPOINT_HIT: irq_upstream_reqfifo ::: Fifo Full ::: wr_count==64");
+ `endif
+ //VCS coverage on
+ //coverage name irq_upstream_reqfifo ::: Fifo Full ::: testpoint_0_goal_0
+ testpoint_0_goal_0 = 1'b1;
+ //VCS coverage off
+ end
+ else
+ testpoint_0_goal_0 = 1'b0;
+ end
+
+ // Increment counters for every condition that's true this clock.
+ always @(posedge testpoint_0_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0
+ if (testpoint_0_internal_wr_testpoint_reset_) begin
+ `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER
+ if ((wr_count==64) && testpoint_got_reset_testpoint_0_internal_wr_testpoint_reset__with_clock_testpoint_0_internal_clk)
+ $display("NVIDIA TESTPOINT: irq_upstream_reqfifo ::: Fifo Full ::: testpoint_0_goal_0");
+ `endif
+ if ((wr_count==64) && testpoint_got_reset_testpoint_0_internal_wr_testpoint_reset__with_clock_testpoint_0_internal_clk)
+ testpoint_0_count_0 <= 1'd1;
+ end
+ else begin
+ `ifndef FV_COVER_ON
+ if (!testpoint_got_reset_testpoint_0_internal_wr_testpoint_reset__with_clock_testpoint_0_internal_clk) begin
+ `endif
+ testpoint_0_count_0 <= 1'd0;
+ `ifndef FV_COVER_ON
+ end
+ `endif
+ end
+ end
+`endif // LINE_TESTPOINTS_OFF
+
+`ifndef SV_TESTPOINTS_OFF
+ wire testpoint_0_goal_0_active = ((wr_count==64) && testpoint_got_reset_testpoint_0_internal_wr_testpoint_reset__with_clock_testpoint_0_internal_clk);
+
+ // system verilog testpoints, to leverage vcs testpoint coverage tools
+ `ifndef SV_TESTPOINTS_DESCRIPTIVE
+ system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_clk), .tp(testpoint_0_goal_0_active));
+ `else
+ system_verilog_testpoint svt_Fifo_Full_0 (.clk (testpoint_0_internal_clk), .tp(testpoint_0_goal_0_active));
+ `endif
+`endif
+
+ //VCS coverage on
+`endif //COVER_OR_TP__Fifo_Full_OR_COVER
+`endif // DISABLE_TESTPOINTS
+
+ // TESTPOINT_END
+`ifndef DISABLE_TESTPOINTS
+ `ifdef COVER
+ `define COVER_OR_TP__Fifo_Full_and_wr_req_OR_COVER
+ `endif // COVER
+
+ `ifdef COVER
+ `define COVER_OR_TP__Fifo_Full_and_wr_req_OR_COVER
+ `endif // COVER
+
+ `ifdef TP__Fifo_Full_and_wr_req
+ `define COVER_OR_TP__Fifo_Full_and_wr_req_OR_COVER
+ `endif // TP__Fifo_Full_and_wr_req
+
+`ifdef COVER_OR_TP__Fifo_Full_and_wr_req_OR_COVER
+
+
+//VCS coverage off
+ // TESTPOINT_START
+ // NAME="Fifo Full and wr_req"
+ // TYPE=OCCURRENCE
+ // AUTOGEN=true
+ // COUNT=1
+ // GROUP="DEFAULT"
+ // INFO=""
+ // RANDOM_COVER=true
+ // ASYNC_RESET=0
+ // ACTIVE_HIGH_RESET=0
+wire testpoint_1_internal_clk = clk;
+wire testpoint_1_internal_wr_testpoint_reset_ = wr_testpoint_reset_;
+
+`ifdef FV_COVER_ON
+ // Synthesizable code for SFV.
+ wire testpoint_got_reset_testpoint_1_internal_wr_testpoint_reset__with_clock_testpoint_1_internal_clk = 1'b1;
+`else
+ // Must be clocked with reset active before we start gathering
+ // coverage.
+ // Reset signal: testpoint_1_internal_wr_testpoint_reset_
+ // Clock signal: testpoint_1_internal_clk
+ reg testpoint_got_reset_testpoint_1_internal_wr_testpoint_reset__with_clock_testpoint_1_internal_clk;
+
+ initial
+ testpoint_got_reset_testpoint_1_internal_wr_testpoint_reset__with_clock_testpoint_1_internal_clk <= 1'b0;
+
+ always @(posedge testpoint_1_internal_clk) begin: HAS_RETENTION_TESTPOINT_RESET_1
+ if (~testpoint_1_internal_wr_testpoint_reset_)
+ testpoint_got_reset_testpoint_1_internal_wr_testpoint_reset__with_clock_testpoint_1_internal_clk <= 1'b1;
+ end
+`endif
+
+`ifndef LINE_TESTPOINTS_OFF
+ reg testpoint_1_count_0;
+
+ reg testpoint_1_goal_0;
+ initial testpoint_1_goal_0 = 0;
+ initial testpoint_1_count_0 = 0;
+ always@(testpoint_1_count_0) begin
+ if(testpoint_1_count_0 >= 1)
+ begin
+ `ifdef COVER_PRINT_TESTPOINT_HITS
+ if (testpoint_1_goal_0 != 1'b1)
+ $display("TESTPOINT_HIT: irq_upstream_reqfifo ::: Fifo Full and wr_req ::: wr_count==64 && wr_req");
+ `endif
+ //VCS coverage on
+ //coverage name irq_upstream_reqfifo ::: Fifo Full and wr_req ::: testpoint_1_goal_0
+ testpoint_1_goal_0 = 1'b1;
+ //VCS coverage off
+ end
+ else
+ testpoint_1_goal_0 = 1'b0;
+ end
+
+ // Increment counters for every condition that's true this clock.
+ always @(posedge testpoint_1_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1
+ if (testpoint_1_internal_wr_testpoint_reset_) begin
+ `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER
+ if ((wr_count==64 && wr_req) && testpoint_got_reset_testpoint_1_internal_wr_testpoint_reset__with_clock_testpoint_1_internal_clk)
+ $display("NVIDIA TESTPOINT: irq_upstream_reqfifo ::: Fifo Full and wr_req ::: testpoint_1_goal_0");
+ `endif
+ if ((wr_count==64 && wr_req) && testpoint_got_reset_testpoint_1_internal_wr_testpoint_reset__with_clock_testpoint_1_internal_clk)
+ testpoint_1_count_0 <= 1'd1;
+ end
+ else begin
+ `ifndef FV_COVER_ON
+ if (!testpoint_got_reset_testpoint_1_internal_wr_testpoint_reset__with_clock_testpoint_1_internal_clk) begin
+ `endif
+ testpoint_1_count_0 <= 1'd0;
+ `ifndef FV_COVER_ON
+ end
+ `endif
+ end
+ end
+`endif // LINE_TESTPOINTS_OFF
+
+`ifndef SV_TESTPOINTS_OFF
+ wire testpoint_1_goal_0_active = ((wr_count==64 && wr_req) && testpoint_got_reset_testpoint_1_internal_wr_testpoint_reset__with_clock_testpoint_1_internal_clk);
+
+ // system verilog testpoints, to leverage vcs testpoint coverage tools
+ `ifndef SV_TESTPOINTS_DESCRIPTIVE
+ system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_clk), .tp(testpoint_1_goal_0_active));
+ `else
+ system_verilog_testpoint svt_Fifo_Full_and_wr_req_0 (.clk (testpoint_1_internal_clk), .tp(testpoint_1_goal_0_active));
+ `endif
+`endif
+
+ //VCS coverage on
+`endif //COVER_OR_TP__Fifo_Full_and_wr_req_OR_COVER
+`endif // DISABLE_TESTPOINTS
+
+ // TESTPOINT_END
+
+
+wire rd_testpoint_reset_ = ( reset_ === 1'bx ? 1'b0 : reset_ );
+
+
+`ifndef DISABLE_TESTPOINTS
+ `ifdef COVER
+ `define COVER_OR_TP__Fifo_not_empty_and_rd_busy_OR_COVER
+ `endif // COVER
+
+ `ifdef COVER
+ `define COVER_OR_TP__Fifo_not_empty_and_rd_busy_OR_COVER
+ `endif // COVER
+
+ `ifdef TP__Fifo_not_empty_and_rd_busy
+ `define COVER_OR_TP__Fifo_not_empty_and_rd_busy_OR_COVER
+ `endif // TP__Fifo_not_empty_and_rd_busy
+
+`ifdef COVER_OR_TP__Fifo_not_empty_and_rd_busy_OR_COVER
+
+
+//VCS coverage off
+ // TESTPOINT_START
+ // NAME="Fifo not empty and rd_busy"
+ // TYPE=OCCURRENCE
+ // AUTOGEN=true
+ // COUNT=1
+ // GROUP="DEFAULT"
+ // INFO=""
+ // RANDOM_COVER=true
+ // ASYNC_RESET=0
+ // ACTIVE_HIGH_RESET=0
+wire testpoint_2_internal_clk = clk;
+wire testpoint_2_internal_rd_testpoint_reset_ = rd_testpoint_reset_;
+
+`ifdef FV_COVER_ON
+ // Synthesizable code for SFV.
+ wire testpoint_got_reset_testpoint_2_internal_rd_testpoint_reset__with_clock_testpoint_2_internal_clk = 1'b1;
+`else
+ // Must be clocked with reset active before we start gathering
+ // coverage.
+ // Reset signal: testpoint_2_internal_rd_testpoint_reset_
+ // Clock signal: testpoint_2_internal_clk
+ reg testpoint_got_reset_testpoint_2_internal_rd_testpoint_reset__with_clock_testpoint_2_internal_clk;
+
+ initial
+ testpoint_got_reset_testpoint_2_internal_rd_testpoint_reset__with_clock_testpoint_2_internal_clk <= 1'b0;
+
+ always @(posedge testpoint_2_internal_clk) begin: HAS_RETENTION_TESTPOINT_RESET_2
+ if (~testpoint_2_internal_rd_testpoint_reset_)
+ testpoint_got_reset_testpoint_2_internal_rd_testpoint_reset__with_clock_testpoint_2_internal_clk <= 1'b1;
+ end
+`endif
+
+`ifndef LINE_TESTPOINTS_OFF
+ reg testpoint_2_count_0;
+
+ reg testpoint_2_goal_0;
+ initial testpoint_2_goal_0 = 0;
+ initial testpoint_2_count_0 = 0;
+ always@(testpoint_2_count_0) begin
+ if(testpoint_2_count_0 >= 1)
+ begin
+ `ifdef COVER_PRINT_TESTPOINT_HITS
+ if (testpoint_2_goal_0 != 1'b1)
+ $display("TESTPOINT_HIT: irq_upstream_reqfifo ::: Fifo not empty and rd_busy ::: rd_req && rd_busy");
+ `endif
+ //VCS coverage on
+ //coverage name irq_upstream_reqfifo ::: Fifo not empty and rd_busy ::: testpoint_2_goal_0
+ testpoint_2_goal_0 = 1'b1;
+ //VCS coverage off
+ end
+ else
+ testpoint_2_goal_0 = 1'b0;
+ end
+
+ // Increment counters for every condition that's true this clock.
+ always @(posedge testpoint_2_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_2
+ if (testpoint_2_internal_rd_testpoint_reset_) begin
+ `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER
+ if ((rd_req && rd_busy) && testpoint_got_reset_testpoint_2_internal_rd_testpoint_reset__with_clock_testpoint_2_internal_clk)
+ $display("NVIDIA TESTPOINT: irq_upstream_reqfifo ::: Fifo not empty and rd_busy ::: testpoint_2_goal_0");
+ `endif
+ if ((rd_req && rd_busy) && testpoint_got_reset_testpoint_2_internal_rd_testpoint_reset__with_clock_testpoint_2_internal_clk)
+ testpoint_2_count_0 <= 1'd1;
+ end
+ else begin
+ `ifndef FV_COVER_ON
+ if (!testpoint_got_reset_testpoint_2_internal_rd_testpoint_reset__with_clock_testpoint_2_internal_clk) begin
+ `endif
+ testpoint_2_count_0 <= 1'd0;
+ `ifndef FV_COVER_ON
+ end
+ `endif
+ end
+ end
+`endif // LINE_TESTPOINTS_OFF
+
+`ifndef SV_TESTPOINTS_OFF
+ wire testpoint_2_goal_0_active = ((rd_req && rd_busy) && testpoint_got_reset_testpoint_2_internal_rd_testpoint_reset__with_clock_testpoint_2_internal_clk);
+
+ // system verilog testpoints, to leverage vcs testpoint coverage tools
+ `ifndef SV_TESTPOINTS_DESCRIPTIVE
+ system_verilog_testpoint svt_testpoint_2_goal_0 (.clk (testpoint_2_internal_clk), .tp(testpoint_2_goal_0_active));
+ `else
+ system_verilog_testpoint svt_Fifo_not_empty_and_rd_busy_0 (.clk (testpoint_2_internal_clk), .tp(testpoint_2_goal_0_active));
+ `endif
+`endif
+
+ //VCS coverage on
+`endif //COVER_OR_TP__Fifo_not_empty_and_rd_busy_OR_COVER
+`endif // DISABLE_TESTPOINTS
+
+ // TESTPOINT_END
+
+reg [1:0] testpoint_empty_state;
+reg [1:0] testpoint_empty_state_nxt;
+reg testpoint_non_empty_to_empty_to_non_empty_reached;
+
+`define FIFO_INIT 2'b00
+`define FIFO_NON_EMPTY 2'b01
+`define FIFO_EMPTY 2'b10
+
+always @(testpoint_empty_state or (!rd_req)) begin
+ testpoint_empty_state_nxt = testpoint_empty_state;
+ testpoint_non_empty_to_empty_to_non_empty_reached = 0;
+ casez (testpoint_empty_state)
+ `FIFO_INIT: begin
+ if (!(!rd_req)) begin
+ testpoint_empty_state_nxt = `FIFO_NON_EMPTY;
+ end
+ end
+ `FIFO_NON_EMPTY: begin
+ if ((!rd_req)) begin
+ testpoint_empty_state_nxt = `FIFO_EMPTY;
+ end
+ end
+ `FIFO_EMPTY: begin
+ if (!(!rd_req)) begin
+ testpoint_non_empty_to_empty_to_non_empty_reached = 1;
+ testpoint_empty_state_nxt = `FIFO_NON_EMPTY;
+ end
+ end
+ // VCS coverage off
+ default: begin
+ testpoint_empty_state_nxt = `FIFO_INIT;
+ end
+ // VCS coverage on
+ endcase
+end
+always @( posedge clk or negedge reset_ ) begin
+ if ( !reset_ ) begin
+ testpoint_empty_state <= 2'b00;
+ end else begin
+ if (testpoint_empty_state != testpoint_empty_state_nxt) begin
+ testpoint_empty_state <= testpoint_empty_state_nxt;
+ end
+ end
+end
+
+`ifndef DISABLE_TESTPOINTS
+ `ifdef COVER
+ `define COVER_OR_TP__Fifo_non_empty_to_empty_to_non_empty_OR_COVER
+ `endif // COVER
+
+ `ifdef COVER
+ `define COVER_OR_TP__Fifo_non_empty_to_empty_to_non_empty_OR_COVER
+ `endif // COVER
+
+ `ifdef TP__Fifo_non_empty_to_empty_to_non_empty
+ `define COVER_OR_TP__Fifo_non_empty_to_empty_to_non_empty_OR_COVER
+ `endif // TP__Fifo_non_empty_to_empty_to_non_empty
+
+`ifdef COVER_OR_TP__Fifo_non_empty_to_empty_to_non_empty_OR_COVER
+
+
+//VCS coverage off
+ // TESTPOINT_START
+ // NAME="Fifo non-empty to empty to non-empty"
+ // TYPE=OCCURRENCE
+ // AUTOGEN=true
+ // COUNT=1
+ // GROUP="DEFAULT"
+ // INFO=""
+ // RANDOM_COVER=true
+ // ASYNC_RESET=0
+ // ACTIVE_HIGH_RESET=0
+wire testpoint_3_internal_clk = clk;
+wire testpoint_3_internal_rd_testpoint_reset_ = rd_testpoint_reset_;
+
+`ifdef FV_COVER_ON
+ // Synthesizable code for SFV.
+ wire testpoint_got_reset_testpoint_3_internal_rd_testpoint_reset__with_clock_testpoint_3_internal_clk = 1'b1;
+`else
+ // Must be clocked with reset active before we start gathering
+ // coverage.
+ // Reset signal: testpoint_3_internal_rd_testpoint_reset_
+ // Clock signal: testpoint_3_internal_clk
+ reg testpoint_got_reset_testpoint_3_internal_rd_testpoint_reset__with_clock_testpoint_3_internal_clk;
+
+ initial
+ testpoint_got_reset_testpoint_3_internal_rd_testpoint_reset__with_clock_testpoint_3_internal_clk <= 1'b0;
+
+ always @(posedge testpoint_3_internal_clk) begin: HAS_RETENTION_TESTPOINT_RESET_3
+ if (~testpoint_3_internal_rd_testpoint_reset_)
+ testpoint_got_reset_testpoint_3_internal_rd_testpoint_reset__with_clock_testpoint_3_internal_clk <= 1'b1;
+ end
+`endif
+
+`ifndef LINE_TESTPOINTS_OFF
+ reg testpoint_3_count_0;
+
+ reg testpoint_3_goal_0;
+ initial testpoint_3_goal_0 = 0;
+ initial testpoint_3_count_0 = 0;
+ always@(testpoint_3_count_0) begin
+ if(testpoint_3_count_0 >= 1)
+ begin
+ `ifdef COVER_PRINT_TESTPOINT_HITS
+ if (testpoint_3_goal_0 != 1'b1)
+ $display("TESTPOINT_HIT: irq_upstream_reqfifo ::: Fifo non-empty to empty to non-empty ::: testpoint_non_empty_to_empty_to_non_empty_reached");
+ `endif
+ //VCS coverage on
+ //coverage name irq_upstream_reqfifo ::: Fifo non-empty to empty to non-empty ::: testpoint_3_goal_0
+ testpoint_3_goal_0 = 1'b1;
+ //VCS coverage off
+ end
+ else
+ testpoint_3_goal_0 = 1'b0;
+ end
+
+ // Increment counters for every condition that's true this clock.
+ always @(posedge testpoint_3_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_3
+ if (testpoint_3_internal_rd_testpoint_reset_) begin
+ `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER
+ if ((testpoint_non_empty_to_empty_to_non_empty_reached) && testpoint_got_reset_testpoint_3_internal_rd_testpoint_reset__with_clock_testpoint_3_internal_clk)
+ $display("NVIDIA TESTPOINT: irq_upstream_reqfifo ::: Fifo non-empty to empty to non-empty ::: testpoint_3_goal_0");
+ `endif
+ if ((testpoint_non_empty_to_empty_to_non_empty_reached) && testpoint_got_reset_testpoint_3_internal_rd_testpoint_reset__with_clock_testpoint_3_internal_clk)
+ testpoint_3_count_0 <= 1'd1;
+ end
+ else begin
+ `ifndef FV_COVER_ON
+ if (!testpoint_got_reset_testpoint_3_internal_rd_testpoint_reset__with_clock_testpoint_3_internal_clk) begin
+ `endif
+ testpoint_3_count_0 <= 1'd0;
+ `ifndef FV_COVER_ON
+ end
+ `endif
+ end
+ end
+`endif // LINE_TESTPOINTS_OFF
+
+`ifndef SV_TESTPOINTS_OFF
+ wire testpoint_3_goal_0_active = ((testpoint_non_empty_to_empty_to_non_empty_reached) && testpoint_got_reset_testpoint_3_internal_rd_testpoint_reset__with_clock_testpoint_3_internal_clk);
+
+ // system verilog testpoints, to leverage vcs testpoint coverage tools
+ `ifndef SV_TESTPOINTS_DESCRIPTIVE
+ system_verilog_testpoint svt_testpoint_3_goal_0 (.clk (testpoint_3_internal_clk), .tp(testpoint_3_goal_0_active));
+ `else
+ system_verilog_testpoint svt_Fifo_non_empty_to_empty_to_non_empty_0 (.clk (testpoint_3_internal_clk), .tp(testpoint_3_goal_0_active));
+ `endif
+`endif
+
+ //VCS coverage on
+`endif //COVER_OR_TP__Fifo_non_empty_to_empty_to_non_empty_OR_COVER
+`endif // DISABLE_TESTPOINTS
+
+ // TESTPOINT_END
+
+
+`endif
+
+
+
+//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH
+// define is set. This is to aid fifogen team search for fifogen fifo
+// instance and module names in a given design.
+`ifdef FIFOGEN_MODULE_SEARCH
+NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
+`endif
+
+// spyglass enable_block W401 -- clock is not input to module
+
+// synopsys dc_script_begin
+// set_boundary_optimization find(design, "irq_upstream_reqfifo") true
+// synopsys dc_script_end
+
+
+`ifdef SYNTH_LEVEL1_COMPILE
+`else
+`ifdef SYNTHESIS
+`else
+`ifdef PRAND_VERILOG
+// Only verilog needs any local variables
+reg [47:0] prand_local_seed0;
+reg prand_initialized0;
+reg prand_no_rollpli0;
+`endif
+`endif
+`endif
+
+function [31:0] prand_inst0;
+//VCS coverage off
+ input [31:0] min;
+ input [31:0] max;
+ reg [32:0] diff;
+
+ begin
+`ifdef SYNTH_LEVEL1_COMPILE
+ prand_inst0 = min;
+`else
+`ifdef SYNTHESIS
+ prand_inst0 = min;
+`else
+`ifdef PRAND_VERILOG
+ if (prand_initialized0 !== 1'b1) begin
+ prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI");
+ if (!prand_no_rollpli0)
+ prand_local_seed0 = {$prand_get_seed(0), 16'b0};
+ prand_initialized0 = 1'b1;
+ end
+ if (prand_no_rollpli0) begin
+ prand_inst0 = min;
+ end else begin
+ diff = max - min + 1;
+ prand_inst0 = min + prand_local_seed0[47:16] % diff;
+ // magic numbers taken from Java's random class (same as lrand48)
+ prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11;
+ end
+`else
+`ifdef PRAND_OFF
+ prand_inst0 = min;
+`else
+ prand_inst0 = $RollPLI(min, max, "auto");
+`endif
+`endif
+`endif
+`endif
+ end
+//VCS coverage on
+endfunction
+
+
+`ifdef SYNTH_LEVEL1_COMPILE
+`else
+`ifdef SYNTHESIS
+`else
+`ifdef PRAND_VERILOG
+// Only verilog needs any local variables
+reg [47:0] prand_local_seed1;
+reg prand_initialized1;
+reg prand_no_rollpli1;
+`endif
+`endif
+`endif
+
+function [31:0] prand_inst1;
+//VCS coverage off
+ input [31:0] min;
+ input [31:0] max;
+ reg [32:0] diff;
+
+ begin
+`ifdef SYNTH_LEVEL1_COMPILE
+ prand_inst1 = min;
+`else
+`ifdef SYNTHESIS
+ prand_inst1 = min;
+`else
+`ifdef PRAND_VERILOG
+ if (prand_initialized1 !== 1'b1) begin
+ prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI");
+ if (!prand_no_rollpli1)
+ prand_local_seed1 = {$prand_get_seed(1), 16'b0};
+ prand_initialized1 = 1'b1;
+ end
+ if (prand_no_rollpli1) begin
+ prand_inst1 = min;
+ end else begin
+ diff = max - min + 1;
+ prand_inst1 = min + prand_local_seed1[47:16] % diff;
+ // magic numbers taken from Java's random class (same as lrand48)
+ prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11;
+ end
+`else
+`ifdef PRAND_OFF
+ prand_inst1 = min;
+`else
+ prand_inst1 = $RollPLI(min, max, "auto");
+`endif
+`endif
+`endif
+`endif
+ end
+//VCS coverage on
+endfunction
+
+
+
+
+endmodule // irq_upstream_reqfifo
+
+//
+// Flop-Based RAM (with internal wr_reg)
+//
+module irq_upstream_reqfifo_flopram_rwsa_64x1 (
+ clk
+ , clk_mgated
+ , pwrbus_ram_pd
+ , di
+ , iwe
+ , we
+ , wa
+ , ra
+ , dout
+ );
+
+input clk; // write clock
+input clk_mgated; // write clock mgated
+input [31 : 0] pwrbus_ram_pd;
+input [0:0] di;
+input iwe;
+input we;
+input [5:0] wa;
+input [6:0] ra;
+output [0:0] dout;
+
+reg [0:0] di_d; // -wr_reg
+
+always @( posedge clk ) begin
+ if ( iwe ) begin
+ di_d <= di; // -wr_reg
+ end
+end
+
+`ifdef EMU
+
+
+wire [0:0] dout_p;
+
+// we use an emulation ram here to save flops on the emulation board
+// so that the monstrous chip can fit :-)
+//
+reg [5:0] Wa0_vmw;
+reg we0_vmw;
+reg [0:0] Di0_vmw;
+
+always @( posedge clk ) begin
+ Wa0_vmw <= wa;
+ we0_vmw <= we;
+ Di0_vmw <= di_d;
+end
+
+vmw_irq_upstream_reqfifo_flopram_rwsa_64x1 emu_ram (
+ .Wa0( Wa0_vmw )
+ , .we0( we0_vmw )
+ , .Di0( Di0_vmw )
+ , .Ra0( ra[5:0] )
+ , .Do0( dout_p )
+ );
+
+assign dout = (ra == 64) ? di_d : dout_p;
+
+`else
+
+reg [0:0] ram_ff0;
+reg [0:0] ram_ff1;
+reg [0:0] ram_ff2;
+reg [0:0] ram_ff3;
+reg [0:0] ram_ff4;
+reg [0:0] ram_ff5;
+reg [0:0] ram_ff6;
+reg [0:0] ram_ff7;
+reg [0:0] ram_ff8;
+reg [0:0] ram_ff9;
+reg [0:0] ram_ff10;
+reg [0:0] ram_ff11;
+reg [0:0] ram_ff12;
+reg [0:0] ram_ff13;
+reg [0:0] ram_ff14;
+reg [0:0] ram_ff15;
+reg [0:0] ram_ff16;
+reg [0:0] ram_ff17;
+reg [0:0] ram_ff18;
+reg [0:0] ram_ff19;
+reg [0:0] ram_ff20;
+reg [0:0] ram_ff21;
+reg [0:0] ram_ff22;
+reg [0:0] ram_ff23;
+reg [0:0] ram_ff24;
+reg [0:0] ram_ff25;
+reg [0:0] ram_ff26;
+reg [0:0] ram_ff27;
+reg [0:0] ram_ff28;
+reg [0:0] ram_ff29;
+reg [0:0] ram_ff30;
+reg [0:0] ram_ff31;
+reg [0:0] ram_ff32;
+reg [0:0] ram_ff33;
+reg [0:0] ram_ff34;
+reg [0:0] ram_ff35;
+reg [0:0] ram_ff36;
+reg [0:0] ram_ff37;
+reg [0:0] ram_ff38;
+reg [0:0] ram_ff39;
+reg [0:0] ram_ff40;
+reg [0:0] ram_ff41;
+reg [0:0] ram_ff42;
+reg [0:0] ram_ff43;
+reg [0:0] ram_ff44;
+reg [0:0] ram_ff45;
+reg [0:0] ram_ff46;
+reg [0:0] ram_ff47;
+reg [0:0] ram_ff48;
+reg [0:0] ram_ff49;
+reg [0:0] ram_ff50;
+reg [0:0] ram_ff51;
+reg [0:0] ram_ff52;
+reg [0:0] ram_ff53;
+reg [0:0] ram_ff54;
+reg [0:0] ram_ff55;
+reg [0:0] ram_ff56;
+reg [0:0] ram_ff57;
+reg [0:0] ram_ff58;
+reg [0:0] ram_ff59;
+reg [0:0] ram_ff60;
+reg [0:0] ram_ff61;
+reg [0:0] ram_ff62;
+reg [0:0] ram_ff63;
+
+always @( posedge clk_mgated ) begin
+ if ( we && wa == 6'd0 ) begin
+ ram_ff0 <= di_d;
+ end
+ if ( we && wa == 6'd1 ) begin
+ ram_ff1 <= di_d;
+ end
+ if ( we && wa == 6'd2 ) begin
+ ram_ff2 <= di_d;
+ end
+ if ( we && wa == 6'd3 ) begin
+ ram_ff3 <= di_d;
+ end
+ if ( we && wa == 6'd4 ) begin
+ ram_ff4 <= di_d;
+ end
+ if ( we && wa == 6'd5 ) begin
+ ram_ff5 <= di_d;
+ end
+ if ( we && wa == 6'd6 ) begin
+ ram_ff6 <= di_d;
+ end
+ if ( we && wa == 6'd7 ) begin
+ ram_ff7 <= di_d;
+ end
+ if ( we && wa == 6'd8 ) begin
+ ram_ff8 <= di_d;
+ end
+ if ( we && wa == 6'd9 ) begin
+ ram_ff9 <= di_d;
+ end
+ if ( we && wa == 6'd10 ) begin
+ ram_ff10 <= di_d;
+ end
+ if ( we && wa == 6'd11 ) begin
+ ram_ff11 <= di_d;
+ end
+ if ( we && wa == 6'd12 ) begin
+ ram_ff12 <= di_d;
+ end
+ if ( we && wa == 6'd13 ) begin
+ ram_ff13 <= di_d;
+ end
+ if ( we && wa == 6'd14 ) begin
+ ram_ff14 <= di_d;
+ end
+ if ( we && wa == 6'd15 ) begin
+ ram_ff15 <= di_d;
+ end
+ if ( we && wa == 6'd16 ) begin
+ ram_ff16 <= di_d;
+ end
+ if ( we && wa == 6'd17 ) begin
+ ram_ff17 <= di_d;
+ end
+ if ( we && wa == 6'd18 ) begin
+ ram_ff18 <= di_d;
+ end
+ if ( we && wa == 6'd19 ) begin
+ ram_ff19 <= di_d;
+ end
+ if ( we && wa == 6'd20 ) begin
+ ram_ff20 <= di_d;
+ end
+ if ( we && wa == 6'd21 ) begin
+ ram_ff21 <= di_d;
+ end
+ if ( we && wa == 6'd22 ) begin
+ ram_ff22 <= di_d;
+ end
+ if ( we && wa == 6'd23 ) begin
+ ram_ff23 <= di_d;
+ end
+ if ( we && wa == 6'd24 ) begin
+ ram_ff24 <= di_d;
+ end
+ if ( we && wa == 6'd25 ) begin
+ ram_ff25 <= di_d;
+ end
+ if ( we && wa == 6'd26 ) begin
+ ram_ff26 <= di_d;
+ end
+ if ( we && wa == 6'd27 ) begin
+ ram_ff27 <= di_d;
+ end
+ if ( we && wa == 6'd28 ) begin
+ ram_ff28 <= di_d;
+ end
+ if ( we && wa == 6'd29 ) begin
+ ram_ff29 <= di_d;
+ end
+ if ( we && wa == 6'd30 ) begin
+ ram_ff30 <= di_d;
+ end
+ if ( we && wa == 6'd31 ) begin
+ ram_ff31 <= di_d;
+ end
+ if ( we && wa == 6'd32 ) begin
+ ram_ff32 <= di_d;
+ end
+ if ( we && wa == 6'd33 ) begin
+ ram_ff33 <= di_d;
+ end
+ if ( we && wa == 6'd34 ) begin
+ ram_ff34 <= di_d;
+ end
+ if ( we && wa == 6'd35 ) begin
+ ram_ff35 <= di_d;
+ end
+ if ( we && wa == 6'd36 ) begin
+ ram_ff36 <= di_d;
+ end
+ if ( we && wa == 6'd37 ) begin
+ ram_ff37 <= di_d;
+ end
+ if ( we && wa == 6'd38 ) begin
+ ram_ff38 <= di_d;
+ end
+ if ( we && wa == 6'd39 ) begin
+ ram_ff39 <= di_d;
+ end
+ if ( we && wa == 6'd40 ) begin
+ ram_ff40 <= di_d;
+ end
+ if ( we && wa == 6'd41 ) begin
+ ram_ff41 <= di_d;
+ end
+ if ( we && wa == 6'd42 ) begin
+ ram_ff42 <= di_d;
+ end
+ if ( we && wa == 6'd43 ) begin
+ ram_ff43 <= di_d;
+ end
+ if ( we && wa == 6'd44 ) begin
+ ram_ff44 <= di_d;
+ end
+ if ( we && wa == 6'd45 ) begin
+ ram_ff45 <= di_d;
+ end
+ if ( we && wa == 6'd46 ) begin
+ ram_ff46 <= di_d;
+ end
+ if ( we && wa == 6'd47 ) begin
+ ram_ff47 <= di_d;
+ end
+ if ( we && wa == 6'd48 ) begin
+ ram_ff48 <= di_d;
+ end
+ if ( we && wa == 6'd49 ) begin
+ ram_ff49 <= di_d;
+ end
+ if ( we && wa == 6'd50 ) begin
+ ram_ff50 <= di_d;
+ end
+ if ( we && wa == 6'd51 ) begin
+ ram_ff51 <= di_d;
+ end
+ if ( we && wa == 6'd52 ) begin
+ ram_ff52 <= di_d;
+ end
+ if ( we && wa == 6'd53 ) begin
+ ram_ff53 <= di_d;
+ end
+ if ( we && wa == 6'd54 ) begin
+ ram_ff54 <= di_d;
+ end
+ if ( we && wa == 6'd55 ) begin
+ ram_ff55 <= di_d;
+ end
+ if ( we && wa == 6'd56 ) begin
+ ram_ff56 <= di_d;
+ end
+ if ( we && wa == 6'd57 ) begin
+ ram_ff57 <= di_d;
+ end
+ if ( we && wa == 6'd58 ) begin
+ ram_ff58 <= di_d;
+ end
+ if ( we && wa == 6'd59 ) begin
+ ram_ff59 <= di_d;
+ end
+ if ( we && wa == 6'd60 ) begin
+ ram_ff60 <= di_d;
+ end
+ if ( we && wa == 6'd61 ) begin
+ ram_ff61 <= di_d;
+ end
+ if ( we && wa == 6'd62 ) begin
+ ram_ff62 <= di_d;
+ end
+ if ( we && wa == 6'd63 ) begin
+ ram_ff63 <= di_d;
+ end
+end
+
+reg [0:0] dout;
+
+always @(*) begin
+ case( ra )
+ 7'd0: dout = ram_ff0;
+ 7'd1: dout = ram_ff1;
+ 7'd2: dout = ram_ff2;
+ 7'd3: dout = ram_ff3;
+ 7'd4: dout = ram_ff4;
+ 7'd5: dout = ram_ff5;
+ 7'd6: dout = ram_ff6;
+ 7'd7: dout = ram_ff7;
+ 7'd8: dout = ram_ff8;
+ 7'd9: dout = ram_ff9;
+ 7'd10: dout = ram_ff10;
+ 7'd11: dout = ram_ff11;
+ 7'd12: dout = ram_ff12;
+ 7'd13: dout = ram_ff13;
+ 7'd14: dout = ram_ff14;
+ 7'd15: dout = ram_ff15;
+ 7'd16: dout = ram_ff16;
+ 7'd17: dout = ram_ff17;
+ 7'd18: dout = ram_ff18;
+ 7'd19: dout = ram_ff19;
+ 7'd20: dout = ram_ff20;
+ 7'd21: dout = ram_ff21;
+ 7'd22: dout = ram_ff22;
+ 7'd23: dout = ram_ff23;
+ 7'd24: dout = ram_ff24;
+ 7'd25: dout = ram_ff25;
+ 7'd26: dout = ram_ff26;
+ 7'd27: dout = ram_ff27;
+ 7'd28: dout = ram_ff28;
+ 7'd29: dout = ram_ff29;
+ 7'd30: dout = ram_ff30;
+ 7'd31: dout = ram_ff31;
+ 7'd32: dout = ram_ff32;
+ 7'd33: dout = ram_ff33;
+ 7'd34: dout = ram_ff34;
+ 7'd35: dout = ram_ff35;
+ 7'd36: dout = ram_ff36;
+ 7'd37: dout = ram_ff37;
+ 7'd38: dout = ram_ff38;
+ 7'd39: dout = ram_ff39;
+ 7'd40: dout = ram_ff40;
+ 7'd41: dout = ram_ff41;
+ 7'd42: dout = ram_ff42;
+ 7'd43: dout = ram_ff43;
+ 7'd44: dout = ram_ff44;
+ 7'd45: dout = ram_ff45;
+ 7'd46: dout = ram_ff46;
+ 7'd47: dout = ram_ff47;
+ 7'd48: dout = ram_ff48;
+ 7'd49: dout = ram_ff49;
+ 7'd50: dout = ram_ff50;
+ 7'd51: dout = ram_ff51;
+ 7'd52: dout = ram_ff52;
+ 7'd53: dout = ram_ff53;
+ 7'd54: dout = ram_ff54;
+ 7'd55: dout = ram_ff55;
+ 7'd56: dout = ram_ff56;
+ 7'd57: dout = ram_ff57;
+ 7'd58: dout = ram_ff58;
+ 7'd59: dout = ram_ff59;
+ 7'd60: dout = ram_ff60;
+ 7'd61: dout = ram_ff61;
+ 7'd62: dout = ram_ff62;
+ 7'd63: dout = ram_ff63;
+ 7'd64: dout = di_d;
+ //VCS coverage off
+ default: dout = {1{`x_or_0}};
+ //VCS coverage on
+ endcase
+end
+
+`endif // EMU
+
+endmodule // irq_upstream_reqfifo_flopram_rwsa_64x1
+
+// emulation model of flopram guts
+//
+`ifdef EMU
+
+
+module vmw_irq_upstream_reqfifo_flopram_rwsa_64x1 (
+ Wa0, we0, Di0,
+ Ra0, Do0
+ );
+
+input [5:0] Wa0;
+input we0;
+input [0:0] Di0;
+input [5:0] Ra0;
+output [0:0] Do0;
+
+// Only visible during Spyglass to avoid blackboxes.
+`ifdef SPYGLASS_FLOPRAM
+
+assign Do0 = 1'd0;
+wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0);
+
+`endif
+
+// VCS coverage off
+`ifndef SYNTH_LEVEL1_COMPILE
+`ifndef SYNTHESIS
+reg [0:0] mem[63:0];
+
+// expand mem for debug ease
+`ifdef EMU_EXPAND_FLOPRAM_MEM
+wire [0:0] Q0 = mem[0];
+wire [0:0] Q1 = mem[1];
+wire [0:0] Q2 = mem[2];
+wire [0:0] Q3 = mem[3];
+wire [0:0] Q4 = mem[4];
+wire [0:0] Q5 = mem[5];
+wire [0:0] Q6 = mem[6];
+wire [0:0] Q7 = mem[7];
+wire [0:0] Q8 = mem[8];
+wire [0:0] Q9 = mem[9];
+wire [0:0] Q10 = mem[10];
+wire [0:0] Q11 = mem[11];
+wire [0:0] Q12 = mem[12];
+wire [0:0] Q13 = mem[13];
+wire [0:0] Q14 = mem[14];
+wire [0:0] Q15 = mem[15];
+wire [0:0] Q16 = mem[16];
+wire [0:0] Q17 = mem[17];
+wire [0:0] Q18 = mem[18];
+wire [0:0] Q19 = mem[19];
+wire [0:0] Q20 = mem[20];
+wire [0:0] Q21 = mem[21];
+wire [0:0] Q22 = mem[22];
+wire [0:0] Q23 = mem[23];
+wire [0:0] Q24 = mem[24];
+wire [0:0] Q25 = mem[25];
+wire [0:0] Q26 = mem[26];
+wire [0:0] Q27 = mem[27];
+wire [0:0] Q28 = mem[28];
+wire [0:0] Q29 = mem[29];
+wire [0:0] Q30 = mem[30];
+wire [0:0] Q31 = mem[31];
+wire [0:0] Q32 = mem[32];
+wire [0:0] Q33 = mem[33];
+wire [0:0] Q34 = mem[34];
+wire [0:0] Q35 = mem[35];
+wire [0:0] Q36 = mem[36];
+wire [0:0] Q37 = mem[37];
+wire [0:0] Q38 = mem[38];
+wire [0:0] Q39 = mem[39];
+wire [0:0] Q40 = mem[40];
+wire [0:0] Q41 = mem[41];
+wire [0:0] Q42 = mem[42];
+wire [0:0] Q43 = mem[43];
+wire [0:0] Q44 = mem[44];
+wire [0:0] Q45 = mem[45];
+wire [0:0] Q46 = mem[46];
+wire [0:0] Q47 = mem[47];
+wire [0:0] Q48 = mem[48];
+wire [0:0] Q49 = mem[49];
+wire [0:0] Q50 = mem[50];
+wire [0:0] Q51 = mem[51];
+wire [0:0] Q52 = mem[52];
+wire [0:0] Q53 = mem[53];
+wire [0:0] Q54 = mem[54];
+wire [0:0] Q55 = mem[55];
+wire [0:0] Q56 = mem[56];
+wire [0:0] Q57 = mem[57];
+wire [0:0] Q58 = mem[58];
+wire [0:0] Q59 = mem[59];
+wire [0:0] Q60 = mem[60];
+wire [0:0] Q61 = mem[61];
+wire [0:0] Q62 = mem[62];
+wire [0:0] Q63 = mem[63];
+`endif
+
+// asynchronous ram writes
+always @(*) begin
+ if ( we0 == 1'b1 ) begin
+ #0.1;
+ mem[Wa0] = Di0;
+ end
+end
+
+assign Do0 = mem[Ra0];
+`endif
+`endif
+// VCS coverage on
+
+// synopsys dc_script_begin
+// synopsys dc_script_end
+
+// g2c if { [find / -null_ok -subdesign vmw_irq_upstream_reqfifo_flopram_rwsa_64x1] != {} } { set_attr preserve 1 [find / -subdesign vmw_irq_upstream_reqfifo_flopram_rwsa_64x1] }
+endmodule // vmw_irq_upstream_reqfifo_flopram_rwsa_64x1
+
+//vmw: Memory vmw_irq_upstream_reqfifo_flopram_rwsa_64x1
+//vmw: Address-size 6
+//vmw: Data-size 1
+//vmw: Sensitivity level 1
+//vmw: Ports W R
+
+//vmw: terminal we0 WriteEnable0
+//vmw: terminal Wa0 address0
+//vmw: terminal Di0[0:0] data0[0:0]
+//vmw:
+//vmw: terminal Ra0 address1
+//vmw: terminal Do0[0:0] data1[0:0]
+//vmw:
+
+//qt: CELL vmw_irq_upstream_reqfifo_flopram_rwsa_64x1
+//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1
+//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1
+//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1
+//qt:
+//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1
+//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1
+//qt:
+
+`endif // EMU
+
+
+
+
diff --git a/common/design/transactors/irq/simulate_x_tick.vh b/common/design/transactors/irq/simulate_x_tick.vh
new file mode 100644
index 0000000..b8e2503
--- /dev/null
+++ b/common/design/transactors/irq/simulate_x_tick.vh
@@ -0,0 +1,43 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: simulate_x_tick.vh
+
+`ifdef _SIMULATE_X_VH_
+`else
+`define _SIMULATE_X_VH_
+
+// synopsys translate_off
+`define SIMULATION_ONLY
+//synopsys translate_on
+
+// useful values
+`ifdef SIMULATION_ONLY
+`define x_or_0 1'b0
+`define x_or_1 1'b1
+
+`define tick_x_or_0 1'b0
+`define tick_x_or_1 1'b1
+`else
+`define x_or_0 1'b0
+`define x_or_1 1'b1
+
+`define tick_x_or_0 1'b0
+`define tick_x_or_1 1'b1
+`endif
+
+// recommended tick defines
+`ifdef SIMULATION_ONLY
+`define tick_x_or_0 1'b0
+`define tick_x_or_1 1'b1
+`else
+`define tick_x_or_0 1'b0
+`define tick_x_or_1 1'b1
+`endif
+
+`endif
diff --git a/common/design/vlibs/NV_BLKBOX_SINK.v b/common/design/vlibs/NV_BLKBOX_SINK.v
new file mode 100644
index 0000000..fe9fd8a
--- /dev/null
+++ b/common/design/vlibs/NV_BLKBOX_SINK.v
@@ -0,0 +1,18 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: NV_BLKBOX_SINK.v
+
+module NV_BLKBOX_SINK (
+ A
+ );
+
+input A ;
+
+endmodule
+
diff --git a/common/design/vlibs/NV_CLK_gate_power.v b/common/design/vlibs/NV_CLK_gate_power.v
new file mode 100644
index 0000000..b325be4
--- /dev/null
+++ b/common/design/vlibs/NV_CLK_gate_power.v
@@ -0,0 +1,41 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: NV_CLK_gate_power.v
+
+module NV_CLK_gate_power (clk, reset_, clk_en, clk_gated);
+input clk, reset_, clk_en;
+output clk_gated;
+
+`ifdef VLIB_BYPASS_POWER_CG
+assign clk_gated = clk;
+`else
+
+CKLNQD12 p_clkgate (.TE(1'b0), .CP(clk), .E(clk_en), .Q(clk_gated));
+
+`endif // VLIB_BYPASS_POWER_CG
+
+// the gated clk better not be x after reset
+//
+`ifdef VERILINT
+`else
+// synopsys translate_off
+
+reg disable_asserts; initial disable_asserts = $test$plusargs( "disable_nv_clk_gate_asserts" ) != 0;
+
+nv_assert_no_x #(0, 1, 0, "clk_gated is X after reset" )
+ clk_not_x( .clk( clk ), .reset_( reset_ || disable_asserts ), .start_event( 1'b1 ), .test_expr( clk_gated ) );
+
+nv_assert_no_x #(0, 1, 0, "clk_en is X after reset" )
+ clk_en_not_x( .clk( clk ), .reset_( reset_ || disable_asserts ), .start_event( 1'b1 ), .test_expr( clk_en ) );
+
+// synopsys translate_on
+`endif
+
+endmodule // NV_CLK_gate
+
diff --git a/common/design/vlibs/p_SSYNC2DO_C_PP.v b/common/design/vlibs/p_SSYNC2DO_C_PP.v
new file mode 100644
index 0000000..048217a
--- /dev/null
+++ b/common/design/vlibs/p_SSYNC2DO_C_PP.v
@@ -0,0 +1,37 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: p_SSYNC2DO_C_PP.v
+
+module p_SSYNC2DO_C_PP (
+ clk
+ ,d
+ ,clr_
+ ,q
+ );
+
+ //---------------------------------------
+ //IO DECLARATIONS
+
+input clk ;
+input d ;
+input clr_ ;
+output q ;
+
+reg q,d0;
+
+always @(posedge clk or negedge clr_)
+begin
+ if(~clr_)
+ {q,d0} <= 2'd0;
+ else
+ {q,d0} <= {d0,d};
+end
+
+
+endmodule
diff --git a/common/design/vlibs/p_SSYNC3DO_C_PPP.v b/common/design/vlibs/p_SSYNC3DO_C_PPP.v
new file mode 100644
index 0000000..3363cd7
--- /dev/null
+++ b/common/design/vlibs/p_SSYNC3DO_C_PPP.v
@@ -0,0 +1,36 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: p_SSYNC3DO_C_PPP.v
+
+module p_SSYNC3DO_C_PPP (
+ clk
+ ,d
+ ,clr_
+ ,q
+ );
+
+ //---------------------------------------
+ //IO DECLARATIONS
+
+input clk ;
+input d ;
+input clr_ ;
+output q ;
+
+reg q,d1,d0;
+
+always @(posedge clk or negedge clr_)
+begin
+ if(~clr_)
+ {q,d1,d0} <= 3'd0;
+ else
+ {q,d1,d0} <= {d1,d0,d};
+end
+
+endmodule
diff --git a/common/design/vlibs/sync2d_c_pp.v b/common/design/vlibs/sync2d_c_pp.v
new file mode 100644
index 0000000..61a5918
--- /dev/null
+++ b/common/design/vlibs/sync2d_c_pp.v
@@ -0,0 +1,18 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: sync2d_c_pp.v
+
+module sync2d_c_pp ( d, clk, clr_, q );
+input d, clk, clr_;
+output q;
+ p_SSYNC2DO_C_PP NV_GENERIC_CELL( .d(d), .clk (clk), .clr_(clr_), .q(q) );
+ // synopsys dc_script_begin
+ // synopsys dc_script_end
+ //g2c if {[find / -null_ok -subdesign sync2d_c_pp] != {} } { set_attr preserve 1 [find / -subdesign sync2d_c_pp] }
+endmodule
diff --git a/common/design/vlibs/sync3d_c_ppp.v b/common/design/vlibs/sync3d_c_ppp.v
new file mode 100644
index 0000000..db855ef
--- /dev/null
+++ b/common/design/vlibs/sync3d_c_ppp.v
@@ -0,0 +1,18 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: sync3d_c_ppp.v
+
+module sync3d_c_ppp ( d, clk, clr_, q );
+input d, clk, clr_;
+output q;
+ p_SSYNC3DO_C_PPP NV_GENERIC_CELL( .d(d), .clk(clk), .clr_(clr_), .q(q) );
+ // synopsys dc_script_begin
+ // synopsys dc_script_end
+ //g2c if {[find / -null_ok -subdesign sync3d_c_ppp] != {} } { set_attr preserve 1 [find / -subdesign sync3d_c_ppp] }
+endmodule
diff --git a/common/design/xilinx_ip/README.md b/common/design/xilinx_ip/README.md
new file mode 100644
index 0000000..6854894
--- /dev/null
+++ b/common/design/xilinx_ip/README.md
@@ -0,0 +1,5 @@
+# Xilinux code
+
+User needs to put all code generated by Xilinux tool here before generate AFI for custom RTL logic.
+
+More details please refer [here](http://nvdla.org/vp_fpga.html).
\ No newline at end of file
diff --git a/common/software/include/cl_common_utils.h b/common/software/include/cl_common_utils.h
new file mode 100644
index 0000000..27def41
--- /dev/null
+++ b/common/software/include/cl_common_utils.h
@@ -0,0 +1,160 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+
+#ifndef CL_COMMON_UTILS_H
+#define CL_COMMON_UTILS_H
+
+#include
+#include
+
+#ifdef VP_TEST
+#define log_printf printf
+#define SIZE_UINT32 2
+#define SIZE_UINT64 3
+#else // #ifdef VP_TEST
+#ifdef SV_TEST
+// Vivado does not support svGetScopeFromName
+#ifndef VIVADO_SIM
+#include "svdpi.h"
+#endif
+#include "sh_dpi_tasks.h"
+#else
+#include
+#include
+#define log_printf printf
+#endif
+#endif // #ifdef VP_TEST
+
+#ifndef VP_TEST
+#ifndef SV_TEST
+extern pci_bar_handle_t pci_bar_handle_ocl;
+extern pci_bar_handle_t pci_bar_handle_bar1;
+extern pci_bar_handle_t pci_bar_handle_pcis;
+
+#define SIZE_UINT32 2
+#define SIZE_UINT64 3
+
+#define CFG_RESET_ADDR (0x14)
+
+#define cl_poke_ocl(addr, data) do { \
+ if (pci_bar_handle_ocl == PCI_BAR_HANDLE_INIT) { \
+ log_printf("Uninitialized pci_bar_handle_ocl!\n"); \
+ assert(0); \
+ } else { \
+ fpga_pci_poke(pci_bar_handle_ocl, addr, data); \
+ } \
+ } \
+ while (0)
+
+#define cl_peek_ocl(addr, data) do { \
+ if (pci_bar_handle_ocl == PCI_BAR_HANDLE_INIT) { \
+ log_printf("Uninitialized pci_bar_handle_ocl!\n"); \
+ assert(0); \
+ } else { \
+ fpga_pci_peek(pci_bar_handle_ocl, addr, data); \
+ } \
+ } \
+ while (0)
+
+#define cl_poke_bar1(addr, data) do { \
+ if (pci_bar_handle_bar1 == PCI_BAR_HANDLE_INIT) { \
+ log_printf("Uninitialized pci_bar_handle_bar1!\n"); \
+ assert(0); \
+ } else { \
+ fpga_pci_poke(pci_bar_handle_bar1, addr, data); \
+ } \
+ } \
+ while (0)
+
+#define cl_peek_bar1(addr, data) do { \
+ if (pci_bar_handle_bar1 == PCI_BAR_HANDLE_INIT) { \
+ log_printf("Uninitialized pci_bar_handle_bar1!\n"); \
+ assert(0); \
+ } else { \
+ fpga_pci_peek(pci_bar_handle_bar1, addr, data); \
+ } \
+ } \
+ while (0)
+
+#define cl_poke_pcis(addr, data, size) do { \
+ if (pci_bar_handle_pcis == PCI_BAR_HANDLE_INIT) { \
+ log_printf("Uninitialized pci_bar_handle_pcis!\n"); \
+ assert(0); \
+ } else { \
+ if (size == SIZE_UINT32) { \
+ fpga_pci_poke(pci_bar_handle_pcis, addr, data); \
+ } else if (size == SIZE_UINT64) { \
+ fpga_pci_poke64(pci_bar_handle_pcis, addr, data); \
+ } else { \
+ log_printf("Unsupported size: %d, only support %d and %d!\n", size, SIZE_UINT32, SIZE_UINT64); \
+ assert(0); \
+ } \
+ } \
+ } \
+ while (0)
+
+#define cl_peek_pcis(addr, data, size) do { \
+ if (pci_bar_handle_pcis == PCI_BAR_HANDLE_INIT) { \
+ log_printf("Uninitialized pci_bar_handle_pcis!\n"); \
+ assert(0); \
+ } else { \
+ if (size == SIZE_UINT32) { \
+ fpga_pci_peek(pci_bar_handle_pcis, addr, (uint32_t*)data); \
+ } else if (size == SIZE_UINT64) { \
+ fpga_pci_peek64(pci_bar_handle_pcis, addr, data); \
+ } else { \
+ log_printf("Unsupported size: %d, only support %d and %d!\n", size, SIZE_UINT32, SIZE_UINT64); \
+ assert(0); \
+ } \
+ } \
+ } \
+ while (0)
+
+#endif
+#endif
+
+// Util functions
+void apb_write(uint64_t addr, uint32_t data);
+void apb_read(uint64_t addr, uint32_t *data);
+void ddr_write(uint64_t addr, uint64_t data, uint32_t size);
+void ddr_read(uint64_t addr, uint64_t *data, uint32_t size);
+void cfg_write(uint64_t addr, uint32_t data);
+void cfg_read(uint64_t addr, uint32_t *data);
+
+#ifndef SV_TEST
+/* check if the corresponding AFI is loaded */
+int check_afi_ready(int slot_id, uint16_t pci_vendor_id, uint16_t pci_device_id);
+#endif
+
+int cl_common_init(uint16_t pci_vendor_id, uint16_t pci_device_id, uint32_t pci_int_mask);
+int cl_common_cleanup(void);
+void cl_common_reset();
+
+#ifndef VP_TEST
+#ifndef SV_TEST
+int cl_msi_poll(int timeout);
+short cl_msi_is_active(uint32_t interrupt_number);
+#endif
+#endif
+
+#ifdef VP_TEST
+void* mmap_device(off_t offset, size_t size);
+#endif
+
+#endif
diff --git a/common/software/include/cosim_top.h b/common/software/include/cosim_top.h
new file mode 100644
index 0000000..b28ba64
--- /dev/null
+++ b/common/software/include/cosim_top.h
@@ -0,0 +1,48 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: cosim_top.h
+
+#ifndef _COSIM_TOP_H_
+#define _COSIM_TOP_H_
+
+#include
+#include "shm_lib/simdb.hpp"
+#include "shm_lib/shm_defs.h"
+
+#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
+#define SC_INCLUDE_DYNAMIC_PROCESSES
+#endif
+#define SIMDB_BLOCK_SIZE 1024
+#define SIMDB_BLOCK_COUNT 1024
+
+using namespace std;
+
+class cosim_top : public sc_core::sc_module{
+public:
+ SC_HAS_PROCESS(cosim_top);
+ cosim_top( sc_core::sc_module_name name = "cosim_top");
+ ~cosim_top();
+
+private:
+ uint32_t poll_time_ns;
+
+ simdb *apb_ipc_db;
+ simdb *irq_ipc_db;
+ simdb *ram_ipc_db;
+
+ char *apb_ipc_db_nm;
+ char *irq_ipc_db_nm;
+ char *ram_ipc_db_nm;
+
+ void apb_ipc_channel();
+ void irq_ipc_channel();
+ void ram_ipc_channel();
+};
+
+#endif
diff --git a/common/software/include/sh_dpi_tasks.h b/common/software/include/sh_dpi_tasks.h
new file mode 100644
index 0000000..c150e42
--- /dev/null
+++ b/common/software/include/sh_dpi_tasks.h
@@ -0,0 +1,68 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+
+#ifndef SH_DPI_TASKS
+#define SH_DPI_TASKS
+
+#include
+#include
+
+#define SIZE_UINT8 0
+#define SIZE_UINT16 1
+#define SIZE_UINT32 2
+#define SIZE_UINT64 3
+
+#define CFG_RESET_ADDR (0x14)
+
+extern void sv_printf(char *msg);
+extern void sv_map_host_memory(uint8_t *memory);
+
+extern void cl_peek_ocl(uint64_t addr, uint32_t *data);
+extern void cl_poke_ocl(uint64_t addr, uint32_t data);
+extern void cl_peek_bar1(uint64_t addr, uint32_t *data);
+extern void cl_poke_bar1(uint64_t addr, uint32_t data);
+extern void cl_peek_pcis(uint64_t addr, uint64_t *data, uint32_t size);
+extern void cl_poke_pcis(uint64_t addr, uint64_t data, uint32_t size);
+extern void sv_int_ack(uint32_t int_num);
+
+extern void sv_pause(uint32_t x);
+
+extern void sv_assert(uint32_t x);
+
+extern void backdoor_mem_write(uint64_t addr, uint64_t data, uint32_t size, uint32_t wstrb);
+extern uint64_t backdoor_mem_read(uint64_t addr, uint32_t size);
+
+void test_main(uint32_t *exit_code);
+void trace_test_main(uint32_t *exit_code, const char *trace_output_lib, int enable_sim_mem);
+
+void cl_int_handler(uint32_t int_num);
+
+void host_memory_putc(uint64_t addr, uint8_t data);
+
+//void host_memory_getc(uint64_t addr, uint8_t *data)
+uint8_t host_memory_getc(uint64_t addr);
+
+void log_printf(const char *format, ...);
+
+void int_handler(uint32_t int_num);
+
+#define LOW_32b(a) ((uint32_t)((uint64_t)(a) & 0xffffffff))
+#define HIGH_32b(a) ((uint32_t)(((uint64_t)(a)) >> 32L))
+
+#endif
diff --git a/common/software/include/shm_lib/shm_defs.h b/common/software/include/shm_lib/shm_defs.h
new file mode 100644
index 0000000..94e596e
--- /dev/null
+++ b/common/software/include/shm_lib/shm_defs.h
@@ -0,0 +1,36 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: shm_defs.h
+
+#ifndef _SHM_DEFS_H__
+#define _SHM_DEFS_H__
+
+#include
+#include
+#define SIMDB_BLOCK_SIZE 1024
+#define SIMDB_BLOCK_COUNT 1024
+
+enum PAYLOAD_TYPE
+{
+ PAYLOAD_TYPE_APB = 0,
+ PAYLOAD_TYPE_RAM
+};
+
+struct trans_payload
+{
+ unsigned int data;
+ unsigned long long addr;
+};
+
+struct irq_trans_payload
+{
+ unsigned int value;
+};
+
+#endif
\ No newline at end of file
diff --git a/common/software/include/shm_lib/simdb.hpp b/common/software/include/shm_lib/simdb.hpp
new file mode 100644
index 0000000..3280138
--- /dev/null
+++ b/common/software/include/shm_lib/simdb.hpp
@@ -0,0 +1,1903 @@
+
+/*
+ Copyright 2017 Simeon Bassett
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ SimDB
+
+ What it does:
+ | SimDB is a key value store that uses arbitrary byte data (of arbitrary length) as both the key and the value.
+ | It additionally uses shared memory, which allows processes to communicate with each other quickly.
+ | It is lock free and scales well with multiple threads writing, reading, and deleting concurrently.
+
+ How it works:
+ |-simdb:
+ | This contains the user facing interface. It contains the ConcurrentHash, ConcurentStore, and SharedMem classes as members.
+ | These data structures are made to be an interface over the contiguous memory given to them using a single address.
+ | They do not allocate any heap memory themselves, but do have a few class members that will be on the stack. At the time of this writing it is 176 bytes on the stack.
+ |-SharedMem:
+ | | Interface to OS specific shared memory functions. Also handles an initial alignment.
+ |-ConcurrentHash:
+ | | Hash map that uses atomic operations on an array of VerIdx structs.
+ | | It uses 64 bit atomic operations to compare-exchange one VerIdx at a time (VerIdx is two unsigned 32 bit integers, a version and an index).
+ | | This makes sure that reading, writing and deleting is lock free.
+ | | Writing is lock free since a VerIdx is already fully created and written to before putting it in the VerIdx array (m_vis) and the put operation here is a single 64 bit compare and swap.
+ | | Deletion is lock free since the index in VerIdx is only freed from the CncrLst after setting the VerIdx here to DELETED. Actually deletion means 1. setting the VerIdx to DELETED 2. decrementing the readers of the blocklist that idx points to 3. If the readers variable of that blocklist is decremented below its initial value then the thread that took it below its initial value is the one to free it.
+ | | Get is lock free since it can read an index from a VerIdx, increment readers, compare its key to the key in the list of blocks, read the value in the blocks to the output buffer and finally decrement the readers variable. Just like deletion, if a thread decrements readers below its initial value, it needs to free the block list. This means the last one out cleans up.
+ |-ConcurrentStore:
+ | | Keeps track of block lists.
+ | | This primarily uses an array of BlkLst structs (which are 24 bytes each).
+ | | The BlkLst lava_vec is used to make linked lists of block indices.
+ | | The idea of a block list ends up being a starting index (from the VerIdx struct in the concurrent hash). The BlkLst struct at the starting index contains an index of the next BlkLst struct and so on until reaching a BlkLst that has an index of LIST_END. This means that one array contains multiple linked lists (using indices and not pointers of course).
+ | | This exposes an alloc() function and a free() function.
+ | | alloc() gets the index of the next block from CncrLst (concurrent list).
+ | | The BlkLst struct keeps the total length and the key length / value offset since it does not have to be atomic and is only initialized and used when one thread allocates and only destroyed when one thread frees, just like the actual data blocks.
+ |-ConcurrentList:
+ | | The concurrent list is an array integers.
+ | | The number of elements (like all the arrays) is the number of blocks.
+ | | There is one integer per block with the integer at a given index representing the next slot in the list.
+ | | The end of the list will have value LIST_END. On initialization the array's values would be |1|2|3|4| ... LIST_END, which makes a list from the start to the end. This means s_lv[0] would return 1.
+
+ Terms:
+ |-Block List:
+ | A sequence of block indices. The entry in ConcurrentHash gives the position in the block list array where the list starts.
+ | The value at each index in the array contains the index of the next block.
+ | The list end is know when a special value of LIST_END is found as the value in the array.
+ |-Block List Version:
+ | This is a version number given to each block list on allocation (not each block).
+ | It is used to link a ConcurrentHash value to the block list.
+ | If the versions are the same, it is known that the block list at the index read from ConcurrentHash has not changed.
+ | This change could happen if:
+ | | 1. Thread ONE reads the entry in ConcurrentHash but has not accessed the block list index in the entry yet. Pretend that thread one stalls and nothing more happens until further down.
+ | | 2. Thread TWO has already allocated a block list and swaps its new entry for the old entry which is still carried by thread one.
+ | | 3. Thread TWO now must free the block list given by the old entry, which it does, because no thread is reading it since thread one is still stalled.
+ | | 4. Thread TWO allocates another block list, which ends up using the blocks it just deallocated.
+ | | 5. Thread ONE wakes up and reads from the block index it found in the ConcurrentHash entry, which is no longer the same and may not even be the head of the list.
+ | | If the index is used purely for matching the binary key, this wouldn't be a problem.
+ | | When the index is used to find a binary value however, this is a problem, since the length of a different value could be the same, and there would be no data to be able to tell that they are different.
+
+ How it achieves lock free concurrency:
+ | ConcurrentHash is treated as the authority of what is stored in the database.
+ | It has an array of VerIdx structs that can also be treated as 64 bit integers. Each is dealt with atomically.
+ | Its individual bits are used as a bitfied struct containing an index into ConcurrentStore's block list as well as the version number of that list.
+ | The core is m_vis, which is an array of VerIdx structs. The memory ordering is swapped on every other index in preparation for robin hood hashing techniques, so the actual memory layout (separated into 128 bit chunks) is |Index Version Version Index|Index Version Version Index|
+ |-Finding a matching index:
+ | | 1. Use the hash of the key bytes to jump to an index.
+ | | 2. Load the integer atomically from that index and treat it as a VerIdx struct.
+ | | 3. Use the index from that struct to read the bytes from the list of blocks in BlkLst.
+ | | 4. Increment the readers variable atomically, so that it won't be deleted before this thread is done with it.
+ | | 5. If there is a match, keep reading the list of blocks to fill the output buffer with the value section of the block list.
+ | | 6. After, decrement the readers variable atomically. If readers goes below its initial value, this thread will be the one to free the block list.
+
+ Other notables:
+ | All of the main classes have a static sizeBytes() function that takes in the same arguments as a constructor and return the number of bytes that it will need in the shared memory
+ | Classes have member variables that are used as interfaces to the shared memory denoted with s_ (s for shared)
+ | Normal member variables that are just data on the stack are denoted with m_ (m for member)
+
+ _________________
+ | Memory Layout |
+ -----------------
+ ______________________________________________________________________________________________________________________
+ |Flags|BlockSize|BlockCount|ConcurrentHash|ConcurrentStore|ConcurentList|...BlockCount*BlockSize bytes for blocks....|
+ _____________________________/ \_______ \______________________________________________________
+ ______|____________________________________ ____________|_________________________________________________ ________|___________________________________________
+ |size(bytes)|...array of VerIdx structs...| |Block List Version|size(bytes)|...array of BlkLst structs...| |size(bytes)|...array of unsigned 32 bit ints (u32)|
+
+
+ First 24 bytes (in 8 byte / unsigned 64 bit chunks):
+ ____________________________
+ |Flags|BlockSize|BlockCount|
+
+ Flags: Right now holds count of the number of processes that have the db open. When the count goes to 0, the last process will delete the shared memory file.
+ BlockSize: The size in bytes of a block. A good default would be to set this to the common page size of 4096 bytes.
+ BlockCount: The number of blocks. This hash table array, block list array and concurrent list array will all be the same length. This multiplied by the BlockSize will give the total amount of bytes available for key and value data. More blocks will also mean the hash table will have less collisions as well as less contention between threads.
+
+*/
+
+#ifdef _MSC_VER
+ #pragma once
+ #pragma warning(push, 0)
+#endif
+
+#ifndef __SIMDB_HEADER_GUARD__
+#define __SIMDB_HEADER_GUARD__
+
+// turn asserts on an off - not sure of the best way to handle this with gcc and clang yet
+#ifdef _MSC_VER
+ #if !defined(_DEBUG)
+ #define NDEBUG
+ #endif
+#endif
+
+#if !defined(SECTION)
+ #define SECTION(_msvc_only_collapses_macros_with_arguments, ...)
+#endif
+
+// platform specific includes - mostly for shared memory mapping and auxillary functions like open, close and the windows equivilents
+#if defined(_WIN32) // windows
+ #include
+ #include
+
+ #include
+ #define NOMINMAX
+ #define WIN32_LEAN_AND_MEAN
+ #include
+ #include
+
+ #ifdef _MSC_VER
+ #if !defined(_CRT_SECURE_NO_WARNINGS)
+ #define _CRT_SECURE_NO_WARNINGS
+ #endif
+
+ #if !defined(_SCL_SECURE_NO_WARNINGS)
+ #define _SCL_SECURE_NO_WARNINGS
+ #endif
+ #endif
+#elif defined(__APPLE__) || defined(__MACH__) || defined(__unix__) || defined(__FreeBSD__) || defined(__linux__) // osx, linux and freebsd
+ // for mmap and munmap
+ // PROT_READ and PROT_WRITE to allow reading and writing but not executing of the mapped memory pages
+ // MAP_ANONYMOUS | MAP_SHARED for the anonymous shared memory we want
+ // mmap is system call 2 on osx, freebsd, and linux
+ // the apple docs for mmap say "BSD System Calls" so I guess they haven't changed them around
+ #include
+ #include
+ #include
+ #include
+ #include // for flock (file lock)
+ #include
+ #include
+ #include
+ #include
+ #include
+#endif
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+// platform specific type definitions
+#ifdef _WIN32 // these have to be outside the anonymous namespace
+ typedef void *HANDLE;
+ typedef HANDLE *PHANDLE;
+ typedef wchar_t WCHAR; // wc, 16-bit UNICODE character
+ typedef UCHAR BOOLEAN; // winnt
+ typedef unsigned long ULONG;
+#endif
+
+namespace {
+ enum Match { MATCH_FALSE=0, MATCH_TRUE=1, MATCH_REMOVED=-1 };
+
+ template
+ class lava_noop
+ {
+ void operator()(){}
+ };
+
+ inline uint64_t fnv_64a_buf(void const *const buf, uint64_t len) // sbassett - I know basically nothing about hash functions and there is likely a better one out there
+ {
+ uint64_t hval = 0xCBF29CE484222325;
+ uint8_t* bp = (uint8_t*)buf; // start of buffer
+ uint8_t* be = bp + len; // beyond end of buffer
+ while(bp < be){ // FNV-1a hash each octet of the buffer
+ hval ^= (uint64_t)*bp++; // xor the bottom with the current octet */
+ hval += (hval << 1) + (hval << 4) + (hval << 5) +
+ (hval << 7) + (hval << 8) + (hval << 40);
+ }
+ return hval;
+ }
+
+ inline void prefetch1(char const* const p)
+ {
+ #ifdef _MSC_VER // if msvc or intel compilers
+ _mm_prefetch(p, _MM_HINT_T1);
+ #elif defined(__GNUC__) || defined(__clang__)
+ __builtin_prefetch(p);
+ #else
+
+ #endif
+ }
+
+ #ifdef _WIN32
+ typedef struct _UNICODE_STRING {
+ USHORT Length;
+ USHORT MaximumLength;
+ #ifdef MIDL_PASS
+ [size_is(MaximumLength / 2), length_is((Length) / 2) ] USHORT * Buffer;
+ #else // MIDL_PASS
+ _Field_size_bytes_part_(MaximumLength, Length) PWCH Buffer;
+ #endif // MIDL_PASS
+ } UNICODE_STRING;
+ typedef UNICODE_STRING *PUNICODE_STRING;
+
+ typedef struct _OBJECT_ATTRIBUTES {
+ ULONG Length;
+ HANDLE RootDirectory;
+ PUNICODE_STRING ObjectName;
+ ULONG Attributes;
+ PVOID SecurityDescriptor; // Points to type SECURITY_DESCRIPTOR
+ PVOID SecurityQualityOfService; // Points to type SECURITY_QUALITY_OF_SERVICE
+ } OBJECT_ATTRIBUTES;
+ typedef OBJECT_ATTRIBUTES *POBJECT_ATTRIBUTES;
+
+ typedef long LONG;
+ typedef LONG NTSTATUS;
+
+ // the following is api poison, but seems to be the only way to list the global anonymous memory maps in windows
+ #define DIRECTORY_QUERY 0x0001
+ #define STATUS_SUCCESS ((NTSTATUS)0x00000000L) // ntsubauth
+ #define OBJ_CASE_INSENSITIVE 0x00000040L
+ #define STATUS_NO_MORE_FILES ((NTSTATUS)0x80000006L)
+ #define STATUS_NO_MORE_ENTRIES ((NTSTATUS)0x8000001AL)
+
+ typedef struct _IO_STATUS_BLOCK {
+ union {
+ NTSTATUS Status;
+ PVOID Pointer;
+ };
+ ULONG_PTR Information;
+ } IO_STATUS_BLOCK, *PIO_STATUS_BLOCK;
+
+ using NTOPENDIRECTORYOBJECT = NTSTATUS (WINAPI*)(
+ _Out_ PHANDLE DirectoryHandle,
+ _In_ ACCESS_MASK DesiredAccess,
+ _In_ POBJECT_ATTRIBUTES ObjectAttributes
+ );
+ using NTOPENFILE = NTSTATUS (WINAPI*)(
+ _Out_ PHANDLE FileHandle,
+ _In_ ACCESS_MASK DesiredAccess,
+ _In_ POBJECT_ATTRIBUTES ObjectAttributes,
+ _Out_ PIO_STATUS_BLOCK IoStatusBlock,
+ _In_ ULONG ShareAccess,
+ _In_ ULONG OpenOptions
+ );
+ using NTQUERYDIRECTORYOBJECT = NTSTATUS(WINAPI*)(
+ _In_ HANDLE DirectoryHandle,
+ _Out_opt_ PVOID Buffer,
+ _In_ ULONG Length,
+ _In_ BOOLEAN ReturnSingleEntry,
+ _In_ BOOLEAN RestartScan,
+ _Inout_ PULONG Context,
+ _Out_opt_ PULONG ReturnLength
+ );
+ using RTLINITUNICODESTRING = VOID(*)(
+ _Out_ PUNICODE_STRING DestinationString,
+ _In_opt_ PCWSTR SourceString
+ );
+
+ struct OBJECT_DIRECTORY_INFORMATION { UNICODE_STRING name; UNICODE_STRING type; };
+
+ //auto GetLastErrorStdStr() -> std::string
+ //{
+ // DWORD error = GetLastError();
+ // if (error)
+ // {
+ // LPVOID lpMsgBuf;
+ // DWORD bufLen = FormatMessage(
+ // FORMAT_MESSAGE_ALLOCATE_BUFFER |
+ // FORMAT_MESSAGE_FROM_SYSTEM |
+ // FORMAT_MESSAGE_IGNORE_INSERTS,
+ // NULL,
+ // error,
+ // MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT),
+ // (LPTSTR) &lpMsgBuf,
+ // 0, NULL );
+ // if (bufLen)
+ // {
+ // LPCSTR lpMsgStr = (LPCSTR)lpMsgBuf;
+ // std::string result(lpMsgStr, lpMsgStr+bufLen);
+ //
+ // LocalFree(lpMsgBuf);
+ //
+ // return result;
+ // }
+ // }
+ // return std::string();
+ //}
+ PVOID GetLibraryProcAddress(PSTR LibraryName, PSTR ProcName)
+ {
+ return GetProcAddress(GetModuleHandleA(LibraryName), ProcName);
+ }
+ int win_printf(const char * format, ...)
+ {
+ char szBuff[1024];
+ int retValue;
+ DWORD cbWritten;
+ va_list argptr;
+
+ va_start( argptr, format );
+ retValue = wvsprintf( szBuff, format, argptr );
+ va_end( argptr );
+
+ WriteFile( GetStdHandle(STD_OUTPUT_HANDLE), szBuff, retValue,
+ &cbWritten, 0 );
+
+ return retValue;
+ }
+ #endif // end #ifdef _WIN32
+}
+
+#ifdef _WIN32
+ #pragma warning(pop)
+#endif
+
+enum class simdb_error {
+ NO_ERRORS=2,
+ DIR_NOT_FOUND,
+ DIR_ENTRY_ERROR,
+ COULD_NOT_OPEN_MAP_FILE,
+ COULD_NOT_MEMORY_MAP_FILE,
+ SHARED_MEMORY_ERROR,
+ FTRUNCATE_FAILURE,
+ FLOCK_FAILURE,
+ PATH_TOO_LONG
+};
+
+template
+class lava_vec
+{
+public:
+ using u64 = uint64_t;
+
+private:
+ void* p;
+
+ void set_sizeBytes(u64 sb){ ((u64*)p)[-1] = sb; } // an offset of -2 should be the first 8 bytes, which store the size in bytes of the whole memory span of this lava_vec
+
+public:
+ static u64 sizeBytes(u64 count) // sizeBytes is meant to take the same arguments as a constructor and return the total number of bytes to hold the entire stucture given those arguments
+ {
+ return sizeof(u64) + count*sizeof(T);
+ }
+
+ lava_vec(){}
+ lava_vec(void* addr, u64 count, bool owner=true) :
+ p( ((u64*)addr) + 1 )
+ {
+ if(owner){
+ set_sizeBytes( lava_vec::sizeBytes(count) );
+ }
+ }
+ lava_vec(void* addr) : p( ((u64*)addr) + 2 ) {}
+ lava_vec(lava_vec const&) = delete;
+ void operator=(lava_vec const&) = delete;
+
+ lava_vec(lava_vec&& rval){ p=rval.p; rval.p=nullptr; }
+ ~lava_vec(){}
+
+ T& operator[](u64 i){ return data()[i]; }
+
+ T* data(){ return (T*)p; }
+ u64 sizeBytes() const { return ((u64*)p)[0]; } // first 8 bytes should be the total size of the buffer in bytes
+ auto addr() const -> void*
+ {
+ return p;
+ }
+};
+class CncrLst
+{
+// Internally this is an array of indices that makes a linked list
+// Externally indices can be gotten atomically and given back atomically
+// | This is used to get free indices one at a time, and give back in-use indices one at a time
+// Uses the first 8 bytes that would normally store sizeBytes as the 64 bits of memory for the Head structure
+// Aligns the head on a 64 bytes boundary with the rest of the memory on a separate 64 byte boudary. This puts them on separate cache lines which should eliminate false sharing between cores when atomicallyaccessing the Head union (which will happen quite a bit)
+public:
+ using u32 = uint32_t;
+ using u64 = uint64_t;
+ using au64 = std::atomic;
+ using ListVec = lava_vec;
+
+ union Head
+ {
+ struct { u32 ver; u32 idx; }; // ver is version, idx is index
+ u64 asInt;
+ };
+
+ static const u32 LIST_END = 0xFFFFFFFF;
+ static const u32 NXT_VER_SPECIAL = 0xFFFFFFFF;
+
+private:
+ ListVec s_lv;
+ au64* s_h;
+
+public:
+ static u64 sizeBytes(u32 size) { return ListVec::sizeBytes(size) + 128; } // an extra 128 bytes so that Head can be placed
+ static u32 incVersion(u32 v) { return v==NXT_VER_SPECIAL? 1 : v+1; }
+
+ CncrLst(){}
+ CncrLst(void* addr, u32 size, bool owner=true) // this constructor is for when the memory is owned an needs to be initialized
+ { // separate out initialization and let it be done explicitly in the simdb constructor?
+ u64 addrRem = (u64)addr % 64;
+ u64 alignAddr = (u64)addr + (64-addrRem);
+ assert( alignAddr % 64 == 0 );
+ s_h = (au64*)alignAddr;
+
+ u32* listAddr = (u32*)((u64)alignAddr+64);
+ new (&s_lv) ListVec(listAddr, size, owner);
+
+ if(owner){
+ for(u32 i=0; i<(size-1); ++i) s_lv[i] = i+1;
+ s_lv[size-1] = LIST_END;
+
+ ((Head*)s_h)->idx = 0;
+ ((Head*)s_h)->ver = 0;
+ }
+ }
+
+ u32 nxt() // moves forward in the list and return the previous index
+ {
+ Head curHead, nxtHead;
+ curHead.asInt = s_h->load();
+ do{
+ if(curHead.idx==LIST_END){return LIST_END;}
+
+ nxtHead.idx = s_lv[curHead.idx];
+ nxtHead.ver = curHead.ver==NXT_VER_SPECIAL? 1 : curHead.ver+1;
+ }while( !s_h->compare_exchange_strong(curHead.asInt, nxtHead.asInt) );
+
+ return curHead.idx;
+ }
+ u32 free(u32 idx) // not thread safe when reading from the list, but it doesn't matter because you shouldn't be reading while freeing anyway, since the CncrHsh will already have the index taken out and the free will only be triggered after the last reader has read from it
+ {
+ Head curHead, nxtHead; u32 retIdx;
+ curHead.asInt = s_h->load();
+ do{
+ retIdx = s_lv[idx] = curHead.idx;
+ nxtHead.idx = idx;
+ nxtHead.ver = curHead.ver + 1;
+ }while( !s_h->compare_exchange_strong(curHead.asInt, nxtHead.asInt) );
+
+ return retIdx;
+ }
+ u32 free(u32 st, u32 en) // not thread safe when reading from the list, but it doesn't matter because you shouldn't be reading while freeing anyway, since the CncrHsh will already have the index taken out and the free will only be triggered after the last reader has read from it
+ {
+ Head curHead, nxtHead; u32 retIdx;
+ curHead.asInt = s_h->load();
+ do{
+ retIdx = s_lv[en] = curHead.idx;
+ nxtHead.idx = st;
+ nxtHead.ver = curHead.ver + 1;
+ }while( !s_h->compare_exchange_strong(curHead.asInt, nxtHead.asInt) );
+
+ return retIdx;
+ }
+ auto count() const -> u32 { return ((Head*)s_h)->ver; }
+ auto idx() const -> u32
+ {
+ Head h;
+ h.asInt = s_h->load();
+ return h.idx;
+ }
+ auto list() -> ListVec const* { return &s_lv; } // not thread safe
+ u32 lnkCnt() // not thread safe
+ {
+ u32 cnt = 0;
+ u32 curIdx = idx();
+ while( curIdx != LIST_END ){
+ curIdx = s_lv[curIdx];
+ ++cnt;
+ }
+ return cnt;
+ }
+ auto head() -> Head* { return (Head*)s_h; }
+};
+class CncrStr // CncrStr is Concurrent Store
+{
+public:
+ using u8 = uint8_t;
+ using u32 = uint32_t;
+ using i32 = int32_t;
+ using u64 = uint64_t;
+ using i64 = int64_t;
+ using au32 = std::atomic;
+ using au64 = std::atomic;
+
+ union VerIdx
+ {
+ struct { u32 idx; u32 version; };
+ u64 asInt;
+
+ VerIdx(){}
+ VerIdx(u32 _idx, u32 _version) : idx(_idx), version(_version) {}
+ };
+ union KeyReaders
+ {
+ struct{ u32 isKey : 1; u32 isDeleted : 1; i32 readers : 30; };
+ u32 asInt;
+ };
+ struct BlkLst // 24 bytes total
+ {
+ union{
+ KeyReaders kr;
+ struct{ u32 isKey : 1; u32 isDeleted : 1; i32 readers : 30; };
+ }; // 4 bytes - kr is key readers
+ u32 idx, version, len, klen, hash; // 20 bytes
+
+ BlkLst() : isKey(0), isDeleted(0), readers(0), idx(0), version(0), len(0), klen(0), hash(0) {}
+ BlkLst(bool _isKey, i32 _readers, u32 _idx, u32 _version, u32 _len=0, u32 _klen=0, u32 _hash=0) :
+ isKey(_isKey),
+ isDeleted(0),
+ readers(_readers),
+ idx(_idx),
+ version(_version),
+ hash(_hash)
+ {
+ len = _len;
+ klen = _klen;
+ }
+ };
+ struct BlkCnt { u32 end : 1; u32 cnt : 31; }; // this is returned from alloc() and may not be neccesary - it is the number of blocks allocated and if the end was reached
+
+ using ai32 = std::atomic;
+ using BlockLists = lava_vec; // only the indices returned from the concurrent list are altered, and only one thread will deal with any single index at a time
+
+ static const u32 LIST_END = CncrLst::LIST_END;
+
+ static VerIdx List_End()
+ {
+ VerIdx vi;
+ vi.idx = CncrLst::LIST_END;
+ vi.version = 0;
+ return vi;
+ }
+ static bool IsListEnd(VerIdx vi)
+ {
+ static const VerIdx empty = List_End();
+ return empty.asInt == vi.asInt;
+ }
+
+ BlkLst incReaders(u32 blkIdx, u32 version) const // BI is Block Index increment the readers by one and return the previous kv from the successful swap
+ {
+ KeyReaders cur, nxt;
+ BlkLst* bl = &s_bls[blkIdx];
+ au32* areaders = (au32*)&(bl->kr);
+ cur.asInt = areaders->load();
+ do{
+ if(bl->version!=version || cur.readers<0 || cur.isDeleted){ return BlkLst(); }
+ nxt = cur;
+ nxt.readers += 1;
+ }while( !areaders->compare_exchange_strong(cur.asInt, nxt.asInt) );
+
+ return *bl; // after readers has been incremented this block list entry is not going away. The only thing that would change would be the readers and that doesn't matter to the calling function.
+ }
+ bool decReadersOrDel(u32 blkIdx, u32 version, bool del=false) const // BI is Block Index increment the readers by one and return the previous kv from the successful swap
+ {
+ KeyReaders cur, nxt; bool doDelete;
+
+ BlkLst* bl = &s_bls[blkIdx];
+ au32* areaders = (au32*)&(bl->kr);
+ cur.asInt = areaders->load();
+ do{
+ doDelete = false;
+ if(bl->version!=version){ return false; }
+ nxt = cur;
+ if(del){
+ if(cur.readers==0 && !cur.isDeleted){ doDelete=true; }
+ nxt.isDeleted = true;
+ }else{
+ if(cur.readers==1 && cur.isDeleted){ doDelete=true; }
+ nxt.readers -= 1;
+ }
+ }while( !areaders->compare_exchange_strong(cur.asInt, nxt.asInt) );
+
+ if(doDelete){ doFree(blkIdx); return false; }
+
+ return true;
+ //return cur.isDeleted;
+ }
+
+private:
+ // s_ variables are used to indicate data structures and memory that is in the shared memory, usually just a pointer on the stack and of course, nothing on the heap
+ // The order of the shared memory as it is in the memory mapped file: Version, CncrLst, BlockLists, Blocks
+ mutable CncrLst s_cl; // flat data structure - pointer to memory
+ mutable BlockLists s_bls; // flat data structure - pointer to memory - bl is Block Lists
+ void* s_blksAddr; // points to the block space in the shared memory
+ au64* s_version; // pointer to the shared version number
+
+ u32 m_blockSize;
+ u64 m_szBytes;
+
+ VerIdx nxtBlock(u32 blkIdx) const
+ {
+ BlkLst bl = s_bls[blkIdx];
+ prefetch1( (char const* const)blockFreePtr(bl.idx) );
+ return VerIdx(bl.idx, bl.version);
+ }
+ u32 blockFreeSize() const { return m_blockSize; }
+ u8* blockFreePtr(u32 blkIdx) const { return ((u8*)s_blksAddr) + blkIdx*m_blockSize; }
+ u8* blkPtr(u32 blkIdx) const { return ((u8*)s_blksAddr) + blkIdx*m_blockSize; }
+ u32 blocksNeeded(u32 len, u32* out_rem=nullptr)
+ {
+ u32 freeSz = blockFreeSize();
+ u32 byteRem = len % freeSz;
+ u32 blocks = len / freeSz + (byteRem? 1 : 0); // should never be 0 if blocksize is greater than the size of the index type
+
+ if(out_rem) *out_rem = byteRem;
+
+ return blocks;
+ }
+ u32 findEndSetVersion(u32 blkIdx, u32 version) const // find the last BlkLst slot in the linked list of blocks to free
+ {
+ u32 cur=blkIdx, prev=blkIdx;
+ while(cur != LIST_END){
+ s_bls[prev].version = version;
+ prev = cur;
+ cur = s_bls[cur].idx;
+ }
+
+ return prev;
+ }
+ void doFree(u32 blkIdx) const // frees a list/chain of blocks - don't need to zero out the memory of the blocks or reset any of the BlkLsts' variables since they will be re-initialized anyway
+ {
+ u32 listEnd = findEndSetVersion(blkIdx, 0);
+ s_cl.free(blkIdx, listEnd);
+ }
+ u32 writeBlock(u32 blkIdx, void const* const bytes, u32 len=0, u32 ofst=0) // don't need to increment readers since write should be done before the block is exposed to any other threads
+ {
+ u32 blkFree = blockFreeSize();
+ u8* p = blockFreePtr(blkIdx);
+ u32 cpyLen = len==0? blkFree : len; // if next is negative, then it will be the length of the bytes in that block
+ p += ofst;
+ memcpy(p, bytes, cpyLen);
+
+ return cpyLen;
+ }
+ u32 readBlock(u32 blkIdx, u32 version, void *const bytes, u32 ofst=0, u32 len=0) const
+ {
+ BlkLst bl = incReaders(blkIdx, version); if(bl.version==0){ return 0; }
+ u32 blkFree = blockFreeSize();
+ u8* p = blockFreePtr(blkIdx);
+ u32 cpyLen = len==0? blkFree-ofst : len;
+ memcpy(bytes, p+ofst, cpyLen);
+ decReadersOrDel(blkIdx, version);
+
+ return cpyLen;
+ }
+
+public:
+ static u64 BlockListsOfst(){ return sizeof(u64); }
+ static u64 CListOfst(u32 blockCount){ return BlockListsOfst() + BlockLists::sizeBytes(blockCount); } // BlockLists::sizeBytes ends up being sizeof(BlkLst)*blockCount + 2 u64 variables
+ static u64 BlksOfst(u32 blockCount){ return CListOfst(blockCount) + CncrLst::sizeBytes(blockCount); }
+ static u64 sizeBytes(u32 blockSize, u32 blockCount){ return BlksOfst(blockCount) + blockSize*blockCount; }
+
+ CncrStr(){}
+ CncrStr(void* addr, u32 blockSize, u32 blockCount, bool owner=true) :
+ s_cl( (u8*)addr + CListOfst(blockCount), blockCount, owner),
+ s_bls( (u8*)addr + BlockListsOfst(), blockCount, owner),
+ s_blksAddr( (u8*)addr + BlksOfst(blockCount) ),
+ s_version( (au64*)addr ),
+ m_blockSize(blockSize),
+ m_szBytes( *((u64*)addr) )
+ {
+ if(owner){
+ for(u32 i=0; istore(1); // todo: what is this version for if CncrLst already has a version?
+ }
+ assert(blockSize > sizeof(i32));
+ }
+
+ auto alloc(u32 size, u32 klen, u32 hash, BlkCnt* out_blocks=nullptr) -> VerIdx
+ {
+ u32 byteRem = 0;
+ u32 blocks = blocksNeeded(size, &byteRem);
+ u32 st = s_cl.nxt();
+ SECTION(get the starting block index and handle errors)
+ {
+ if(st==LIST_END){
+ if(out_blocks){ *out_blocks = {1, 0} ; }
+ return List_End();
+ }
+ }
+
+
+ u32 ver = (u32)s_version->fetch_add(1);
+ u32 cur = st;
+ u32 nxt = 0;
+ u32 cnt = 0;
+ SECTION(loop for the number of blocks needed and get new block and link it to the list)
+ {
+ for(u32 i=0; iend = nxt==LIST_END;
+ out_blocks->cnt = cnt;
+ }
+ VerIdx vi(st, ver);
+ return vi;
+ }
+ }
+ bool free(u32 blkIdx, u32 version) // doesn't always free a list/chain of blocks - it decrements the readers and when the readers gets below the value that it started at, only then it is deleted (by the first thread to take it below the starting number)
+ {
+ return decReadersOrDel(blkIdx, version, true);
+ }
+ void put(u32 blkIdx, void const *const kbytes, u32 klen, void const *const vbytes, u32 vlen) // don't need version because this will only be used after allocating and therefore will only be seen by one thread until it is inserted into the ConcurrentHash
+ {
+ using namespace std;
+
+ u8* b = (u8*)kbytes;
+ bool kjagged = (klen % blockFreeSize()) != 0;
+ u32 kblocks = kjagged? blocksNeeded(klen)-1 : blocksNeeded(klen);
+ u32 remklen = klen - (kblocks*blockFreeSize());
+
+ u32 fillvlen = min(vlen, blockFreeSize()-remklen);
+ u32 tailvlen = vlen-fillvlen;
+ bool vjagged = (tailvlen % blockFreeSize()) != 0;
+ u32 vblocks = vjagged? blocksNeeded(tailvlen)-1 : blocksNeeded(tailvlen);
+ u32 remvlen = max(0, tailvlen - (vblocks*blockFreeSize()) );
+
+ u32 cur = blkIdx;
+ for(u32 i=0; i0){
+ b += writeBlock(cur, b, remvlen);
+ }
+ }
+ u32 get(u32 blkIdx, u32 version, void *const bytes, u32 maxlen, u32* out_readlen=nullptr) const
+ {
+ using namespace std;
+
+ if(blkIdx == LIST_END){ return 0; }
+
+ BlkLst bl = incReaders(blkIdx, version);
+
+ u32 vlen = bl.len-bl.klen;
+ if(bl.len==0 || vlen>maxlen ) return 0;
+
+ auto kdiv = div((i64)bl.klen, (i64)blockFreeSize());
+ auto kblks = kdiv.quot;
+ u32 krem = (u32)kdiv.rem;
+ auto vrdLen = 0;
+ u32 len = 0;
+ u32 rdLen = 0;
+ u8* b = (u8*)bytes;
+ i32 cur = blkIdx;
+ VerIdx nxt;
+ for(int i=0; i(blockFreeSize()-krem, vlen);
+ rdLen = (u32)readBlock(cur, version, b, krem, vrdLen);
+ b += rdLen;
+ len += rdLen;
+ nxt = nxtBlock(cur); if(nxt.version!=version){ goto read_failure; }
+
+ while(len(blockFreeSize(), maxlen-len);
+ cur = nxt.idx;
+ rdLen = readBlock(cur, version, b, 0, vrdLen); if(rdLen==0) break; // rdLen is read length
+ b += rdLen;
+ len += rdLen;
+ nxt = nxtBlock(cur);
+ }
+
+ if(out_readlen){ *out_readlen = len; }
+
+ read_failure:
+ decReadersOrDel(blkIdx, version);
+
+ return len; // only one return after the top to make sure readers can be decremented - maybe it should be wrapped in a struct with a destructor
+ }
+ u32 getKey(u32 blkIdx, u32 version, void *const bytes, u32 maxlen) const
+ {
+ if(blkIdx == LIST_END){ return 0; }
+
+ BlkLst bl = incReaders(blkIdx, version);
+
+ if(bl.len==0 || (bl.klen)>maxlen ) return 0;
+
+ auto kdiv = div((i64)bl.klen, (i64)blockFreeSize());
+ auto kblks = kdiv.quot;
+ u32 krem = (u32)kdiv.rem;
+ u32 len = 0;
+ u32 rdLen = 0;
+ u8* b = (u8*)bytes;
+ VerIdx vi = { blkIdx, version };
+
+ int i=0;
+ while( i curlen){
+ return memcmpBlk(curidx, version, curbuf, p, curlen);
+ }else{
+ Match cmp = memcmpBlk(curidx, version, curbuf, p, blksz); if(cmp!=MATCH_TRUE){ return cmp; }
+ }
+
+ curbuf += blksz;
+ curlen -= blksz;
+ curidx = nxt.idx;
+ nxt = nxtBlock(curidx); if(nxt.version!=version){ return MATCH_FALSE; }
+ }
+ }
+ u32 len(u32 blkIdx, u32 version, u32* out_vlen=nullptr) const
+ {
+ BlkLst bl = s_bls[blkIdx];
+ if(version==bl.version && bl.len>0){
+ if(out_vlen) *out_vlen = bl.len - bl.klen;
+ return bl.len;
+ }else
+ return 0;
+ }
+ auto list() const -> CncrLst const& { return s_cl; }
+ auto data() const -> const void* { return (void*)s_blksAddr; }
+ auto blkLst(u32 i) const -> BlkLst { return s_bls[i]; }
+
+ friend class CncrHsh;
+};
+class CncrHsh
+{
+public:
+ using u8 = uint8_t;
+ using u32 = uint32_t;
+ using u64 = uint64_t;
+ using i64 = int64_t;
+ using au64 = std::atomic;
+ using VerIdx = CncrStr::VerIdx;
+ using BlkLst = CncrStr::BlkLst;
+
+ struct VerIpd { u32 version, ipd; }; // ipd is Ideal Position Distance
+
+ static const u32 KEY_MAX = 0xFFFFFFFF;
+ static const u32 EMPTY = KEY_MAX; // first 21 bits set
+ static const u32 DELETED = KEY_MAX - 1; // 0xFFFFFFFE; // 1 less than the EMPTY
+ static const u32 LIST_END = CncrStr::LIST_END;
+ static const u32 SLOT_END = CncrStr::LIST_END;
+
+ static u64 sizeBytes(u32 size) // the size in bytes that this structure will take up in the shared memory
+ {
+ return lava_vec::sizeBytes(size) + 16; // extra 16 bytes for 128 bit alignment padding
+ }
+ static u32 nextPowerOf2(u32 v)
+ {
+ v--;
+ v |= v >> 1;
+ v |= v >> 2;
+ v |= v >> 4;
+ v |= v >> 8;
+ v |= v >> 16;
+ v++;
+
+ return v;
+ }
+ static u32 HashBytes(const void *const buf, u32 len)
+ {
+ u64 hsh = fnv_64a_buf(buf, len);
+ return (u32)( (hsh>>32) ^ ((u32)hsh));
+ }
+ static VerIdx empty_vi(){ return VerIdx(EMPTY,0); }
+ static VerIdx deleted_vi(){ return VerIdx(DELETED,0); }
+ static i64 vi_i64(VerIdx vi){ u64 iVi=vi.asInt; return *((i64*)(&iVi)); } // interpret the u64 bits directly as a signed 64 bit integer instead
+ static i64 vi_i64(u64 i){ return *((i64*)&i); } // interpret the u64 bits directly as a signed 64 bit integer instead
+ static bool IsEmpty(VerIdx vi)
+ {
+ static VerIdx emptyvi = empty_vi();
+ return emptyvi.asInt == vi.asInt;
+ }
+ static u32 lo32(u64 n){ return (n>>32); }
+ static u32 hi32(u64 n){ return (n<<32)>>32; }
+ static u64 swp32(u64 n){ return (((u64)hi32(n))<<32) | ((u64)lo32(n)); }
+ static u64 inclo32(u64 n, u32 i){ return ((u64)hi32(n)+i)<<32 | lo32(n); }
+ static u64 incHi32(u64 n, u32 i){ return ((u64)hi32(n))<<32 | (lo32(n)+i); }
+ static u64 shftToHi64(u32 n){ return ((u64)n)<<32; }
+ static u64 make64(u32 lo, u32 hi){ return (((u64)lo)<<32) | ((u64)hi); }
+
+private:
+ using VerIdxs = lava_vec;
+
+ u32 m_sz;
+ mutable VerIdxs s_vis; // s_vis is key value(s) - needs to be changed to versioned indices, m_vis
+ CncrStr* m_csp; // csp is concurrent store pointer
+
+ VerIdx store_vi(u32 i, u64 vi) const
+ {
+ using namespace std;
+
+ bool odd = i%2 == 1;
+ VerIdx strVi;
+ if(odd) strVi = VerIdx(lo32(vi), hi32(vi)); // the odd numbers need to be swapped so that their indices are on the outer border of 128 bit alignment - the indices need to be on the border of the 128 bit boundary so they can be swapped with an unaligned 64 bit atomic operation
+ else strVi = VerIdx(hi32(vi), lo32(vi));
+
+ u64 prev = atomic_exchange( (au64*)(s_vis.data()+i), *((u64*)(&strVi)) );
+
+ if(odd) return VerIdx(lo32(prev), hi32(prev));
+ else return VerIdx(hi32(prev), lo32(prev));
+ }
+ bool cmpex_vi(u32 i, VerIdx expected, VerIdx desired) const
+ {
+ using namespace std;
+
+ u64 exp = i%2? swp32(expected.asInt) : expected.asInt; // if the index (i) is odd, swap the upper and lower 32 bits around
+ u64 desi = i%2? swp32(desired.asInt) : desired.asInt; // desi is desired int
+ au64* addr = (au64*)(s_vis.data()+i);
+ bool ok = addr->compare_exchange_strong( exp, desi );
+
+ return ok;
+ }
+ void doFree(u32 i) const
+ {
+ store_vi(i, empty_vi().asInt);
+ }
+ VerIpd ipd(u32 i, u32 blkIdx) const // ipd is Ideal Position Distance - it is the distance a CncrHsh index value is from the position that it gets hashed to
+ {
+ BlkLst bl = m_csp->blkLst(blkIdx);
+ u32 ip = bl.hash % m_sz; // ip is Ideal Position
+ u32 ipd = i>ip? i-ip : m_sz - ip + i;
+ return {bl.version, ipd};
+ }
+ VerIdx prev(u32 i, u32* out_idx) const
+ {
+ *out_idx=prevIdx(i);
+ return load(*out_idx);
+ }
+ VerIdx nxt(u32 i, u32* out_idx) const
+ {
+ *out_idx=nxtIdx(i);
+ return load(*out_idx);
+ }
+
+ template
+ bool runIfMatch(VerIdx vi, const void* const buf, u32 len, u32 hash, FUNC f) const
+ { // todo: should this increment and decrement the readers, as well as doing something different if it was the thread that freed the blocks
+ //VerIdx kv = incReaders(vi.idx, vi.version);
+ Match m = m_csp->compare(vi.idx, vi.version, buf, len, hash);
+ bool matched = false; // not inside a scope
+ if(m==MATCH_TRUE){ matched=true; f(vi); }
+ //decReaders(vi.idx, vi.version);
+ //decReaders(i);
+
+ return matched;
+ }
+
+public:
+ CncrHsh(){}
+ CncrHsh(void* addr, u32 size, CncrStr* cs, bool owner=true) :
+ m_sz(nextPowerOf2(size)),
+ m_csp(cs)
+ {
+ u64 paddr = (u64)addr; // paddr is padded address
+ u8 rem = 16 - paddr%16;
+ u8 ofst = 16 - rem;
+ void* algnMem = (void*)(paddr+ofst); assert( ((u64)algnMem) % 16 == 0 );
+
+ new (&s_vis) VerIdxs(algnMem, m_sz); // initialize the lava_vec of VerIdx structs with the 128 bit aligned address
+
+ if(owner){
+ init(size, cs);
+ }
+ }
+ CncrHsh(CncrHsh const& lval) = delete;
+ CncrHsh(CncrHsh&& rval) = delete;
+ CncrHsh& operator=(CncrHsh const& lval) = delete;
+ CncrHsh& operator=(CncrHsh&& rval) = delete;
+
+ VerIdx operator[](u32 idx) const { return s_vis[idx]; }
+
+ VerIdx putHashed(u32 hash, VerIdx lstVi, const void *const key, u32 klen) const
+ {
+ using namespace std;
+ static const VerIdx empty = empty_vi();
+
+ VerIdx desired = lstVi;
+ u32 i=hash%m_sz, en=prevIdx(i);
+ for(;; i=nxtIdx(i) )
+ {
+ VerIdx vi = load(i);
+ if(vi.idx>=DELETED){ // it is either deleted or empty
+ bool success = cmpex_vi(i, vi, desired);
+ if(success){
+ return vi;
+ }else{
+ i=prevIdx(i);
+ continue;
+ } // retry the same loop again if a good slot was found but it was changed by another thread between the load and the compare-exchange
+ } // Either we just added the key, or another thread did.
+
+ if(m_csp->compare(vi.idx,vi.version,key,klen,hash) != MATCH_TRUE){
+ if(i==en){return empty;}
+ else{continue;}
+ }
+
+ bool success = cmpex_vi(i, vi, desired);
+ if(success){
+ return vi;
+ }else{
+ i=prevIdx(i);
+ continue;
+ }
+ }
+
+ // return empty; // should never be reached
+ }
+
+ template
+ bool runMatch(const void *const key, u32 klen, u32 hash, FUNC f) const
+ {
+ using namespace std;
+
+ u32 i = hash % m_sz;
+ u32 en = prevIdx(i);
+ for(;; i=nxtIdx(i) )
+ {
+ VerIdx vi = load(i);
+ if(vi.idx!=EMPTY && vi.idx!=DELETED && runIfMatch(vi,key,klen,hash,f) ){ return true; }
+
+ if(i==en){ return false; }
+ }
+ }
+
+ VerIdx delHashed(const void *const key, u32 klen, u32 hash) const
+ {
+ using namespace std;
+ static const VerIdx empty = empty_vi();
+ static const VerIdx deleted = deleted_vi();
+
+ u32 i = hash % m_sz;
+ u32 en = prevIdx(i);
+ for(; i!=en ; i=nxtIdx(i) )
+ {
+ VerIdx vi = load(i);
+ if(vi.idx>=DELETED){continue;}
+
+ Match m = m_csp->compare(vi.idx, vi.version, key, klen, hash);
+ if(m==MATCH_TRUE){
+ bool success = cmpex_vi(i, vi, deleted);
+ if(success){
+ //cleanDeletion(i);
+ return vi;
+ }else{
+ i=prevIdx(i); continue;
+ }
+
+ //return vi; // unreachable
+ }
+
+ if(m==MATCH_REMOVED || i==en){ return empty; }
+ }
+
+ return empty; // not unreachable
+ }
+
+ bool init(u32 sz, CncrStr* cs)
+ {
+ using namespace std;
+
+ m_csp = cs;
+ m_sz = sz;
+
+ for(u32 i=0; i void* { return s_vis.data(); }
+ u64 sizeBytes() const { return s_vis.sizeBytes(); }
+ i64 len(const void *const key, u32 klen, u32* out_vlen=nullptr, u32* out_version=nullptr) const
+ {
+ if(klen<1){return 0;}
+
+ u32 hash=HashBytes(key,klen), i=hash%m_sz, en=prevIdx(i);
+ for(;; i=nxtIdx(i) )
+ {
+ VerIdx vi = load(i);
+ if(vi.idx!=EMPTY && vi.idx!=DELETED){
+ Match m = m_csp->compare(vi.idx, vi.version, key, klen, hash);
+ if(m==MATCH_TRUE){
+ if(out_version){ *out_version = vi.version; }
+ return m_csp->len(vi.idx, vi.version, out_vlen);
+ }
+ }
+
+ if(i==en){ return 0ull; }
+ }
+ }
+ bool get(const void *const key, u32 klen, void *const out_val, u32 vlen, u32* out_readlen=nullptr) const
+ {
+ if(klen<1){ return 0; }
+
+ u32 hash=HashBytes(key,klen);
+ CncrStr* csp = m_csp;
+ auto runFunc = [csp, out_val, vlen, out_readlen](VerIdx vi){
+ return csp->get(vi.idx, vi.version, out_val, vlen, out_readlen);
+ };
+
+ return runMatch(key, klen, hash, runFunc);
+ }
+ bool put(const void *const key, u32 klen, const void *const val, u32 vlen, u32* out_startBlock=nullptr)
+ {
+ assert(klen>0);
+
+ u32 hash = CncrHsh::HashBytes(key, klen);
+ VerIdx lstVi = m_csp->alloc(klen+vlen, klen, hash); // lstVi is block list versioned index
+ if(out_startBlock){ *out_startBlock = lstVi.idx; }
+ if(lstVi.idx==LIST_END){ return false; }
+
+ m_csp->put(lstVi.idx, key, klen, val, vlen);
+
+ VerIdx vi = putHashed(hash, lstVi, key, klen);
+ if(vi.idxfree(vi.idx, vi.version);
+ } // putHashed returns the entry that was there before, which is the entry that was replaced. If it wasn't empty, we free it here.
+
+ return true;
+ }
+ bool del(const void *const key, u32 klen)
+ {
+ auto hash = CncrHsh::HashBytes(key, klen);
+ VerIdx vi = delHashed(key, klen, hash);
+ bool doFree = vi.idxfree(vi.idx, vi.version); }
+
+ return doFree;
+ }
+ VerIdx load(u32 i) const
+ {
+ assert(i < m_sz);
+
+ au64* avi = (au64*)(s_vis.data()+i); // avi is atomic versioned index
+ u64 cur = swp32(avi->load()); // need because of endianess? // atomic_load( (au64*)(m_vis.data()+i) ); // Load the key that was there.
+
+ if(i%2==1) return VerIdx(hi32(cur), lo32(cur));
+ else return VerIdx(lo32(cur), hi32(cur));
+ }
+ u32 nxtIdx(u32 i) const { return (i+1)%m_sz; }
+ u32 prevIdx(u32 i) const { return std::min(i-1, m_sz-1); } // clamp to m_sz-1 for the case that hash==0, which will result in an unsigned integer wrap
+
+};
+struct SharedMem
+{
+ using u32 = uint32_t;
+ using u64 = uint64_t;
+ using au32 = std::atomic;
+
+ static const int alignment = 0;
+
+ #ifdef _WIN32
+ void* fileHndl;
+ #elif defined(__APPLE__) || defined(__MACH__) || defined(__unix__) || defined(__FreeBSD__) // || defined(__linux__) ? // osx, linux and freebsd
+ int fileHndl;
+ #endif
+
+ void* hndlPtr;
+ void* ptr;
+ u64 size;
+ bool owner;
+ char path[256];
+
+ void mv(SharedMem&& rval)
+ {
+ fileHndl = rval.fileHndl;
+ hndlPtr = rval.hndlPtr;
+ ptr = rval.ptr;
+ size = rval.size;
+ owner = rval.owner;
+
+ strncpy(path, rval.path, sizeof(path));
+
+ rval.clear();
+ }
+
+public:
+ static void FreeAnon(SharedMem& sm)
+ {
+ #ifdef _WIN32
+ if(sm.hndlPtr){
+ UnmapViewOfFile(sm.hndlPtr);
+ }
+ if(sm.fileHndl){
+ CloseHandle(sm.fileHndl);
+ }
+ #elif defined(__APPLE__) || defined(__MACH__) || defined(__unix__) || defined(__FreeBSD__) || defined(__linux__) // osx, linux and freebsd
+ if(sm.hndlPtr){
+ munmap(sm.hndlPtr, sm.size); // todo: size here needs to be the total size, and errors need to be checked
+ }
+ remove(sm.path);
+ // todo: deal with errors here as well
+ #endif
+
+ sm.clear();
+ }
+ static SharedMem AllocAnon(const char* name, u64 sizeBytes, bool raw_path=false, simdb_error* error_code=nullptr)
+ {
+ using namespace std;
+
+ SharedMem sm;
+ sm.hndlPtr = nullptr;
+ sm.owner = false;
+ //sm.size = alignment==0? sizeBytes : alignment-(sizeBytes%alignment);
+ sm.size = sizeBytes;
+ if(error_code){ *error_code = simdb_error::NO_ERRORS; }
+
+ #ifdef _WIN32 // windows
+ sm.fileHndl = nullptr;
+ if(!raw_path){ strcpy(sm.path, "simdb_"); }
+ #elif defined(__APPLE__) || defined(__MACH__) || defined(__unix__) || defined(__FreeBSD__) || defined(__linux__) // osx, linux and freebsd
+ sm.fileHndl = 0;
+ strcpy(sm.path, P_tmpdir "/simdb_");
+ #endif
+
+ u64 len = strlen(sm.path) + strlen(name);
+ if(len > sizeof(sm.path)-1){
+ *error_code = simdb_error::PATH_TOO_LONG;
+ return move(sm);
+ }else{ strcat(sm.path, name); }
+
+ #ifdef _WIN32 // windows
+ if(raw_path)
+ {
+ sm.fileHndl = CreateFile(
+ sm.path,
+ GENERIC_READ|GENERIC_WRITE, //FILE_MAP_READ|FILE_MAP_WRITE, // apparently FILE_MAP constants have no effects here
+ FILE_SHARE_READ|FILE_SHARE_WRITE,
+ NULL,
+ CREATE_NEW,
+ FILE_ATTRIBUTE_NORMAL, //_In_ DWORD dwFlagsAndAttributes
+ NULL //_In_opt_ HANDLE hTemplateFile
+ );
+ }
+ sm.fileHndl = OpenFileMapping(FILE_MAP_READ | FILE_MAP_WRITE, FALSE, sm.path);
+
+ if(sm.fileHndl==NULL)
+ {
+ sm.fileHndl = CreateFileMapping( // todo: simplify and call this right away, it will open the section if it already exists
+ INVALID_HANDLE_VALUE,
+ NULL,
+ PAGE_READWRITE,
+ 0,
+ (DWORD)sizeBytes,
+ sm.path);
+ if(sm.fileHndl!=NULL){ sm.owner=true; }
+ }
+
+ if(sm.fileHndl != nullptr){
+ sm.hndlPtr = MapViewOfFile(sm.fileHndl, // handle to map object
+ FILE_MAP_READ | FILE_MAP_WRITE, // FILE_MAP_ALL_ACCESS, // read/write permission
+ 0,
+ 0,
+ 0);
+ }
+
+ if(sm.hndlPtr==nullptr){
+ int err = (int)GetLastError();
+ LPSTR msgBuf = nullptr;
+ /*size_t msgSz =*/ FormatMessageA(FORMAT_MESSAGE_ALLOCATE_BUFFER | FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS,
+ NULL, err, MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT), (LPSTR)&msgBuf, 0, NULL);
+ win_printf("simdb initialization error: %d - %s", err, msgBuf);
+ LocalFree(msgBuf);
+
+ CloseHandle(sm.fileHndl);
+ sm.clear();
+ return move(sm);
+ }
+ #elif defined(__APPLE__) || defined(__MACH__) || defined(__unix__) || defined(__FreeBSD__) || defined(__linux__) // osx, linux and freebsd
+ sm.owner = true; // todo: have to figure out how to detect which process is the owner
+
+ sm.fileHndl = open(sm.path, O_RDWR);
+ if(sm.fileHndl == -1)
+ {
+ sm.fileHndl = open(sm.path, O_CREAT|O_RDWR, S_IRUSR|S_IWUSR |S_IRGRP|S_IWGRP | S_IROTH|S_IWOTH ); // O_CREAT | O_SHLOCK ); // | O_NONBLOCK );
+ if(sm.fileHndl == -1){
+ if(error_code){ *error_code = simdb_error::COULD_NOT_OPEN_MAP_FILE; }
+ }
+ else{
+ //flock(sm.fileHndl, LOCK_EX); // exclusive lock // LOCK_NB
+ }
+ }else{ sm.owner = false; }
+
+ if(sm.owner){ // todo: still need more concrete race protection?
+ fcntl(sm.fileHndl, F_GETLK, &flock);
+ flock(sm.fileHndl, LOCK_EX); // exclusive lock // LOCK_NB
+ //fcntl(sm.fileHndl, F_PREALLOCATE);
+ #if defined(__linux__)
+ #else
+ fcntl(sm.fileHndl, F_ALLOCATECONTIG);
+ #endif
+
+ if( ftruncate(sm.fileHndl, sizeBytes)!=0 ){
+ if(error_code){ *error_code = simdb_error::FTRUNCATE_FAILURE; }
+ }
+ if( flock(sm.fileHndl, LOCK_UN)!=0 ){
+ if(error_code){ *error_code = simdb_error::FLOCK_FAILURE; }
+ }
+ }
+
+ sm.hndlPtr = mmap(NULL, sizeBytes, PROT_READ|PROT_WRITE, MAP_SHARED , sm.fileHndl, 0); // MAP_PREFAULT_READ | MAP_NOSYNC
+ close(sm.fileHndl);
+ sm.fileHndl = 0;
+
+ if(sm.hndlPtr==MAP_FAILED){
+ if(error_code){ *error_code = simdb_error::COULD_NOT_MEMORY_MAP_FILE; }
+ }
+ #endif
+
+ u64 addr = (u64)(sm.hndlPtr);
+ u64 alignAddr = addr;
+ //if(alignment!=0){ alignAddr = addr + ((alignment-addr%alignment)%alignment); } // why was the second modulo needed?
+ sm.ptr = (void*)(alignAddr);
+
+ return move(sm);
+ }
+
+ SharedMem(){}
+ SharedMem(SharedMem&) = delete;
+ SharedMem(SharedMem&& rval){ mv(std::move(rval)); }
+ SharedMem& operator=(SharedMem&& rval){ mv(std::move(rval)); return *this; }
+ ~SharedMem()
+ {
+ if(ptr){
+ au32* cnt = ((au32*)ptr)+1;
+ u64 prev = 0;
+ if(cnt->load()>0){ prev = cnt->fetch_sub(1); }
+ if(prev==1){ SharedMem::FreeAnon(*this); }
+ }
+ }
+ void clear()
+ {
+ fileHndl = (decltype(fileHndl))0;
+ hndlPtr = nullptr;
+ ptr = nullptr;
+ size = 0;
+ owner = false;
+ }
+ auto data() -> void*
+ {
+ return ptr;
+ }
+};
+class simdb
+{
+public:
+ using u8 = uint8_t;
+ using u32 = uint32_t;
+ using i32 = int32_t;
+ using u64 = uint64_t;
+ using i64 = int64_t;
+ using au32 = std::atomic;
+ using au64 = std::atomic;
+ using str = std::string;
+ using BlkCnt = CncrStr::BlkCnt;
+ using VerIdx = CncrHsh::VerIdx;
+ using string = std::string;
+
+private:
+ au32* s_flags;
+ au32* s_cnt;
+ au64* s_blockSize;
+ au64* s_blockCount;
+ CncrStr s_cs; // store data in blocks and get back indices
+ CncrHsh s_ch; // store the indices of keys and values - contains a ConcurrentList
+
+ // these variables are local to the stack where simdb lives, unlike the others, they are not simply a pointer into the shared memory
+ SharedMem m_mem;
+ mutable simdb_error m_error;
+ mutable u32 m_nxtChIdx;
+ mutable u32 m_curChIdx;
+ u64 m_blkCnt;
+ u64 m_blkSz;
+ bool m_isOpen;
+
+public:
+ static const u32 EMPTY = CncrHsh::EMPTY; // 28 bits set
+ static const u32 DELETED = CncrHsh::DELETED; // 28 bits set
+ static const u32 FAILED_PUT = CncrHsh::EMPTY; // 28 bits set
+ static const u32 SLOT_END = CncrHsh::SLOT_END;
+ static const u32 LIST_END = CncrStr::LIST_END;
+
+private:
+ static u64 OffsetBytes(){ return sizeof(au64)*3; }
+ static u64 MemSize(u64 blockSize, u64 blockCount)
+ {
+ auto hashbytes = CncrHsh::sizeBytes((u32)blockCount);
+ auto storebytes = CncrStr::sizeBytes((u32)blockSize, (u32)blockCount);
+ return hashbytes + storebytes + OffsetBytes();
+ }
+ static Match CompareBlock(simdb const *const ths, i32 blkIdx, u32 version, void const *const buf, u32 len, u32 hash)
+ {
+ return ths->s_cs.compare(blkIdx, version, buf, len, hash);
+ }
+ static bool IsEmpty(VerIdx vi){return CncrHsh::IsEmpty(vi);} // special value for CncrHsh
+ static bool IsListEnd(VerIdx vi){return CncrStr::IsListEnd(vi);} // special value for CncrStr
+
+ void mv(simdb&& rval)
+ {
+ using namespace std;
+
+ s_flags = rval.s_flags;
+ s_cnt = rval.s_cnt;
+ s_blockSize = rval.s_blockSize;
+ s_blockCount = rval.s_blockCount;
+ memcpy(&s_cs, &rval.s_cs, sizeof(s_cs));
+ memcpy(&s_ch, &rval.s_ch, sizeof(s_ch));
+
+ m_mem = move(rval.m_mem);
+ m_error = rval.m_error;
+ m_nxtChIdx = rval.m_nxtChIdx;
+ m_curChIdx = rval.m_curChIdx;
+ m_blkCnt = rval.m_blkCnt;
+ m_blkSz = rval.m_blkSz;
+ m_isOpen = rval.m_isOpen;
+ }
+
+public:
+ simdb(){}
+ simdb(const char* name, u32 blockSize, u32 blockCount, bool raw_path=false) :
+ m_nxtChIdx(0),
+ m_curChIdx(0),
+ m_isOpen(false)
+ {
+ simdb_error error_code = simdb_error::NO_ERRORS;
+ new (&m_mem) SharedMem( SharedMem::AllocAnon(name, MemSize(blockSize,blockCount), raw_path, &error_code) );
+
+ if(error_code!=simdb_error::NO_ERRORS){ m_error = error_code; return; }
+ if(!m_mem.hndlPtr){ m_error = simdb_error::SHARED_MEMORY_ERROR; return; }
+
+ s_blockCount = ((au64*)m_mem.data())+2;
+ s_blockSize = ((au64*)m_mem.data())+1;
+ s_flags = (au32*)m_mem.data();
+ s_cnt = ((au32*)m_mem.data())+1;
+
+ if(isOwner()){
+ s_blockCount->store(blockCount);
+ s_blockSize->store(blockSize);
+ s_cnt->store(1);
+ }else{
+ #if defined(_WIN32) // do we need to spin until ready on windows? unix has file locks built in to the system calls
+ //while(s_flags->load()<1){continue;}
+ #endif
+ s_cnt->fetch_add(1);
+ m_mem.size = MemSize(s_blockSize->load(), s_blockCount->load());
+ }
+
+ //auto cncrHashSize = CncrHsh::sizeBytes(blockCount);
+ uint64_t cncrHashSize = CncrHsh::sizeBytes(s_blockCount->load());
+ new (&s_cs) CncrStr( ((u8*)m_mem.data())+cncrHashSize+OffsetBytes(),
+ (u32)s_blockSize->load(),
+ (u32)s_blockCount->load(),
+ m_mem.owner);
+
+ new (&s_ch) CncrHsh( ((u8*)m_mem.data())+OffsetBytes(),
+ (u32)s_blockCount->load(),
+ &s_cs, // the address of the CncrStr
+ m_mem.owner);
+
+ m_blkCnt = s_blockCount->load();
+ m_blkSz = s_blockSize->load();
+ m_isOpen = true;
+
+ if(isOwner()){ s_flags->store(1); }
+ }
+ ~simdb(){ close(); }
+
+ simdb(simdb&& rval){ mv(std::move(rval)); }
+ simdb& operator=(simdb&& rval){ mv(std::move(rval)); return *this; }
+
+ i64 len(const void *const key, u32 klen, u32* out_vlen=nullptr, u32* out_version=nullptr) const
+ {
+ return s_ch.len(key, klen, out_vlen, out_version);
+ }
+ bool get(const void *const key, u32 klen, void *const out_val, u32 vlen, u32* out_readlen=nullptr) const
+ {
+ return s_ch.get(key, klen, out_val, vlen, out_readlen);
+ }
+ bool put(const void *const key, u32 klen, const void *const val, u32 vlen, u32* out_startBlock=nullptr)
+ {
+ return s_ch.put(key, klen, val, vlen, out_startBlock);
+ }
+ bool del(const void *const key, u32 klen){ return s_ch.del(key, klen); }
+
+ i64 len(u32 idx, u32 version, u32* out_klen=nullptr, u32* out_vlen=nullptr) const
+ {
+ VerIdx vi = s_ch.load(idx);
+ if(vi.idx>=DELETED || vi.version!=version){return 0;}
+ u32 total_len = s_cs.len(vi.idx, vi.version, out_vlen);
+ if(total_len>0){
+ *out_klen = total_len - *out_vlen;
+ return total_len;
+ }
+ return 0;
+ }
+ bool get(char const* const key, void* val, u32 vlen) const
+ {
+ return get(key, (u32)strlen(key), val, vlen);
+ }
+ bool put(char const* const key, const void *const val, u32 vlen, u32* out_startBlock=nullptr)
+ {
+ assert(strlen(key)>0);
+ return put(key, (u32)strlen(key), val, vlen, out_startBlock);
+ }
+
+ void flush() const
+ {
+ #ifdef _WIN32
+ FlushViewOfFile(m_mem.hndlPtr, m_mem.size);
+ #endif
+ }
+ VerIdx nxt() const // this version index represents a hash index, not an block storage index
+ {
+ VerIdx ret = s_ch.empty_vi();
+ u32 chNxt = s_ch.nxt(m_nxtChIdx);
+ if(chNxt!=SLOT_END){
+ m_nxtChIdx = (chNxt + 1) % m_blkCnt;
+ ret = s_ch.at(chNxt);
+ }else{
+ m_nxtChIdx = (m_nxtChIdx + 1) % m_blkCnt;
+ }
+
+ return ret;
+ }
+ bool getKey(u32 idx, u32 version, void *const out_buf, u32 klen) const
+ {
+ if(klen<1) return false;
+
+ VerIdx vi = s_ch.load(idx);
+ if(vi.idx >= CncrHsh::DELETED || vi.version!=version){return false;}
+ u32 l = s_cs.getKey(vi.idx, vi.version, out_buf, klen); // l is length
+ if(l<1){return false;}
+
+ return true;
+ }
+ u32 cur() const { return m_curChIdx; }
+ auto data() const -> const void* const { return s_cs.data(); } // return a pointer to the start of the block data
+ u64 size() const { return CncrStr::sizeBytes( (u32)s_blockSize->load(), (u32)s_blockCount->load()); }
+ bool isOwner() const { return m_mem.owner; }
+ u64 blocks() const { return s_blockCount->load(); } // return the total number of blocks the shared memory
+ u64 blockSize() const { return s_blockSize->load(); }
+ auto mem() const -> void* { return m_mem.hndlPtr; } // returns a pointer to the start of the shared memory, which will contain the data structures first
+ u64 memsize() const { return m_mem.size; }
+ auto hashData() const -> void const* const { return s_ch.data(); }
+ bool close()
+ {
+ if(m_isOpen){
+ m_isOpen = false;
+ u64 prev = s_flags->fetch_sub(1); // prev is previous flags value - the number of simdb instances across process that had the shared memory file open
+ if(prev==1){ // if the previous value was 1, that means the value is now 0, and we are the last one to stop using the file, which also means we need to be the one to clean it up
+ SharedMem::FreeAnon(m_mem); // close and delete the shared memory - this is done automatically on windows when all processes are no longer accessing a shared memory file
+ return true;
+ }
+ }
+ return false;
+ }
+ auto error() const -> simdb_error
+ {
+ return m_error;
+ }
+
+ // separated C++ functions - these won't need to exist if compiled for a C interface
+ struct VerStr {
+ u32 ver; string str;
+ bool operator<(VerStr const& vs) const { return strdata(), vlen);
+
+ return ok;
+ }
+ auto get(str const& key) const -> std::string
+ {
+ str ret;
+ if(this->get(key, &ret)) return ret;
+ else return str("");
+ }
+ VerStr nxtKey(u64* searched=nullptr) const
+ {
+ u32 klen, vlen;
+ bool ok = false;
+ i64 prev = (i64)m_nxtChIdx;
+ VerIdx viNxt = this->nxt();
+ i64 inxt = (i64)m_nxtChIdx;
+ u32 cur = s_ch.prevIdx((u32)(inxt));
+
+ if(searched){
+ *searched = (inxt-prev-1)>0? inxt-prev-1 : (m_blkCnt-prev)+inxt; //(m_blkCnt-prev-1) + inxt+1;
+ }
+ if(viNxt.idx>=DELETED){ return {viNxt.version, ""}; }
+
+ i64 total_len = this->len(cur, viNxt.version, &klen, &vlen);
+ if(total_len==0){ return {viNxt.version, ""}; }
+
+ str key(klen,'\0');
+ ok = this->getKey(cur, viNxt.version,
+ (void*)key.data(), klen);
+
+ if(!ok || strlen(key.c_str())!=key.length() )
+ return {viNxt.version, ""};
+
+ return { viNxt.version, key }; // copy elision
+ }
+ auto getKeyStrs() const -> std::vector
+ {
+ using namespace std;
+
+ set keys; VerStr nxt; u64 searched=0, srchCnt=0;
+ while(srchCnt < m_blkCnt)
+ {
+ nxt = nxtKey(&searched);
+ if(nxt.str.length() > 0){ keys.insert(nxt); }
+
+ srchCnt += searched;
+ }
+
+ return vector(keys.begin(), keys.end());
+ }
+ bool del(str const& key)
+ {
+ return this->del( (void const* const)key.data(), (u32)key.length() );
+ }
+
+ template
+ auto get(str const& key) -> std::vector
+ {
+ u32 vlen = 0;
+ len(key.data(), (u32)key.length(), &vlen);
+ if (vlen == 0)
+ {
+ std::vector ret_null;
+ ret_null.clear();
+ return ret_null;
+ }
+ std::vector ret(vlen);
+ get(key.data(), (u32)key.length(), (void*)ret.data(), vlen);
+ return ret;
+ }
+ template
+ i64 put(str const& key, std::vector const& val)
+ {
+ return put(key.data(), (u32)key.length(), val.data(), (u32)(val.size()*sizeof(T)) );
+ }
+ // end separated C++ functions
+
+};
+
+// // simdb_listDBs()
+// #ifdef _WIN32
+// auto simdb_listDBs(simdb_error* error_code=nullptr) -> std::vector
+// {
+// using namespace std;
+
+// static HMODULE _hModule = nullptr;
+// static NTOPENDIRECTORYOBJECT NtOpenDirectoryObject = nullptr;
+// static NTOPENFILE NtOpenFile = nullptr;
+// static NTQUERYDIRECTORYOBJECT NtQueryDirectoryObject = nullptr;
+// static RTLINITUNICODESTRING RtlInitUnicodeString = nullptr;
+
+// vector ret;
+
+// if(!NtOpenDirectoryObject){
+// NtOpenDirectoryObject = (NTOPENDIRECTORYOBJECT)GetLibraryProcAddress( _T("ntdll.dll"), "NtOpenDirectoryObject");
+// }
+// if(!NtQueryDirectoryObject){
+// NtQueryDirectoryObject = (NTQUERYDIRECTORYOBJECT)GetLibraryProcAddress(_T("ntdll.dll"), "NtQueryDirectoryObject");
+// }
+// if(!NtOpenFile){
+// NtOpenFile = (NTOPENFILE)GetLibraryProcAddress(_T("ntdll.dll"), "NtOpenFile");
+// }
+
+// HANDLE hDir = NULL;
+// IO_STATUS_BLOCK isb = { 0 };
+// DWORD sessionId;
+// BOOL ok = ProcessIdToSessionId(GetCurrentProcessId(), &sessionId);
+// if(!ok){ return { "Could not get current session" }; }
+
+// wstring sesspth = L"\\Sessions\\" + to_wstring(sessionId) + L"\\BaseNamedObjects";
+// const WCHAR* mempth = sesspth.data();
+
+// WCHAR buf[4096];
+// UNICODE_STRING pth = { 0 };
+// pth.Buffer = (WCHAR*)mempth;
+// pth.Length = (USHORT)lstrlenW(mempth) * sizeof(WCHAR);
+// pth.MaximumLength = pth.Length;
+
+// OBJECT_ATTRIBUTES oa = { 0 };
+// oa.Length = sizeof( OBJECT_ATTRIBUTES );
+// oa.RootDirectory = NULL;
+// oa.Attributes = OBJ_CASE_INSENSITIVE;
+// oa.ObjectName = &pth;
+// oa.SecurityDescriptor = NULL;
+// oa.SecurityQualityOfService = NULL;
+
+// NTSTATUS status;
+// status = NtOpenDirectoryObject(
+// &hDir,
+// /*STANDARD_RIGHTS_READ |*/ DIRECTORY_QUERY,
+// &oa);
+
+// if(hDir==NULL || status!=STATUS_SUCCESS){ return { "Could not open file" }; }
+
+// BOOLEAN rescan = TRUE;
+// ULONG ctx = 0;
+// ULONG retLen = 0;
+// do
+// {
+// status = NtQueryDirectoryObject(hDir, buf, sizeof(buf), TRUE, rescan, &ctx, &retLen);
+// rescan = FALSE;
+// auto info = (OBJECT_DIRECTORY_INFORMATION*)buf;
+
+// if( lstrcmpW(info->type.Buffer, L"Section")!=0 ){ continue; }
+// WCHAR wPrefix[] = L"simdb_";
+// size_t pfxSz = sizeof(wPrefix);
+// if( strncmp( (char*)info->name.Buffer, (char*)wPrefix, pfxSz)!=0 ){ continue; }
+
+// wstring wname = wstring( ((WCHAR*)info->name.Buffer)+6 );
+// wstring_convert> cnvrtr;
+// string name = cnvrtr.to_bytes(wname);
+
+// ret.push_back(name);
+// }while(status!=STATUS_NO_MORE_ENTRIES);
+
+// return ret;
+// }
+// #else
+// auto simdb_listDBs(simdb_error* error_code=nullptr) -> std::vector
+// {
+// using namespace std;
+
+// char prefix[] = "simdb_";
+// size_t pfxSz = sizeof(prefix)-1;
+
+// vector ret;
+
+// DIR* d; // d is directory handle
+// errno = ENOENT;
+// if( (d=opendir(P_tmpdir))==NULL || errno!=ENOENT){
+// closedir(d);
+// if(error_code){ *error_code = simdb_error::DIR_NOT_FOUND; }
+// return ret;
+// }
+
+// struct dirent* dent; // dent is directory entry
+// while( (dent=readdir(d)) != NULL )
+// {
+// if(errno != ENOENT){
+// closedir(d);
+// if(error_code){ *error_code = simdb_error::DIR_ENTRY_ERROR; }
+// return ret;
+// }
+
+// if(strncmp(dent->d_name, prefix, pfxSz)==0){
+// ret.push_back(dent->d_name + 6);
+// }
+// }
+
+// closedir(d);
+// if(error_code){ *error_code = simdb_error::NO_ERRORS; }
+// return ret;
+// }
+// #endif
+
+
+#endif
+
+
diff --git a/common/software/src/cl_common_utils.c b/common/software/src/cl_common_utils.c
new file mode 100644
index 0000000..2bf8f0f
--- /dev/null
+++ b/common/software/src/cl_common_utils.c
@@ -0,0 +1,364 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+
+#include "cl_common_utils.h"
+#include
+#include
+#include
+#include
+#include
+
+#ifndef VP_TEST
+#ifndef SV_TEST
+#include
+#endif
+#endif
+
+#ifdef VP_TEST
+#include
+#include
+#define OCL_BASE 0x10200000
+#define OCL_SIZE (0x10220000 - 0x10200000)
+#define DDR_BASE 0xc0000000
+#define DDR_SIZE 0x40000000
+uint32_t *p_reg;
+uint64_t *p_mem;
+#else
+#ifndef SV_TEST
+#define MAX_NUM_INT 16
+pci_bar_handle_t pci_bar_handle_ocl = PCI_BAR_HANDLE_INIT;
+pci_bar_handle_t pci_bar_handle_bar1 = PCI_BAR_HANDLE_INIT;
+pci_bar_handle_t pci_bar_handle_pcis = PCI_BAR_HANDLE_INIT;
+struct pollfd pci_int_fds[MAX_NUM_INT];
+#endif
+#endif
+
+// Util functions
+void apb_write(uint64_t addr, uint32_t data)
+{
+#ifdef VP_TEST
+ *(p_reg+addr/4) = data;
+#else
+ cl_poke_ocl(addr, data);
+#endif
+}
+
+void apb_read(uint64_t addr, uint32_t *data)
+{
+#ifdef VP_TEST
+ *data = *(p_reg+addr/4);
+#else
+ cl_peek_ocl(addr, data);
+#endif
+}
+
+void ddr_write(uint64_t addr, uint64_t data, uint32_t size)
+{
+#ifdef VP_TEST
+ switch (size) {
+ case 0:
+ ((uint8_t *)p_mem)[addr] = data & 0xFF;
+ break;
+ case 1:
+ ((uint16_t *)p_mem)[addr>>1] = data & 0xFFFF;
+ break;
+ case 2:
+ ((uint32_t *)p_mem)[addr>>2] = data & 0xFFFFFFFF;
+ break;
+ default:
+ p_mem[addr>>3] = data;
+ break;
+ }
+#else
+ cl_poke_pcis(addr, data, size);
+#endif
+}
+
+void ddr_read(uint64_t addr, uint64_t *data, uint32_t size)
+{
+#ifdef VP_TEST
+ switch (size) {
+ case 0:
+ *data = ((uint8_t *)p_mem)[addr];
+ break;
+ case 1:
+ *data = ((uint16_t *)p_mem)[addr>>1];
+ break;
+ case 2:
+ *data = ((uint32_t *)p_mem)[addr>>2];
+ break;
+ default:
+ *data = p_mem[addr>>3];
+ break;
+ }
+#else
+ cl_peek_pcis(addr, data, size);
+#endif
+}
+
+void cfg_write(uint64_t addr, uint32_t data)
+{
+#ifndef VP_TEST
+ cl_poke_bar1(addr, data);
+#endif
+}
+
+void cfg_read(uint64_t addr, uint32_t *data)
+{
+#ifndef VP_TEST
+ cl_peek_bar1(addr, data);
+#endif
+}
+
+#ifndef VP_TEST
+#ifndef SV_TEST
+/* check if the corresponding AFI is loaded */
+int check_afi_ready(int slot_id, uint16_t pci_vendor_id, uint16_t pci_device_id)
+{
+ struct fpga_mgmt_image_info info = {0};
+ int rc;
+
+ /* get local image description, contains status, vendor id, and device id. */
+ rc = fpga_mgmt_describe_local_image(slot_id, &info,0);
+ fail_on(rc, out, "Unable to get AFI information from slot %d. Are you running as root?",slot_id);
+
+ /* check to see if the slot is ready */
+ if (info.status != FPGA_STATUS_LOADED) {
+ rc = 1;
+ fail_on(rc, out, "AFI in Slot %d is not in READY state !", slot_id);
+ }
+
+ printf("AFI PCI Vendor ID: 0x%x, Device ID 0x%x\n",
+ info.spec.map[FPGA_APP_PF].vendor_id,
+ info.spec.map[FPGA_APP_PF].device_id);
+
+ /* confirm that the AFI that we expect is in fact loaded */
+ if (info.spec.map[FPGA_APP_PF].vendor_id != pci_vendor_id ||
+ info.spec.map[FPGA_APP_PF].device_id != pci_device_id) {
+ printf("AFI does not show expected PCI vendor id and device ID. If the AFI "
+ "was just loaded, it might need a rescan. Rescanning now.\n");
+
+ rc = fpga_pci_rescan_slot_app_pfs(slot_id);
+ fail_on(rc, out, "Unable to update PF for slot %d",slot_id);
+ /* get local image description, contains status, vendor id, and device id. */
+ rc = fpga_mgmt_describe_local_image(slot_id, &info,0);
+ fail_on(rc, out, "Unable to get AFI information from slot %d",slot_id);
+
+ printf("AFI PCI Vendor ID: 0x%x, Device ID 0x%x\n",
+ info.spec.map[FPGA_APP_PF].vendor_id,
+ info.spec.map[FPGA_APP_PF].device_id);
+
+ /* confirm that the AFI that we expect is in fact loaded after rescan */
+ if (info.spec.map[FPGA_APP_PF].vendor_id != pci_vendor_id ||
+ info.spec.map[FPGA_APP_PF].device_id != pci_device_id) {
+ rc = 1;
+ fail_on(rc, out, "The PCI vendor id and device of the loaded AFI are not "
+ "the expected values.");
+ }
+ }
+
+ return (rc != 0 ? 1: 0);
+out:
+ return 1;
+}
+#endif
+#endif
+
+int cl_common_init(uint16_t pci_vendor_id, uint16_t pci_device_id, uint32_t pci_int_mask)
+{
+#ifdef VP_TEST
+ void* ocl_mm = mmap_device(OCL_BASE, OCL_SIZE);
+ void* ddr_mm = mmap_device(DDR_BASE, DDR_SIZE);
+ p_reg = (uint32_t *)ocl_mm;
+ p_mem = (uint64_t *)ddr_mm;
+ return 0;
+#else
+ int rc;
+
+#ifdef SV_TEST
+// Vivado does not support svGetScopeFromName
+//#ifdef INCLUDE_DPI_CALLS
+#ifndef VIVADO_SIM
+ svScope scope;
+ scope = svGetScopeFromName("tb");
+ svSetScope(scope);
+
+ rc = 0;
+#endif
+//#endif
+#else
+ int slot_id;
+ int pf_id;
+ int bar_id;
+
+ /* initialize the fpga_pci library so we could have access to FPGA PCIe from this applications */
+ rc = fpga_pci_init();
+ fail_on(rc, out, "Unable to initialize the fpga_pci library");
+
+ /* This demo works with single FPGA slot, we pick slot #0 as it works for both f1.2xl and f1.16xl */
+ slot_id = 0;
+ rc = check_afi_ready(slot_id, pci_vendor_id, pci_device_id);
+ fail_on(rc, out, "AFI not ready");
+
+ /* initialize the bar handle */
+ pf_id = FPGA_APP_PF;
+
+ bar_id = APP_PF_BAR0;
+ rc = fpga_pci_attach(slot_id, pf_id, bar_id, 0, &pci_bar_handle_ocl);
+ fail_on(rc, out, "Unable to attach to the AFI on slot id %d, bar_id %d", slot_id, bar_id);
+ bar_id = APP_PF_BAR1;
+ rc = fpga_pci_attach(slot_id, pf_id, bar_id, 0, &pci_bar_handle_bar1);
+ fail_on(rc, out, "Unable to attach to the AFI on slot id %d, bar_id %d", slot_id, bar_id);
+ bar_id = APP_PF_BAR4;
+ rc = fpga_pci_attach(slot_id, pf_id, bar_id, 0, &pci_bar_handle_pcis);
+ fail_on(rc, out, "Unable to attach to the AFI on slot id %d, bar_id %d", slot_id, bar_id);
+
+ /* initialize the MSI interrupt fd */
+ uint32_t i;
+ char event_file_name[256];
+ int fd;
+ for (i=0; i>i)&0x1) {
+ rc = sprintf(event_file_name, "/dev/fpga%i_event%i", slot_id, i);
+ fail_on((rc = (rc < 0)? 1:0), out, "Unable to format event file name.");
+ if((fd = open(event_file_name, O_RDONLY)) == -1) {
+ printf("Error - invalid device %s\n", event_file_name);
+ rc = 1;
+ fail_on(rc, out, "Unable to open event device %s", event_file_name);
+ }
+ pci_int_fds[i].fd = fd;
+ pci_int_fds[i].events = POLLIN;
+ } else {
+ pci_int_fds[i].fd = -1;
+ }
+ }
+
+#endif
+
+ return (rc != 0 ? 1 : 0);
+out:
+ return 1;
+#endif
+}
+
+int cl_common_cleanup()
+{
+#ifdef VP_TEST
+ return 0;
+#else
+ int rc = 0;;
+#ifndef SV_TEST
+ if (pci_bar_handle_ocl >= 0) {
+ if (fpga_pci_detach(pci_bar_handle_ocl) != 0) {
+ printf("Failure while detaching bar0 from the fpga.\n");
+ rc = 1;
+ }
+ }
+ if (pci_bar_handle_bar1 >= 0) {
+ if (fpga_pci_detach(pci_bar_handle_bar1) != 0) {
+ printf("Failure while detaching bar1 from the fpga.\n");
+ rc = 1;
+ }
+ }
+ if (pci_bar_handle_pcis >= 0) {
+ if (fpga_pci_detach(pci_bar_handle_pcis) != 0) {
+ printf("Failure while detaching bar4 from the fpga.\n");
+ rc = 1;
+ }
+ }
+ uint32_t i;
+ for (i=0; i
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cosim_top.h"
+
+enum EVENT_TYPE
+{
+ EVENT_APB_WR = 0,
+ EVENT_RAM_WR,
+ EVENT_IRQ_WR,
+ EVENT_APB_RD,
+ EVENT_RAM_RD,
+ EVENT_IRQ_RD,
+ EVENT_ST
+};
+
+#define SIZE_UINT8 0
+#define SIZE_UINT16 1
+#define SIZE_UINT32 2
+#define SIZE_UINT64 3
+
+#define LOW_32b(a) ((uint32_t)((uint64_t)(a) & 0xffffffff))
+#define HIGH_32b(a) ((uint32_t)(((uint64_t)(a)) >> 32L))
+
+static sc_core::sc_event apb_rd_done_event;
+static sc_core::sc_event apb_wr_done_event;
+static sc_core::sc_event ram_rd_done_event;
+static sc_core::sc_event ram_wr_done_event;
+static sc_core::sc_event irq_rd_done_event;
+static sc_core::sc_event irq_wr_done_event;
+static sc_core::sc_event start_event;
+
+extern "C" {
+
+#include
+#include "svdpi.h"
+extern void sv_int_ack(uint32_t int_num);
+extern void sv_printf(char *msg);
+void host_memory_putc(uint64_t addr, uint8_t data)
+{
+ *(uint8_t *)addr = data;
+}
+
+uint8_t host_memory_getc(uint64_t addr)
+{
+ return *(uint8_t *)addr;
+}
+
+void log_printf(const char *format, ...)
+{
+ static char sv_msg_buffer[256];
+ va_list args;
+
+ va_start(args, format);
+ vsprintf(sv_msg_buffer, format, args);
+ sv_printf(sv_msg_buffer);
+
+ va_end(args);
+}
+
+void int_handler(uint32_t int_num)
+{
+ svScope scope;
+ scope = svGetScopeFromName("tb");
+ svSetScope(scope);
+
+ log_printf("Received interrupt %2d", int_num);
+ sv_int_ack(int_num);
+}
+
+
+extern void set_apb_rd(uint64_t addr, uint32_t *data);
+extern void set_apb_wr(uint64_t addr, uint32_t data);
+extern void set_irq_rd(uint32_t *data);
+extern void set_irq_wr(uint32_t data);
+extern void set_ram_rd(uint64_t addr, uint64_t *data, uint32_t size);
+extern void set_ram_wr(uint64_t addr, uint64_t data, uint32_t size);
+extern void set_ev_trigger(uint32_t int_num);
+extern uint32_t apb_read_ack();
+extern uint64_t ram_read_ack();
+extern uint64_t irq_read_ack();
+
+// Called by sv side to notify the DPI process is done
+void sv_done_notify(int idx)
+{
+ switch(idx)
+ {
+ case EVENT_APB_WR:
+ apb_wr_done_event.notify();
+ break;
+ case EVENT_RAM_WR:
+ ram_wr_done_event.notify();
+ break;
+ case EVENT_IRQ_WR:
+ irq_wr_done_event.notify();
+ break;
+ case EVENT_APB_RD:
+ apb_rd_done_event.notify();
+ break;
+ case EVENT_RAM_RD:
+ ram_rd_done_event.notify();
+ break;
+ case EVENT_IRQ_RD:
+ irq_rd_done_event.notify();
+ break;
+ case EVENT_ST:
+ start_event.notify();
+ break;
+ default:
+ cout<< "Error: Invild event index!" << endl;
+ sc_stop();
+ break;
+ }
+}
+
+}
+
+
+cosim_top::cosim_top( sc_core::sc_module_name name)
+ : sc_core::sc_module( name )
+{
+ poll_time_ns = 1;
+
+ char *cosim_pid = getenv("COSIM_PID_HOST");
+
+ std::stringstream apb_channel_str;
+ std::stringstream ram_channel_str;
+ std::stringstream irq_channel_str;
+
+ apb_channel_str << "apb_ipc_db_" << cosim_pid;
+ irq_channel_str << "irq_ipc_db_" << cosim_pid;
+ ram_channel_str << "ram_ipc_db_" << cosim_pid;
+
+ apb_ipc_db_nm = new char [apb_channel_str.str().length()+1];
+ strcpy(apb_ipc_db_nm, apb_channel_str.str().c_str());
+ irq_ipc_db_nm = new char [irq_channel_str.str().length()+1];
+ strcpy(irq_ipc_db_nm, irq_channel_str.str().c_str());
+ ram_ipc_db_nm = new char [ram_channel_str.str().length()+1];
+ strcpy(ram_ipc_db_nm, ram_channel_str.str().c_str());
+
+ apb_ipc_db = new simdb(const_cast(apb_channel_str.str().c_str()), SIMDB_BLOCK_SIZE, SIMDB_BLOCK_COUNT);
+ irq_ipc_db = new simdb(const_cast(irq_channel_str.str().c_str()), SIMDB_BLOCK_SIZE, SIMDB_BLOCK_COUNT);
+ ram_ipc_db = new simdb(const_cast(ram_channel_str.str().c_str()), SIMDB_BLOCK_SIZE, SIMDB_BLOCK_COUNT);
+
+ SC_THREAD(apb_ipc_channel);
+ SC_THREAD(irq_ipc_channel);
+ SC_THREAD(ram_ipc_channel);
+}
+
+cosim_top::~cosim_top()
+{
+ if (apb_ipc_db)
+ {
+ apb_ipc_db->close();
+ delete apb_ipc_db;
+ }
+ if (irq_ipc_db)
+ {
+ irq_ipc_db->close();
+ delete irq_ipc_db;
+ }
+ if (ram_ipc_db)
+ {
+ ram_ipc_db->close();
+ delete ram_ipc_db;
+ }
+
+ if (apb_ipc_db_nm)
+ delete apb_ipc_db_nm;
+ if (irq_ipc_db_nm)
+ delete irq_ipc_db_nm;
+ if (ram_ipc_db_nm)
+ delete ram_ipc_db_nm;
+}
+void cosim_top::apb_ipc_channel()
+{
+ uint64_t addr = 0;
+ uint32_t data = 0xdeadbeef;
+
+ std::stringstream str_wr_up;
+ std::stringstream str_wr_dn;
+ std::stringstream str_rd_up;
+ std::stringstream str_rd_dn;
+ str_wr_up << apb_ipc_db_nm << "_wr_up";
+ str_wr_dn << apb_ipc_db_nm << "_wr_dn";
+ str_rd_up << apb_ipc_db_nm << "_rd_up";
+ str_rd_dn << apb_ipc_db_nm << "_rd_dn";
+
+ // Make sure the RTL testbench is ready
+ sc_core::wait(start_event);
+ while(1)
+ {
+ wait(poll_time_ns, SC_NS);
+ auto tpv_dn = apb_ipc_db->get(str_wr_dn.str());
+ auto tpv_up = apb_ipc_db->get(str_wr_up.str());
+ if (!tpv_dn.empty()) // handle the write transaction
+ {
+ tpv_up = apb_ipc_db->get(str_wr_up.str());
+ if (!tpv_up.empty())
+ {
+ cout << name() << "WARNING: The last write stream FIFO is not empty!" << endl;
+ apb_ipc_db->del(str_wr_up.str()); // Clear the ack fifo which should be cleared by QEMU side.
+ }
+ addr = tpv_dn[0].addr;
+ data = tpv_dn[0].data;
+
+ svSetScope(svGetScopeFromName("cosim_test"));
+ set_apb_wr(addr, data); // call dpi function
+ set_ev_trigger(EVENT_APB_WR);
+
+ sc_core::wait(apb_wr_done_event);
+
+ struct trans_payload t;
+ t.addr = addr;
+ t.data = data;
+ std::vector v;
+ v.push_back(t);
+
+ apb_ipc_db->del(str_wr_dn.str()); // Clear the write FIFO
+ apb_ipc_db->put(str_wr_up.str(), v);
+ }
+
+ tpv_dn = apb_ipc_db->get(str_rd_dn.str());
+ if (!tpv_dn.empty()) // handle the read transaction
+ {
+ tpv_up = apb_ipc_db->get(str_rd_up.str());
+ if (!tpv_up.empty())
+ {
+ cout << name() << "WARNING: The last read stream FIFO is not empty!\n";
+ apb_ipc_db->del(str_rd_up.str()); // Clear the ack fifo which should be cleared by QEMU side.
+ }
+ addr = tpv_dn[0].addr;
+
+ svSetScope(svGetScopeFromName("cosim_test"));
+ set_apb_rd(addr, &data); // call dpi function
+ set_ev_trigger(EVENT_APB_RD);
+
+ sc_core::wait(apb_rd_done_event);
+
+ data = apb_read_ack();
+
+ struct trans_payload t;
+ t.addr = addr;
+ t.data = data;
+ std::vector v;
+ v.push_back(t);
+
+ apb_ipc_db->del(str_rd_dn.str()); // Clear the read FIFO
+ apb_ipc_db->put(str_rd_up.str(), v);
+ }
+
+ }
+}
+void cosim_top::ram_ipc_channel()
+{
+ uint64_t addr = 0;
+ uint64_t data = 0xdeadbeef;
+
+ std::stringstream str_wr_up;
+ std::stringstream str_wr_dn;
+ std::stringstream str_rd_up;
+ std::stringstream str_rd_dn;
+ str_wr_up << ram_ipc_db_nm << "_wr_up";
+ str_wr_dn << ram_ipc_db_nm << "_wr_dn";
+ str_rd_up << ram_ipc_db_nm << "_rd_up";
+ str_rd_dn << ram_ipc_db_nm << "_rd_dn";
+
+ // Make sure the RTL testbench is ready
+ sc_core::wait(start_event);
+ while(1)
+ {
+ wait(poll_time_ns, SC_NS);
+ auto tpv_dn = ram_ipc_db->get(str_wr_dn.str());
+ auto tpv_up = ram_ipc_db->get(str_wr_up.str());
+ if (!tpv_dn.empty()) // handle the write transaction
+ {
+ tpv_up = ram_ipc_db->get(str_wr_up.str());
+ if (!tpv_up.empty())
+ {
+ cout << name() << "WARNING: The last write stream FIFO is not empty!\n";
+ ram_ipc_db->del(str_wr_up.str()); // Clear the ack fifo which should be cleared by QEMU side.
+ }
+ addr = tpv_dn[0].addr;
+ data = tpv_dn[0].data;
+
+ svSetScope(svGetScopeFromName("cosim_test"));
+ set_ram_wr(addr, data, SIZE_UINT32); // call dpi function
+ set_ev_trigger(EVENT_RAM_WR);
+
+ sc_core::wait(ram_wr_done_event);
+
+ struct trans_payload t;
+ t.addr = addr;
+ t.data = data;
+ std::vector v;
+ v.push_back(t);
+
+ ram_ipc_db->del(str_wr_dn.str()); // Clear the write FIFO
+ ram_ipc_db->put(str_wr_up.str(), v);
+ }
+
+ tpv_dn = ram_ipc_db->get(str_rd_dn.str());
+ if (!tpv_dn.empty()) // handle the read transaction
+ {
+ tpv_up = ram_ipc_db->get(str_rd_up.str());
+ if (!tpv_up.empty())
+ {
+ cout << name() << "WARNING: The last read stream FIFO is not empty!\n";
+ ram_ipc_db->del(str_rd_up.str()); // Clear the ack fifo which should be cleared by QEMU side.
+ }
+ addr = tpv_dn[0].addr;
+ data = tpv_dn[0].data;
+
+ svSetScope(svGetScopeFromName("cosim_test"));
+ set_ram_rd(addr, &data, SIZE_UINT32); // call dpi function
+ set_ev_trigger(EVENT_RAM_RD);
+
+ sc_core::wait(ram_rd_done_event);
+
+ data = ram_read_ack();
+
+ struct trans_payload t;
+ t.addr = addr;
+ t.data = LOW_32b(data);
+ std::vector v;
+ v.push_back(t);
+
+ ram_ipc_db->del(str_rd_dn.str()); // Clear the read FIFO
+ ram_ipc_db->put(str_rd_up.str(), v);
+ }
+
+ }
+}
+void cosim_top::irq_ipc_channel()
+{
+ uint32_t data = 0;
+
+ // Make sure the RTL testbench is ready
+ sc_core::wait(start_event);
+ while(1)
+ {
+ wait(poll_time_ns, SC_NS);
+ auto tpv_dn = irq_ipc_db->get("irq_ipc_db_dn");
+ auto tpv_up = irq_ipc_db->get("irq_ipc_db_up");
+
+ if (!tpv_up.empty())
+ {
+ cout << name() << "WARNING: The last INT up stream FIFO is not empty!\n";
+ irq_ipc_db->del("irq_ipc_db_up");
+ }
+ if (!tpv_dn.empty())
+ {
+ cout << name() << "WARNING: The last INT down stream FIFO is not empty!\n";
+ irq_ipc_db->del("irq_ipc_db_dn");
+ }
+
+ svSetScope(svGetScopeFromName("cosim_test"));
+ set_irq_rd(&data); // call dpi function
+ set_ev_trigger(EVENT_IRQ_RD);
+
+ sc_core::wait(irq_rd_done_event);
+
+ data = irq_read_ack();
+
+ if (data != 0)
+ {
+ struct irq_trans_payload irq_stat;
+ irq_stat.value = data;
+ std::vector v;
+ v.push_back(irq_stat);
+ irq_ipc_db->put("irq_ipc_db_up", v);
+
+ while(1)
+ {
+ tpv_dn = irq_ipc_db->get("irq_ipc_db_dn");
+ if(!tpv_dn.empty())
+ {
+ svSetScope(svGetScopeFromName("cosim_test"));
+ set_irq_wr(data); // call dpi function
+ set_ev_trigger(EVENT_IRQ_WR);
+
+ sc_core::wait(irq_wr_done_event);
+ break;
+ }
+ wait(poll_time_ns, SC_NS);
+ }
+
+ irq_ipc_db->del("irq_ipc_db_dn");
+ }
+ }
+}
diff --git a/common/software/src/sh_dpi_tasks.c b/common/software/src/sh_dpi_tasks.c
new file mode 100644
index 0000000..909bb0f
--- /dev/null
+++ b/common/software/src/sh_dpi_tasks.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2015-2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You may
+ * not use this file except in compliance with the License. A copy of the
+ * License is located at
+ *
+ * http://aws.amazon.com/apache2.0/
+ *
+ * or in the "license" file accompanying this file. This file is distributed
+ * on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
+ * express or implied. See the License for the specific language governing
+ * permissions and limitations under the License.
+ */
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+
+#ifndef VIVADO_SIM
+#include "svdpi.h"
+#endif
+
+#include "sh_dpi_tasks.h"
+
+void host_memory_putc(uint64_t addr, uint8_t data)
+{
+ *(uint8_t *)addr = data;
+}
+
+//void host_memory_getc(uint64_t addr, uint8_t *data)
+uint8_t host_memory_getc(uint64_t addr)
+{
+ return *(uint8_t *)addr;
+}
+
+void log_printf(const char *format, ...)
+{
+ static char sv_msg_buffer[256];
+ va_list args;
+
+ va_start(args, format);
+ vsprintf(sv_msg_buffer, format, args);
+ sv_printf(sv_msg_buffer);
+
+ va_end(args);
+}
+
+void int_handler(uint32_t int_num)
+{
+// Vivado does not support svGetScopeFromName
+#ifndef VIVADO_SIM
+ svScope scope;
+ scope = svGetScopeFromName("tb");
+ svSetScope(scope);
+#endif
+
+ log_printf("Received interrupt %2d", int_num);
+ sv_int_ack(int_num);
+
+ cl_int_handler(int_num);
+
+}
diff --git a/common/trace_player/Makefile.inc b/common/trace_player/Makefile.inc
new file mode 100644
index 0000000..0068288
--- /dev/null
+++ b/common/trace_player/Makefile.inc
@@ -0,0 +1,38 @@
+# ================================================================
+# NVDLA Open Source Project
+#
+# Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+# NVDLA Open Hardware License; Check \"LICENSE\" which comes with
+# this distribution for more information.
+# ================================================================
+
+export NVDLA_TRACE_PARSER ?= $(NVDLA_TRACE_PLAYER_ROOT)/parser/nvdla_trace_parser.py
+export NVDLA_TRACE_PARSER_COMMAND_NAME ?= trace_parser_command
+export NVDLA_TRACE_PARSER_COMMAND_SRC ?= $(addsuffix .c, $(NVDLA_TRACE_PARSER_COMMAND_NAME))
+export NVDLA_TRACE_PARSER_COMMAND_OBJ ?= $(addsuffix .o, $(NVDLA_TRACE_PARSER_COMMAND_NAME))
+export NVDLA_TRACE_PARSER_COMMAND_LIB ?= $(addprefix lib, $(addsuffix .so, $(NVDLA_TRACE_PARSER_COMMAND_NAME)))
+
+export NVDLA_TRACE_PLAYER_INCLUDES ?= $(NVDLA_TRACE_PLAYER_ROOT)/include
+export NVDLA_TRACE_PLAYER_SRC_DIR ?= $(NVDLA_TRACE_PLAYER_ROOT)/src
+export NVDLA_TRACE_PLAYER_SRCS ?= \
+ trace_player_cmd.c \
+ trace_player_intr.c \
+ trace_player_sync.c \
+ trace_player_reg.c \
+ trace_player_mem.c \
+ trace_player_thread.c \
+
+export NVDLA_TRACE_PLAYER_LIB_DIR ?= $(NVDLA_TRACE_PLAYER_ROOT)/build
+export NVDLA_TRACE_PLAYER_LIB ?= trace_player_shared
+
+export NVDLA_TRACE_PLAYER_SRCS_FULLPATH ?= $(addprefix $(NVDLA_TRACE_PLAYER_SRC_DIR)/,${NVDLA_TRACE_PLAYER_SRCS})
+
+$(NVDLA_TRACE_PARSER_COMMAND_SRC):
+ $(NVDLA_TRACE_PARSER) -f $(NVDLA_TRACE)
+
+$(NVDLA_TRACE_PARSER_COMMAND_LIB): $(NVDLA_TRACE_PARSER_COMMAND_SRC)
+ $(CC) -fPIC -c $(NVDLA_TRACE_PARSER_COMMAND_SRC) -o $(NVDLA_TRACE_PARSER_COMMAND_OBJ) -I$(NVDLA_TRACE_PLAYER_INCLUDES) -I$(NVDLA_REGISTER_HEADER_DIR)
+ $(CC) -fPIC -shared -o $(NVDLA_TRACE_PARSER_COMMAND_LIB) $(NVDLA_TRACE_PARSER_COMMAND_OBJ)
+
+$(NVDLA_TRACE_PLAYER_LIB_DIR)/$(NVDLA_TRACE_PLAYER_LIB):
+ cd $(NVDLA_TRACE_PLAYER_LIB_DIR) && make clean && make NVDLA_TRACE_PLAYER_CFLAGS=$(NVDLA_TRACE_PLAYER_CFLAGS) CC=$(CC)
diff --git a/common/trace_player/build/Makefile b/common/trace_player/build/Makefile
new file mode 100644
index 0000000..86191fe
--- /dev/null
+++ b/common/trace_player/build/Makefile
@@ -0,0 +1,35 @@
+# ================================================================
+# NVDLA Open Source Project
+#
+# Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+# NVDLA Open Hardware License; Check \"LICENSE\" which comes with
+# this distribution for more information.
+# ================================================================
+
+VPATH = ../src
+
+INCLUDES = -I../../../common/software/include -I../include
+
+CC ?= gcc
+CFLAGS = -Wall -fPIC $(INCLUDES) $(NVDLA_TRACE_PLAYER_CFLAGS)
+LDLIBS = -ldl
+
+SRC = \
+ trace_player.c \
+ trace_player_cmd.c \
+ trace_player_intr.c \
+ trace_player_sync.c \
+ trace_player_reg.c \
+ trace_player_mem.c \
+ trace_player_thread.c \
+
+OBJ = $(SRC:.c=.o)
+TARGET = libtrace_player_shared.so
+
+all: $(TARGET)
+
+$(TARGET): $(OBJ)
+ $(CC) $(CFLAGS) -shared -o $@ $^ $(LDFLAGS) $(LDLIBS)
+
+clean:
+ rm -f *.o $(TARGET)
diff --git a/common/trace_player/include/trace_player.h b/common/trace_player/include/trace_player.h
new file mode 100644
index 0000000..3ebbf74
--- /dev/null
+++ b/common/trace_player/include/trace_player.h
@@ -0,0 +1,20 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player.h
+
+#ifndef TRACE_PLAYER_H
+#define TRACE_PLAYER_H
+
+void trace_player_set_stop_on_error(int val);
+void trace_player_set_wait_interval(int val);
+void trace_player_set_skip_mem_init(int val);
+void trace_player_set_dump_mem_enable(int val);
+int trace_player_run(const char *parser_output_lib);
+
+#endif
diff --git a/common/trace_player/include/trace_player_cmd.h b/common/trace_player/include/trace_player_cmd.h
new file mode 100644
index 0000000..3dfef8a
--- /dev/null
+++ b/common/trace_player/include/trace_player_cmd.h
@@ -0,0 +1,151 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_cmd.h
+
+#ifndef TRACE_PLAYER_CMD_H
+#define TRACE_PLAYER_CMD_H
+
+#include
+
+typedef enum {
+ TRACE_PLAYER_CMD_WRITE,
+ TRACE_PLAYER_CMD_READ,
+ TRACE_PLAYER_CMD_READ_CHECK,
+ TRACE_PLAYER_CMD_POLL_REG_EQUAL,
+ TRACE_PLAYER_CMD_MEM_LOAD,
+ TRACE_PLAYER_CMD_MEM_INIT_PATTERN,
+ TRACE_PLAYER_CMD_MEM_INIT_FILE,
+ TRACE_PLAYER_CMD_INTR_NOTIFY,
+ TRACE_PLAYER_CMD_SYNC_WAIT,
+ TRACE_PLAYER_CMD_SYNC_NOTIFY,
+ TRACE_PLAYER_CMD_CHECK_CRC,
+ TRACE_PLAYER_CMD_CHECK_FILE,
+ TRACE_PLAYER_CMD_CHECK_NOTHING
+} trace_player_cmd_type_t;
+
+typedef enum {
+ TRACE_PLAYER_CMD_RESULT_DONE,
+ TRACE_PLAYER_CMD_RESULT_NORUN,
+ TRACE_PLAYER_CMD_RESULT_BLOCKED,
+ TRACE_PLAYER_CMD_RESULT_ERROR
+} trace_player_cmd_result_t;
+
+typedef struct {
+ uint64_t offset;
+ uint32_t value;
+} reg_write_cmd_t;
+
+typedef struct {
+ uint64_t offset;
+ char *sync_id;
+} reg_read_cmd_t;
+
+typedef struct {
+ uint64_t offset;
+ uint32_t golden_val;
+} reg_read_check_cmd_t;
+
+typedef struct {
+ uint64_t offset;
+ uint32_t expect_val;
+} poll_reg_equal_cmd_t;
+
+typedef struct {
+ char *mem_type;
+ uint64_t base;
+ char *file_path;
+} mem_load_cmd_t;
+
+typedef struct {
+ char *mem_type;
+ uint64_t base;
+ uint32_t size;
+ char *pattern;
+} mem_init_pattern_cmd_t;
+
+typedef struct {
+ char *mem_type;
+ uint64_t base;
+ char *file_path;
+} mem_init_file_cmd_t;
+
+typedef struct {
+ uint32_t intr_id;
+ char *sync_id;
+} intr_notify_cmd_t;
+
+typedef struct {
+ char *sync_id;
+} sync_wait_cmd_t;
+
+typedef struct {
+ char *sync_id;
+} sync_notify_cmd_t;
+
+typedef struct {
+ char *sync_id;
+ char *mem_type;
+ uint64_t base;
+ uint32_t size;
+ uint32_t golden_crc;
+} check_crc_cmd_t;
+
+typedef struct {
+ char *sync_id;
+ char *mem_type;
+ uint64_t base;
+ uint32_t size;
+ char *file_path;
+} check_file_cmd_t;
+
+typedef struct {
+ char *sync_id;
+} check_nothing_cmd_t;
+
+typedef struct {
+ trace_player_cmd_type_t type;
+ union {
+ reg_write_cmd_t reg_write_cmd;
+ reg_read_cmd_t reg_read_cmd;
+ reg_read_check_cmd_t reg_read_check_cmd;
+ poll_reg_equal_cmd_t poll_reg_equal_cmd;
+ mem_load_cmd_t mem_load_cmd;
+ mem_init_pattern_cmd_t mem_init_pattern_cmd;
+ mem_init_file_cmd_t mem_init_file_cmd;
+ intr_notify_cmd_t intr_notify_cmd;
+ sync_wait_cmd_t sync_wait_cmd;
+ sync_notify_cmd_t sync_notify_cmd;
+ check_crc_cmd_t check_crc_cmd;
+ check_file_cmd_t check_file_cmd;
+ check_nothing_cmd_t check_nothing_cmd;
+ };
+} trace_player_cmd_t;
+
+typedef struct trace_player_cmd_node {
+ trace_player_cmd_t cmd;
+ struct trace_player_cmd_node *next;
+} trace_player_cmd_node_t;
+
+trace_player_cmd_result_t trace_player_cmd_run(const trace_player_cmd_t *cmd);
+void trace_player_cmd_list_pop(trace_player_cmd_node_t **p_head);
+void trace_player_cmd_list_push_cmd_reg_write(trace_player_cmd_node_t **p_head, uint64_t offset, uint32_t value);
+void trace_player_cmd_list_push_cmd_reg_read(trace_player_cmd_node_t **p_head, uint64_t offset, const char *sync_id);
+void trace_player_cmd_list_push_cmd_reg_read_check(trace_player_cmd_node_t **p_head, uint64_t offset, uint32_t golden_val);
+void trace_player_cmd_list_push_cmd_poll_reg_equal(trace_player_cmd_node_t **p_head, uint64_t offset, uint32_t expect_val);
+void trace_player_cmd_list_push_cmd_mem_load(trace_player_cmd_node_t **p_head, const char* mem_type, uint64_t base, const char *file_path);
+void trace_player_cmd_list_push_cmd_mem_init_pattern(trace_player_cmd_node_t **p_head, const char* mem_type, uint64_t base, uint32_t size, const char *pattern);
+void trace_player_cmd_list_push_cmd_mem_init_file(trace_player_cmd_node_t **p_head, const char* mem_type, uint64_t base, const char *file_path);
+void trace_player_cmd_list_push_cmd_intr_notify(trace_player_cmd_node_t **p_head, uint32_t intr_id, const char *sync_id);
+void trace_player_cmd_list_push_cmd_sync_wait(trace_player_cmd_node_t **p_head, const char *sync_id);
+void trace_player_cmd_list_push_cmd_sync_notify(trace_player_cmd_node_t **p_head, const char *sync_id);
+void trace_player_cmd_list_push_cmd_check_crc(trace_player_cmd_node_t **p_head, const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, uint32_t golden_crc);
+void trace_player_cmd_list_push_cmd_check_file(trace_player_cmd_node_t **p_head, const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, const char *file_path);
+void trace_player_cmd_list_push_cmd_check_nothing(trace_player_cmd_node_t **p_head, const char *sync_id);
+
+#endif
diff --git a/common/trace_player/include/trace_player_impl.h b/common/trace_player/include/trace_player_impl.h
new file mode 100644
index 0000000..e5e53c3
--- /dev/null
+++ b/common/trace_player/include/trace_player_impl.h
@@ -0,0 +1,29 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_impl.h
+
+#ifndef TRACE_PLAYER_IMPL_H
+#define TRACE_PLAYER_IMPL_H
+
+#include
+
+extern void reg_write(uint64_t offset, uint32_t val);
+extern void reg_read(uint64_t offset, uint32_t *val);
+extern void mem_write64(const char *mem_type, uint64_t offset, uint64_t val);
+extern void mem_write32(const char *mem_type, uint64_t offset, uint32_t val);
+extern void mem_write16(const char *mem_type, uint64_t offset, uint16_t val);
+extern void mem_write8(const char *mem_type, uint64_t offset, uint8_t val);
+extern void mem_read64(const char *mem_type, uint64_t offset, uint64_t *val);
+extern void mem_read32(const char *mem_type, uint64_t offset, uint32_t *val);
+extern void mem_read16(const char *mem_type, uint64_t offset, uint16_t *val);
+extern void mem_read8(const char *mem_type, uint64_t offset, uint8_t *val);
+extern void trace_player_wait(int num);
+extern uint32_t trace_player_check_and_clear_pending_intr(void);
+
+#endif
diff --git a/common/trace_player/include/trace_player_intr.h b/common/trace_player/include/trace_player_intr.h
new file mode 100644
index 0000000..44aa95c
--- /dev/null
+++ b/common/trace_player/include/trace_player_intr.h
@@ -0,0 +1,29 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_intr.h
+
+#ifndef TRACE_PLAYER_INTR_H
+#define TRACE_PLAYER_INTR_H
+
+#include
+
+typedef struct {
+ uint32_t intr_id;
+ char *sync_id;
+} trace_player_intr_t;
+
+typedef struct trace_player_intr_node {
+ trace_player_intr_t intr;
+ struct trace_player_intr_node *next;
+} trace_player_intr_node_t;
+
+void trace_player_push_expect_intr(uint32_t intr_id, const char* sync_id);
+int trace_player_intr_check(uint32_t intr_id);
+
+#endif
diff --git a/common/trace_player/include/trace_player_mem.h b/common/trace_player/include/trace_player_mem.h
new file mode 100644
index 0000000..25d8538
--- /dev/null
+++ b/common/trace_player/include/trace_player_mem.h
@@ -0,0 +1,24 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_mem.h
+
+#ifndef TRACE_PLAYER_MEM_H
+#define TRACE_PLAYER_MEM_H
+
+#include
+
+void trace_player_mem_set_skip_mem_init(int val);
+void trace_player_mem_set_dump_mem_enable(int val);
+int trace_player_mem_load(const char *mem_type, uint64_t base, const char *file_path);
+int trace_player_mem_init_pattern(const char *mem_type, uint64_t base, uint32_t size, const char *pattern);
+int trace_player_mem_init_file(const char *mem_type, uint64_t base, const char *file_path);
+int trace_player_mem_check_crc(const char *mem_type, uint64_t base, uint32_t size, uint32_t golden_crc);
+int trace_player_mem_check_file(const char *mem_type, uint64_t base, uint32_t size, const char *file_path);
+
+#endif
diff --git a/common/trace_player/include/trace_player_parser.h b/common/trace_player/include/trace_player_parser.h
new file mode 100644
index 0000000..532799f
--- /dev/null
+++ b/common/trace_player/include/trace_player_parser.h
@@ -0,0 +1,30 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_parser.h
+
+#ifndef TRACE_PLAYER_PARSER_H
+#define TRACE_PLAYER_PARSER_H
+
+#include
+
+extern void trace_player_thread_push_cmd_reg_write(const char* thread_name, uint64_t offset, uint32_t value);
+extern void trace_player_thread_push_cmd_reg_read(const char* thread_name, uint64_t offset, const char *sync_id);
+extern void trace_player_thread_push_cmd_reg_read_check(const char* thread_name, uint64_t offset, uint32_t golden_val);
+extern void trace_player_thread_push_cmd_poll_reg_equal(const char* thread_name, uint64_t offset, uint32_t expect_val);
+extern void trace_player_thread_push_cmd_mem_load(const char* mem_type, uint64_t base, const char *file_path);
+extern void trace_player_thread_push_cmd_mem_init_pattern(const char* mem_type, uint64_t base, uint32_t size, const char *pattern);
+extern void trace_player_thread_push_cmd_mem_init_file(const char* mem_type, uint64_t base, const char *file_path);
+extern void trace_player_thread_push_cmd_intr_notify(uint32_t intr_id, const char *sync_id);
+extern void trace_player_thread_push_cmd_sync_wait(const char* thread_name, const char *sync_id);
+extern void trace_player_thread_push_cmd_sync_notify(const char* thread_name, const char *sync_id);
+extern void trace_player_thread_push_cmd_check_crc(const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, uint32_t golden_crc);
+extern void trace_player_thread_push_cmd_check_file(const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, const char *file_path);
+extern void trace_player_thread_push_cmd_check_nothing(const char *sync_id);
+
+#endif
diff --git a/common/trace_player/include/trace_player_reg.h b/common/trace_player/include/trace_player_reg.h
new file mode 100644
index 0000000..879d2ad
--- /dev/null
+++ b/common/trace_player/include/trace_player_reg.h
@@ -0,0 +1,19 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_reg.h
+
+#ifndef TRACE_PLAYER_REG_H_
+#define TRACE_PLAYER_REG_H_
+
+#include
+
+int trace_player_reg_read_check(uint64_t offset, uint32_t golden_val);
+int trace_player_reg_poll_reg_equal(uint64_t offset, uint32_t expect_val);
+
+#endif
diff --git a/common/trace_player/include/trace_player_sync.h b/common/trace_player/include/trace_player_sync.h
new file mode 100644
index 0000000..bf3dc01
--- /dev/null
+++ b/common/trace_player/include/trace_player_sync.h
@@ -0,0 +1,27 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_sync.h
+
+#ifndef TRACE_PLAYER_SYNC_H
+#define TRACE_PLAYER_SYNC_H
+
+typedef struct {
+ char *sync_id;
+ int notified;
+} trace_player_sync_t;
+
+typedef struct trace_player_sync_node {
+ trace_player_sync_t sync;
+ struct trace_player_sync_node *next;
+} trace_player_sync_node_t;
+
+void trace_player_sync_notify(const char *sync_id);
+int trace_player_sync_is_notified(const char *sync_id);
+
+#endif
diff --git a/common/trace_player/include/trace_player_thread.h b/common/trace_player/include/trace_player_thread.h
new file mode 100644
index 0000000..bed95bb
--- /dev/null
+++ b/common/trace_player/include/trace_player_thread.h
@@ -0,0 +1,43 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_thread.h
+
+#ifndef TRACE_PLAYER_THREAD_H
+#define TRACE_PLAYER_THREAD_H
+
+#include "trace_player_cmd.h"
+
+typedef struct {
+ char *name;
+ trace_player_cmd_node_t *cmd_head;
+} trace_player_thread_t;
+
+typedef struct trace_player_thread_node {
+ trace_player_thread_t thread;
+ struct trace_player_thread_node *next;
+} trace_player_thread_node_t;
+
+trace_player_thread_node_t** trace_player_thread_list_get_head(void);
+trace_player_cmd_result_t trace_player_thread_run(trace_player_thread_t *thread);
+void trace_player_thread_list_remove_node(trace_player_thread_node_t *rnode);
+void trace_player_thread_push_cmd_reg_write(const char* thread_name, uint64_t offset, uint32_t value);
+void trace_player_thread_push_cmd_reg_read(const char* thread_name, uint64_t offset, const char *sync_id);
+void trace_player_thread_push_cmd_reg_read_check(const char* thread_name, uint64_t offset, uint32_t golden_val);
+void trace_player_thread_push_cmd_poll_reg_equal(const char* thread_name, uint64_t offset, uint32_t expect_val);
+void trace_player_thread_push_cmd_mem_load(const char* mem_type, uint64_t base, const char *file_path);
+void trace_player_thread_push_cmd_mem_init_pattern(const char* mem_type, uint64_t base, uint32_t size, const char *pattern);
+void trace_player_thread_push_cmd_mem_init_file(const char* mem_type, uint64_t base, const char *file_path);
+void trace_player_thread_push_cmd_intr_notify(uint32_t intr_id, const char *sync_id);
+void trace_player_thread_push_cmd_sync_wait(const char* thread_name, const char *sync_id);
+void trace_player_thread_push_cmd_sync_notify(const char* thread_name, const char *sync_id);
+void trace_player_thread_push_cmd_check_crc(const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, uint32_t golden_crc);
+void trace_player_thread_push_cmd_check_file(const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, const char *file_path);
+void trace_player_thread_push_cmd_check_nothing(const char *sync_id);
+
+#endif
diff --git a/common/trace_player/include/trace_player_utils.h b/common/trace_player/include/trace_player_utils.h
new file mode 100644
index 0000000..aa7e8c4
--- /dev/null
+++ b/common/trace_player/include/trace_player_utils.h
@@ -0,0 +1,22 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_utils.h
+
+#ifndef TRACE_PLAYER_UTILS_H
+#define TRACE_PLAYER_UTILS_H
+
+#include
+
+#ifdef DEBUG
+ #define DEBUG_PRINT(a) printf a
+#else
+ #define DEBUG_PRINT(a) (void)0
+#endif
+
+#endif
diff --git a/common/trace_player/parser/nvdla_trace_parser.py b/common/trace_player/parser/nvdla_trace_parser.py
new file mode 100755
index 0000000..0d0739b
--- /dev/null
+++ b/common/trace_player/parser/nvdla_trace_parser.py
@@ -0,0 +1,176 @@
+#!/usr/bin/python
+
+# ================================================================
+# NVDLA Open Source Project
+#
+# Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+# NVDLA Open Hardware License; Check \"LICENSE\" which comes with
+# this distribution for more information.
+# ================================================================
+
+
+import argparse
+import re
+import os
+from pprint import pprint
+__DESCRIPTION__='''
+ 1. Read in trace file
+ 2. Generated file for trace parser to dispatch to other component
+'''
+class TraceParser(object):
+ re_comment = re.compile(r'^\s*(\/\/).*$')
+ re_empty_line = re.compile(r'^\s*$')
+ re_sequence_command = re.compile(r'^\s*(?P(reg_write|reg_read_check|reg_read))\s*\(\s*(?P[\w\.]+)\s*,\s*(?P(\w+|\d+|0x[0-9a-fA-F]+))\s*\)\s*;\s*(\/\/.*)*$')
+ re_sequence_command_read_write = re.compile(r'^\s*reg_(?P(write|read_check))\s*\(\s*(?P[\w\.]+)\s*,\s*(?P(\w+|\d+|0x[0-9a-fA-F]+))\s*\)\s*;\s*(\/\/.*)*$')
+ re_sequence_command_read_to_value = re.compile(r'^\s*reg_(?Pread)\s*\(\s*(?P[\w\.]+)\s*,\s*(?P(\w+|\d+|0x[0-9a-fA-F]+))\s*\)\s*;\s*(\/\/.*)*$')
+ re_sequence_command_event = re.compile(r'^\s*sync_(?P(notify|wait))\s*\(\s*(?P[\w\.]+)\s*,\s*(?P(\w+|\d+|0x[0-9a-fA-F]+))\s*\)\s*;\s*(\/\/.*)*$')
+ re_interrupt_handler_command = re.compile(r'^\s*intr_notify\s*\(\s*((?P\w+)\s*,\s*)?(?P\w+)\s*\)\s*;\s*(\/\/.*)*$')
+ #re_result_checker_command = re.compile(r'^\s*(?P(check_crc|check_file|check_nothing))\s*\(\s*(?P\w+)\s*,\s*(?P\w+)\s*,\s*(?P0x[0-9a-fA-F]+)\s*,\s*(?P0x[0-9a-fA-F]+)\s*,\s*(?P0x[0-9a-fA-F]+)\s*\)\s*;\s*(\/\/)*$')
+ re_result_checker_command = re.compile(r'^\s*(?P(check_crc|check_file|check_nothing))\s*\(\s*(?P\w+)\s*(,\s*(?P\w+)\s*,\s*(?P0x[0-9a-fA-F]+)\s*,\s*(?P(0x[0-9a-fA-F]+)|(\d+))\s*,\s*((?P0x[0-9a-fA-F]+)|"(?P[\w\.\/]+)")\s*)?\)\s*;\s*(\/\/.*)*$')
+ re_memory_model_command = re.compile(r'^\s*(?P(mem_load|mem_init))\s*\(\s*(?P\w+)\s*,\s*(?P0x[0-9a-fA-F]+)\s*,\s*("(?P[\w\.\/]+)"|(?P(0x[0-9a-fA-F]+)|(\d+)))\s*(,\s*(?P\w+)\s*)?\)\s*;\s*(\/\/.*)*$')
+ re_sequence_command_poll_reg = re.compile(r'^\s*(?Ppoll_reg_equal)\s*\(\s*(?P[\w\.]+)\s*,\s*(?P(\w+|\d+|0x[0-9a-fA-F]+))\s*\)\s*;\s*(\/\/.*)*$')
+
+ #mem_load ( sec_mem, 0x8000, "python/over/perl.dat");
+ #mem_init ( pri_mem, 0x2000, "python/over/perl.dat", RANDOM);
+ #mem_init ( sec_mem, 0x5000, 0x2000, ALL_ZERO);
+
+ def load_trace_file(self, test_dict):
+ self.trace_file_path = test_dict
+
+ #------------------------------------------------------------------------------------------------------
+ # | kind | block_name | reg_name | field_name | data | sync_id
+ # | WRITE | block_name | reg_name | N.A | data | N.A
+ # | READ_CHECK | block_name | reg_name | N.A | expected data | N.A
+ # | READ | block_name | reg_name | N.A | N.A | sync_id
+ # | NOTIFY | block_name | N.A | N.A | N.A | sync_id
+ # | WAIT | block_name | N.A | N.A | N.A | sync_id
+ # | POLL_REG_* | block_name | reg_name | N.A | expected data | N.A
+ # | POLL_FIELD_* | block_name | reg_name | field_name | expected data | N.A
+ #------------------------------------------------------------------------------------------------------
+ #--------------------------------------------------
+ # kind | interrupt_id | sync_id
+ # SINGLE_SHOT | N.A | sync_id
+ # MULTI_SHOT | sequence_id | sync_id
+ #--------------------------------------------------
+ #def gen_sequence_command(self):
+ # for pre_process_method in pre_process_method_list:
+ # pre_process_method()
+
+ def is_sequence_command(self, string):
+ pass
+
+ def do_parsing(self):
+ trace_dir = os.path.dirname(self.trace_file_path)
+ f_trace = open (self.trace_file_path, 'r')
+# f_seq_cmd = open ('trace_parser_cmd_sequence_command.log', 'w')
+# f_ic_cmd = open ('trace_parser_cmd_interrupt_controller_command.log', 'w')
+# f_rc_cmd = open ('trace_parser_cmd_result_checker_command.log', 'w')
+# f_mm_cmd = open ('trace_parser_cmd_memory_model_command.log', 'w')
+ f_c_cmd = open ('trace_parser_command.c', 'w')
+ f_c_cmd.write("#include \"trace_player_parser.h\"\n")
+ f_c_cmd.write("#include \"opendla.h\"\n\n")
+ f_c_cmd.write("void trace_parser_prepare_commands(void)\n")
+ f_c_cmd.write("{\n")
+ for line in f_trace:
+ print ("line:" + line.rstrip())
+ m = self.re_empty_line.match(line)
+ if m:
+ continue
+ m = self.re_comment.match(line)
+ if m:
+ continue
+ m = self.re_sequence_command_read_write.match(line)
+ if m:
+ print (m.groupdict())
+ #### kind block_name®_name field_name data sync_id
+#f_seq_cmd.write("%s %s NA %X NA\n" % ( m.group('kind').upper(), ' '.join(m.group('name').split('.')), int(m.group('value'),0) ) )
+ #f_c_cmd.write("\ttrace_player_thread_push_cmd_reg_%s(\"%s\", %s, 0x%X);\n" % ( m.group('kind'), m.group('name').split(".")[0][6:]+"_"+m.group('name')[-1], m.group('name').replace(".", "_"), int(m.group('value'),0) ) )
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_reg_%s(\"%s\", %s, 0x%X);\n" % ( m.group('kind'), m.group('name').split(".")[0], m.group('name').replace(".", "_"), int(m.group('value'),0) ) )
+ continue
+ m = self.re_sequence_command_read_to_value.match(line)
+ if m:
+ print (m.groupdict())
+ #### kind block_name®_name field_name data sync_id
+#f_seq_cmd.write("%s %s NA NA %s\n" % ( m.group('kind').upper(), ' '.join(m.group('name').split('.')), m.group('value') ) )
+ #f_c_cmd.write("\ttrace_player_thread_push_cmd_reg_%s(\"%s\", %s, \"%s\");\n" % ( m.group('kind'), m.group('name').split(".")[0][6:]+"_"+m.group('name')[-1], m.group('name').replace(".", "_"), m.group('value') ) )
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_reg_%s(\"%s\", %s, \"%s\");\n" % ( m.group('kind'), m.group('name').split(".")[0], m.group('name').replace(".", "_"), m.group('value') ) )
+ continue
+ m = self.re_sequence_command_event.match(line)
+ if m:
+ print (m.groupdict())
+ #### kind block_name reg_name field_name data sync_id
+#f_seq_cmd.write("%s %s NA NA 0 %s\n" % (m.group('kind').upper(), ' '.join(m.group('name').split('.')), m.group('value')))
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_sync_%s(\"%s\", \"%s\");\n" % ( m.group('kind'), m.group('name'), m.group('value') ) )
+ continue
+ m = self.re_interrupt_handler_command.match(line)
+ if m:
+ print (m.groupdict())
+ if m.group('intr_id') is not None:
+#f_ic_cmd.write("MULTI_SHOT %s %s\n" % (m.group('intr_id').upper(), m.group('sync_id')))
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_intr_notify(NVDLA_GLB_S_INTR_STATUS_0_%s_DONE_STATUS%s_FIELD, \"%s\");\n" % ( m.group('intr_id')[0:-2], m.group('intr_id')[-1], m.group('sync_id') ) )
+ else:
+#f_ic_cmd.write("SINGLE_SHOT NA %s\n" % (m.group('sync_id')))
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_intr_notify(0xFFFFFFFF, \"%s\");\n" % ( m.group('sync_id') ) )
+ continue
+ #--------------------------------------------------
+ # kind | sync_id | memory_type | base_addr | size | crc | file_path
+ # CHECK_NOTHING | sync_id | N.A | N.A | N.A | N.A | N.A
+ # CHECK_CRC | sync_id | memory_type | base_addr | size | crc | N.A
+ # CHECK_FILE | sync_id | memory_type | base_addr | size | N.A | file_path
+ #--------------------------------------------------
+ #check_crc(sync_id_0, pri_mem, 0x80100000, 0x1000, 0x33d91a71);
+ m = self.re_result_checker_command.match(line)
+ if m:
+ print (m.groupdict())
+ if "check_nothing" == m.group('kind').lower():
+#f_rc_cmd.write("%s %s NA 0 0 0 NA\n" % (m.group('kind').upper(), m.group('sync_id')))
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_%s(\"%s\");\n" % ( m.group('kind'), m.group('sync_id') ) )
+ elif "check_crc" == m.group('kind').lower():
+#f_rc_cmd.write("%s %s %s %X %X %X NA\n" % (m.group('kind').upper(), m.group('sync_id'), m.group('memory_type').upper(), int(m.group('base_addr'),0), int(m.group('size'),0), int(m.group('golden_crc'),0) ))
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_%s(\"%s\", \"%s\", 0x%X, 0x%X, 0x%X);\n" % ( m.group('kind'), m.group('sync_id'), m.group('memory_type').upper(), int(m.group('base_addr'),0), int(m.group('size'),0), int(m.group('golden_crc'),0) ) )
+ elif "check_file" == m.group('kind').lower():
+#f_rc_cmd.write("%s %s %s %X %X 0 %s\n" % (m.group('kind').upper(), m.group('sync_id'), m.group('memory_type').upper(), int(m.group('base_addr'),0), int(m.group('size'),0), os.path.join(trace_dir, m.group('golden_file_path')) ))
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_%s(\"%s\", \"%s\", 0x%X, 0x%X, \"%s\");\n" % ( m.group('kind'), m.group('sync_id'), m.group('memory_type').upper(), int(m.group('base_addr'),0), int(m.group('size'),0), os.path.join(trace_dir, m.group('golden_file_path') ) ) )
+ continue
+ m = self.re_memory_model_command.match(line)
+ if m:
+ print (m.groupdict())
+ # kind | memory_type | base_addr | size | pattern | file_path
+ if "mem_load" == m.group('kind').lower():
+#f_mm_cmd.write("%s %s %X 0 NA %s\n" % (m.group('kind').upper(), m.group('memory_type').upper(), int(m.group('base_addr'),0), os.path.join(trace_dir, m.group('file_path')) ))
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_%s(\"%s\", 0x%X, \"%s\");\n" % (m.group('kind'), m.group('memory_type').upper(), int(m.group('base_addr'),0), os.path.join(trace_dir, m.group('file_path')) ))
+ elif "mem_init" == m.group('kind').lower():
+ if m.group('size') is not None:
+ ## Initialized memory by pattern
+#f_mm_cmd.write("%s %s %X %X %s NA\n" % (m.group('kind').upper()+"_PATTERN", m.group('memory_type').upper(), int(m.group('base_addr'),0), int(m.group('size'),0), m.group('pattern') ))
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_%s(\"%s\", 0x%X, 0x%X, \"%s\");\n" % (m.group('kind')+"_pattern", m.group('memory_type').upper(), int(m.group('base_addr'),0), int(m.group('size'),0), m.group('pattern') ))
+ else:
+ ## Initialized memory by path
+#f_mm_cmd.write("%s %s %X NA %s %s\n" % (m.group('kind').upper()+"_FILE", m.group('memory_type').upper(), int(m.group('base_addr'),0), m.group('pattern'), os.path.join(trace_dir, m.group('file_path')) ))
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_%s(\"%s\", 0x%X, \"%s\", \"%s\");\n" % (m.group('kind')+"_file", m.group('memory_type').upper(), int(m.group('base_addr'),0), m.group('pattern'), os.path.join(trace_dir, m.group('file_path')) ))
+
+ continue
+ m = self.re_sequence_command_poll_reg.match(line)
+ if m:
+ print (m.groupdict())
+#f_seq_cmd.write("%s %s NA %X NA\n" % ( m.group('kind').upper(), ' '.join(m.group('name').split('.')), int(m.group('value'),0) ) )
+ f_c_cmd.write("\ttrace_player_thread_push_cmd_%s(\"%s\", %s, 0x%X);\n" % ( m.group('kind'), m.group('name').split(".")[0], m.group('name').replace(".", "_"), int(m.group('value'),0) ) )
+ continue
+ raise Exception("Unregconized line:\n%s" % line)
+#f_seq_cmd.close()
+#f_ic_cmd.close()
+#f_rc_cmd.close()
+#f_mm_cmd.close()
+ f_c_cmd.write("}\n")
+ f_c_cmd.close()
+ f_trace.close()
+
+if __name__ == '__main__':
+ parser = argparse.ArgumentParser(description=__DESCRIPTION__)
+ parser.add_argument('--file_path','-f', dest='file_path', required=True,
+ help='Specify trace file path')
+ config = vars( parser.parse_args() )
+ pprint (config)
+ trace_parser = TraceParser()
+ trace_parser.load_trace_file(config['file_path'])
+ trace_parser.do_parsing()
diff --git a/common/trace_player/src/trace_player.c b/common/trace_player/src/trace_player.c
new file mode 100644
index 0000000..7d58e1f
--- /dev/null
+++ b/common/trace_player/src/trace_player.c
@@ -0,0 +1,169 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player.c
+
+#include
+#include
+#include
+#include
+#include
+#include "trace_player.h"
+#include "trace_player_utils.h"
+#include "trace_player_cmd.h"
+#include "trace_player_thread.h"
+#include "trace_player_mem.h"
+#include "trace_player_intr.h"
+#include "trace_player_impl.h"
+
+typedef void (*PREPARE_CMD_FUNC)(void);
+
+#define TRACE_TEST_TIMEOUT_SEC 120
+
+static int stop_on_error = 1;
+static int wait_interval = 1;
+
+void trace_player_set_stop_on_error(int val)
+{
+ stop_on_error = val;
+}
+
+void trace_player_set_wait_interval(int val)
+{
+ wait_interval = val;
+}
+
+void trace_player_set_skip_mem_init(int val)
+{
+ trace_player_mem_set_skip_mem_init(val);
+}
+
+void trace_player_set_dump_mem_enable(int val)
+{
+ trace_player_mem_set_dump_mem_enable(val);
+}
+
+static uint64_t sys_sec = 0;
+int trace_player_run(const char *parser_output_lib)
+{
+ int rc = 0;
+
+ struct timeval tv;
+ gettimeofday(&tv, NULL);
+
+ sys_sec = tv.tv_sec;
+
+ /* open parser output library */
+ DEBUG_PRINT(("TRACE_PLAYER_RUN: open library %s\n", parser_output_lib));
+ void *handle = dlopen(parser_output_lib, RTLD_LAZY);
+ if (!handle) {
+ DEBUG_PRINT(("TRACE_PLAYER_RUN: ERROR! unable to open library %s\n", parser_output_lib));
+ exit(EXIT_FAILURE);
+ }
+
+ /* get prepare commands function from parser output library */
+ char *error;
+ PREPARE_CMD_FUNC prepare_cmd_func = NULL;
+ dlerror();
+ *(void **)(&prepare_cmd_func) = dlsym(handle, "trace_parser_prepare_commands");
+ if ((error = dlerror()) != NULL) {
+ DEBUG_PRINT(("TRACE_PLAYER_RUN: ERROR! %s\n", error));
+ exit(EXIT_FAILURE);
+ }
+
+ /* prepare commands */
+ DEBUG_PRINT(("TRACE_PLAYER_RUN: prepare commands\n"));
+ prepare_cmd_func();
+
+ /* run */
+ DEBUG_PRINT(("TRACE_PLAYER_RUN: run start, stop_on_error=%d, wait_interval=%d\n", stop_on_error, wait_interval));
+
+ trace_player_thread_node_t **p_head = trace_player_thread_list_get_head();
+
+ /* set interrupt sync id before run the trace test */
+ trace_player_thread_node_t *p_int_cfg_thread = *p_head;
+
+ /* update thread list head */
+ p_head = &(p_int_cfg_thread->next);
+
+ while (1)
+ {
+ if (trace_player_thread_run(&(p_int_cfg_thread->thread)) == TRACE_PLAYER_CMD_RESULT_NORUN)
+ {
+ DEBUG_PRINT(("Sync ID for interrupt configure DONE!\n"));
+ break;
+ }
+ }
+
+
+ while (1) {
+ int all_blocked = 1;
+ if (*p_head == NULL) {
+ DEBUG_PRINT(("TRACE_PLAYER_RUN: empty thread list!\n"));
+ break;
+ } else {
+ /* check and handle interrupt */
+ uint32_t pending_intr = trace_player_check_and_clear_pending_intr();
+ if (0 != trace_player_intr_check(pending_intr)) {
+ if (stop_on_error != 0) {
+ rc = 1;
+ goto out;
+ }
+ }
+ /* iterate the thread list */
+ trace_player_thread_node_t *node = *p_head;
+ while (node != NULL) {
+ trace_player_thread_node_t *tmp;
+ switch (trace_player_thread_run(&(node->thread))) {
+ case TRACE_PLAYER_CMD_RESULT_NORUN:
+ tmp = node->next;
+ trace_player_thread_list_remove_node(node);
+ node = tmp;
+ all_blocked = 0;
+ break;
+ case TRACE_PLAYER_CMD_RESULT_DONE:
+ node = node->next;
+ all_blocked = 0;
+ break;
+ case TRACE_PLAYER_CMD_RESULT_BLOCKED:
+ node = node->next;
+ break;
+ case TRACE_PLAYER_CMD_RESULT_ERROR:
+ all_blocked = 0;
+ if (stop_on_error != 0) {
+ rc = 1;
+ goto out;
+ } else {
+ node = node->next;
+ }
+ break;
+ default:
+ assert(0);
+ }
+ }
+ }
+ if (all_blocked) {
+ trace_player_wait(wait_interval);
+ }
+
+ uint64_t cur_sec = 0;
+ uint64_t det_sec = 0;
+ gettimeofday(&tv, NULL);
+ cur_sec = tv.tv_sec;
+ det_sec = cur_sec - sys_sec;
+ if (det_sec >= TRACE_TEST_TIMEOUT_SEC)
+ {
+ rc = 2;
+ goto out;
+ }
+ }
+
+out:
+ DEBUG_PRINT(("TRACE_PLAYER_RUN: run end, rc=%d\n", rc));
+ return rc;
+}
diff --git a/common/trace_player/src/trace_player_cmd.c b/common/trace_player/src/trace_player_cmd.c
new file mode 100644
index 0000000..151b1ee
--- /dev/null
+++ b/common/trace_player/src/trace_player_cmd.c
@@ -0,0 +1,292 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_cmd.c
+
+#include
+#include
+#include "trace_player_utils.h"
+#include "trace_player_cmd.h"
+#include "trace_player_impl.h"
+#include "trace_player_reg.h"
+#include "trace_player_mem.h"
+#include "trace_player_sync.h"
+#include "trace_player_intr.h"
+
+static void trace_player_cmd_free(trace_player_cmd_node_t **p_head)
+{
+ if (*p_head != NULL) {
+ switch ((*p_head)->cmd.type) {
+ case TRACE_PLAYER_CMD_READ:
+ free((*p_head)->cmd.reg_read_cmd.sync_id);
+ break;
+ case TRACE_PLAYER_CMD_MEM_LOAD:
+ free((*p_head)->cmd.mem_load_cmd.mem_type);
+ free((*p_head)->cmd.mem_load_cmd.file_path);
+ break;
+ case TRACE_PLAYER_CMD_MEM_INIT_PATTERN:
+ free((*p_head)->cmd.mem_init_pattern_cmd.mem_type);
+ free((*p_head)->cmd.mem_init_pattern_cmd.pattern);
+ break;
+ case TRACE_PLAYER_CMD_MEM_INIT_FILE:
+ free((*p_head)->cmd.mem_init_file_cmd.mem_type);
+ free((*p_head)->cmd.mem_init_file_cmd.file_path);
+ break;
+ case TRACE_PLAYER_CMD_INTR_NOTIFY:
+ free((*p_head)->cmd.intr_notify_cmd.sync_id);
+ break;
+ case TRACE_PLAYER_CMD_SYNC_WAIT:
+ free((*p_head)->cmd.sync_wait_cmd.sync_id);
+ break;
+ case TRACE_PLAYER_CMD_SYNC_NOTIFY:
+ free((*p_head)->cmd.sync_notify_cmd.sync_id);
+ break;
+ case TRACE_PLAYER_CMD_CHECK_CRC:
+ free((*p_head)->cmd.check_crc_cmd.sync_id);
+ free((*p_head)->cmd.check_crc_cmd.mem_type);
+ break;
+ case TRACE_PLAYER_CMD_CHECK_FILE:
+ free((*p_head)->cmd.check_file_cmd.sync_id);
+ free((*p_head)->cmd.check_file_cmd.mem_type);
+ free((*p_head)->cmd.check_file_cmd.file_path);
+ break;
+ case TRACE_PLAYER_CMD_CHECK_NOTHING:
+ free((*p_head)->cmd.check_nothing_cmd.sync_id);
+ break;
+ default:
+ break;
+ }
+ free(*p_head);
+ }
+}
+
+static void trace_player_cmd_list_push(trace_player_cmd_node_t **p_head, trace_player_cmd_node_t *node)
+{
+ if (*p_head == NULL) {
+ *p_head = node;
+ } else {
+ trace_player_cmd_node_t *tmp = (*p_head);
+ while (tmp->next != NULL) {
+ tmp = tmp->next;
+ }
+ tmp->next = node;
+ }
+ node->next = NULL;
+}
+
+trace_player_cmd_result_t trace_player_cmd_run(const trace_player_cmd_t *cmd)
+{
+ trace_player_cmd_result_t rc = TRACE_PLAYER_CMD_RESULT_DONE;
+ uint32_t val;
+
+ switch (cmd->type) {
+ case TRACE_PLAYER_CMD_WRITE:
+ reg_write(cmd->reg_write_cmd.offset, cmd->reg_write_cmd.value);
+ break;
+ case TRACE_PLAYER_CMD_READ:
+ reg_read(cmd->reg_read_cmd.offset, &val);
+ trace_player_sync_notify(cmd->reg_read_cmd.sync_id);
+ break;
+ case TRACE_PLAYER_CMD_READ_CHECK:
+ if (0 != trace_player_reg_read_check(cmd->reg_read_check_cmd.offset, cmd->reg_read_check_cmd.golden_val)) {
+ rc = TRACE_PLAYER_CMD_RESULT_ERROR;
+ }
+ break;
+ case TRACE_PLAYER_CMD_POLL_REG_EQUAL:
+ if (0 != trace_player_reg_poll_reg_equal(cmd->poll_reg_equal_cmd.offset, cmd->poll_reg_equal_cmd.expect_val)) {
+ rc = TRACE_PLAYER_CMD_RESULT_BLOCKED;
+ }
+ break;
+ case TRACE_PLAYER_CMD_MEM_LOAD:
+ if (0 != trace_player_mem_load(cmd->mem_load_cmd.mem_type, cmd->mem_load_cmd.base, cmd->mem_load_cmd.file_path)) {
+ rc = TRACE_PLAYER_CMD_RESULT_ERROR;
+ }
+ break;
+ case TRACE_PLAYER_CMD_MEM_INIT_PATTERN:
+ if (0 != trace_player_mem_init_pattern(cmd->mem_init_pattern_cmd.mem_type, cmd->mem_init_pattern_cmd.base, cmd->mem_init_pattern_cmd.size, cmd->mem_init_pattern_cmd.pattern)) {
+ rc = TRACE_PLAYER_CMD_RESULT_ERROR;
+ }
+ break;
+ case TRACE_PLAYER_CMD_MEM_INIT_FILE:
+ if (0 != trace_player_mem_init_file(cmd->mem_init_file_cmd.mem_type, cmd->mem_init_file_cmd.base, cmd->mem_init_file_cmd.file_path)) {
+ rc = TRACE_PLAYER_CMD_RESULT_ERROR;
+ }
+ break;
+ case TRACE_PLAYER_CMD_INTR_NOTIFY:
+ trace_player_push_expect_intr(cmd->intr_notify_cmd.intr_id, cmd->intr_notify_cmd.sync_id);
+ break;
+ case TRACE_PLAYER_CMD_SYNC_WAIT:
+ if (trace_player_sync_is_notified(cmd->sync_wait_cmd.sync_id) == 0) {
+ rc = TRACE_PLAYER_CMD_RESULT_BLOCKED;
+ }
+ break;
+ case TRACE_PLAYER_CMD_SYNC_NOTIFY:
+ trace_player_sync_notify(cmd->sync_notify_cmd.sync_id);
+ break;
+ case TRACE_PLAYER_CMD_CHECK_CRC:
+ if (trace_player_sync_is_notified(cmd->check_crc_cmd.sync_id) == 0) {
+ rc = TRACE_PLAYER_CMD_RESULT_BLOCKED;
+ } else if (0 != trace_player_mem_check_crc(cmd->check_crc_cmd.mem_type, cmd->check_crc_cmd.base, cmd->check_crc_cmd.size, cmd->check_crc_cmd.golden_crc)) {
+ rc = TRACE_PLAYER_CMD_RESULT_ERROR;
+ }
+ break;
+ case TRACE_PLAYER_CMD_CHECK_FILE:
+ if (trace_player_sync_is_notified(cmd->check_file_cmd.sync_id) == 0) {
+ rc = TRACE_PLAYER_CMD_RESULT_BLOCKED;
+ } else if (0 != trace_player_mem_check_file(cmd->check_file_cmd.mem_type, cmd->check_file_cmd.base, cmd->check_file_cmd.size, cmd->check_file_cmd.file_path)) {
+ rc = TRACE_PLAYER_CMD_RESULT_ERROR;
+ }
+ break;
+ case TRACE_PLAYER_CMD_CHECK_NOTHING:
+ if (trace_player_sync_is_notified(cmd->check_nothing_cmd.sync_id) == 0) {
+ rc = TRACE_PLAYER_CMD_RESULT_BLOCKED;
+ }
+ break;
+ default:
+ rc = TRACE_PLAYER_CMD_RESULT_ERROR;
+ break;
+ }
+
+ DEBUG_PRINT(("TRACE_PLAYER_CMD: run cmd type=%d, rc=%d\n", cmd->type, rc));
+
+ return rc;
+}
+
+void trace_player_cmd_list_pop(trace_player_cmd_node_t **p_head)
+{
+ if (*p_head != NULL) {
+ trace_player_cmd_node_t *tmp = (*p_head)->next;
+ trace_player_cmd_free(p_head);
+ *p_head = tmp;
+ }
+}
+
+void trace_player_cmd_list_push_cmd_reg_write(trace_player_cmd_node_t **p_head, uint64_t offset, uint32_t value)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_WRITE;
+ node->cmd.reg_write_cmd.offset = offset;
+ node->cmd.reg_write_cmd.value = value;
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_reg_read(trace_player_cmd_node_t **p_head, uint64_t offset, const char *sync_id)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_READ;
+ node->cmd.reg_read_cmd.offset = offset;
+ node->cmd.reg_read_cmd.sync_id = strdup(sync_id);
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_reg_read_check(trace_player_cmd_node_t **p_head, uint64_t offset, uint32_t golden_val)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_READ_CHECK;
+ node->cmd.reg_read_check_cmd.offset = offset;
+ node->cmd.reg_read_check_cmd.golden_val = golden_val;
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_poll_reg_equal(trace_player_cmd_node_t **p_head, uint64_t offset, uint32_t expect_val)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_POLL_REG_EQUAL;
+ node->cmd.poll_reg_equal_cmd.offset = offset;
+ node->cmd.poll_reg_equal_cmd.expect_val = expect_val;
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_mem_load(trace_player_cmd_node_t **p_head, const char* mem_type, uint64_t base, const char *file_path)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_MEM_LOAD;
+ node->cmd.mem_load_cmd.mem_type = strdup(mem_type);
+ node->cmd.mem_load_cmd.base = base;
+ node->cmd.mem_load_cmd.file_path = strdup(file_path);
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_mem_init_pattern(trace_player_cmd_node_t **p_head, const char* mem_type, uint64_t base, uint32_t size, const char *pattern)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_MEM_INIT_PATTERN;
+ node->cmd.mem_init_pattern_cmd.mem_type = strdup(mem_type);
+ node->cmd.mem_init_pattern_cmd.base = base;
+ node->cmd.mem_init_pattern_cmd.size = size;
+ node->cmd.mem_init_pattern_cmd.pattern = strdup(pattern);
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_mem_init_file(trace_player_cmd_node_t **p_head, const char* mem_type, uint64_t base, const char *file_path)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_MEM_INIT_FILE;
+ node->cmd.mem_init_file_cmd.mem_type = strdup(mem_type);
+ node->cmd.mem_init_file_cmd.base = base;
+ node->cmd.mem_init_file_cmd.file_path = strdup(file_path);
+ trace_player_cmd_list_push(p_head, node);
+}
+
+
+void trace_player_cmd_list_push_cmd_intr_notify(trace_player_cmd_node_t **p_head, uint32_t intr_id, const char *sync_id)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_INTR_NOTIFY;
+ node->cmd.intr_notify_cmd.intr_id = intr_id;
+ node->cmd.intr_notify_cmd.sync_id = strdup(sync_id);
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_sync_wait(trace_player_cmd_node_t **p_head, const char *sync_id)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_SYNC_WAIT;
+ node->cmd.sync_wait_cmd.sync_id = strdup(sync_id);
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_sync_notify(trace_player_cmd_node_t **p_head, const char *sync_id)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_SYNC_NOTIFY;
+ node->cmd.sync_notify_cmd.sync_id = strdup(sync_id);
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_check_crc(trace_player_cmd_node_t **p_head, const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, uint32_t golden_crc)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_CHECK_CRC;
+ node->cmd.check_crc_cmd.sync_id = strdup(sync_id);
+ node->cmd.check_crc_cmd.mem_type = strdup(mem_type);
+ node->cmd.check_crc_cmd.base = base;
+ node->cmd.check_crc_cmd.size = size;
+ node->cmd.check_crc_cmd.golden_crc = golden_crc;
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_check_file(trace_player_cmd_node_t **p_head, const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, const char *file_path)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_CHECK_FILE;
+ node->cmd.check_file_cmd.sync_id = strdup(sync_id);
+ node->cmd.check_file_cmd.mem_type = strdup(mem_type);
+ node->cmd.check_file_cmd.base = base;
+ node->cmd.check_file_cmd.size = size;
+ node->cmd.check_file_cmd.file_path = strdup(file_path);
+ trace_player_cmd_list_push(p_head, node);
+}
+
+void trace_player_cmd_list_push_cmd_check_nothing(trace_player_cmd_node_t **p_head, const char *sync_id)
+{
+ trace_player_cmd_node_t *node = malloc(sizeof(trace_player_cmd_node_t));
+ node->cmd.type = TRACE_PLAYER_CMD_CHECK_NOTHING;
+ node->cmd.check_nothing_cmd.sync_id = strdup(sync_id);
+ trace_player_cmd_list_push(p_head, node);
+}
diff --git a/common/trace_player/src/trace_player_intr.c b/common/trace_player/src/trace_player_intr.c
new file mode 100644
index 0000000..babecb4
--- /dev/null
+++ b/common/trace_player/src/trace_player_intr.c
@@ -0,0 +1,88 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_intr.c
+
+#include
+#include
+#include "trace_player_utils.h"
+#include "trace_player_intr.h"
+#include "trace_player_sync.h"
+
+static trace_player_intr_node_t *head = NULL;
+
+void trace_player_push_expect_intr(uint32_t intr_id, const char* sync_id)
+{
+ DEBUG_PRINT(("TRACE_PLAYER_INTR: push expect intr, id=0x%x, sync_id=%s\n", intr_id, sync_id));
+ trace_player_intr_node_t *new_node;
+ new_node = malloc(sizeof(trace_player_intr_node_t));
+ new_node->intr.intr_id = intr_id;
+ new_node->intr.sync_id = strdup(sync_id);
+ new_node->next = NULL;
+
+ if (head == NULL) {
+ head = new_node;
+ } else {
+ trace_player_intr_node_t *current = head;
+ while (current->next != NULL) {
+ current = current->next;
+ }
+ current->next = new_node;
+ }
+
+}
+
+int trace_player_intr_check(uint32_t intr_id)
+{
+ int rc = 0;
+
+ if (intr_id != 0 && head != NULL) {
+ while ((intr_id & head->intr.intr_id) == head->intr.intr_id) {
+ DEBUG_PRINT(("TRACE_PLAYER_INTR: get expected intr id=0x%x\n", head->intr.intr_id));
+ /* notify sync_id */
+ trace_player_sync_notify(head->intr.sync_id);
+ /* clear head intr */
+ intr_id = intr_id & (~(head->intr.intr_id));
+ /* pop intr list */
+ trace_player_intr_node_t *next_node = head->next;
+ free(head->intr.sync_id);
+ free(head);
+ head = next_node;
+ if (head == NULL)
+ break;
+ }
+ }
+ if (intr_id != 0 && head != NULL) {
+ trace_player_intr_node_t *p1 = head;
+ trace_player_intr_node_t *p2 = p1->next;
+ while (p2 != NULL) {
+ if ((intr_id & p2->intr.intr_id) == p2->intr.intr_id) {
+ DEBUG_PRINT(("TRACE_PLAYER_INTR: get expected intr id=0x%x\n", p2->intr.intr_id));
+ /* notify sync_id */
+ trace_player_sync_notify(p2->intr.sync_id);
+ /* clear p2 intr */
+ intr_id = intr_id & (~(p2->intr.intr_id));
+
+ p1->next = p2->next;
+
+ free(p2->intr.sync_id);
+ free(p2);
+ } else {
+ p1 = p1->next;
+ }
+ p2 = p1->next;
+ }
+ }
+
+ if (intr_id != 0) {
+ DEBUG_PRINT(("TRACE_PLAYER_INTR: WARNING! unexpect intr_id=0x%x\n", intr_id));
+ //rc = 1;
+ }
+
+ return rc;
+}
diff --git a/common/trace_player/src/trace_player_mem.c b/common/trace_player/src/trace_player_mem.c
new file mode 100644
index 0000000..be9832d
--- /dev/null
+++ b/common/trace_player/src/trace_player_mem.c
@@ -0,0 +1,659 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_mem.c
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "trace_player_mem.h"
+#include "trace_player_utils.h"
+#include "trace_player_impl.h"
+
+#define TRACE_PLAYER_MEM_CHAR2UINT64(array, index) \
+ (((uint64_t)(array[index])) \
+ | (((uint64_t)(array[index+1]))<<8) \
+ | (((uint64_t)(array[index+2]))<<16) \
+ | (((uint64_t)(array[index+3]))<<24) \
+ | (((uint64_t)(array[index+4]))<<32) \
+ | (((uint64_t)(array[index+5]))<<40) \
+ | (((uint64_t)(array[index+6]))<<48) \
+ | (((uint64_t)(array[index+7]))<<56))
+#define TRACE_PLAYER_MEM_CHAR2UINT32(array, index) \
+ (((uint32_t)(array[index])) \
+ | (((uint32_t)(array[index+1]))<<8) \
+ | (((uint32_t)(array[index+2]))<<16) \
+ | (((uint32_t)(array[index+3]))<<24))
+#define TRACE_PLAYER_MEM_CHAR2UINT16(array, index) \
+ (((uint16_t)(array[index])) \
+ | (((uint16_t)(array[index+1]))<<8))
+
+typedef enum {RANDOM, ALL_ZERO, ONES, X, AFIVE, FIVEA, ADDR} MEM_PATTERN_E;
+
+static int skip_mem_init = 0;
+static int dump_mem_enable = 1;
+static int mem_dump_index = 0;
+
+static int trace_player_mem_read64_check(const char *mem_type, uint64_t offset, uint64_t golden_val, uint64_t *rdata)
+{
+ int rc = 0;
+ mem_read64(mem_type, offset, rdata);
+ if (*rdata != golden_val) {
+ DEBUG_PRINT(("TRACE_PLAYER_MEM_READ64_CHECK: ERROR! addr=0x%lx, exp=0x%lx, act=0x%lx\n", offset, golden_val, *rdata));
+ rc = 1;
+ }
+ return rc;
+}
+
+static int trace_player_mem_read32_check(const char *mem_type, uint64_t offset, uint32_t golden_val, uint32_t *rdata)
+{
+ int rc = 0;
+ mem_read32(mem_type, offset, rdata);
+ if (*rdata != golden_val) {
+ DEBUG_PRINT(("TRACE_PLAYER_MEM_READ32_CHECK: ERROR! addr=0x%lx, exp=0x%x, act=0x%x\n", offset, golden_val, *rdata));
+ rc = 1;
+ }
+ return rc;
+}
+
+static int trace_player_mem_read16_check(const char *mem_type, uint64_t offset, uint16_t golden_val, uint16_t *rdata)
+{
+ int rc = 0;
+ mem_read16(mem_type, offset, rdata);
+ if (*rdata != golden_val) {
+ DEBUG_PRINT(("TRACE_PLAYER_MEM_READ16_CHECK: ERROR! addr=0x%lx, exp=0x%x, act=0x%x\n", offset, golden_val, *rdata));
+ rc = 1;
+ }
+ return rc;
+}
+
+static int trace_player_mem_read8_check(const char *mem_type, uint64_t offset, uint8_t golden_val, uint8_t *rdata)
+{
+ int rc = 0;
+ mem_read8(mem_type, offset, rdata);
+ if (*rdata != golden_val) {
+ DEBUG_PRINT(("TRACE_PLAYER_MEM_READ8_CHECK: ERROR! addr=0x%lx, exp=0x%x, act=0x%x\n", offset, golden_val, *rdata));
+ rc = 1;
+ }
+ return rc;
+}
+
+static int trace_player_mem_string_trim(char *str)
+{
+ char *tmp = str;
+ int len = strlen(tmp);
+
+ /* strip tail spaces, '}', and ',' */
+ while(isspace((unsigned char)tmp[len-1])
+ || tmp[len-1] == EOF
+ || tmp[len-1] == '\n'
+ || tmp[len-1] == ','
+ || tmp[len-1] == '}') {
+ tmp[--len] = 0;
+ }
+
+ /* strip front spaces and '{' */
+ while(*tmp && (isspace((unsigned char)*tmp) || *tmp == '{')) {
+ tmp++;
+ len--;
+ }
+
+ /* update the original pointer */
+ memmove(str, tmp, len+1);
+ return len;
+}
+
+static char* trace_player_mem_string_trimh_space(char *str)
+{
+ char *tmp = str;
+
+ while(*tmp && isspace((unsigned char)*tmp)) {
+ tmp++;
+ }
+
+ return tmp;
+}
+
+static int trace_player_mem_parse_line(char *line, uint64_t *p_offset, uint32_t *p_size, unsigned char **p_payload)
+{
+ int rc = 0;
+
+ char *offset_str;
+ char *size_str;
+ char *payload_str;
+ static long int last_size = 0;
+ char *tmp;
+
+ // skip comments
+ if (line[0] == '#') {
+ return 1;
+ }
+ // trim line
+ trace_player_mem_string_trim(line);
+ //DEBUG_PRINT(("MEM_PARSER: parse line after trim: %s\n", line));
+ // 1st section: offset
+ offset_str = strtok(line, ",");
+ if (offset_str == NULL) {
+ DEBUG_PRINT(("MEM_PARSE: WARNING! unable to extract offset!\n"));
+ return 1;
+ }
+ // 2nd section: size
+ size_str = strtok(NULL, ",");
+ if (size_str == NULL) {
+ DEBUG_PRINT(("MEM_PARSE: WARNING! unable to extract size!\n"));
+ return 1;
+ }
+ // 3rd section: payload
+ payload_str = strtok(NULL, ",");
+ if (payload_str == NULL) {
+ DEBUG_PRINT(("MEM_PARSE: WARNING! unable to extract payload!\n"));
+ return 1;
+ }
+
+ // parse offset
+ tmp = strtok(offset_str, ":");
+ if (strcmp(tmp, "offset") != 0) {
+ DEBUG_PRINT(("MEM_PARSE: ERROR! offset part (%s) must start with 'offset'!\n", tmp));
+ assert(0);
+ return 1;
+ }
+ tmp = strtok(NULL, ":");
+ *p_offset = strtol(tmp, NULL, 0);
+
+ // parse size
+ tmp = strtok(size_str, ":");
+ if (strcmp(trace_player_mem_string_trimh_space(tmp), "size") != 0) {
+ DEBUG_PRINT(("MEM_PARSE: ERROR! size part (%s) must start with 'size'!\n", tmp));
+ assert(0);
+ return 1;
+ }
+ tmp = strtok(NULL, ":");
+ *p_size = strtol(tmp, NULL, 0);
+
+ // parser payload
+ tmp = strtok(payload_str, ":");
+ if (strcmp(trace_player_mem_string_trimh_space(tmp), "payload") != 0) {
+ DEBUG_PRINT(("MEM_PARSE: ERROR! payload part (%s) must start with 'payload'!\n", tmp));
+ assert(0);
+ return 1;
+ }
+ tmp = strtok(NULL, ":");
+ if (*p_payload == NULL) {
+ *p_payload = malloc(*p_size);
+ last_size = *p_size;
+ } else if (*p_size > last_size) {
+ *p_payload = realloc(*p_payload, *p_size);
+ last_size = *p_size;
+ }
+ memset(*p_payload, 0, *p_size);
+ int i = 0;
+ char *payload_s = strtok(tmp, " ");
+ while (payload_s != NULL && i < *p_size) {
+ (*p_payload)[i++] = strtol(payload_s, NULL, 0);
+ payload_s = strtok(NULL, " ");
+ }
+
+ return rc;
+}
+
+static uint8_t trace_player_mem_gen_pattern8(MEM_PATTERN_E pattern_e, uint64_t addr)
+{
+ uint8_t data;
+ switch (pattern_e) {
+ case RANDOM:
+ data = rand()&0xFF;
+ break;
+ case ALL_ZERO:
+ data = 0;
+ break;
+ case ONES:
+ data = 0xFF;
+ break;
+ case AFIVE:
+ data = 0xA5;
+ break;
+ case FIVEA:
+ data = 0x5A;
+ break;
+ case ADDR:
+ data = addr&0xFF;
+ break;
+ default:
+ data = 0;
+ }
+ return data;
+}
+
+static uint16_t trace_player_mem_gen_pattern16(MEM_PATTERN_E pattern_e, uint64_t addr)
+{
+ uint16_t data;
+ switch (pattern_e) {
+ case RANDOM:
+ data = rand()&0xFFFF;
+ break;
+ case ALL_ZERO:
+ data = 0;
+ break;
+ case ONES:
+ data = 0xFFFF;
+ break;
+ case AFIVE:
+ data = 0xA5A5;
+ break;
+ case FIVEA:
+ data = 0x5A5A;
+ break;
+ case ADDR:
+ data = (((addr+1)&0xFF)<<8)+(addr&0xFF);
+ break;
+ default:
+ data = 0;
+ }
+ return data;
+}
+
+static uint32_t trace_player_mem_gen_pattern32(MEM_PATTERN_E pattern_e, uint64_t addr)
+{
+ uint32_t data;
+ switch (pattern_e) {
+ case RANDOM:
+ data = ((((uint32_t)rand())&0xFFFF)<<16)+(((uint32_t)rand())&0xFFFF);
+ break;
+ case ALL_ZERO:
+ data = 0;
+ break;
+ case ONES:
+ data = 0xFFFFFFFF;
+ break;
+ case AFIVE:
+ data = 0xA5A5A5A5;
+ break;
+ case FIVEA:
+ data = 0x5A5A5A5A;
+ break;
+ case ADDR:
+ data = (((addr+3)&0xFF)<<24)+(((addr+2)&0xFF)<<16)+(((addr+1)&0xFF)<<8)+(addr&0xFF);
+ break;
+ default:
+ data = 0;
+ }
+ return data;
+}
+
+static uint64_t trace_player_mem_gen_pattern64(MEM_PATTERN_E pattern_e, uint64_t addr)
+{
+ uint64_t data;
+ switch (pattern_e) {
+ case RANDOM:
+ data = ((((uint64_t)rand())&0xFFFF)<<48)+((((uint64_t)rand())&0xFFFF)<<32)+((((uint64_t)rand())&0xFFFF)<<16)+(((uint64_t)rand())&0xFFFF);
+ break;
+ case ALL_ZERO:
+ data = 0;
+ break;
+ case ONES:
+ data = 0xFFFFFFFFFFFFFFFF;
+ break;
+ case AFIVE:
+ data = 0xA5A5A5A5A5A5A5A5;
+ break;
+ case FIVEA:
+ data = 0x5A5A5A5A5A5A5A5A;
+ break;
+ case ADDR:
+ data = (((addr+7)&0xFF)<<56)+(((addr+6)&0xFF)<<48)+(((addr+5)&0xFF)<<40)+(((addr+4)&0xFF)<<32)+(((addr+3)&0xFF)<<24)+(((addr+2)&0xFF)<<16)+(((addr+1)&0xFF)<<8)+(addr&0xFF);
+ break;
+ default:
+ data = 0;
+ }
+ return data;
+}
+
+static uint32_t trace_player_mem_calc_crc(const char* mem_type, uint64_t base, uint32_t len)
+{
+ static const uint32_t crc32_table[] = {0x00000000,0x77073096,0xee0e612c,0x990951ba,
+ 0x076dc419,0x706af48f,0xe963a535,0x9e6495a3,
+ 0x0edb8832,0x79dcb8a4,0xe0d5e91e,0x97d2d988,
+ 0x09b64c2b,0x7eb17cbd,0xe7b82d07,0x90bf1d91,
+ 0x1db71064,0x6ab020f2,0xf3b97148,0x84be41de,
+ 0x1adad47d,0x6ddde4eb,0xf4d4b551,0x83d385c7,
+ 0x136c9856,0x646ba8c0,0xfd62f97a,0x8a65c9ec,
+ 0x14015c4f,0x63066cd9,0xfa0f3d63,0x8d080df5,
+ 0x3b6e20c8,0x4c69105e,0xd56041e4,0xa2677172,
+ 0x3c03e4d1,0x4b04d447,0xd20d85fd,0xa50ab56b,
+ 0x35b5a8fa,0x42b2986c,0xdbbbc9d6,0xacbcf940,
+ 0x32d86ce3,0x45df5c75,0xdcd60dcf,0xabd13d59,
+ 0x26d930ac,0x51de003a,0xc8d75180,0xbfd06116,
+ 0x21b4f4b5,0x56b3c423,0xcfba9599,0xb8bda50f,
+ 0x2802b89e,0x5f058808,0xc60cd9b2,0xb10be924,
+ 0x2f6f7c87,0x58684c11,0xc1611dab,0xb6662d3d,
+ 0x76dc4190,0x01db7106,0x98d220bc,0xefd5102a,
+ 0x71b18589,0x06b6b51f,0x9fbfe4a5,0xe8b8d433,
+ 0x7807c9a2,0x0f00f934,0x9609a88e,0xe10e9818,
+ 0x7f6a0dbb,0x086d3d2d,0x91646c97,0xe6635c01,
+ 0x6b6b51f4,0x1c6c6162,0x856530d8,0xf262004e,
+ 0x6c0695ed,0x1b01a57b,0x8208f4c1,0xf50fc457,
+ 0x65b0d9c6,0x12b7e950,0x8bbeb8ea,0xfcb9887c,
+ 0x62dd1ddf,0x15da2d49,0x8cd37cf3,0xfbd44c65,
+ 0x4db26158,0x3ab551ce,0xa3bc0074,0xd4bb30e2,
+ 0x4adfa541,0x3dd895d7,0xa4d1c46d,0xd3d6f4fb,
+ 0x4369e96a,0x346ed9fc,0xad678846,0xda60b8d0,
+ 0x44042d73,0x33031de5,0xaa0a4c5f,0xdd0d7cc9,
+ 0x5005713c,0x270241aa,0xbe0b1010,0xc90c2086,
+ 0x5768b525,0x206f85b3,0xb966d409,0xce61e49f,
+ 0x5edef90e,0x29d9c998,0xb0d09822,0xc7d7a8b4,
+ 0x59b33d17,0x2eb40d81,0xb7bd5c3b,0xc0ba6cad,
+ 0xedb88320,0x9abfb3b6,0x03b6e20c,0x74b1d29a,
+ 0xead54739,0x9dd277af,0x04db2615,0x73dc1683,
+ 0xe3630b12,0x94643b84,0x0d6d6a3e,0x7a6a5aa8,
+ 0xe40ecf0b,0x9309ff9d,0x0a00ae27,0x7d079eb1,
+ 0xf00f9344,0x8708a3d2,0x1e01f268,0x6906c2fe,
+ 0xf762575d,0x806567cb,0x196c3671,0x6e6b06e7,
+ 0xfed41b76,0x89d32be0,0x10da7a5a,0x67dd4acc,
+ 0xf9b9df6f,0x8ebeeff9,0x17b7be43,0x60b08ed5,
+ 0xd6d6a3e8,0xa1d1937e,0x38d8c2c4,0x4fdff252,
+ 0xd1bb67f1,0xa6bc5767,0x3fb506dd,0x48b2364b,
+ 0xd80d2bda,0xaf0a1b4c,0x36034af6,0x41047a60,
+ 0xdf60efc3,0xa867df55,0x316e8eef,0x4669be79,
+ 0xcb61b38c,0xbc66831a,0x256fd2a0,0x5268e236,
+ 0xcc0c7795,0xbb0b4703,0x220216b9,0x5505262f,
+ 0xc5ba3bbe,0xb2bd0b28,0x2bb45a92,0x5cb36a04,
+ 0xc2d7ffa7,0xb5d0cf31,0x2cd99e8b,0x5bdeae1d,
+ 0x9b64c2b0,0xec63f226,0x756aa39c,0x026d930a,
+ 0x9c0906a9,0xeb0e363f,0x72076785,0x05005713,
+ 0x95bf4a82,0xe2b87a14,0x7bb12bae,0x0cb61b38,
+ 0x92d28e9b,0xe5d5be0d,0x7cdcefb7,0x0bdbdf21,
+ 0x86d3d2d4,0xf1d4e242,0x68ddb3f8,0x1fda836e,
+ 0x81be16cd,0xf6b9265b,0x6fb077e1,0x18b74777,
+ 0x88085ae6,0xff0f6a70,0x66063bca,0x11010b5c,
+ 0x8f659eff,0xf862ae69,0x616bffd3,0x166ccf45,
+ 0xa00ae278,0xd70dd2ee,0x4e048354,0x3903b3c2,
+ 0xa7672661,0xd06016f7,0x4969474d,0x3e6e77db,
+ 0xaed16a4a,0xd9d65adc,0x40df0b66,0x37d83bf0,
+ 0xa9bcae53,0xdebb9ec5,0x47b2cf7f,0x30b5ffe9,
+ 0xbdbdf21c,0xcabac28a,0x53b39330,0x24b4a3a6,
+ 0xbad03605,0xcdd70693,0x54de5729,0x23d967bf,
+ 0xb3667a2e,0xc4614ab8,0x5d681b02,0x2a6f2b94,
+ 0xb40bbe37,0xc30c8ea1,0x5a05df1b,0x2d02ef8d};
+
+ DEBUG_PRINT(("TRACE_PLAYER_MEM_CALC_CRC: base=0x%lx, len=0x%x\n", base, len));
+ uint32_t result = 0xFFFFFFFF;
+
+ assert(base%4==0 && len%4==0);
+
+ FILE *wstream;
+ int dump_nbytes=0;
+ if (dump_mem_enable) {
+ char file_path[256];
+ sprintf(file_path, "trace_player_mem_dump_%d_base_0x%lx_size_0x%x.dat", mem_dump_index++, base, len);
+ wstream = fopen(file_path, "w");
+ }
+
+ uint32_t rdata;
+ int i;
+ while (len >= 4) {
+ mem_read32(mem_type, base, &rdata);
+ for (i=0; i<4; i++) {
+ uint8_t b = (rdata>>(i*8)) & 0xFF;
+ result = (result>>8) ^ crc32_table[(result&0xFF)^b];
+ }
+ if (dump_mem_enable) {
+ if (dump_nbytes == 0) {
+ fprintf(wstream, "{offset:0x%lx, size:32, payload:", base);
+ }
+ fprintf(wstream, "0x%x 0x%x 0x%x 0x%x", rdata&0xFF, (rdata>>8)&0xFF, (rdata>>16)&0xFF, (rdata>>24)&0xFF);
+ dump_nbytes += 4;
+ if (dump_nbytes == 32) {
+ fprintf(wstream, "},\n");
+ dump_nbytes = 0;
+ } else {
+ fprintf(wstream, " ");
+ }
+ }
+ base += 4;
+ len -= 4;
+ }
+
+ if (dump_mem_enable) {
+ fclose(wstream);
+ }
+
+ return ~result;
+}
+
+void trace_player_mem_set_skip_mem_init(int val)
+{
+ skip_mem_init = val;
+}
+
+void trace_player_mem_set_dump_mem_enable(int val)
+{
+ dump_mem_enable = val;
+}
+
+int trace_player_mem_load(const char *mem_type, uint64_t base, const char *file_path)
+{
+ DEBUG_PRINT(("MEM_LOAD: mem_type=%s, base=0x%lx, file_path=%s\n", mem_type, base, file_path));
+ int rc = 0;
+ FILE *stream;
+ stream = fopen(file_path, "r");
+
+ if (stream == NULL) {
+ DEBUG_PRINT(("MEM_LOAD: ERROR! open file %s failed!\n", file_path));
+ assert(0);
+ return 1;
+ }
+
+ int max_len = 256;
+ char buf[max_len];
+ uint64_t offset;
+ uint32_t size;
+ unsigned char *payload = NULL;
+ while(fgets(buf, max_len, stream)) {
+ char *line = strdup(buf);
+ // parse one line to get payload
+ //DEBUG_PRINT(("MEM_LOAD: parser line: %s\n", line));
+ if (0 != trace_player_mem_parse_line(line, &offset, &size, &payload)) {
+ continue;
+ }
+ // write payload to memory
+ offset+=base;
+ int num_written = 0;
+ while (num_written < size) {
+ if ((size-num_written >= 8) && ((offset+num_written)%8==0)) {
+ mem_write64(mem_type, offset+num_written, TRACE_PLAYER_MEM_CHAR2UINT64(payload, num_written));
+ num_written += 8;
+ } else if ((size-num_written >= 4) && ((offset+num_written))%4==0) {
+ mem_write32(mem_type, offset+num_written, TRACE_PLAYER_MEM_CHAR2UINT32(payload, num_written));
+ num_written += 4;
+ } else if ((size-num_written >= 2) && ((offset+num_written))%2==0) {
+ mem_write16(mem_type, offset+num_written, TRACE_PLAYER_MEM_CHAR2UINT16(payload, num_written));
+ num_written += 2;
+ } else {
+ mem_write8(mem_type, offset+num_written, payload[num_written]);
+ num_written += 1;
+ }
+ }
+ free(line);
+ }
+ if (payload) {
+ free(payload);
+ }
+ fclose(stream);
+
+ return rc;
+}
+
+int trace_player_mem_init_pattern(const char *mem_type, uint64_t base, uint32_t size, const char *pattern)
+{
+ DEBUG_PRINT(("MEM_INIT_PATTERN: mem_type=%s, base=0x%lx, size=0x%x, pattern=%s\n", mem_type, base, size, pattern));
+
+ if (skip_mem_init) {
+ DEBUG_PRINT(("MEM_INIT_PATTERN: WARNING! skip mem_init_pattern!\n"));
+ return 0;
+ }
+
+ MEM_PATTERN_E pattern_e;
+ if (strcmp(pattern, "RANDOM") == 0) {
+ pattern_e = RANDOM;
+ } else if (strcmp(pattern, "ALL_ZERO") == 0) {
+ pattern_e = ALL_ZERO;
+ } else if (strcmp(pattern, "ONES") == 0) {
+ pattern_e = ONES;
+ } else if (strcmp(pattern, "X") == 0) {
+ pattern_e = X;
+ } else if (strcmp(pattern, "AFIVE") == 0) {
+ pattern_e = AFIVE;
+ } else if (strcmp(pattern, "FIVEA") == 0) {
+ pattern_e = FIVEA;
+ } else if (strcmp(pattern, "ADDR") == 0) {
+ pattern_e = ADDR;
+ }
+
+ // write payload to memory
+ int num_written = 0;
+ while (num_written < size) {
+ if ((size-num_written >= 8) && ((base+num_written)%8==0)) {
+ mem_write64(mem_type, base+num_written, trace_player_mem_gen_pattern64(pattern_e, base+num_written));
+ num_written += 8;
+ } else if ((size-num_written >= 4) && ((base+num_written))%4==0) {
+ mem_write32(mem_type, base+num_written, trace_player_mem_gen_pattern32(pattern_e, base+num_written));
+ num_written += 4;
+ } else if ((size-num_written >= 2) && ((base+num_written))%2==0) {
+ mem_write16(mem_type, base+num_written, trace_player_mem_gen_pattern16(pattern_e, base+num_written));
+ num_written += 2;
+ } else {
+ mem_write8(mem_type, base+num_written, trace_player_mem_gen_pattern8(pattern_e, base+num_written));
+ num_written += 1;
+ }
+ }
+ return 0;
+}
+
+int trace_player_mem_init_file(const char *mem_type, uint64_t base, const char *file_path)
+{
+ DEBUG_PRINT(("MEM_INIT_FILE: mem_type=%s, base=0x%lx, file_path=%s\n", mem_type, base, file_path));
+ return trace_player_mem_load(mem_type, base, file_path);
+}
+
+int trace_player_mem_check_crc(const char *mem_type, uint64_t base, uint32_t size, uint32_t golden_crc)
+{
+ DEBUG_PRINT(("TRACE_PLAYER_MEM_CHECK_CRC: mem_type=%s, base=0x%lx, size=%d, golden_crc=0x%x\n", mem_type, base, size, golden_crc));
+ int rc = 0;
+
+ uint32_t crc_calc = trace_player_mem_calc_crc(mem_type, base, size);
+ if (crc_calc != golden_crc) {
+ DEBUG_PRINT(("TRACE_PLAYER_MEM_CHECK_CRC: ERROR! expect_crc=0x%x, act_crc=0x%x\n", golden_crc, crc_calc));
+ rc = 1;
+ } else {
+ DEBUG_PRINT(("TRACE_PLAYER_MEM_CHECK_CRC: PASS! expect_crc=0x%x, act_crc=0x%x\n", golden_crc, crc_calc));
+ }
+
+ return rc;
+}
+
+int trace_player_mem_check_file(const char *mem_type, uint64_t base, uint32_t size, const char *file_path)
+{
+ DEBUG_PRINT(("CHECK_FILE: mem_type=%s, base=0x%lx, size=%d, file_path=%s\n", mem_type, base, size, file_path));
+ int rc = 0;
+ FILE *stream;
+ stream = fopen(file_path, "r");
+
+ if (stream == NULL) {
+ DEBUG_PRINT(("CHECK_FILE: ERROR! open file %s failed!\n", file_path));
+ assert(0);
+ return 1;
+ }
+
+ FILE *wstream;
+ if (dump_mem_enable) {
+ char file_path[256];
+ sprintf(file_path, "trace_player_mem_dump_%d_base_0x%lx_size_0x%x.dat", mem_dump_index++, base, size);
+ wstream = fopen(file_path, "w");
+ }
+
+ int max_len = 256;
+ char buf[max_len];
+ uint64_t offset;
+ uint32_t size_f;
+ unsigned char *payload = NULL;
+ int num_compared = 0;
+ while(fgets(buf, max_len, stream)) {
+ char *line = strdup(buf);
+ // parse one line to get payload
+ if (0 != trace_player_mem_parse_line(line, &offset, &size_f, &payload)) {
+ continue;
+ }
+ //dump mem head
+ if (dump_mem_enable) {
+ fprintf(wstream, "{offset:0x%lx, size:%d, payload:", offset, size_f);
+ }
+ // compare memory
+ offset+=base;
+ int num_read = 0;
+ while (num_read < size_f) {
+ if ((size_f-num_read >= 8) && ((offset+num_read)%8==0)) {
+ uint64_t rdata;
+ if (0 != trace_player_mem_read64_check(mem_type, offset+num_read, TRACE_PLAYER_MEM_CHAR2UINT64(payload, num_read), &rdata)) {
+ rc = 1;
+ }
+ num_read += 8;
+ if (dump_mem_enable) {
+ fprintf(wstream, "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", (uint8_t)(rdata&0xFF), (uint8_t)((rdata>>8)&0xFF), (uint8_t)((rdata>>16)&0xFF), (uint8_t)((rdata>>24)&0xFF), (uint8_t)((rdata>>32)&0xFF), (uint8_t)((rdata>>40)&0xFF), (uint8_t)((rdata>>48)&0xFF), (uint8_t)((rdata>>56)&0xFF));
+ }
+ } else if ((size_f-num_read >= 4) && ((offset+num_read)%4==0)) {
+ uint32_t rdata;
+ if (0 != trace_player_mem_read32_check(mem_type, offset+num_read, TRACE_PLAYER_MEM_CHAR2UINT32(payload, num_read), &rdata)) {
+ rc = 1;
+ }
+ num_read += 4;
+ if (dump_mem_enable) {
+ fprintf(wstream, "0x%x 0x%x 0x%x 0x%x", rdata&0xFF, (rdata>>8)&0xFF, (rdata>>16)&0xFF, (rdata>>24)&0xFF);
+ }
+ } else if ((size_f-num_read >= 2) && ((offset+num_read)%2==0)) {
+ uint16_t rdata;
+ if (0 != trace_player_mem_read16_check(mem_type, offset+num_read, TRACE_PLAYER_MEM_CHAR2UINT16(payload, num_read), &rdata)) {
+ rc = 1;
+ }
+ num_read += 2;
+ if (dump_mem_enable) {
+ fprintf(wstream, "0x%x 0x%x", rdata&0xFF, (rdata>>8)&0xFF);
+ }
+ } else {
+ uint8_t rdata;
+ if (0 != trace_player_mem_read8_check(mem_type, offset+num_read, payload[num_read], &rdata)) {
+ rc = 1;
+ }
+ num_read += 1;
+ if (dump_mem_enable) {
+ fprintf(wstream, "0x%x", rdata&0xFF);
+ }
+ }
+ if (dump_mem_enable) {
+ if (num_read == size_f) {
+ fprintf(wstream, "},\n");
+ } else {
+ fprintf(wstream, " ");
+ }
+ }
+ }
+ num_compared+=size_f;
+ free(line);
+ }
+ if (payload) {
+ free(payload);
+ }
+ fclose(stream);
+ if (dump_mem_enable) {
+ fclose(wstream);
+ }
+
+ return rc;
+}
diff --git a/common/trace_player/src/trace_player_reg.c b/common/trace_player/src/trace_player_reg.c
new file mode 100644
index 0000000..8029382
--- /dev/null
+++ b/common/trace_player/src/trace_player_reg.c
@@ -0,0 +1,36 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_reg.c
+
+#include "trace_player_reg.h"
+#include "trace_player_utils.h"
+#include "trace_player_impl.h"
+
+int trace_player_reg_read_check(uint64_t offset, uint32_t golden_val)
+{
+ int rc = 0;
+ uint32_t val;
+ reg_read(offset, &val);
+ if (val != golden_val) {
+ DEBUG_PRINT(("TRACE_PLAYER_REG_READ_CHECK: ERROR! addr=0x%lx, exp=0x%x, act=0x%x\n", offset, golden_val, val));
+ rc = 1;
+ }
+ return rc;
+}
+
+int trace_player_reg_poll_reg_equal(uint64_t offset, uint32_t expect_val)
+{
+ int rc = 0;
+ uint32_t val;
+ reg_read(offset, &val);
+ if (val != expect_val) {
+ rc = 1;
+ }
+ return rc;
+}
diff --git a/common/trace_player/src/trace_player_sync.c b/common/trace_player/src/trace_player_sync.c
new file mode 100644
index 0000000..2ec79c5
--- /dev/null
+++ b/common/trace_player/src/trace_player_sync.c
@@ -0,0 +1,57 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_sync.c
+
+#include
+#include
+#include "trace_player_utils.h"
+#include "trace_player_sync.h"
+
+static trace_player_sync_node_t *head = NULL;
+
+static trace_player_sync_node_t* trace_player_sync_find_or_create_node(const char *sync_id)
+{
+ trace_player_sync_node_t *node = head;
+ trace_player_sync_node_t *prev = NULL;
+
+ while (node != NULL) {
+ if (strcmp(sync_id, node->sync.sync_id) == 0) {
+ break;
+ }
+ prev = node;
+ node = node->next;
+ }
+
+ if (node == NULL) {
+ node = malloc(sizeof(trace_player_sync_node_t));
+ node->sync.sync_id = strdup(sync_id);
+ node->sync.notified = 0;
+ node->next = NULL;
+ if (prev != NULL) {
+ prev->next = node;
+ }
+ if (head == NULL) {
+ head = node;
+ }
+ }
+
+ return node;
+}
+
+void trace_player_sync_notify(const char *sync_id)
+{
+ trace_player_sync_node_t* node = trace_player_sync_find_or_create_node(sync_id);
+ node->sync.notified = 1;
+}
+
+int trace_player_sync_is_notified(const char *sync_id)
+{
+ trace_player_sync_node_t* node = trace_player_sync_find_or_create_node(sync_id);
+ return node->sync.notified;
+}
diff --git a/common/trace_player/src/trace_player_thread.c b/common/trace_player/src/trace_player_thread.c
new file mode 100644
index 0000000..b79cd9a
--- /dev/null
+++ b/common/trace_player/src/trace_player_thread.c
@@ -0,0 +1,178 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_thread.c
+
+#include
+#include
+#include
+#include "trace_player_utils.h"
+#include "trace_player_thread.h"
+#include "trace_player_impl.h"
+
+static trace_player_thread_node_t *head = NULL;
+
+static trace_player_thread_node_t* trace_player_thread_list_find_or_create_node(const char* name)
+{
+ trace_player_thread_node_t *node = head;
+ trace_player_thread_node_t *prev = NULL;
+
+ while (node != NULL) {
+ if (strcmp(name, node->thread.name) == 0) {
+ break;
+ }
+ prev = node;
+ node = node->next;
+ }
+
+ if (node == NULL) {
+ node = malloc(sizeof(trace_player_thread_node_t));
+ node->thread.name = strdup(name);
+ node->thread.cmd_head = NULL;
+ node->next = NULL;
+ if (prev != NULL) {
+ prev->next = node;
+ }
+ if (head == NULL) {
+ trace_player_thread_node_t *int_cfg_node;
+ int_cfg_node = malloc(sizeof(trace_player_thread_node_t));
+ int_cfg_node->thread.name = strdup("INT_CFG");
+ int_cfg_node->thread.cmd_head = NULL;
+ int_cfg_node->next = node;
+ head = int_cfg_node;
+ DEBUG_PRINT(("TRACE_PLAYER_THREAD: create thread %s\n", "INT_CFG"));
+ }
+ DEBUG_PRINT(("TRACE_PLAYER_THREAD: create thread %s\n", name));
+ }
+
+ return node;
+}
+
+static trace_player_thread_node_t* trace_player_thread_get_node(const char* thread_name)
+{
+ static trace_player_thread_node_t *thread_node_cache = NULL;
+ if (thread_node_cache == NULL || strcmp(thread_name, thread_node_cache->thread.name) != 0) {
+ thread_node_cache = trace_player_thread_list_find_or_create_node(thread_name);
+ }
+ return thread_node_cache;
+}
+
+trace_player_thread_node_t** trace_player_thread_list_get_head(void)
+{
+ return &head;
+}
+
+trace_player_cmd_result_t trace_player_thread_run(trace_player_thread_t *thread)
+{
+ trace_player_cmd_result_t rc = TRACE_PLAYER_CMD_RESULT_NORUN;
+ if (thread->cmd_head != NULL) {
+ rc = trace_player_cmd_run(&(thread->cmd_head->cmd));
+ if (rc != TRACE_PLAYER_CMD_RESULT_BLOCKED) {
+ trace_player_cmd_list_pop(&(thread->cmd_head));
+ }
+ }
+ DEBUG_PRINT(("TRACE_PLAYER_THREAD: run thread %s, result=%d\n", thread->name, rc));
+ return rc;
+}
+
+void trace_player_thread_list_remove_node(trace_player_thread_node_t *rnode)
+{
+ if (rnode == head) {
+ head = head->next;
+ } else {
+ trace_player_thread_node_t *node = head;
+ while (node != NULL) {
+ if (rnode == node->next) {
+ node->next = rnode->next;
+ break;
+ }
+ node = node->next;
+ }
+ }
+
+ free(rnode->thread.name);
+ free(rnode);
+}
+
+void trace_player_thread_push_cmd_reg_write(const char* thread_name, uint64_t offset, uint32_t value)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node(thread_name);
+ trace_player_cmd_list_push_cmd_reg_write(&(node->thread.cmd_head), offset, value);
+}
+
+void trace_player_thread_push_cmd_reg_read(const char* thread_name, uint64_t offset, const char *sync_id)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node(thread_name);
+ trace_player_cmd_list_push_cmd_reg_read(&(node->thread.cmd_head), offset, sync_id);
+}
+
+void trace_player_thread_push_cmd_reg_read_check(const char* thread_name, uint64_t offset, uint32_t golden_val)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node(thread_name);
+ trace_player_cmd_list_push_cmd_reg_read_check(&(node->thread.cmd_head), offset, golden_val);
+}
+
+void trace_player_thread_push_cmd_poll_reg_equal(const char* thread_name, uint64_t offset, uint32_t expect_val)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node(thread_name);
+ trace_player_cmd_list_push_cmd_poll_reg_equal(&(node->thread.cmd_head), offset, expect_val);
+}
+
+void trace_player_thread_push_cmd_mem_load(const char* mem_type, uint64_t base, const char *file_path)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node("UTILS");
+ trace_player_cmd_list_push_cmd_mem_load(&(node->thread.cmd_head), mem_type, base, file_path);
+}
+
+void trace_player_thread_push_cmd_mem_init_pattern(const char* mem_type, uint64_t base, uint32_t size, const char *pattern)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node("UTILS");
+ trace_player_cmd_list_push_cmd_mem_init_pattern(&(node->thread.cmd_head), mem_type, base, size, pattern);
+}
+
+void trace_player_thread_push_cmd_mem_init_file(const char* mem_type, uint64_t base, const char *file_path)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node("UTILS");
+ trace_player_cmd_list_push_cmd_mem_init_file(&(node->thread.cmd_head), mem_type, base, file_path);
+}
+
+void trace_player_thread_push_cmd_intr_notify(uint32_t intr_id, const char *sync_id)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node("INT_CFG");
+ trace_player_cmd_list_push_cmd_intr_notify(&(node->thread.cmd_head), intr_id, sync_id);
+}
+
+void trace_player_thread_push_cmd_sync_wait(const char* thread_name, const char *sync_id)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node(thread_name);
+ trace_player_cmd_list_push_cmd_sync_wait(&(node->thread.cmd_head), sync_id);
+}
+
+void trace_player_thread_push_cmd_sync_notify(const char* thread_name, const char *sync_id)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node(thread_name);
+ trace_player_cmd_list_push_cmd_sync_notify(&(node->thread.cmd_head), sync_id);
+}
+
+void trace_player_thread_push_cmd_check_crc(const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, uint32_t golden_crc)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node("UTILS");
+ trace_player_cmd_list_push_cmd_check_crc(&(node->thread.cmd_head), sync_id, mem_type, base, size, golden_crc);
+}
+
+void trace_player_thread_push_cmd_check_file(const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, const char *file_path)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node("UTILS");
+ trace_player_cmd_list_push_cmd_check_file(&(node->thread.cmd_head), sync_id, mem_type, base, size, file_path);
+}
+
+void trace_player_thread_push_cmd_check_nothing(const char *sync_id)
+{
+ trace_player_thread_node_t *node = trace_player_thread_get_node("UTILS");
+ trace_player_cmd_list_push_cmd_check_nothing(&(node->thread.cmd_head), sync_id);
+}
diff --git a/common/trace_player/test/test_trace/test_trace.cfg b/common/trace_player/test/test_trace/test_trace.cfg
new file mode 100644
index 0000000..7798575
--- /dev/null
+++ b/common/trace_player/test/test_trace/test_trace.cfg
@@ -0,0 +1,18 @@
+mem_load(pri_mem, 0xC0000000, "test_trace_input.dat");
+reg_write(NVDLA_BDMA.CFG_SRC_ADDR_HIGH_0, 0);
+reg_write(NVDLA_BDMA.CFG_SRC_ADDR_LOW_0, 0xC0000000);
+reg_write(NVDLA_BDMA.CFG_DST_ADDR_HIGH_0, 0);
+reg_write(NVDLA_BDMA.CFG_DST_ADDR_LOW_0 , 0xC0000000);
+reg_write(NVDLA_BDMA.CFG_DST_SURF_0, 0x800);
+reg_write(NVDLA_BDMA.CFG_DST_LINE_0, 0x100);
+reg_write(NVDLA_BDMA.CFG_SRC_SURF_0, 0x800);
+reg_write(NVDLA_BDMA.CFG_SRC_LINE_0, 0x100);
+reg_write(NVDLA_BDMA.CFG_SURF_REPEAT_0, 0);
+reg_write(NVDLA_BDMA.CFG_LINE_REPEAT_0, 7);
+reg_write(NVDLA_BDMA.CFG_LINE_0, 7);
+reg_write(NVDLA_BDMA.CFG_CMD_0, 3);
+reg_write(NVDLA_BDMA.CFG_OP_0, 1);
+reg_write(NVDLA_BDMA.CFG_LAUNCH0_0, 1);
+intr_notify(BDMA_0, BDMA_0_BDMA_0_interrupt);
+check_crc(BDMA_0_BDMA_0_interrupt, pri_mem, 0xC00017C0, 0x800, 0xf1e8ba9e);
+check_file(BDMA_0_BDMA_0_interrupt, pri_mem, 0xC00017C0, 0x800, "test_trace_output.dat");
diff --git a/common/trace_player/test/test_trace/test_trace_input.dat b/common/trace_player/test/test_trace/test_trace_input.dat
new file mode 100644
index 0000000..938100e
--- /dev/null
+++ b/common/trace_player/test/test_trace/test_trace_input.dat
@@ -0,0 +1,64 @@
+{offset:0x0, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x20, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x40, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x60, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x80, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0xa0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0xc0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0xe0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x100, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x120, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x140, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x160, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x180, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x1a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x1c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x1e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x200, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x220, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x240, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x260, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x280, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x2a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x2c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x2e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x300, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x320, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x340, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x360, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x380, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x3a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x3c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x3e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x400, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x420, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x440, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x460, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x480, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x4a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x4c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x4e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x500, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x520, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x540, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x560, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x580, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x5a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x5c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x5e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x600, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x620, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
+{offset:0x640, size:32, payload:0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F},
+{offset:0x660, size:32, payload:0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F},
+{offset:0x680, size:32, payload:0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F},
+{offset:0x6a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x6c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x6e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
+{offset:0x700, size:32, payload:0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F},
+{offset:0x720, size:32, payload:0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F},
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+{offset:0x7a0, size:32, payload:0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF},
+{offset:0x7c0, size:32, payload:0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF},
+{offset:0x7e0, size:32, payload:0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF},
\ No newline at end of file
diff --git a/common/trace_player/test/test_trace/test_trace_output.dat b/common/trace_player/test/test_trace/test_trace_output.dat
new file mode 100644
index 0000000..3c71574
--- /dev/null
+++ b/common/trace_player/test/test_trace/test_trace_output.dat
@@ -0,0 +1,64 @@
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+{offset:0xc0001f04, size:32, payload:0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0},
+{offset:0xc0001f24, size:32, payload:0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0},
+{offset:0xc0001f44, size:32, payload:0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0},
+{offset:0xc0001f64, size:32, payload:0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0},
+{offset:0xc0001f84, size:32, payload:0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0},
+{offset:0xc0001fa4, size:32, payload:0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0},
diff --git a/common/trace_player/test/trace_player_test.c b/common/trace_player/test/trace_player_test.c
new file mode 100644
index 0000000..2ef6b28
--- /dev/null
+++ b/common/trace_player/test/trace_player_test.c
@@ -0,0 +1,22 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_test.c
+
+#include "trace_player_utils.h"
+#include "trace_player.h"
+
+int main()
+{
+ int rc = 0;
+ DEBUG_PRINT(("TEST: START\n"));
+ rc = trace_player_run("./libtrace_parser_command.so");
+ DEBUG_PRINT(("TEST: END, rc=%d\n", rc));
+
+ return rc;
+}
diff --git a/common/trace_player/test/trace_player_test_impl.c b/common/trace_player/test/trace_player_test_impl.c
new file mode 100644
index 0000000..77c13cd
--- /dev/null
+++ b/common/trace_player/test/trace_player_test_impl.c
@@ -0,0 +1,86 @@
+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+
+// File Name: trace_player_test_impl.c
+
+#include
+#include
+
+void reg_write(uint64_t offset, uint32_t val)
+{
+ printf("REG_WRITE: offset=0x%lx, val=0x%x\n", offset, val);
+}
+
+void reg_read(uint64_t offset, uint32_t *val)
+{
+ printf("REG_READ: offset=0x%lx, val=0x%x\n", offset, 0);
+}
+
+void mem_write64(const char *mem_type, uint64_t offset, uint64_t val)
+{
+ printf("MEM_WRITE64: mem_type=%s, offset=0x%lx, val=0x%lx\n", mem_type, offset, val);
+}
+
+void mem_write32(const char *mem_type, uint64_t offset, uint32_t val)
+{
+ printf("MEM_WRITE32: mem_type=%s, offset=0x%lx, val=0x%x\n", mem_type, offset, val);
+}
+
+void mem_write16(const char *mem_type, uint64_t offset, uint16_t val)
+{
+ printf("MEM_WRITE16: mem_type=%s, offset=0x%lx, val=0x%x\n", mem_type, offset, val);
+}
+
+void mem_write8(const char *mem_type, uint64_t offset, uint8_t val)
+{
+ printf("MEM_WRITE8: mem_type=%s, offset=0x%lx, val=0x%x\n", mem_type, offset, val);
+}
+
+void mem_read64(const char *mem_type, uint64_t offset, uint64_t *val)
+{
+ printf("MEM_read64: mem_type=%s, offset=0x%lx\n", mem_type, offset);
+ *val = 0;
+}
+
+void mem_read32(const char *mem_type, uint64_t offset, uint32_t *val)
+{
+ printf("MEM_read32: mem_type=%s, offset=0x%lx\n", mem_type, offset);
+ *val = 0;
+}
+
+void mem_read16(const char *mem_type, uint64_t offset, uint16_t *val)
+{
+ printf("MEM_read16: mem_type=%s, offset=0x%lx\n", mem_type, offset);
+ *val = 0;
+}
+
+void mem_read8(const char *mem_type, uint64_t offset, uint8_t *val)
+{
+ printf("MEM_read8: mem_type=%s, offset=0x%lx\n", mem_type, offset);
+ *val = 0;
+}
+
+void trace_player_wait(uint32_t num)
+{
+ printf("WAIT: %d\n", num);
+}
+
+/* fake interrupt generate and handle */
+uint32_t trace_player_check_and_clear_pending_intr(void)
+{
+ uint32_t rc = 0;
+ static int i = 0;
+
+ if (i++ == 1000) {
+ i = 0;
+ rc = 0x1<<6;
+ printf("NOTIFY_INTR: 0x%x\n", rc);
+ }
+
+ return rc;
+}
diff --git a/common/verif/include/sh_dpi_tasks.svh b/common/verif/include/sh_dpi_tasks.svh
new file mode 100755
index 0000000..a34476e
--- /dev/null
+++ b/common/verif/include/sh_dpi_tasks.svh
@@ -0,0 +1,565 @@
+// Amazon FPGA Hardware Development Kit
+//
+// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Licensed under the Amazon Software License (the "License"). You may not use
+// this file except in compliance with the License. A copy of the License is
+// located at
+//
+// http://aws.amazon.com/asl/
+//
+// or in the "license" file accompanying this file. This file is distributed on
+// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
+// implied. See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
+// NVIDIA’s contributions are offered under the Amazon Software License
+
+
+`ifndef SV_SH_DPI_TASKS
+`define SV_SH_DPI_TASKS
+
+import tb_type_defines_pkg::*;
+
+ import "DPI-C" context task test_main(output int unsigned exit_code);
+ import "DPI-C" context task trace_test_main(output int unsigned exit_code, input string trace_output_lib, input int enable_sim_mem);
+ import "DPI-C" context task int_handler(input int unsigned int_num);
+ import "DPI-C" context function void host_memory_putc(input longint unsigned addr, byte data); // even though a int is used, only the lower 8b are used
+ import "DPI-C" context function byte host_memory_getc(input longint unsigned addr);
+
+ export "DPI-C" task sv_printf;
+ export "DPI-C" task sv_map_host_memory;
+ export "DPI-C" task cl_peek;
+ export "DPI-C" task cl_poke;
+ export "DPI-C" task cl_peek_ocl;
+ export "DPI-C" task cl_poke_ocl;
+ export "DPI-C" task cl_peek_bar1;
+ export "DPI-C" task cl_poke_bar1;
+ export "DPI-C" task cl_peek_pcis;
+ export "DPI-C" task cl_poke_pcis;
+ export "DPI-C" task sv_int_ack;
+ export "DPI-C" task sv_pause;
+ export "DPI-C" task sv_assert;
+
+ export "DPI-C" function backdoor_mem_write;
+ export "DPI-C" function backdoor_mem_read;
+
+ static int h2c_desc_index = 0;
+ static int c2h_desc_index = 0;
+
+ task sv_printf(input string msg);
+ $display("%S", msg);
+ endtask
+
+ task sv_map_host_memory(input longint unsigned addr);
+ tb.card.fpga.sh.map_host_memory(addr);
+ endtask
+
+ task cl_peek(input longint unsigned addr, output int unsigned data);
+ tb.card.fpga.sh.peek(.addr(addr), .data(data), .intf(AxiPort::PORT_OCL));
+ endtask
+
+ task cl_poke(input longint unsigned addr, int unsigned data);
+ tb.card.fpga.sh.poke(.addr(addr), .data(data), .intf(AxiPort::PORT_OCL));
+ endtask
+
+ task cl_peek_ocl(input longint unsigned addr, output int unsigned data);
+ tb.card.fpga.sh.peek(.addr(addr), .data(data), .intf(AxiPort::PORT_OCL));
+ endtask
+
+ task cl_poke_ocl(input longint unsigned addr, int unsigned data);
+ tb.card.fpga.sh.poke(.addr(addr), .data(data), .intf(AxiPort::PORT_OCL));
+ endtask
+
+ task cl_peek_bar1(input longint unsigned addr, output int unsigned data);
+ tb.card.fpga.sh.peek(.addr(addr), .data(data), .intf(AxiPort::PORT_BAR1));
+ endtask
+
+ task cl_poke_bar1(input longint unsigned addr, int unsigned data);
+ tb.card.fpga.sh.poke(.addr(addr), .data(data), .intf(AxiPort::PORT_BAR1));
+ endtask
+
+ task cl_peek_pcis(input longint unsigned addr, output longint unsigned data, input int unsigned size);
+ tb.card.fpga.sh.peek(.addr(addr), .data(data), .size(size), .intf(AxiPort::PORT_DMA_PCIS));
+ endtask
+
+ task cl_poke_pcis(input longint unsigned addr, longint unsigned data, int unsigned size);
+ tb.card.fpga.sh.poke(.addr(addr), .data(data), .size(size), .intf(AxiPort::PORT_DMA_PCIS));
+ endtask
+
+ task sv_int_ack(input int unsigned int_num);
+ tb.card.fpga.sh.set_ack_bit(int_num);
+ endtask
+
+ task sv_pause(input int x);
+ repeat (x) #1us;
+ endtask
+
+ task sv_assert(input int x);
+ if (x == 0) begin
+ $display("Error: sv_assert failed.");
+ $finish;
+ end
+ endtask
+
+ function void hm_put_byte(input longint unsigned addr, byte d);
+ if (tb.use_c_host_memory)
+ host_memory_putc(addr, d);
+ else begin
+ int unsigned t;
+
+ if (tb.sv_host_memory.exists({addr[63:2], 2'b00})) begin
+ t = tb.sv_host_memory[{addr[63:2], 2'b00}];
+ end
+ else
+ t = 32'hffff_ffff;
+
+ t = t & ~(32'h0000_00ff << (addr[1:0] * 8) );
+ t = t | ({24'h000000, d} << (addr[1:0] * 8) );
+ tb.sv_host_memory[{addr[63:2], 2'b00}] = t;
+ end
+ endfunction
+
+ function byte hm_get_byte(input longint unsigned addr);
+ byte d;
+
+ if (tb.use_c_host_memory)
+ d = host_memory_getc(addr);
+ else begin
+ int unsigned t;
+ if (tb.sv_host_memory.exists({addr[63:2], 2'b00})) begin
+ t = tb.sv_host_memory[{addr[63:2], 2'b00}];
+ t = t >> (addr[1:0] * 8);
+ d = t[7:0];
+ end
+ else
+ d = 'hff;
+ end
+ return d;
+ endfunction
+
+`define SLOT_MACRO_TASK(ARG) \
+begin \
+ case (slot_id) \
+ 0: tb.card.fpga.sh.ARG; \
+`ifdef SLOT_1 \
+ 1: tb.`SLOT_1.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_2 \
+ 2: tb.`SLOT_2.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_3 \
+ 3: tb.`SLOT_3.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_4 \
+ 4: tb.`SLOT_4.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_5 \
+ 5: tb.`SLOT_5.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_6 \
+ 6: tb.`SLOT_6.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_7 \
+ 7: tb.`SLOT_7.fpga.sh.ARG; \
+`endif \
+ default: begin \
+ $display("Error: Invalid Slot ID specified."); \
+ $finish; \
+ end \
+ endcase \
+end
+
+`define SLOT_MACRO_FUNC(ARG) \
+begin \
+ case (slot_id) \
+ 0: return tb.card.fpga.sh.ARG; \
+`ifdef SLOT_1 \
+ 1: return tb.`SLOT_1.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_2 \
+ 2: return tb.`SLOT_2.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_3 \
+ 3: return tb.`SLOT_3.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_4 \
+ 4: return tb.`SLOT_4.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_5 \
+ 5: return tb.`SLOT_5.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_6 \
+ 6: return tb.`SLOT_6.fpga.sh.ARG; \
+`endif \
+`ifdef SLOT_7 \
+ 7: return tb.`SLOT_7.fpga.sh.ARG; \
+`endif \
+ default: begin \
+ $display("Error: Invalid Slot ID specified."); \
+ $finish; \
+ end \
+ endcase \
+end
+
+ function void que_buffer_to_cl(input int slot_id = 0, int chan, logic [63:0] src_addr, logic [63:0] cl_addr, logic [27:0] len);
+ `SLOT_MACRO_TASK(dma_buffer_to_cl(.chan(chan), .src_addr(src_addr), .cl_addr(cl_addr), .len(len)))
+ endfunction
+
+ function void que_cl_to_buffer(input int slot_id = 0, int chan, logic [63:0] dst_addr, logic [63:0] cl_addr, logic [27:0] len);
+ `SLOT_MACRO_TASK(dma_cl_to_buffer(.chan(chan), .dst_addr(dst_addr), .cl_addr(cl_addr), .len(len)))
+ endfunction
+
+ function void start_que_to_cl(input int slot_id = 0, int chan);
+ `SLOT_MACRO_TASK(start_dma_to_cl(chan))
+ endfunction
+
+ function void start_que_to_buffer(input int slot_id = 0, int chan);
+ `SLOT_MACRO_TASK(start_dma_to_buffer(chan))
+ endfunction
+
+ task power_up(input int slot_id = 0,
+ ClockRecipe::A_RECIPE clk_recipe_a = ClockRecipe::A0,
+ ClockRecipe::B_RECIPE clk_recipe_b = ClockRecipe::B0,
+ ClockRecipe::C_RECIPE clk_recipe_c = ClockRecipe::C0);
+ `SLOT_MACRO_TASK(power_up(.clk_recipe_a(clk_recipe_a),
+ .clk_recipe_b(clk_recipe_b),
+ .clk_recipe_c(clk_recipe_c)))
+ endtask
+
+ task power_down(input int slot_id = 0);
+ `SLOT_MACRO_TASK(power_down())
+ endtask
+
+ //=================================================
+ //
+ // set_virtual_dip_switch
+ //
+ // Description: writes virtual dip switches
+ // Outputs: None
+ //
+ //=================================================
+ function void set_virtual_dip_switch(input int slot_id = 0, int dip);
+ `SLOT_MACRO_TASK(set_virtual_dip_switch(dip))
+ endfunction
+
+ //=================================================
+ //
+ // get_virtual_dip_switch
+ //
+ // Description: reads virtual dip switch status
+ // Outputs: dip_status
+ //
+ //=================================================
+ function logic [15:0] get_virtual_dip_switch(input int slot_id = 0);
+ `SLOT_MACRO_FUNC(get_virtual_dip_switch())
+ endfunction
+
+ //=================================================
+ //
+ // get_virtual_led
+ //
+ // Description: reads virtual led status
+ // Outputs: led status
+ //
+ //=================================================
+ function logic[15:0] get_virtual_led(input int slot_id = 0);
+ `SLOT_MACRO_FUNC(get_virtual_led())
+ endfunction
+
+ //=================================================
+ //
+ // Kernel_reset
+ //
+ // Description: sets kernel_reset
+ // Outputs: None
+ //
+ //=================================================
+ function void kernel_reset(input int slot_id = 0, logic d = 1);
+ `SLOT_MACRO_TASK(kernel_reset(d))
+ endfunction
+
+ //=================================================
+ //
+ // poke
+ //
+ // Description: used to write a single beat of data at addr into one of the four CL AXI ports specified by intf.
+ // Intf
+ // 0 = PCIS
+ // 1 = SDA
+ // 2 = OCL
+ // 3 = BAR1
+ //
+ // id - AXI bus ID
+ //
+ // Size
+ // 0 = 1 byte, 1 = 2 bytes, 2 = 4 bytes (32 bits), 3 = 8 bytes (64 bits)
+ //
+ // Outputs: None
+ //
+ //=================================================
+ task poke(input int slot_id = 0,
+ logic [63:0] addr,
+ logic [511:0] data,
+ logic [5:0] id = 6'h0,
+ DataSize::DATA_SIZE size = DataSize::UINT32,
+ AxiPort::AXI_PORT intf = AxiPort::PORT_DMA_PCIS);
+ `SLOT_MACRO_TASK(poke(.addr(addr), .data(data), .id(id), .size(size), .intf(intf)))
+ endtask
+
+ //=================================================
+ //
+ // poke_pcis
+ //
+ // Description: used to write a single beat of data at addr into CL PCIS port.
+ // Outputs: None
+ //
+ //=================================================
+ task poke_pcis(input int slot_id = 0,
+ logic [63:0] addr,
+ logic [511:0] data,
+ logic [63:0] strb,
+ logic [5:0] id = 6'h0);
+ `SLOT_MACRO_TASK(poke_pcis(.addr(addr), .data(data), .id(id), .strb(strb)))
+ endtask
+
+ //=================================================
+ //
+ // peek
+ //
+ // Description: used to read a single beat of data at addr from one of the four CL AXI ports specified by intf.
+ // Intf
+ // 0 = PCIS
+ // 1 = SDA
+ // 2 = OCL
+ // 3 = BAR1
+ //
+ // id - AXI bus ID
+ //
+ // Size
+ // 0 = 1 byte, 1 = 2 bytes, 2 = 4 bytes (32 bits), 3 = 8 bytes (64 bits)
+ //
+ // Outputs: Read Data Value
+ //
+ //=================================================
+ task peek(input int slot_id = 0,
+ logic [63:0] addr,
+ output logic [511:0] data,
+ input logic [5:0] id = 6'h0,
+ DataSize::DATA_SIZE size = DataSize::UINT32,
+ AxiPort::AXI_PORT intf = AxiPort::PORT_DMA_PCIS);
+ `SLOT_MACRO_TASK(peek(.addr(addr), .data(data), .id(id), .size(size), .intf(intf)))
+ endtask
+
+ //=================================================
+ //
+ // peek_pcis
+ //
+ // Description: used to read a single beat of data at addr from the CL PCIS AXI port.
+ // Outputs: Read Data Value
+ //
+ //=================================================
+ task peek_pcis(input int slot_id = 0,
+ logic [63:0] addr,
+ output logic [511:0] data,
+ input logic [5:0] id = 6'h0);
+ `SLOT_MACRO_TASK(peek_pcis(.addr(addr), .data(data), .id(id)))
+ endtask
+
+ //=================================================
+ //
+ // set_ack_bit
+ //
+ // Description: used to acknowledge an interrupt and clear pending bit
+ // Outputs: None
+ //
+ //=================================================
+ function void set_ack_bit(input int slot_id = 0,
+ int int_num);
+ `SLOT_MACRO_TASK(set_ack_bit(.int_num(int_num)))
+ endfunction
+
+ //=================================================
+ //
+ // issue_flr
+ //
+ // Description: issue a FLR command
+ // Outputs: None
+ //
+ //=================================================
+ task issue_flr(input int slot_id = 0);
+ `SLOT_MACRO_TASK(issue_flr())
+ endtask
+
+ //=================================================
+ //
+ // nsec_delay
+ //
+ // Description: sets a delay in nsec
+ // Outputs: None
+ //
+ //=================================================
+ task nsec_delay(int dly = 10000);
+ tb.card.fpga.sh.nsec_delay(dly);
+ endtask
+
+ //=================================================
+ //
+ // poke_ocl
+ //
+ // Description: used to write a single 32b of data at addr into the OCL interface.
+ //
+ // id - AXI bus ID
+ //
+ // Outputs: None
+ //
+ //=================================================
+ task poke_ocl(input int slot_id = 0,
+ logic [63:0] addr,
+ logic [31:0] data,
+ logic [5:0] id = 6'h0);
+ `SLOT_MACRO_TASK(poke(.addr(addr), .data({32'h0, data}), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_OCL)))
+ endtask
+
+ //=================================================
+ //
+ // peek_ocl
+ //
+ // Description: used to read a single 32b of data at addr from the OCL interface.
+ //
+ // id - AXI bus ID
+ //
+ // Outputs: Read Data Value
+ //
+ //=================================================
+ task peek_ocl(input int slot_id = 0,
+ logic [63:0] addr,
+ output logic [63:0] data,
+ input logic [5:0] id = 6'h0);
+ logic [63:0] tmp;
+ `SLOT_MACRO_TASK(peek(.addr(addr), .data(tmp), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_OCL)))
+ data = {32'h0, tmp[31:0]};
+ endtask
+
+ //=================================================
+ //
+ // poke_sda
+ //
+ // Description: used to write a single 32b of data at addr into the SDA interface.
+ //
+ // id - AXI bus ID
+ //
+ // Outputs: None
+ //
+ //=================================================
+ task poke_sda(input int slot_id = 0,
+ logic [63:0] addr,
+ logic [31:0] data,
+ logic [5:0] id = 6'h00);
+ `SLOT_MACRO_TASK(poke(.addr(addr), .data({32'h0, data}), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_SDA)))
+ endtask
+
+ //=================================================
+ //
+ // peek_sda
+ //
+ // Description: used to read a single 32b of data at addr from the OCL interface.
+ //
+ // id - AXI bus ID
+ //
+ // Outputs: Read Data Value
+ //
+ //=================================================
+ task peek_sda(input int slot_id = 0,
+ logic [63:0] addr,
+ output logic [63:0] data,
+ input logic [5:0] id = 6'h0);
+ logic [63:0] tmp;
+ `SLOT_MACRO_TASK(peek(.addr(addr), .data(data), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_SDA)))
+ data = {32'h0, tmp[31:0]};
+ endtask
+
+ //=================================================
+ //
+ // poke_bar1
+ //
+ // Description: used to write a single 32b of data at addr into the BAR1 interface.
+ //
+ // id - AXI bus ID
+ //
+ // Outputs: None
+ //
+ //=================================================
+ task poke_bar1(input int slot_id = 0,
+ logic [63:0] addr,
+ logic [31:0] data,
+ logic [5:0] id = 6'h0);
+ `SLOT_MACRO_TASK(poke(.addr(addr), .data({32'h0, data}), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_BAR1)))
+ endtask
+
+ //=================================================
+ //
+ // peek_bar1
+ //
+ // Description: used to read a single 32b of data at addr from the BAR1 interface.
+ //
+ // id - AXI bus ID
+ //
+ // Outputs: Read Data Value
+ //
+ //=================================================
+ task peek_bar1(input int slot_id = 0,
+ logic [63:0] addr,
+ output logic [63:0] data,
+ input logic [5:0] id = 6'h0);
+ logic [63:0] tmp;
+ `SLOT_MACRO_TASK(peek(.addr(addr), .data(data), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_BAR1)))
+ data = {32'h0, tmp[31:0]};
+ endtask
+
+ function bit is_dma_to_cl_done(input int slot_id = 0, input int chan);
+ `SLOT_MACRO_FUNC(is_dma_to_cl_done(chan))
+ endfunction // is_dma_to_cl_done
+
+ function bit is_dma_to_buffer_done(input int slot_id = 0, input int chan);
+ `SLOT_MACRO_FUNC(is_dma_to_buffer_done(chan))
+ endfunction // is_dma_to_buffer_done
+
+ task poke_stat(input int slot_id = 0,
+ input logic [7:0] addr, logic [1:0] ddr_idx, logic[31:0] data);
+ `SLOT_MACRO_TASK(poke_stat(.addr(addr), .ddr_idx(ddr_idx), .data(data)))
+ endtask
+
+ //===================================================
+ // Backdoor memory function
+ //===================================================
+ byte unsigned array[*];
+ bit enable_mem_log = 0;
+ function void enable_backdoor_mem_log(input bit enable);
+ enable_mem_log = enable;
+ endfunction
+ function void backdoor_mem_write(input longint unsigned addr, input longint unsigned data, input int unsigned size_in_bytes, input int unsigned wstrb);
+ if (enable_mem_log)
+ $display("backdoor_mem_write: addr=0x%h, wstrb=0x%h, nbytes=0x%h, data=0x%h\n", addr, wstrb, size_in_bytes, data);
+ for (int i=0; i