$mul not being converted correctly

[nachiket]

Here's a simple example of a Verilog file I'm trying to translate to SVG.

module mult (
  input logic [7:0] a,
  input logic [7:0] b,
  input logic [7:0] c,
  output logic [7:0] y
  );

always_comb begin
  y = a*b + c;
end

endmodule

When I compile it with Verilog

yosys -p "read_verilog -sv mult.sv; proc; opt; write_json temp.json"; netlistsvg temp.json -o temp.svg; cairosvg temp.svg -o mult.pdf

I get the following result with $mul staying as a block instead of the multiply symbol.

What am I missing?

Thakns
Nachiket

[nachiket]

Just an FYI, even $sdff isn't getting mapped correctly to FF symbols.

[nachiket]

I think I was using npm install version instead of building from source. I'm not sure if there was a plan to not need rebuilding from source to get the latest snazziest drawing flow!