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Fix cache string description in config files (gpgpu-sim#96)
* fix_cache_string: update cache desc in config files and remove typos * fix_cache_string: update gitignore
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‎.gitignore‎

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@@ -56,9 +56,17 @@ debug_tools/WatchYourStep/ptxjitplus/gpgpu*
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debug_tools/WatchYourStep/ptxjitplus/*.old
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debug_tools/WatchYourStep/ptxjitplus/ptxjitplus
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debug_tools/WatchYourStep/ptxjitplus/*.ptx
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*.tmp
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# Accel-sim packages used for regressions
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accel-sim-framework/
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gpu-app-collection/
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setup
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# OS/IDE specific files
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.idea/
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.vscode/
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.DS_Store
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.DS_store
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__pycache__/

‎configs/tested-cfgs/SM2_GTX480/gpgpusim.config‎

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# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
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# ** Optional parameter - Required when mshr_type==Texture Fifo
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>,<data_port_width>
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# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used
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# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
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-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,S:64:8,8
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-gpgpu_shmem_size 49152

‎configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config‎

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# Greedy then oldest scheduler
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-gpgpu_scheduler gto
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
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# ** Optional parameter - Required when mshr_type==Texture Fifo
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>,<data_port_width>
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# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used
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# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
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# The defulat is to disable the L1 cache, unless cache modifieres are used
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-gpgpu_cache:dl1 S:4:128:32,L:L:s:N:L,A:256:8,16:0,32

‎configs/tested-cfgs/SM6_TITANX/gpgpusim.config‎

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-gpgpu_dual_issue_diff_exec_units 1
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## L1/shared memory configuration
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
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# ** Optional parameter - Required when mshr_type==Texture Fifo
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>,<data_port_width>
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# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used
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# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
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# The defulat is to disable the L1 cache, unless cache modifieres are used
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-gpgpu_l1_banks 2

‎configs/tested-cfgs/SM75_RTX2060/gpgpusim.config‎

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-gpgpu_dual_issue_diff_exec_units 1
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## L1/shared memory configuration
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
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# ** Optional parameter - Required when mshr_type==Texture Fifo
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>,<data_port_width>
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# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used
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# In adaptive cache, we adaptively assign the remaining shared memory to L1 cache
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# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
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-gpgpu_adaptive_cache_config 1

‎configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config‎

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-gpgpu_num_reg_banks 16
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-gpgpu_reg_file_port_throughput 2
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
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# ** Optional parameter - Required when mshr_type==Texture Fifo
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>,<data_port_width>
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# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used
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-gpgpu_adaptive_cache_config 0
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-gpgpu_l1_banks 4
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-gpgpu_cache:dl1 S:1:128:512,L:L:s:N:L,A:256:8,16:0,32

‎configs/tested-cfgs/SM7_GV100/gpgpusim.config‎

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-gpgpu_dual_issue_diff_exec_units 1
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## L1/shared memory configuration
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
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# ** Optional parameter - Required when mshr_type==Texture Fifo
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>,<data_port_width>
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# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used
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# Defualt config is 32KB DL1 and 96KB shared memory
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# In Volta, we assign the remaining shared memory to L1 cache
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# if the assigned shd mem = 0, then L1 cache = 128KB

‎configs/tested-cfgs/SM7_QV100/gpgpusim.config‎

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-gpgpu_dual_issue_diff_exec_units 1
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## L1/shared memory configuration
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
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# ** Optional parameter - Required when mshr_type==Texture Fifo
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>,<data_port_width>
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# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used
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# Defualt config is 32KB DL1 and 96KB shared memory
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# In Volta, we assign the remaining shared memory to L1 cache
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# if the assigned shd mem = 0, then L1 cache = 128KB

‎configs/tested-cfgs/SM7_TITANV/gpgpusim.config‎

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-gpgpu_dual_issue_diff_exec_units 1
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## L1/shared memory configuration
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
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# ** Optional parameter - Required when mshr_type==Texture Fifo
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>,<data_port_width>
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# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used
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# Defualt config is 32KB DL1 and 96KB shared memory
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# In Volta, we assign the remaining shared memory to L1 cache
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# if the assigned shd mem = 0, then L1 cache = 128KB

‎configs/tested-cfgs/SM86_RTX3070/gpgpusim.config‎

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-gpgpu_dual_issue_diff_exec_units 1
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## L1/shared memory configuration
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
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# ** Optional parameter - Required when mshr_type==Texture Fifo
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# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>,<data_port_width>
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# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used
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# In adaptive cache, we adaptively assign the remaining shared memory to L1 cache
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# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
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-gpgpu_adaptive_cache_config 1

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