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self . config_reg = self . config_reg . as_tx ( ) ;
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self . spi_write_byte ( registers:: CONFIG , self . config_reg . into_bits ( ) ) ?;
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+ let addr_len = self . feature . address_length ( ) ;
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+ // use `spi_transfer()` to avoid multiple borrows of self (`spi_write_buf()` and `tx_address`)
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+ for reg in [ registers:: TX_ADDR , registers:: RX_ADDR_P0 ] {
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+ self . buf [ 0 ] = reg | commands:: W_REGISTER ;
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+ self . buf [ 1 ..addr_len as usize + 1 ]
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+ . copy_from_slice ( & self . tx_address [ 0 ..addr_len as usize ] ) ;
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+ self . spi_transfer ( addr_len + 1 ) ?;
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+ }
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+
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self . spi_read ( 1 , registers:: EN_RXADDR ) ?;
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- let out = self . buf [ 1 ] | 1 ;
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- self . spi_write_byte ( registers:: EN_RXADDR , out)
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+ self . spi_write_byte ( registers:: EN_RXADDR , self . buf [ 1 ] | 1 )
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}
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fn is_rx ( & self ) -> bool {
@@ -98,23 +106,22 @@ where
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// TX FIFO is full already
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return Ok ( false ) ;
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}
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- let mut buf_len = buf. len ( ) . min ( 32 ) as u8 ;
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+ let buf_len = buf. len ( ) . min ( 32 ) ;
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// to avoid resizing the given buf, we'll have to use self._buf directly
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self . buf [ 0 ] = if !ask_no_ack {
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commands:: W_TX_PAYLOAD
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} else {
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commands:: W_TX_PAYLOAD_NO_ACK
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} ;
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- self . buf [ 1 ..( buf_len + 1 ) as usize ] . copy_from_slice ( & buf[ ..buf_len as usize ] ) ;
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+ self . buf [ 1 ..buf_len + 1 ] . copy_from_slice ( & buf[ ..buf_len] ) ;
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// ensure payload_length setting is respected
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- if !self . feature . dynamic_payloads ( ) && buf_len < self . payload_length {
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+ if !self . feature . dynamic_payloads ( ) && ( buf_len as u8 ) < self . payload_length {
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// pad buf with zeros
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- for i in ( buf_len + 1 ) .. ( self . payload_length + 1 ) {
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- self . buf [ i as usize ] = 0 ;
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- }
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- buf_len = self . payload_length ;
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+ self . buf [ buf_len + 1 .. self . payload_length as usize + 1 ] . fill ( 0 ) ;
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+ self . spi_transfer ( self . payload_length + 1 ) ? ;
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+ } else {
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+ self . spi_transfer ( buf_len as u8 + 1 ) ? ;
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}
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- self . spi_transfer ( buf_len + 1 ) ?;
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if start_tx {
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self . ce_pin . set_high ( ) . map_err ( Nrf24Error :: Gpo ) ?;
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}
@@ -150,9 +157,7 @@ where
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return Ok ( 0 ) ;
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}
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self . spi_read ( buf_len, commands:: R_RX_PAYLOAD ) ?;
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- for i in 0 ..buf_len {
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- buf[ i as usize ] = self . buf [ i as usize + 1 ] ;
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- }
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+ buf[ 0 ..buf_len as usize ] . copy_from_slice ( & self . buf [ 1 ..buf_len as usize + 1 ] ) ;
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let flags = StatusFlags :: from_bits ( mnemonics:: MASK_RX_DR ) ;
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self . clear_status_flags ( flags) ?;
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Ok ( buf_len)
@@ -256,7 +261,7 @@ mod test {
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vec![ registers:: STATUS | commands:: W_REGISTER , 0x70u8 ] ,
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vec![ 0xEu8 , 0u8 ] ,
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) ,
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- // write cached _pipe0_rx_addr
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+ // write cached pipe0_rx_addr
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( buf_expected. to_vec( ) , vec![ 0xEu8 , 0u8 , 0u8 , 0u8 , 0u8 , 0u8 ] ) ,
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] ;
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let mocks = mk_radio ( & ce_expectations, & spi_expectations) ;
@@ -279,6 +284,29 @@ mod test {
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vec![ registers:: CONFIG | commands:: W_REGISTER , 0xCu8 ] ,
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vec![ 0xEu8 , 0u8 ] ,
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) ,
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+ // set cached TX address to RX pipe 0
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+ (
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+ vec![
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+ registers:: TX_ADDR | commands:: W_REGISTER ,
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+ 0xE7 ,
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+ 0xE7 ,
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+ 0xE7 ,
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+ 0xE7 ,
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+ 0xE7
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+ ] ,
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+ vec![ 0xE , 0 , 0 , 0 , 0 , 0 ]
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+ ) ,
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+ (
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+ vec![
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+ registers:: RX_ADDR_P0 | commands:: W_REGISTER ,
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+ 0xE7 ,
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+ 0xE7 ,
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+ 0xE7 ,
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+ 0xE7 ,
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+ 0xE7
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+ ] ,
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+ vec![ 0xE , 0 , 0 , 0 , 0 , 0 ]
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+ ) ,
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// open pipe 0 for TX (regardless of auto-ack)
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( vec![ registers:: EN_RXADDR , 0u8 ] , vec![ 0xEu8 , 0u8 ] ) ,
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(
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