forked from acontis/atemsys
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathatemsys.c
3769 lines (3268 loc) · 114 KB
/
atemsys.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*-----------------------------------------------------------------------------
* atemsys.c
* Copyright (c) 2009 - 2020 acontis technologies GmbH, Ravensburg, Germany
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Response Paul Bussmann
* Description Provides usermode access to:
* - PCI configuration space
* - Device IO memory
* - Contiguous DMA memory
* - Single device interrupt
*
*
* The driver should be used in the following way:
*
* - Make sure this driver's device node is present. I.e. call "mknod /dev/atemsys c 101 0"
*
* - open()
* Open driver (There can be more then one file descriptor active in parallel).
*
* - close()
* Close driver. Free resources, if any were allocated.
*
* - ioctl(ATEMSYS_IOCTL_PCI_FIND_DEVICE)
* Scan for PCI Devices.
* Input: VendorID, DeviceID, InstanceNo
* Output: BusNo, DevNo, FuncNo
*
* - ioctl(ATEMSYS_IOCTL_PCI_CONF_DEVICE)
* Configures PCI device. This ioctl pins the given PCI device to the current filedescriptor.
* Input: BusNo, DevNo, FuncNo
* Output: Physical IO base address, IO area length, IRQ number
* The device must be released explicitly in order to configure the next device. The ioctl gets
* errno EBUSY if the device is in use by another device driver.
*
* - ioctl(ATEMSYS_IOCTL_PCI_RELEASE_DEVICE)
* Release PCI device and free resources assigned to PCI device (interrupt, DMA memory, ...).
*
* - mmap(0, dwSize, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_LOCKED, fd, 0);
* Allocates and maps DMA memory of size dwSize. Note that the last parameter (offset) must be 0.
* Input: Length in byte
* Output: Pointer to the allocated memory and DMA physical address. On success this address is
* written into the first 4 bytes of the allocated memory.
*
* - mmap(0, IOphysSize, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_LOCKED, fd, IOphysAddr);
* Maps IO memory of size IOphysSize.
* PCI device:
* First call ioctl(ATEMSYS_IOCTL_PCI_CONF_DEVICE). The IOphysAddr and IOphysSize
* parameter must corespond with the base IO address and size returned by
* ioctl(ATEMSYS_IOCTL_PCI_CONF_DEVICE), or the ioctl will fail.
* Non-PCI device:
* Don't call ioctl(ATEMSYS_IOCTL_PCI_CONF_DEVICE) before and just pass
* IOphysAddr and IOphysSize. There are no checks done.
* Input: Phys.IO base address, IO area length in byte
* Output: Pointer to the mapped IO memory.
* The user should call dev_munmap() if the requested DMA memory is not needed anymore. In any cases
* the allocated / mapped memory is released / unmapped if the module is unloaded.
*
* - ioctl(ATEMSYS_IOCTL_INT_CONNECT)
* Connect an ISR to the device's interrupt.
* If the parameter is USE_PCI_INT, then the IRQ is taken from the selected PCI device.
* So in this case you have to call ioctl(ATEMSYS_IOCTL_PCI_CONF_DEVICE) first, or it will fail.
* Input: IRQ-Number or USE_PCI_INT
* Output: none
* The device interrupt is active if this ioctl succeeds. The caller should do a read() on the file
* descriptor. The read call unblocks if an interrupt is received. If the read is unblocked, the
* interrupt is disabled on the (A)PIC and the caller must acknowledge the interrupt on the device
* (write to mmaped IO register). If the next read() is executed, the interrupt is enabled again
* on the (A)PIC. So a missing interrupt acknowledge will held the INT line active and interrupt
* trashing will happen (ISR is called again, read() unblocks, ...).
* Note that this ioctl will fail with errno EPERM if the interrupt line is shared.
* PCI device:
* The ioctl will try to use Message Signaled Interrupts (MSI) if supported
* by the PCI device. By definition, interrupts are never shared with MSI and MSI are mandatory
* for PCI-Express :).
*
* - ioctl(ATEMSYS_IOCTL_INT_DISCONNECT)
* Disconnect from device's interrupt.
*
* - ioctl(ATEMSYS_IOCTL_INT_INFO)
* Query used interrupt number.
*
* - read()
* see ioctl(ATEMSYS_IOCTL_INT_CONNECT)
*
*
* Changes see atemsys.h
*
*----------------------------------------------------------------------------*/
#define ATEMSYS_C
#include <linux/module.h>
#include "atemsys.h"
#include <linux/pci.h>
#include <linux/platform_device.h>
#if !(defined NO_IRQ) && (defined __aarch64__)
#define NO_IRQ ((unsigned int)(-1))
#endif
#if (defined CONFIG_XENO_COBALT)
#include <rtdm/driver.h>
#else
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/semaphore.h>
#include <linux/mutex.h>
#include <linux/sched.h>
#include <linux/smp.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,11,00))
#include <linux/sched/signal.h>
#endif
#include <linux/irq.h>
#include <linux/list.h>
#if (defined CONFIG_OF)
#include <linux/of_device.h>
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,13,0))
#include <linux/uaccess.h>
#else
#include <asm/uaccess.h>
#endif
#include <asm/current.h>
#include <linux/compat.h>
#include <linux/slab.h>
#include <linux/device.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,0))
#include <linux/dma-direct.h>
#endif
#if (defined CONFIG_DTC)
#include <linux/of.h>
#include <linux/of_irq.h>
#endif /* CONFIG_DTC */
#endif /* CONFIG_XENO_COBALT */
#if ((defined CONFIG_OF) \
&& (LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0) /* not tested */))
#define INCLUDE_ATEMSYS_DT_DRIVER 1
#include <linux/etherdevice.h>
#include <linux/clk.h>
#include <linux/phy.h>
#include <linux/clk/clk-conf.h>
#include <linux/pinctrl/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/of_mdio.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_net.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/wait.h>
#include <asm/param.h>
#endif
#if ((defined CONFIG_PCI) \
&& (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0) /* not tested */))
#define INCLUDE_ATEMSYS_PCI_DRIVER 1
#include <linux/aer.h>
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,1))
#define INCLUDE_IRQ_TO_DESC
#endif
/* legacy support */
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,13,0))
#define wait_queue_entry_t wait_queue_t
#endif
#ifndef VM_RESERVED
#define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
#endif
/* define this if IO memory should also be mapped into the kernel (for debugging only) */
#undef DEBUG_IOREMAP
MODULE_AUTHOR("acontis technologies GmbH <[email protected]>");
MODULE_DESCRIPTION("Generic usermode PCI driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(ATEMSYS_VERSION_STR);
static char *AllowedPciDevices = "PCI_ANY_ID";
module_param(AllowedPciDevices, charp, 0000);
MODULE_PARM_DESC(AllowedPciDevices, "Bind only pci devices in semicolon separated list e.g. AllowedPciDevices=\"0000:01:00.0\", empty string will turn off atemsys_pci driver.");
static int loglevel = LOGLEVEL_INFO;
module_param(loglevel, int, 0);
MODULE_PARM_DESC(loglevel, "Set log level default LOGLEVEL_INFO, see /include/linux/kern_levels.h");
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
#error "At least kernel version 2.6.18 is needed to compile!"
#endif
#if (defined CONFIG_XENO_COBALT)
#define PRINTK(prio, str, ...) rtdm_printk(prio ATEMSYS_DEVICE_NAME ": " str, ##__VA_ARGS__)
#else
#define PRINTK(prio, str, ...) printk(prio ATEMSYS_DEVICE_NAME ": " str, ##__VA_ARGS__)
#endif /* CONFIG_XENO_COBALT */
/* Workaround for older kernels */
/* from 'linux/kern_levels.h' */
/* integer equivalents of KERN_<LEVEL> */
#ifndef LOGLEVEL_ERR
#define LOGLEVEL_ERR 3 /* error conditions */
#endif
#ifndef LOGLEVEL_WARNING
#define LOGLEVEL_WARNING 4 /* warning conditions */
#endif
#ifndef LOGLEVEL_INFO
#define LOGLEVEL_INFO 6 /* informational */
#endif
#ifndef LOGLEVEL_DEBUG
#define LOGLEVEL_DEBUG 7 /* debug-level messages */
#endif
#define ERR(str, ...) (LOGLEVEL_ERR <= loglevel)? PRINTK(KERN_ERR, str, ##__VA_ARGS__) :0
#define WRN(str, ...) (LOGLEVEL_WARNING <= loglevel)? PRINTK(KERN_WARNING, str, ##__VA_ARGS__) :0
#define INF(str, ...) (LOGLEVEL_INFO <= loglevel)? PRINTK(KERN_INFO, str, ##__VA_ARGS__) :0
#define DBG(str, ...) (LOGLEVEL_DEBUG <= loglevel)? PRINTK(KERN_INFO, str, ##__VA_ARGS__) :0
#ifndef PAGE_UP
#define PAGE_UP(addr) (((addr)+((PAGE_SIZE)-1))&(~((PAGE_SIZE)-1)))
#endif
#ifndef PAGE_DOWN
#define PAGE_DOWN(addr) ((addr)&(~((PAGE_SIZE)-1)))
#endif
/* Comments: for kernel 2.6.18 add DMA_BIT_MASK*/
#ifndef DMA_BIT_MASK
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
#endif
#ifndef HAVE_ACCESS_OK_TYPE
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0))
#define HAVE_ACCESS_OK_TYPE 0
#else
#define HAVE_ACCESS_OK_TYPE 1
#endif
#endif
#if HAVE_ACCESS_OK_TYPE
#define ACCESS_OK(type, addr, size) access_ok(type, addr, size)
#else
#define ACCESS_OK(type, addr, size) access_ok(addr, size)
#endif
#if ((defined CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,18,0)) && !(defined CONFIG_XENO_COBALT))
#define OF_DMA_CONFIGURE(dev, of_node) of_dma_configure(dev, of_node, true)
#elif ((defined CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)) && !(defined CONFIG_XENO_COBALT))
#define OF_DMA_CONFIGURE(dev, of_node) of_dma_configure(dev, of_node)
#else
#define OF_DMA_CONFIGURE(dev, of_node)
#endif
typedef struct _ATEMSYS_T_IRQ_DESC
{
u32 irq;
atomic_t count;
atomic_t totalCount;
#if (defined CONFIG_XENO_COBALT)
rtdm_irq_t irq_handle;
rtdm_event_t irq_event;
#else
atomic_t irqStatus;
wait_queue_head_t q;
#endif /* CONFIG_XENO_COBALT */
#if (defined INCLUDE_IRQ_TO_DESC)
bool irq_is_level;
#endif
} ATEMSYS_T_IRQ_DESC;
struct _ATEMSYS_T_PCI_DRV_DESC_PRIVATE;
struct _ATEMSYS_T_DRV_DESC_PRIVATE;
typedef struct _ATEMSYS_T_DEVICE_DESC
{
struct list_head list;
#if (defined CONFIG_PCI)
struct pci_dev *pPcidev;
#if (defined INCLUDE_ATEMSYS_PCI_DRIVER)
struct _ATEMSYS_T_PCI_DRV_DESC_PRIVATE *pPciDrvDesc;
#endif
#endif
struct platform_device* pPlatformDev;
#if (defined INCLUDE_ATEMSYS_DT_DRIVER)
struct _ATEMSYS_T_DRV_DESC_PRIVATE *pDrvDesc;
#endif
ATEMSYS_T_IRQ_DESC irqDesc;
/* supported features */
bool bSupport64BitDma;
} ATEMSYS_T_DEVICE_DESC;
typedef struct _ATEMSYS_T_MMAP_DESC
{
struct list_head list;
ATEMSYS_T_DEVICE_DESC *pDevDesc;
dma_addr_t dmaAddr;
void *pVirtAddr;
size_t len;
} ATEMSYS_T_MMAP_DESC;
#if (defined CONFIG_OF)
#define ATEMSYS_DT_DRIVER_NAME "atemsys"
/* udev auto-loading support via DTB */
static const struct of_device_id atemsys_ids[] = {
{ .compatible = ATEMSYS_DT_DRIVER_NAME },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, atemsys_ids);
#endif /* CONFIG_OF */
#define ATEMSYS_MAX_NUMBER_DRV_INSTANCES 10
#if (defined INCLUDE_ATEMSYS_PCI_DRIVER)
typedef struct _ATEMSYS_T_PCI_DRV_DESC_PRIVATE
{
struct pci_dev* pPciDev;
int nPciDomain;
int nPciBus;
int nPciDev;
int nPciFun;
unsigned short wVendorId;
unsigned short wDevice;
unsigned short wRevision;
unsigned short wSubsystem_vendor;
unsigned short wSubsystem_device;
ATEMSYS_T_PCI_MEMBAR aBars[ATEMSYS_PCI_MAXBAR];
int nBarCnt;
ATEMSYS_T_DEVICE_DESC* pDevDesc;
unsigned int dwIndex;
} ATEMSYS_T_PCI_DRV_DESC_PRIVATE;
static ATEMSYS_T_PCI_DRV_DESC_PRIVATE* S_apPciDrvDescPrivate[ATEMSYS_MAX_NUMBER_DRV_INSTANCES];
#endif
#if (defined INCLUDE_ATEMSYS_DT_DRIVER)
#define ATEMSYS_MAX_NUMBER_OF_CLOCKS 10
typedef struct _ATEMSYS_T_DRV_DESC_PRIVATE
{
int nDev_id;
struct net_device* netdev;
struct platform_device* pPDev;
struct device_node* pDevNode;
/* storage and identification */
ATEMSYS_T_MAC_INFO MacInfo;
/* clocks */
const char* clk_ids[ATEMSYS_MAX_NUMBER_OF_CLOCKS];
struct clk* clks[ATEMSYS_MAX_NUMBER_OF_CLOCKS];
int nCountClk;
/* PHY */
ATEMSYS_T_PHY_INFO PhyInfo;
phy_interface_t PhyInterface;
struct device_node* pPhyNode;
struct phy_device* pPhyDev;
struct regulator* pPhyRegulator;
struct task_struct* etx_thread_StartPhy;
struct task_struct* etx_thread_StopPhy;
/* mdio */
ATEMSYS_T_MDIO_ORDER MdioOrder;
struct mii_bus* pMdioBus;
struct mutex mdio_order_mutex;
struct mutex mdio_mutex;
wait_queue_head_t mdio_wait_queue;
int mdio_wait_queue_cnt;
/* frame descriptor of the EcMaster connection */
ATEMSYS_T_DEVICE_DESC* pDevDesc;
} ATEMSYS_T_DRV_DESC_PRIVATE;
static ATEMSYS_T_DRV_DESC_PRIVATE* S_apDrvDescPrivate[ATEMSYS_MAX_NUMBER_DRV_INSTANCES];
static int StartPhyThread(void* pvData);
static int StopPhyThread(void* pvData);
static int CleanUpEthernetDriverOnRelease(ATEMSYS_T_DEVICE_DESC* pDevDesc);
static int GetMacInfoIoctl(ATEMSYS_T_DEVICE_DESC* pDevDesc, unsigned long ioctlParam);
static int PhyStartStopIoctl( unsigned long ioctlParam);
static int GetMdioOrderIoctl(unsigned long ioctlParam);
static int ReturnMdioOrderIoctl(unsigned long ioctlParam);
static int GetPhyInfoIoctl(unsigned long ioctlParam);
static int EthernetDriverRemove(struct platform_device *pPDev);
static int EthernetDriverProbe(struct platform_device *pPDev);
#endif /* INCLUDE_ATEMSYS_DT_DRIVER */
static void dev_munmap(struct vm_area_struct *vma);
#if (defined CONFIG_XENO_COBALT)
static int dev_interrupt_handler(rtdm_irq_t *irq_handle);
#else
static irqreturn_t dev_interrupt_handler(int nIrq, void *pParam);
#endif /* CONFIG_XENO_COBALT */
static struct vm_operations_struct mmap_vmop =
{
.close = dev_munmap,
};
static DEFINE_MUTEX(S_mtx);
static ATEMSYS_T_DEVICE_DESC S_DevNode;
static struct class* S_pDevClass;
static struct device* S_pDev;
static struct platform_device* S_pPlatformDev = NULL;
#if !(defined CONFIG_XENO_COBALT)
static void dev_enable_irq(ATEMSYS_T_IRQ_DESC* pIrqDesc)
{
/* enable/disable level type interrupts, not edge type interrupts */
#if (defined INCLUDE_IRQ_TO_DESC)
if (pIrqDesc->irq_is_level)
#endif
{
atomic_inc(&pIrqDesc->irqStatus);
enable_irq(pIrqDesc->irq);
}
}
static void dev_disable_irq(ATEMSYS_T_IRQ_DESC* pIrqDesc)
{
/* enable/disable level type interrupts, not edge type interrupts */
#if (defined INCLUDE_IRQ_TO_DESC)
if (!pIrqDesc->irq_is_level) return;
#endif
if (atomic_read(&pIrqDesc->irqStatus) > 0)
{
disable_irq_nosync(pIrqDesc->irq);
atomic_dec(&pIrqDesc->irqStatus);
}
}
static int dev_irq_disabled(ATEMSYS_T_IRQ_DESC* pIrqDesc)
{
/* only level type interrupts get disabled */
#if (defined INCLUDE_IRQ_TO_DESC)
if (!pIrqDesc->irq_is_level) return 0;
#endif
if (atomic_read(&pIrqDesc->irqStatus) == 0)
{
return 1;
}
return 0;
}
#endif /* !CONFIG_XENO_COBALT */
#if (!defined __arm__) && (!defined __aarch64__)
static void * dev_dma_alloc(u32 dwLen, dma_addr_t *pDmaAddr)
{
unsigned long virtAddr;
unsigned long tmpAddr;
u32 tmpSize;
virtAddr = __get_free_pages(GFP_KERNEL | GFP_DMA, get_order(dwLen));
if (! virtAddr)
{
ERR("mmap: __get_free_pages failed\n");
return NULL;
}
tmpAddr = virtAddr;
tmpSize = dwLen;
while (tmpSize > 0)
{
SetPageReserved( virt_to_page(tmpAddr) );
tmpAddr += PAGE_SIZE;
tmpSize -= PAGE_SIZE;
}
*pDmaAddr = virt_to_phys((void *) virtAddr);
return (void *) virtAddr;
}
static void dev_dma_free(u32 dwLen, void *virtAddr)
{
unsigned long tmpAddr = (unsigned long) virtAddr;
u32 tmpSize = dwLen;
while (tmpSize > 0)
{
ClearPageReserved( virt_to_page(tmpAddr) );
tmpAddr += PAGE_SIZE;
tmpSize -= PAGE_SIZE;
}
free_pages((unsigned long) virtAddr, get_order(dwLen));
}
#endif /* !__arm__ */
static void dev_munmap(struct vm_area_struct *vma)
{
ATEMSYS_T_MMAP_DESC *pMmapDesc = (ATEMSYS_T_MMAP_DESC *) vma->vm_private_data;
INF("dev_munmap: 0x%px -> 0x%px (%d)\n",
(void *) pMmapDesc->pVirtAddr, (void *)(unsigned long)pMmapDesc->dmaAddr, (int) pMmapDesc->len);
if (0 == pMmapDesc->dmaAddr) { INF("dev_munmap: 0 == pMmapDesc->dmaAddr!\n"); return; }
if (NULL == pMmapDesc->pVirtAddr) { INF("dev_munmap: NULL == pMmapDesc->pVirtAddr!\n"); return; }
/* free DMA memory */
#if (defined CONFIG_PCI)
if (pMmapDesc->pDevDesc->pPcidev == NULL)
#endif
{
#if (defined __arm__) || (defined __aarch64__)
dmam_free_coherent(&pMmapDesc->pDevDesc->pPlatformDev->dev, pMmapDesc->len, pMmapDesc->pVirtAddr, pMmapDesc->dmaAddr);
#else
dev_dma_free(pMmapDesc->len, pMmapDesc->pVirtAddr);
#endif
}
#if (defined CONFIG_PCI)
else
{
#if ((defined __aarch64__) \
|| (LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)) \
|| ((defined __arm__) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0))) \
|| ((defined __amd64__) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0))) )
dma_free_coherent(&pMmapDesc->pDevDesc->pPcidev->dev, pMmapDesc->len, pMmapDesc->pVirtAddr, pMmapDesc->dmaAddr);
#else
pci_free_consistent(pMmapDesc->pDevDesc->pPcidev, pMmapDesc->len, pMmapDesc->pVirtAddr, pMmapDesc->dmaAddr);
#endif /* __aarch64__ */
}
#endif /* CONFIG_PCI */
kfree(pMmapDesc);
}
#if (defined CONFIG_PCI)
/*
* Lookup PCI device
*/
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
{
struct pci_dev *dev = NULL;
for_each_pci_dev(dev) {
if (pci_domain_nr(dev->bus) == 0 &&
(dev->bus->number == bus && dev->devfn == devfn))
return dev;
}
return dev;
}
#endif
static int dev_pci_select_device(ATEMSYS_T_DEVICE_DESC* pDevDesc, ATEMSYS_T_PCI_SELECT_DESC* pciDesc, size_t size)
{
int nRetval = -EFAULT;
s32 nPciBus, nPciDev, nPciFun;
s32 nPciDomain = 0;
switch (size)
{
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_0_00):
{
ATEMSYS_T_PCI_SELECT_DESC_v1_0_00* pciDesc_v1_0_00 = (ATEMSYS_T_PCI_SELECT_DESC_v1_0_00*)pciDesc;
get_user(nPciBus, &pciDesc_v1_0_00->nPciBus);
get_user(nPciDev, &pciDesc_v1_0_00->nPciDev);
get_user(nPciFun, &pciDesc_v1_0_00->nPciFun);
} break;
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_3_05):
{
ATEMSYS_T_PCI_SELECT_DESC_v1_3_05* pciDesc_v1_3_05 = (ATEMSYS_T_PCI_SELECT_DESC_v1_3_05*)pciDesc;
get_user(nPciBus, &pciDesc_v1_3_05->nPciBus);
get_user(nPciDev, &pciDesc_v1_3_05->nPciDev);
get_user(nPciFun, &pciDesc_v1_3_05->nPciFun);
get_user(nPciDomain,&pciDesc_v1_3_05->nPciDomain);
} break;
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_4_12):
{
ATEMSYS_T_PCI_SELECT_DESC_v1_4_12* pciDesc_v1_4_12 = (ATEMSYS_T_PCI_SELECT_DESC_v1_4_12*)pciDesc;
get_user(nPciBus, &pciDesc_v1_4_12->nPciBus);
get_user(nPciDev, &pciDesc_v1_4_12->nPciDev);
get_user(nPciFun, &pciDesc_v1_4_12->nPciFun);
get_user(nPciDomain,&pciDesc_v1_4_12->nPciDomain);
} break;
default:
{
nRetval = -EFAULT;
ERR("pci_conf: EFAULT\n");
goto Exit;
}
}
/* Lookup for pci_dev object */
pDevDesc->pPcidev = NULL;
#if (defined INCLUDE_ATEMSYS_PCI_DRIVER)
pDevDesc->pPciDrvDesc = NULL;
{
unsigned int i = 0;
for (i = 0; i < ATEMSYS_MAX_NUMBER_DRV_INSTANCES; i++)
{
ATEMSYS_T_PCI_DRV_DESC_PRIVATE* pDrvInstance = S_apPciDrvDescPrivate[i];
if ( (pDrvInstance != NULL)
&& (pDrvInstance->nPciDomain == nPciDomain)
&& (pDrvInstance->nPciBus == nPciBus)
&& (pDrvInstance->nPciDev == nPciDev)
&& (pDrvInstance->nPciFun == nPciFun))
{
if (pDrvInstance->pDevDesc != NULL)
{
ERR("dev_pci_select_device: device \"%s\" in use by another instance?\n", pci_name(pDrvInstance->pPciDev));
nRetval = -EBUSY;
goto Exit;
}
pDevDesc->pPcidev = pDrvInstance->pPciDev;
pDevDesc->pPciDrvDesc = pDrvInstance;
pDrvInstance->pDevDesc = pDevDesc;
INF("pci_select: from pci driver %04x:%02x:%02x.%x\n", (u32)nPciDomain, (u32)nPciBus, (u32)nPciDev, (u32)nPciFun);
break;
}
}
}
if (pDevDesc->pPcidev == NULL)
#endif
{
pDevDesc->pPcidev = pci_get_domain_bus_and_slot(nPciDomain, nPciBus, PCI_DEVFN(nPciDev, nPciFun));
INF("pci_select: %04x:%02x:%02x.%x\n", (u32)nPciDomain, (u32)nPciBus, (u32)nPciDev, (u32)nPciFun);
}
if (pDevDesc->pPcidev == NULL)
{
WRN("pci_select: PCI-Device %04x:%02x:%02x.%x not found\n",
(unsigned) nPciDomain, (unsigned) nPciBus, (unsigned) nPciDev, (unsigned) nPciFun);
goto Exit;
}
nRetval = DRIVER_SUCCESS;
Exit:
return nRetval;
}
static int DefaultPciSettings(struct pci_dev* pPciDev)
{
int nRetval = -EIO;
int nRes = -EIO;
/* Turn on Memory-Write-Invalidate if it is supported by the device*/
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
pci_set_mwi(pPciDev);
#else
pci_try_set_mwi(pPciDev);
#endif
/* remove wrong dma_coherent bit on ARM systems */
#if ((defined __aarch64__) || (defined __arm__))
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,12,0))
#if (defined CONFIG_PHYS_ADDR_T_64BIT)
if (is_device_dma_coherent(&pPciDev->dev))
{
pPciDev->dev.archdata.dma_coherent = false;
INF("%s: DefaultPciSettings: Clear device.archdata dma_coherent bit!\n", pci_name(pPciDev));
}
#endif
#else
#if ((defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)))
if (0 != pPciDev->dev.dma_coherent)
{
pPciDev->dev.dma_coherent = 0;
INF("%s: DefaultPciSettings: Clear device dma_coherent bit!\n", pci_name(pPciDev));
}
#endif
#endif
#endif
#if ((LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0)) || !(defined __aarch64__))
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,12,55))
nRes = dma_set_coherent_mask(&pPciDev->dev, DMA_BIT_MASK(32));
#else
nRes = dma_set_mask_and_coherent(&pPciDev->dev, DMA_BIT_MASK(32));
#endif
if (nRes)
#endif
{
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,12,55))
nRes = dma_set_coherent_mask(&pPciDev->dev, DMA_BIT_MASK(64));
#else
nRes = dma_set_mask_and_coherent(&pPciDev->dev, DMA_BIT_MASK(64));
#endif
if (nRes)
{
ERR("%s: DefaultPciSettings: dma_set_mask_and_coherent failed\n", pci_name(pPciDev));
nRetval = nRes;
goto Exit;
}
}
pci_set_master(pPciDev);
/* Try to enable MSI (Message Signaled Interrupts). MSI's are non shared, so we can
* use interrupt mode, also if we have a non exclusive interrupt line with legacy
* interrupts.
*/
if (pci_enable_msi(pPciDev))
{
INF("%s: DefaultPciSettings: legacy INT configured\n", pci_name(pPciDev));
}
else
{
INF("%s: DefaultPciSettings: MSI configured\n", pci_name(pPciDev));
}
nRetval = 0;
Exit:
return nRetval;
}
/*
* See also kernel/Documentation/PCI/pci.txt for the recommended PCI initialization sequence
*/
static int ioctl_pci_configure_device(ATEMSYS_T_DEVICE_DESC* pDevDesc, unsigned long ioctlParam, size_t size)
{
int nRetval = -EIO;
int nRc;
int i;
unsigned long ioBase;
u32 dwIOLen;
s32 nBar = 0;
u32 dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,0,0);
ATEMSYS_T_PCI_SELECT_DESC_v1_4_12* pPciDesc_v1_4_12 = NULL;
ATEMSYS_T_PCI_SELECT_DESC_v1_3_05* pPciDesc_v1_3_05 = NULL;
ATEMSYS_T_PCI_SELECT_DESC_v1_0_00* pPciDesc_v1_0_00= NULL;
switch (size)
{
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_0_00):
{
dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,0,0);
pPciDesc_v1_0_00 = (ATEMSYS_T_PCI_SELECT_DESC_v1_0_00*)ioctlParam;
if (!ACCESS_OK(VERIFY_WRITE, pPciDesc_v1_0_00, sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_0_00)))
{
nRetval = -EFAULT;
}
} break;
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_3_05):
{
dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,3,5);
pPciDesc_v1_3_05 = (ATEMSYS_T_PCI_SELECT_DESC_v1_3_05*)ioctlParam;
if (!ACCESS_OK(VERIFY_WRITE, pPciDesc_v1_3_05, sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_3_05)))
{
nRetval = -EFAULT;
}
} break;
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_4_12):
{
dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,4,12);
pPciDesc_v1_4_12 = (ATEMSYS_T_PCI_SELECT_DESC_v1_4_12*)ioctlParam;
if (!ACCESS_OK(VERIFY_WRITE, pPciDesc_v1_4_12, sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_4_12)))
{
nRetval = -EFAULT;
}
} break;
default:
{
nRetval = -EFAULT;
}
}
if (-EFAULT == nRetval)
{
ERR("pci_conf: EFAULT\n");
goto Exit;
}
if (pDevDesc->pPcidev != NULL)
{
WRN("pci_conf: error call ioctl(ATEMSYS_IOCTL_PCI_RELEASE_DEVICE) first\n");
goto Exit;
}
if (dev_pci_select_device(pDevDesc, (ATEMSYS_T_PCI_SELECT_DESC*)ioctlParam, size) != DRIVER_SUCCESS)
{
goto Exit;
}
#if (defined INCLUDE_ATEMSYS_PCI_DRIVER)
if (NULL != pDevDesc->pPciDrvDesc)
{
for (i = 0; i < pDevDesc->pPciDrvDesc->nBarCnt ; i++)
{
if ((EC_ATEMSYSVERSION(1,4,12) != dwAtemsysApiVersion) && (pDevDesc->pPciDrvDesc->aBars[i].qwIOMem > 0xFFFFFFFF))
{
ERR("pci_conf: 64-Bit IO address not supported\n");
INF("pci_conf: Update LinkLayer for 64-Bit IO address support!\n");
nRetval = -ENODEV;
goto Exit;
}
switch (dwAtemsysApiVersion)
{
case EC_ATEMSYSVERSION(1,0,0):
{
put_user((u32)pDevDesc->pPciDrvDesc->aBars[i].qwIOMem, &(pPciDesc_v1_0_00->aBar[i].dwIOMem));
put_user(pDevDesc->pPciDrvDesc->aBars[i].dwIOLen, &(pPciDesc_v1_0_00->aBar[i].dwIOLen));
} break;
case EC_ATEMSYSVERSION(1,3,5):
{
put_user((u32)pDevDesc->pPciDrvDesc->aBars[i].qwIOMem, &(pPciDesc_v1_3_05->aBar[i].dwIOMem));
put_user(pDevDesc->pPciDrvDesc->aBars[i].dwIOLen, &(pPciDesc_v1_3_05->aBar[i].dwIOLen));
} break;
case EC_ATEMSYSVERSION(1,4,12):
{
put_user(pDevDesc->pPciDrvDesc->aBars[i].qwIOMem, &(pPciDesc_v1_4_12->aBar[i].qwIOMem));
put_user(pDevDesc->pPciDrvDesc->aBars[i].dwIOLen, &(pPciDesc_v1_4_12->aBar[i].dwIOLen));
} break;
}
}
switch (dwAtemsysApiVersion)
{
case EC_ATEMSYSVERSION(1,0,0):
{
put_user(pDevDesc->pPciDrvDesc->nBarCnt, &(pPciDesc_v1_0_00->nBarCnt));
put_user((u32)pDevDesc->pPcidev->irq, &(pPciDesc_v1_0_00->dwIrq));
} break;
case EC_ATEMSYSVERSION(1,3,5):
{
put_user(pDevDesc->pPciDrvDesc->nBarCnt, &(pPciDesc_v1_3_05->nBarCnt));
put_user((u32)pDevDesc->pPcidev->irq, &(pPciDesc_v1_3_05->dwIrq));
} break;
case EC_ATEMSYSVERSION(1,4,12):
{
put_user(pDevDesc->pPciDrvDesc->nBarCnt, &(pPciDesc_v1_4_12->nBarCnt));
put_user((u32)pDevDesc->pPcidev->irq, &(pPciDesc_v1_4_12->dwIrq));
} break;
}
}
else
#endif
{
/* enable device */
nRc = pci_enable_device(pDevDesc->pPcidev);
if (nRc < 0)
{
ERR("pci_conf: pci_enable_device failed\n");
pDevDesc->pPcidev = NULL;
goto Exit;
}
/* Check if IO-memory is in use by another driver */
nRc = pci_request_regions(pDevDesc->pPcidev, ATEMSYS_DEVICE_NAME);
if (nRc < 0)
{
ERR("pci_conf: device \"%s\" in use by another driver?\n", pci_name(pDevDesc->pPcidev));
pDevDesc->pPcidev = NULL;
nRetval = -EBUSY;
goto Exit;
}
/* find the memory BAR */
for (i = 0; i < ATEMSYS_PCI_MAXBAR ; i++)
{
if (pci_resource_flags(pDevDesc->pPcidev, i) & IORESOURCE_MEM)
{
/* IO area address */
ioBase = pci_resource_start(pDevDesc->pPcidev, i);
if ((EC_ATEMSYSVERSION(1,4,12) != dwAtemsysApiVersion) && (ioBase > 0xFFFFFFFF))
{
ERR("pci_conf: 64-Bit IO address not supported\n");
pci_release_regions(pDevDesc->pPcidev);
pDevDesc->pPcidev = NULL;
nRetval = -ENODEV;
goto Exit;
}
/* IO area length */
dwIOLen = pci_resource_len(pDevDesc->pPcidev, i);
switch (dwAtemsysApiVersion)
{
case EC_ATEMSYSVERSION(1,0,0):
{
put_user((u32)ioBase, &(pPciDesc_v1_0_00->aBar[nBar].dwIOMem));
put_user(dwIOLen, &(pPciDesc_v1_0_00->aBar[nBar].dwIOLen));
} break;
case EC_ATEMSYSVERSION(1,3,5):
{
put_user((u32)ioBase, &(pPciDesc_v1_3_05->aBar[nBar].dwIOMem));
put_user(dwIOLen, &(pPciDesc_v1_3_05->aBar[nBar].dwIOLen));
} break;
case EC_ATEMSYSVERSION(1,4,12):
{
put_user((u64)ioBase, &(pPciDesc_v1_4_12->aBar[nBar].qwIOMem));
put_user(dwIOLen, &(pPciDesc_v1_4_12->aBar[nBar].dwIOLen));
} break;
}
nBar++;
}
}
/* number of memory BARs */
switch (dwAtemsysApiVersion)
{
case EC_ATEMSYSVERSION(1,0,0):
{
put_user(nBar, &(pPciDesc_v1_0_00->nBarCnt));
} break;
case EC_ATEMSYSVERSION(1,3,5):
{
put_user(nBar, &(pPciDesc_v1_3_05->nBarCnt));
} break;
case EC_ATEMSYSVERSION(1,4,12):
{
put_user(nBar, &(pPciDesc_v1_4_12->nBarCnt));
} break;
}
nRc = DefaultPciSettings(pDevDesc->pPcidev);
if (nRc)
{
pci_release_regions(pDevDesc->pPcidev);
pDevDesc->pPcidev = NULL;
goto Exit;
}
/* assigned IRQ */
switch (dwAtemsysApiVersion)
{
case EC_ATEMSYSVERSION(1,0,0):
{
put_user((u32)pDevDesc->pPcidev->irq, &(pPciDesc_v1_0_00->dwIrq));
} break;
case EC_ATEMSYSVERSION(1,3,5):
{
put_user((u32)pDevDesc->pPcidev->irq, &(pPciDesc_v1_3_05->dwIrq));
} break;
case EC_ATEMSYSVERSION(1,4,12):
{
put_user((u32)pDevDesc->pPcidev->irq, &(pPciDesc_v1_4_12->dwIrq));
} break;
}
}
#if defined(__arm__) && 0
/*
* This is required for TI's TMDXEVM8168 (Cortex A8) eval board
* \sa TI "DM81xx AM38xx PCI Express Root Complex Driver User Guide"
* "DM81xx RC supports maximum remote read request size (MRRQS) as 256 bytes"
*/
pcie_set_readrq(pDevDesc->pPcidev, 256);
#endif
nRetval = 0;
Exit:
return nRetval;
}
static int ioctl_pci_finddevice(ATEMSYS_T_DEVICE_DESC* pDevDesc, unsigned long ioctlParam, size_t size)
{
int nRetval = -EIO;
struct pci_dev* pPciDev = NULL;
s32 nVendor, nDevice, nInstance, nInstanceId;
u32 dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,0,0);
ATEMSYS_T_PCI_SELECT_DESC_v1_0_00* pPciDesc_v1_0_00 = NULL;
ATEMSYS_T_PCI_SELECT_DESC_v1_3_05* pPciDesc_v1_3_05 = NULL;
ATEMSYS_T_PCI_SELECT_DESC_v1_4_12* pPciDesc_v1_4_12 = NULL;
switch (size)
{
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_0_00):
{
dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,0,0);
pPciDesc_v1_0_00 = (ATEMSYS_T_PCI_SELECT_DESC_v1_0_00*)ioctlParam;
if (!ACCESS_OK(VERIFY_WRITE, pPciDesc_v1_0_00, sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_0_00)))
{
nRetval = -EFAULT;
}
} break;
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_3_05):
{
dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,3,5);
pPciDesc_v1_3_05 = (ATEMSYS_T_PCI_SELECT_DESC_v1_3_05*)ioctlParam;
if (!ACCESS_OK(VERIFY_WRITE, pPciDesc_v1_3_05, sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_3_05)))
{