diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index 7036c52bd7..a3bc1e7265 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -171,6 +171,10 @@ jobs: if: always() run: | (cd examples && ../tools/scripts/examples_compile.py nucleo_l552ze-q) + - name: Examples STM32U0 Series + if: always() + run: | + (cd examples && ../tools/scripts/examples_compile.py stm32u083c_dk) - name: Examples STM32U5 Series if: always() run: | diff --git a/.gitmodules b/.gitmodules index 8658da233d..c6969d897b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -3,7 +3,8 @@ url = https://github.com/modm-io/cmsis-header-stm32.git [submodule "ext/modm-devices"] path = ext/modm-devices - url = https://github.com/modm-io/modm-devices.git + url = https://github.com/FranzForstmayr/modm-devices.git + branch = stm32u0 [submodule "ext/ros/ros-lib"] path = ext/ros/ros-lib url = https://github.com/modm-io/ros-lib diff --git a/examples/stm32u083c_dk/blink/main.cpp b/examples/stm32u083c_dk/blink/main.cpp new file mode 100644 index 0000000000..fb343fdec3 --- /dev/null +++ b/examples/stm32u083c_dk/blink/main.cpp @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024, Franz Forstmayr + * + * This file is part of the modm project. + * + * This Source Code Form is subject to the terms of the Mozilla Public + * License, v. 2.0. If a copy of the MPL was not distributed with this + * file, You can obtain one at http://mozilla.org/MPL/2.0/. + */ + +#include + +using namespace Board; + +int +main() +{ + Board::initialize(); + + LedGreen::set(); + LedBlue::reset(); + + while (true) { + LedGreen::toggle(); + LedBlue::toggle(); + modm::delay(Board::Button::read() ? 0.5s : 1s); + } +} diff --git a/examples/stm32u083c_dk/blink/project.xml b/examples/stm32u083c_dk/blink/project.xml new file mode 100644 index 0000000000..44be0cf044 --- /dev/null +++ b/examples/stm32u083c_dk/blink/project.xml @@ -0,0 +1,9 @@ + + modm:disco-u083c + + + + + modm:build:scons + + diff --git a/examples/stm32u083c_dk/logger/main.cpp b/examples/stm32u083c_dk/logger/main.cpp new file mode 100644 index 0000000000..4fa8b89d09 --- /dev/null +++ b/examples/stm32u083c_dk/logger/main.cpp @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2024, Franz Forstmayr + * + * This file is part of the modm project. + * + * This Source Code Form is subject to the terms of the Mozilla Public + * License, v. 2.0. If a copy of the MPL was not distributed with this + * file, You can obtain one at http://mozilla.org/MPL/2.0/. + */ + +#include +#include +#include + +// ---------------------------------------------------------------------------- +// Set the log level +#undef MODM_LOG_LEVEL +#define MODM_LOG_LEVEL modm::log::INFO + +// Create an IODeviceWrapper around the Uart Peripheral we want to use +using Usart1 = BufferedUart>; +modm::IODeviceWrapper< Usart1, modm::IOBuffer::BlockIfFull > loggerDevice; + +// Set all four logger streams to use the UART +modm::log::Logger modm::log::debug(loggerDevice); +modm::log::Logger modm::log::info(loggerDevice); +modm::log::Logger modm::log::warning(loggerDevice); +modm::log::Logger modm::log::error(loggerDevice); + +int +main() +{ + Board::initialize(); + + // initialize Uart1 for MODM_LOG_* + Usart1::connect(); + Usart1::initialize(); + + // Use the logging streams to print some messages. + // Change MODM_LOG_LEVEL above to enable or disable these messages + MODM_LOG_DEBUG << "debug" << modm::endl; + MODM_LOG_INFO << "info" << modm::endl; + MODM_LOG_WARNING << "warning" << modm::endl; + MODM_LOG_ERROR << "error" << modm::endl; + + Board::LedBlue::reset(); + + uint32_t ii(1); + modm::Timeout timeout; + + while (true) { + Board::LedBlue::set(); + timeout.restart(100ms); + while(not timeout.isExpired()) + {}; + + Board::LedBlue::reset(); + timeout.restart(900ms); + while(not timeout.isExpired()) + {}; + + MODM_LOG_INFO << "Seconds since reboot: " << ii++ << modm::endl; + } +} diff --git a/examples/stm32u083c_dk/logger/project.xml b/examples/stm32u083c_dk/logger/project.xml new file mode 100644 index 0000000000..55c43935e4 --- /dev/null +++ b/examples/stm32u083c_dk/logger/project.xml @@ -0,0 +1,13 @@ + + modm:disco-u083c + + + + + modm:debug + modm:platform:gpio + modm:platform:uart:1 + modm:processing:timer + modm:build:scons + + diff --git a/ext/modm-devices b/ext/modm-devices index 7d5855812d..56ef5a7910 160000 --- a/ext/modm-devices +++ b/ext/modm-devices @@ -1 +1 @@ -Subproject commit 7d5855812d5657f1e65335d2f85be3f6820201df +Subproject commit 56ef5a7910b5d1fcbda71a1cb9ba9adbbc27b39c diff --git a/repo.lb b/repo.lb index ace0a02dcc..c6eba469bc 100644 --- a/repo.lb +++ b/repo.lb @@ -87,7 +87,7 @@ class DevicesCache(dict): "stm32g0", "stm32g4", "stm32h7", "stm32l0", "stm32l1", "stm32l4", "stm32l5", - "stm32u5", + "stm32u0", "stm32u5", "at90", "attiny", "atmega", "samd21", "samg55", "same70", "sams70", "samv70", "samv71", diff --git a/src/modm/board/disco_u083c/board.hpp b/src/modm/board/disco_u083c/board.hpp new file mode 100644 index 0000000000..decbea1774 --- /dev/null +++ b/src/modm/board/disco_u083c/board.hpp @@ -0,0 +1,81 @@ +// coding: utf-8 +/* + * Copyright (c) 2024, Franz Forstmayr + * + * This file is part of the modm project. + * + * This Source Code Form is subject to the terms of the Mozilla Public + * License, v. 2.0. If a copy of the MPL was not distributed with this + * file, You can obtain one at http://mozilla.org/MPL/2.0/. + */ +// ---------------------------------------------------------------------------- + +#ifndef MODM_STM32_U083_DK_HPP +#define MODM_STM32_U083_DK_HPP + +#include +#include + +using namespace modm::platform; + +namespace Board +{ +/// @ingroup modm_board_stm32u83_dk +/// @{ +using namespace modm::literals; + +/// STM32F0 running at 48MHz generated from the internal 8MHz with PLL. +struct SystemClock +{ + static constexpr int Frequency = 48_MHz; + static constexpr int Usart1 = Frequency; + static constexpr int Usart2 = Frequency; + static constexpr int Spi2 = Frequency; + static constexpr uint32_t Iwdg = Rcc::LsiFrequency; + + static bool inline + enable() + { + // enable internal 8 MHz HSI RC clock + Rcc::enableInternalClock(); + // (internal clock / 2) * 12 = 48MHz + const Rcc::PllFactors pllFactors{ + .pllM = 4, + }; + Rcc::enablePll(Rcc::PllSource::Hse, pllFactors); + // set flash latency for 48MHz + Rcc::setFlashLatency(); + // switch system clock to PLL output + Rcc::enableSystemClock(Rcc::SystemClockSource::Pll); + Rcc::setAhbPrescaler(Rcc::AhbPrescaler::Div1); + Rcc::setApbPrescaler(Rcc::ApbPrescaler::Div1); + // update frequencies for busy-wait delay functions + Rcc::updateCoreFrequency(); + + return true; + } +}; + +using Button = GpioInputA0; + +using LedGreen = GpioOutputC9; +using LedBlue = GpioOutputC8; + +using Leds = SoftwareGpioPort< LedGreen, LedBlue >; + +inline void +initialize() +{ + SystemClock::enable(); + SysTickTimer::initialize(); + + LedGreen::setOutput(modm::Gpio::Low); + LedBlue::setOutput(modm::Gpio::Low); + + Button::setInput(); +} +/// @} + +} // namespace Board + +#endif // MODM_STM32_U083_DK_HPP diff --git a/src/modm/board/disco_u083c/board.xml b/src/modm/board/disco_u083c/board.xml new file mode 100644 index 0000000000..c555bdeacb --- /dev/null +++ b/src/modm/board/disco_u083c/board.xml @@ -0,0 +1,16 @@ + + + + ../../../../repo.lb + + + + + + + + + + modm:board:disco-u083c + + diff --git a/src/modm/board/disco_u083c/module.lb b/src/modm/board/disco_u083c/module.lb new file mode 100644 index 0000000000..a68a7bc928 --- /dev/null +++ b/src/modm/board/disco_u083c/module.lb @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (c) 2024, Franz Forstmayr +# +# This file is part of the modm project. +# +# This Source Code Form is subject to the terms of the Mozilla Public +# License, v. 2.0. If a copy of the MPL was not distributed with this +# file, You can obtain one at http://mozilla.org/MPL/2.0/. +# ----------------------------------------------------------------------------- + +def init(module): + module.name = ":board:disco-u083c" + module.description = """\ +# STM32U083C-DK + +[Discovery kit for STM32U083](https://www.st.com/en/evaluation-tools/stm32u083c-dk.html) +""" + +def prepare(module, options): + if not options[":target"].partname.startswith("stm32u083mct"): + return False + + module.depends( + ":architecture:clock", + ":platform:clock", + ":platform:core", + ":platform:gpio") + return True + +def build(env): + env.outbasepath = "modm/src/modm/board" + env.substitutions = { + "with_logger": False, + "with_assert": env.has_module(":architecture:assert") + } + env.template("../board.cpp.in", "board.cpp") + env.copy('.') + env.collect(":build:openocd.source") diff --git a/src/modm/board/disco_u083c/openocd.cfg b/src/modm/board/disco_u083c/openocd.cfg new file mode 100644 index 0000000000..a2f1387976 --- /dev/null +++ b/src/modm/board/disco_u083c/openocd.cfg @@ -0,0 +1,44 @@ +# This is an STM32U083C-DK board with a single STM32U083MCTx chip +# +# Generated by STM32CubeIDE +# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s) + +source [find interface/stlink-dap.cfg] + + +set WORKAREASIZE 0x8000 + +transport select "dapdirect_swd" + +set CHIPNAME STM32U083MCTx +set BOARDNAME STM32U083C-DK + +# Enable debug when in low power modes +set ENABLE_LOW_POWER 1 + +# Stop Watchdog counters when halt +set STOP_WATCHDOG 1 + +# STlink Debug clock frequency +set CLOCK_FREQ 8000 + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +reset_config srst_only srst_nogate connect_assert_srst +set CONNECT_UNDER_RESET 1 +set CORE_RESET 0 + +# ACCESS PORT NUMBER +set AP_NUM 0 +# GDB PORT +set GDB_PORT 3333 + + + + + +# BCTM CPU variables + +source [find target/stm32u0x.cfg] + diff --git a/src/modm/platform/adc/stm32/module.lb b/src/modm/platform/adc/stm32/module.lb index daa42f642b..4f65b15c23 100644 --- a/src/modm/platform/adc/stm32/module.lb +++ b/src/modm/platform/adc/stm32/module.lb @@ -79,7 +79,7 @@ def prepare(module, options): if target["family"] in ["f2", "f4", "f7"]: props["shared_irqs"] = {"ADC": listify([int(i) for i in device.get_driver("adc")["instance"]])} props["shared_irq_ids"] = props["shared_irqs"]["ADC"] - elif target["family"] in ["u5"]: + elif target["family"] in ["u5", "u0"]: # STM32U5 is not yet supported with any ADC implementation im modm return False else: diff --git a/src/modm/platform/clock/stm32/rcc.cpp.in b/src/modm/platform/clock/stm32/rcc.cpp.in index 62d6dd9f8a..4e843665ec 100644 --- a/src/modm/platform/clock/stm32/rcc.cpp.in +++ b/src/modm/platform/clock/stm32/rcc.cpp.in @@ -266,7 +266,7 @@ Rcc::enablePll{{id}}(PllSource source, const PllFactors& pllFactors, uint32_t wa ; return tmp; -%% elif target.family in ["g0", "l4", "l5", "g4"] +%% elif target.family in ["g0", "l4", "l5", "g4", "u0"] // Read reserved values and clear all other values uint32_t tmp = RCC->PLLCFGR & ~( RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | diff --git a/src/modm/platform/clock/stm32/rcc.hpp.in b/src/modm/platform/clock/stm32/rcc.hpp.in index 72a379e84a..9b1134e542 100644 --- a/src/modm/platform/clock/stm32/rcc.hpp.in +++ b/src/modm/platform/clock/stm32/rcc.hpp.in @@ -86,7 +86,7 @@ public: InternalClock = Hsi16, /// High speed external clock Hse = RCC_CFGR_PLLSRC, -%% elif target.family == "l5" +%% elif target.family in ["l5"] /// High speed internal clock (16 MHz) Hsi = RCC_PLLCFGR_PLLSRC_1, Hsi16 = Hsi, @@ -96,7 +96,7 @@ public: /// Multi speed internal clock Msi = RCC_PLLCFGR_PLLSRC_0, MultiSpeedInternalClock = Msi, -%% elif target.family in ["u5"] +%% elif target.family in ["u0", "u5"] None = 0b00, MsiS = 0b01, Hsi16 = 0b10, @@ -134,17 +134,21 @@ public: enum class SystemClockSource : uint32_t { -%% if target.family == "l5" +%% if target.family in ["l5"] Msi = 0, Hsi = RCC_CFGR_SW_0, Hsi16 = Hsi, Hse = RCC_CFGR_SW_1, Pll = RCC_CFGR_SW_1 | RCC_CFGR_SW_0, -%% elif target.family in ["u5"] +%% elif target.family in ["u0", "u5"] Msi = 0b00, Hsi16 = 0b01, Hse = 0b10, Pll = 0b11, + %% if target.family in ["u0"] + Lsi = 0b100, + Lse = 0b101, + %% endif %% else Hsi = RCC_CFGR_SW_HSI, %% if target.family == "l0" @@ -194,7 +198,7 @@ public: enum class AhbPrescaler : uint32_t { -%% if target.family in ["l5", "u5"] +%% if target.family in ["l5", "u0", "u5"] Div1 = 0b0000 << RCC_{{cfgr_prescaler}}_HPRE_Pos, Div2 = 0b1000 << RCC_{{cfgr_prescaler}}_HPRE_Pos, Div4 = 0b1001 << RCC_{{cfgr_prescaler}}_HPRE_Pos, @@ -227,6 +231,16 @@ public: Div8 = RCC_CFGR_PPRE_DIV8, Div16 = RCC_CFGR_PPRE_DIV16 }; +%% elif target.family in ["u0"] + enum class + ApbPrescaler : uint32_t + { + Div1 = RCC_CFGR_PPRE_0, + Div2 = RCC_CFGR_PPRE_2, + Div4 = RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0, + Div8 = RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1, + Div16 = RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0 + }; %% else enum class Apb1Prescaler : uint32_t @@ -255,6 +269,7 @@ public: Div4 = 0b101 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE2_Pos, Div8 = 0b110 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE2_Pos, Div16 = 0b111 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE2_Pos +%% elif target.family == "u0" %% else Div1 = RCC_{{cfgr2}}_{{d2}}PPRE2_DIV1, Div2 = RCC_{{cfgr2}}_{{d2}}PPRE2_DIV2, @@ -355,6 +370,7 @@ public: }; %% endif +%% set cfgr_mco="CFGR1" if target.family in ["u5"] else "CFGR" %% if target.family in ["f2", "f4", "f7"] enum class ClockOutput1Source : uint32_t @@ -396,8 +412,37 @@ public: Csi = RCC_CFGR_MCO2_2, Lsi = RCC_CFGR_MCO2_2 | RCC_CFGR_MCO2_0 }; +%% elif target.family in ["u0"] + enum class + ClockOutput1Source : uint32_t + { + Disable = 0b0000, + SystemClock = RCC_CFGR_MCO1SEL_0, + MultiSpeedInternalClockS = RCC_CFGR_MCO1SEL_1, + Hsi16 = RCC_CFGR_MCO1SEL_0 | RCC_CFGR_MCO1SEL_1, + Hse = RCC_CFGR_MCO1SEL_2, + Pll = RCC_CFGR_MCO1SEL_2 | RCC_CFGR_MCO1SEL_0, + Lsi = RCC_CFGR_MCO1SEL_2 | RCC_CFGR_MCO1SEL_1, + Lse = RCC_CFGR_MCO1SEL_2 | RCC_CFGR_MCO1SEL_1 | RCC_CFGR_MCO1SEL_0, + Hsi48 = RCC_CFGR_MCO1SEL_3, + MsiK = RCC_CFGR_MCO1SEL_3 | RCC_CFGR_MCO1SEL_0 + }; + + enum class + ClockOutput2Source : uint32_t + { + Disable = 0b0000, + SystemClock = RCC_CFGR_MCO2SEL_0, + MultiSpeedInternalClockS = RCC_CFGR_MCO2SEL_1, + Hsi16 = RCC_CFGR_MCO2SEL_0 | RCC_CFGR_MCO2SEL_1, + Hse = RCC_CFGR_MCO2SEL_2, + Pll = RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0, + Lsi = RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1, + Lse = RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0, + Hsi48 = RCC_CFGR_MCO2SEL_3, + MsiK = RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0 + }; %% elif target.family in ["l0", "l1", "l4", "l5", "g0", "g4", "u5"] -%% set cfgr_mco="CFGR1" if target.family in ["u5"] else "CFGR" enum class ClockOutputSource : uint32_t { @@ -625,6 +670,12 @@ public: uint8_t pllQ; uint8_t pllR; uint16_t pllFrac = 0; +%% elif target.family in ["u0"] + uint8_t pllM; + uint16_t pllN; + uint8_t pllP; + uint8_t pllQ; + uint8_t pllR; %% elif target.family in ["u5"] PllInputRange range; uint8_t pllM; @@ -835,6 +886,54 @@ public: RCC->CFGR = tmp | uint32_t(src); return true; } +%% elif target.family in ["u0"] + enum class + ClockOutput1Prescaler : uint32_t + { + Div1 = 0x0UL << RCC_CFGR_MCO1PRE_Pos, + Div2 = 0x1UL << RCC_CFGR_MCO1PRE_Pos, + Div4 = 0x2UL << RCC_CFGR_MCO1PRE_Pos, + Div8 = 0x3UL << RCC_CFGR_MCO1PRE_Pos, + Div16 = 0x4UL << RCC_CFGR_MCO1PRE_Pos, + Div32 = 0x5UL << RCC_CFGR_MCO1PRE_Pos, + Div64 = 0x6UL << RCC_CFGR_MCO1PRE_Pos, + Div128 = 0x7UL << RCC_CFGR_MCO1PRE_Pos, + Div256 = 0x8UL << RCC_CFGR_MCO1PRE_Pos, + Div512 = 0x9UL << RCC_CFGR_MCO1PRE_Pos, + Div1024 = 0xaUL << RCC_CFGR_MCO1PRE_Pos, + }; + + static inline bool + enableClockOutput1(ClockOutput1Source src, ClockOutput1Prescaler div = ClockOutput1Prescaler::Div1) + { + RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_MCO1PRE)) | uint32_t(src) | uint32_t(div); + return true; + } + + enum class + ClockOutput2Prescaler : uint32_t + { + Div1 = 0x0UL << RCC_CFGR_MCO2PRE_Pos, + Div2 = 0x1UL << RCC_CFGR_MCO2PRE_Pos, + Div4 = 0x2UL << RCC_CFGR_MCO2PRE_Pos, + Div8 = 0x3UL << RCC_CFGR_MCO2PRE_Pos, + Div16 = 0x4UL << RCC_CFGR_MCO2PRE_Pos, + Div32 = 0x5UL << RCC_CFGR_MCO2PRE_Pos, + Div64 = 0x6UL << RCC_CFGR_MCO2PRE_Pos, + Div128 = 0x7UL << RCC_CFGR_MCO2PRE_Pos, + Div256 = 0x8UL << RCC_CFGR_MCO2PRE_Pos, + Div512 = 0x9UL << RCC_CFGR_MCO2PRE_Pos, + Div1024 = 0xaUL << RCC_CFGR_MCO2PRE_Pos, + }; + + static inline bool + enableClockOutput2(ClockOutput2Source src, ClockOutput2Prescaler div = ClockOutput2Prescaler::Div1) + { + RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_MCO2PRE)) | uint32_t(src) | uint32_t(div); + return true; + } + + %% elif target.family in ["l0", "l1", "l4", "l5", "g0", "g4", "u5"] enum class ClockOutputPrescaler : uint32_t @@ -874,7 +973,7 @@ public: return true; } -%% if target.family in ["f0", "g0"] +%% if target.family in ["f0", "g0", "u0"] static inline bool setApbPrescaler(ApbPrescaler prescaler) { diff --git a/src/modm/platform/clock/stm32/rcc_impl.hpp.in b/src/modm/platform/clock/stm32/rcc_impl.hpp.in index f71428ec39..59666a0823 100644 --- a/src/modm/platform/clock/stm32/rcc_impl.hpp.in +++ b/src/modm/platform/clock/stm32/rcc_impl.hpp.in @@ -63,7 +63,7 @@ Rcc::setFlashLatency() %% if target["family"] in ["f2", "f4", "l4", "g4"] // enable flash prefetch and data and instruction cache acr |= FLASH_ACR_PRFTEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN; -%% elif target["family"] in ["g0"] +%% elif target["family"] in ["g0", "u0"] // enable flash prefetch and instruction cache acr |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN; %% elif target["family"] == "f7" diff --git a/src/modm/platform/core/stm32/module.lb b/src/modm/platform/core/stm32/module.lb index 8e0141b5c4..68a1cd6462 100644 --- a/src/modm/platform/core/stm32/module.lb +++ b/src/modm/platform/core/stm32/module.lb @@ -59,6 +59,7 @@ def build(env): "g4": (3, 4), # CM4 tested on G476 in RAM "l0": (3, 4), # CM0+ tested on L031 in RAM "g0": (3, 4), # CM0+ tested on G072 in RAM + "u0": (3, 4), # CM0+ untested "f7": (4, 4), # CM7 tested on F767 in ITCM "h7": (4, 4), # CM7 tested on H743 in ITCM "l4": (3, 4), # CM4 tested on L476 in SRAM2 diff --git a/src/modm/platform/core/stm32/startup_platform.c.in b/src/modm/platform/core/stm32/startup_platform.c.in index 5764524b36..f850447031 100644 --- a/src/modm/platform/core/stm32/startup_platform.c.in +++ b/src/modm/platform/core/stm32/startup_platform.c.in @@ -29,12 +29,14 @@ void __modm_initialize_platform(void) { // Enable SYSCFG -%% if target.family == "g0" +%% if target.family in ["g0", "u0"] RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN; %% elif target.family == "f1" RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; %% elif target.family == "h7" RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; +%% elif target.family == "u0" + RCC->AHBENR |= RCC_APBENR2_SYSCFGEN; %% elif target.family == "u5" RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN; %% else diff --git a/src/modm/platform/gpio/stm32/enable.cpp.in b/src/modm/platform/gpio/stm32/enable.cpp.in index 701fb88c13..9803685098 100644 --- a/src/modm/platform/gpio/stm32/enable.cpp.in +++ b/src/modm/platform/gpio/stm32/enable.cpp.in @@ -28,7 +28,7 @@ modm_gpio_enable(void) %% set prefix = "IOP" %% elif target.family in ["l4", "l5", "g4", "u5"] %% set clock_tree = 'AHB2' -%% elif target.family in ["g0", "l0"] +%% elif target.family in ["g0", "l0", "u0"] %% set clock_tree = 'IOP' %% endif