[stm32] Use register map query for RCC module

Author: salkinium

src/modm/platform/clock/stm32/module.lb

@@ -32,7 +32,7 @@ def build(env):
     driver = device.get_driver("rcc")
     regs = env.query(":cmsis:device:registers")
 
-    properties = {}
+    properties = {"regs": regs}
     properties["target"] = target = device.identifier
     properties["partname"] = device.partname
     properties["core"] = core = device.get_driver("core")["type"]
@@ -64,23 +64,34 @@ def build(env):
         properties["lsi_frequency"] = 32_000
         properties["boot_frequency"] = properties["hsi_frequency"]
 
+    properties["hsi48"] = regs.search(r"RCC_(.*?)_HSI48ON")
+    properties["bdcr"] = regs.search(r"RCC_(.*?)_RTCSEL_\d")
+    properties["usbprescaler"] = regs.search("RCC_CFGR_USBPRE")
+    properties["pll_input_range"] = regs.findall("RCC_.*?_PLL1RGE_\d")
+
+    # STM32H7 map of domains to APB bus index
+    name_map = {
+        "D1": 3, "D21": 1, "D22": 2, "D3": 4,
+        "CD": 3, "CD1": 1, "CD2": 2, "SRD": 4}
+    bus_prescalers = defaultdict(list)
+    for whole, reg, domain, index, div in regs.findall("(RCC_(.*?)_(.*?)PPRE(\d?)_DIV(\d+))"):
+        bus_prescalers[name_map.get(domain+index, index)].append((whole, reg, div))
+    # Not all header define the _DIV enumerations, so we manually add them here…
+    if not bus_prescalers:
+        for whole, reg, domain, index in regs.findall("(RCC_(.*?)_(.*?)PPRE(\d?))"):
+            for div, value in enumerate((0b000, 0b100, 0b101, 0b110, 0b111)):
+                value = (f"{value} << {whole}_Pos", reg, 2**div)
+                bus_prescalers[name_map.get(domain+index, index)].append(value)
+    properties["bus_prescalers"] = bus_prescalers
+    import pprint
+    pprint.pprint(bus_prescalers)
+
     # TODO: Move this data into the device files
-    properties["usbprescaler"] = device.has_driver("usb") and target.family in ["f0", "f1", "f3"]
     properties["pllprediv"] = \
         (target["family"] in ["f0", "f3"] or (target["family"] == "f1" and target["name"] in ["00", "05", "07"]))
     properties["pllprediv2"] = False    # FIXME: not sure what value this should have
     properties["pll_hse_prediv2"] = target["family"] == "f1" and target["name"] in ["01", "02", "03"]
-    properties["hsi48"] = \
-        (target["family"] == "f0" and target["name"] in ["42", "48", "71", "72", "78", "91", "98"]) or \
-        (target["family"] == "l4" and target["name"][0] not in ["7", "8"]) or \
-        (target["family"] == "l5") or \
-        (target["family"] == "u5")
-    if target["family"] in ["l4", "l5"]:
-        properties["hsi48_cr"] = "CRRCR"
-    elif target["family"] in ["c0", "u5"]:
-        properties["hsi48_cr"] = "CR"
-    else:
-        properties["hsi48_cr"] = "CR2"
+
     properties["pll_p"] = ((target["family"] == "l4" and target["name"] not in ["12", "22"]) or target["family"] == "g4")
     properties["overdrive"] = (target["family"] == "f7") or \
         ((target["family"] == "f4") and target["name"] in ["27", "29", "37", "39", "46", "69", "79"])
@@ -127,7 +138,6 @@ def build(env):
                         if target.family == "h7" else ""
     properties["cfgr3"] = ("SRDCFGR" if target.name in ["a0", "a3", "b0", "b3"] else "D3CFGR")
     properties["d3"] = ("SRD" if target.name in ["a0", "a3", "b0", "b3"] else "D3")
-    properties["bdcr"] = "CSR1" if target.family in ["c0"] else "CSR" if target.family in ["l0", "l1"] else "BDCR"
     properties["pll_ids"] = ["1", "2", "3"] if target.family in ["h7", "u5"] else [] if target.family in ["c0"] else [""]
     properties["has_smps"] = target["family"] == "h7" and (target["name"] in ["25", "35", "45", "47", "55", "57"] or \
         (target["name"] in ["30", "a3", "b0", "b3"] and target["variant"] == "q"))
@@ -145,7 +155,7 @@ def build(env):
 
     all_peripherals = env.query(":cmsis:device:peripherals")
     rcc_map = defaultdict(dict)
-    for (reg, per, typ) in regs.findall(r"RCC_([A-Z0-9]*?)_([A-Z0-9]+?)(EN|RST)"):
+    for (reg, per, typ) in regs.findall(r"RCC_(A[HP]B\d?(?:ENR|RSTR)\d?)_(.*?)(EN|RST)"):
         rcc_map[per][typ] = reg
     rcc_enable = {}
     rcc_reset = {}

src/modm/platform/clock/stm32/rcc.cpp.in

@@ -44,8 +44,8 @@ bool
 Rcc::enableInternalClockMHz48(uint32_t waitCycles)
 {
 	bool retval;
-	RCC->{{hsi48_cr}} |= RCC_{{hsi48_cr}}_HSI48ON;
-	while (not (retval = (RCC->{{hsi48_cr}} & RCC_{{hsi48_cr}}_HSI48RDY)) and --waitCycles)
+	RCC->{{hsi48}} |= RCC_{{hsi48}}_HSI48ON;
+	while (not (retval = (RCC->{{hsi48}} & RCC_{{hsi48}}_HSI48RDY)) and --waitCycles)
 		;
 	return retval;
 }