Main Cache Entity

[miloliebster]

Cache > VHDL

Main parametric cache component

• set generation
• set selection logic
• external interface

[miloliebster]

since this is the outside facing part of the cache, I need to have a better idea of what exactly the interface will look like between the memory controller and the cache before I can write this. The hard part of the cache is all complete. all this unit requires is a generate loop of cache_set s, a decoder for the 5 set bits of the address, and the external pin designations.