diff --git a/lld/test/ELF/eravm-binary-layout.s b/lld/test/ELF/eravm-binary-layout.s
index f3d5c7ad636f..20cd130dc248 100644
--- a/lld/test/ELF/eravm-binary-layout.s
+++ b/lld/test/ELF/eravm-binary-layout.s
@@ -7,7 +7,7 @@
 
         .text
 	nop	stack+=[2 + r0]
-	add	@glob_initializer[0], r0, stack[@glob]
+	add	code[@glob_initializer], r0, stack[@glob]
 
 	.globl	get_glob
 get_glob:
diff --git a/lld/test/ELF/eravm-code-reloc.s b/lld/test/ELF/eravm-code-reloc.s
index 386ffe9bf896..5f55544cf1d5 100644
--- a/lld/test/ELF/eravm-code-reloc.s
+++ b/lld/test/ELF/eravm-code-reloc.s
@@ -68,7 +68,7 @@ foo_local:
 caller_g:
   near_call r1, @foo, @handler
   far_call  r3, r4, @foo
-  add   @.OUTLINED_FUNCTION_RET0[0], r0, stack-[1]
+  add   @.OUTLINED_FUNCTION_RET0, r0, stack-[1]
   jump  @foo_local
 .OUTLINED_FUNCTION_RET0:
   jump @label
@@ -77,7 +77,7 @@ caller_g:
   ret.panic.to_label @label
   .globl label
 label:
-  jump @jump_table[1]
+  jump code[@jump_table + 1]
   ret
 ; INPUT-LABEL: <caller_g>:
 ; INPUT-NEXT:  00 00 00 00 00 01 04 0f        near_call       r1, 0, 0
@@ -85,7 +85,7 @@ label:
 ; INPUT-NEXT:                 R_ERAVM_16_SCALE_8      foo
 ; INPUT-NEXT:  00 00 00 00 00 43 04 21        far_call        r3, r4, 0
 ; INPUT-NEXT:                 R_ERAVM_16_SCALE_8      foo
-; INPUT-NEXT:  00 01 00 00 00 00 00 45 add code[0], r0, stack-[1 + r0]
+; INPUT-NEXT:  00 01 00 00 00 00 00 3d add 0, r0, stack-[1 + r0]
 ; INPUT-NEXT:                 R_ERAVM_16_SCALE_8 .text+0x40
 ; INPUT-NEXT:  00 00 00 00 00 00 01 3d        jump    0
 ; INPUT-NEXT:                 R_ERAVM_16_SCALE_8  .text+0x18
@@ -105,7 +105,7 @@ label:
 ; OUTPUT-LABEL: <caller_g>:
 ; OUTPUT-NEXT:  00 12 00 13 00 01 04 0f        near_call       r1, 19, 18
 ; OUTPUT-NEXT:  00 00 00 13 00 43 04 21        far_call        r3, r4, 19
-; OUTPUT-NEXT:  00 01 00 18 00 00 00 45        add     code[24], r0, stack-[1 + r0]
+; OUTPUT-NEXT:  00 01 00 18 00 00 00 3d        add     24, r0, stack-[1 + r0]
 ; OUTPUT-NEXT:  00 00 00 13 00 00 01 3d        jump    19
 ; OUTPUT-NEXT:  00 00 00 1c 00 00 01 3d        jump    28
 ; OUTPUT-NEXT:  00 00 00 1c 00 01 04 2e        ret.ok.to_label r1, 28
@@ -127,7 +127,7 @@ caller_l:
   ret.panic.to_label @label_local
   .local label_local
 label_local:
-  jump @jump_table_local[1]
+  jump code[@jump_table_local + 1]
   ret
 
 ; INPUT-LABEL: <caller_l>:
diff --git a/lld/test/ELF/eravm-data-reloc.s b/lld/test/ELF/eravm-data-reloc.s
index aa413e983aff..51b8b66fbca1 100644
--- a/lld/test/ELF/eravm-data-reloc.s
+++ b/lld/test/ELF/eravm-data-reloc.s
@@ -75,9 +75,9 @@ array_const_local:
   .text
   .p2align 3
 reloc_src_g:
-  add @scalar_const[0], r1, r1
+  add code[@scalar_const], r1, r1
   add stack[@scalar_var], r1, r1
-  add @array_const[1], r1, r1
+  add code[@array_const + 1], r1, r1
   add stack[@array_var + 1], r1, r1
   ret
 ; INPUT-LABEL: <reloc_src_g>:
@@ -99,9 +99,9 @@ reloc_src_g:
 ; OUTPUT-NEXT:  00 00 00 00 00 01 04 2d        ret
 
 reloc_src_l:
-  add @scalar_const_local[0], r1, r1
+  add code[@scalar_const_local], r1, r1
   add stack[@scalar_var_local], r1, r1
-  add @array_const_local[1], r1, r1
+  add code[@array_const_local + 1], r1, r1
   add stack[@array_var_local + 1], r1, r1
   ret
 ; INPUT-LABEL: <reloc_src_l>:
@@ -155,9 +155,9 @@ reloc_dst_l:
 ; OUTPUT-NEXT:  00 00 00 00 00 01 04 2d        ret
 
 reloc_both_g:
-  add @scalar_const[0], r1, stack[@array_var + 1]
+  add code[@scalar_const], r1, stack[@array_var + 1]
   add stack[@scalar_var], r1, stack[@array_var + 1]
-  add @array_const[1], r1, stack[@scalar_var]
+  add code[@array_const + 1], r1, stack[@scalar_var]
   add stack[@array_var + 1], r1, stack[@scalar_var]
   ret
 ; INPUT-LABEL: <reloc_both_g>:
@@ -183,9 +183,9 @@ reloc_both_g:
 ; OUTPUT-NEXT:  00 00 00 00 00 01 04 2d        ret
 
 reloc_both_l:
-  add @scalar_const_local[0], r1, stack[@array_var_local + 1]
+  add code[@scalar_const_local], r1, stack[@array_var_local + 1]
   add stack[@scalar_var_local], r1, stack[@array_var_local + 1]
-  add @array_const_local[1], r1, stack[@scalar_var_local]
+  add code[@array_const_local + 1], r1, stack[@scalar_var_local]
   add stack[@array_var_local + 1], r1, stack[@scalar_var_local]
   ret
 ; INPUT-LABEL: <reloc_both_l>:
diff --git a/llvm/lib/Target/EraVM/AsmParser/EraVMAsmParser.cpp b/llvm/lib/Target/EraVM/AsmParser/EraVMAsmParser.cpp
index e1b12d2d34cb..a0829886e37a 100644
--- a/llvm/lib/Target/EraVM/AsmParser/EraVMAsmParser.cpp
+++ b/llvm/lib/Target/EraVM/AsmParser/EraVMAsmParser.cpp
@@ -64,6 +64,7 @@ class EraVMAsmParser : public MCTargetAsmParser {
   bool parseRegOperand(OperandVector &Operands);
   OperandMatchResultTy tryParseUImm16Operand(OperandVector &Operands);
   OperandMatchResultTy tryParseJumpTargetOperand(OperandVector &Operands);
+  bool parseAddend(int &Addend, bool SignRequired);
   bool parseRegisterWithAddend(MCRegister &RegNo, MCSymbol *&Symbol,
                                int &Addend);
   bool parseOperand(StringRef Mnemonic, OperandVector &Operands);
@@ -418,6 +419,31 @@ bool EraVMAsmParser::parseRegOperand(OperandVector &Operands) {
 
 OperandMatchResultTy
 EraVMAsmParser::tryParseUImm16Operand(OperandVector &Operands) {
+  // First check if this is a symbol + addend.
+  if (getTok().is(AsmToken::At)) {
+    MCSymbol *Symbol = nullptr;
+    SMLoc StartOfOperand = getLexer().getLoc();
+    int Addend = 0;
+
+    Lex(); // eat "@" token
+    Symbol = getContext().getOrCreateSymbol(getTok().getString());
+    Lex(); // eat symbol name
+    if (getTok().is(AsmToken::Plus) || getTok().is(AsmToken::Minus))
+      if (parseAddend(Addend, /*SignRequired=*/true))
+        return MatchOperand_ParseFail;
+
+    const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, getContext());
+    // FIXME Should we support negative addends?
+    Addend &= (unsigned)0xffff;
+    if (Addend) {
+      const MCExpr *AddendExpr = createConstant(Addend);
+      Expr = MCBinaryExpr::createAdd(Expr, AddendExpr, getContext());
+    }
+    Operands.push_back(
+        EraVMOperand::CreateImm(Expr, StartOfOperand, getTok().getEndLoc()));
+    return MatchOperand_Success;
+  }
+
   if (getLexer().is(AsmToken::Minus) &&
       getLexer().peekTok().is(AsmToken::Integer)) {
     TokError("negative immediate operands are not supported");
@@ -462,34 +488,33 @@ EraVMAsmParser::tryParseJumpTargetOperand(OperandVector &Operands) {
   return MatchOperand_Success;
 }
 
-bool EraVMAsmParser::parseRegisterWithAddend(MCRegister &RegNo,
-                                             MCSymbol *&Symbol, int &Addend) {
-  auto ParseAddend = [this, &Addend](bool SignRequired) {
-    int Multiplier = 1;
-
-    switch (getTok().getKind()) {
-    case AsmToken::Plus:
-      Multiplier = 1;
-      Lex(); // eat "+" token
-      break;
-    case AsmToken::Minus:
-      Multiplier = -1;
-      Lex(); // eat "-" token
-      break;
-    default:
-      if (SignRequired)
-        return TokError("'+' or '-' expected");
-      break;
-    }
+bool EraVMAsmParser::parseAddend(int &Addend, bool SignRequired) {
+  int Multiplier = 1;
+  switch (getTok().getKind()) {
+  case AsmToken::Plus:
+    Multiplier = 1;
+    Lex(); // eat "+" token
+    break;
+  case AsmToken::Minus:
+    Multiplier = -1;
+    Lex(); // eat "-" token
+    break;
+  default:
+    if (SignRequired)
+      return TokError("'+' or '-' expected");
+    break;
+  }
 
-    if (!getLexer().is(AsmToken::Integer))
-      return TokError("integer addend expected");
-    Addend = Multiplier * getTok().getIntVal();
-    Lex(); // eat integer token
+  if (!getLexer().is(AsmToken::Integer))
+    return TokError("integer addend expected");
+  Addend = Multiplier * getTok().getIntVal();
+  Lex(); // eat integer token
 
-    return false;
-  };
+  return false;
+}
 
+bool EraVMAsmParser::parseRegisterWithAddend(MCRegister &RegNo,
+                                             MCSymbol *&Symbol, int &Addend) {
   auto ParseRegister = [this, &RegNo]() {
     SMLoc S, E;
     if (tryParseRegister(RegNo, S, E))
@@ -529,10 +554,10 @@ bool EraVMAsmParser::parseRegisterWithAddend(MCRegister &RegNo,
       return true;
     if (getTok().is(AsmToken::RBrac))
       return false; // keep "]" token for the caller
-    return ParseAddend(/*SignRequired=*/true);
+    return parseAddend(Addend, /*SignRequired=*/true);
   }
 
-  if (ParseAddend(/*SignRequired=*/false))
+  if (parseAddend(Addend, /*SignRequired=*/false))
     return true;
   if (getTok().is(AsmToken::RBrac))
     return false; // keep "]" token for the caller
@@ -633,33 +658,18 @@ EraVMAsmParser::tryParseStackOperand(OperandVector &Operands) {
 OperandMatchResultTy
 EraVMAsmParser::tryParseCodeOperand(OperandVector &Operands) {
   SMLoc StartOfOperand = getLexer().getLoc();
-  MCSymbol *Symbol = nullptr;
   MCSymbol *SymbolInSubscript = nullptr;
   MCRegister RegNo = 0;
   int Addend = 0;
 
-  // Decide if this is a code operand
-  SmallVector<AsmToken, 2> PeekedTokens(2);
-  getLexer().peekTokens(PeekedTokens);
-  if (getTok().is(AsmToken::At)) {
-    // "@symbol_name[...]"
-    if (!PeekedTokens[0].is(AsmToken::Identifier) ||
-        !PeekedTokens[1].is(AsmToken::LBrac))
-      return MatchOperand_NoMatch;
-
-    Lex(); // eat "@" token
-    Symbol = getContext().getOrCreateSymbol(getTok().getString());
-    Lex(); // eat constant symbol name
-    Lex(); // eat "[" token
-  } else {
-    // "code[...]"
-    if (!getTok().is(AsmToken::Identifier) ||
-        !PeekedTokens[0].is(AsmToken::LBrac) || getTok().getString() != "code")
-      return MatchOperand_NoMatch;
+  // "code[...]"
+  if (!getTok().is(AsmToken::Identifier) ||
+      !getLexer().peekTok().is(AsmToken::LBrac) ||
+      getTok().getString() != "code")
+    return MatchOperand_NoMatch;
 
-    Lex(); // eat "code" token
-    Lex(); // eat "[" token
-  }
+  Lex(); // eat "code" token
+  Lex(); // eat "[" token
 
   if (parseRegisterWithAddend(RegNo, SymbolInSubscript, Addend))
     return MatchOperand_ParseFail;
@@ -670,21 +680,9 @@ EraVMAsmParser::tryParseCodeOperand(OperandVector &Operands) {
   if (parseToken(AsmToken::RBrac, "']' expected"))
     return MatchOperand_ParseFail;
 
-  if (Symbol) {
-    // @symbol_name[reg + imm]
-    if (SymbolInSubscript) {
-      Error(StartOfOperand, "two symbols in a single operand");
-      return MatchOperand_ParseFail;
-    }
-    Operands.push_back(EraVMOperand::CreateMem(
-        &getContext(), EraVM::OperandCode, RegNo, Symbol, Addend,
-        StartOfOperand, getTok().getEndLoc()));
-  } else {
-    // code[...]
-    Operands.push_back(EraVMOperand::CreateMem(
-        &getContext(), EraVM::OperandCode, RegNo, SymbolInSubscript, Addend,
-        StartOfOperand, getTok().getEndLoc()));
-  }
+  Operands.push_back(EraVMOperand::CreateMem(
+      &getContext(), EraVM::OperandCode, RegNo, SymbolInSubscript, Addend,
+      StartOfOperand, getTok().getEndLoc()));
 
   return MatchOperand_Success;
 }
diff --git a/llvm/lib/Target/EraVM/EraVMInstrInfo.cpp b/llvm/lib/Target/EraVM/EraVMInstrInfo.cpp
index ead4e387e02f..e26b030e0ab9 100644
--- a/llvm/lib/Target/EraVM/EraVMInstrInfo.cpp
+++ b/llvm/lib/Target/EraVM/EraVMInstrInfo.cpp
@@ -1125,9 +1125,8 @@ MachineBasicBlock::iterator EraVMInstrInfo::insertOutlinedCall(
     It->setPostInstrSymbol(MF, RetSym);
 
     // Add instruction to store return address onto the top of the stack.
-    BuildMI(MBB, It, DL, get(EraVM::ADDcrs_s))
+    BuildMI(MBB, It, DL, get(EraVM::ADDirs_s))
         .addSym(RetSym, EraVMII::MO_SYM_RET_ADDRESS)
-        .addImm(0 /* RetSymOffset */)
         .addReg(EraVM::R0)
         .addReg(EraVM::SP)
         .addImm(0 /* AMBase2 */)
diff --git a/llvm/lib/Target/EraVM/MCTargetDesc/EraVMELFObjectWriter.cpp b/llvm/lib/Target/EraVM/MCTargetDesc/EraVMELFObjectWriter.cpp
index 5bdb434456cb..dc96c51091a6 100644
--- a/llvm/lib/Target/EraVM/MCTargetDesc/EraVMELFObjectWriter.cpp
+++ b/llvm/lib/Target/EraVM/MCTargetDesc/EraVMELFObjectWriter.cpp
@@ -39,32 +39,8 @@ class EraVMELFObjectWriter : public MCELFObjectTargetWriter {
                         const MCFixup &Fixup, bool IsPCRel) const override {
     // Translate fixup kind to ELF relocation type.
     switch (Fixup.getTargetKind()) {
-    case EraVM::fixup_16_scale_32: {
-      // There may be cases where the relocation symbol is in the code,
-      // for example:
-      //
-      //     add   @.OUTLINED_FUNCTION_RET0[0], r0, stack-[1]
-      //     jump  @OUTLINED_FUNCTION_0
-      //   .OUTLINED_FUNCTION_RET0:
-      //     jump.ge @.BB1_16
-      //     jump  @.BB1_23
-      //
-      // Here the .OUTLINED_FUNCTION_RET0[0] represents the code offset,
-      // measured in 8-byte units.
-      // In such cases the actual relocation type should be R_ERAVM_16_SCALE_8.
-      if (const MCSymbolRefExpr *A = Target.getSymA()) {
-        const MCSymbol &Sym = A->getSymbol();
-        assert(Sym.isDefined());
-        MCSection &Section = Sym.getSection();
-        const MCSectionELF *SectionELF = dyn_cast<MCSectionELF>(&Section);
-        assert(SectionELF && "Null section for reloc symbol");
-
-        unsigned Flags = SectionELF->getFlags();
-        if ((Flags & ELF::SHF_ALLOC) && (Flags & ELF::SHF_EXECINSTR))
-          return ELF::R_ERAVM_16_SCALE_8;
-      }
+    case EraVM::fixup_16_scale_32:
       return ELF::R_ERAVM_16_SCALE_32;
-    }
     case EraVM::fixup_16_scale_8:
       return ELF::R_ERAVM_16_SCALE_8;
     default:
diff --git a/llvm/lib/Target/EraVM/MCTargetDesc/EraVMInstPrinter.cpp b/llvm/lib/Target/EraVM/MCTargetDesc/EraVMInstPrinter.cpp
index d677393bc530..24fedfee8a02 100644
--- a/llvm/lib/Target/EraVM/MCTargetDesc/EraVMInstPrinter.cpp
+++ b/llvm/lib/Target/EraVM/MCTargetDesc/EraVMInstPrinter.cpp
@@ -114,25 +114,28 @@ void EraVMInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
   if (BaseReg == EraVM::R0)
     BaseReg = 0;
 
-  if (Symbol)
-    O << "@" << Symbol->getName() << "[";
-  else
-    O << "code[";
+  O << "code[";
 
-  if (!BaseReg && !Addend)
-    O << "0";
+  if (Symbol)
+    O << "@" << Symbol->getName();
 
-  if (BaseReg)
+  if (BaseReg) {
+    if (Symbol)
+      O << "+";
     O << getRegisterName(BaseReg);
+  }
 
   if (Addend) {
     if (Addend < 0)
       O << "-";
-    else if (BaseReg)
+    else if (Symbol || BaseReg)
       O << "+";
     O << std::abs(Addend);
   }
 
+  if (!Symbol && !BaseReg && !Addend)
+    O << "0";
+
   O << "]";
 }
 
diff --git a/llvm/lib/Target/EraVM/MCTargetDesc/EraVMMCCodeEmitter.cpp b/llvm/lib/Target/EraVM/MCTargetDesc/EraVMMCCodeEmitter.cpp
index 0e8fd4230f1c..0a3a3c1e69de 100644
--- a/llvm/lib/Target/EraVM/MCTargetDesc/EraVMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/EraVM/MCTargetDesc/EraVMMCCodeEmitter.cpp
@@ -153,6 +153,13 @@ EraVMMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
   if (MO.isImm())
     return MO.getImm();
+  if (MO.isExpr()) {
+    // This corresponds to the cases where the operand
+    // is an expression of the form: @symbol + imm.
+    auto FK = static_cast<MCFixupKind>(EraVM::fixup_16_scale_8);
+    Fixups.push_back(MCFixup::create(2, MO.getExpr(), FK, MI.getLoc()));
+    return 0;
+  }
 
   llvm_unreachable("Unexpected generic operand type");
 }
diff --git a/llvm/test/CodeGen/EraVM/add.ll b/llvm/test/CodeGen/EraVM/add.ll
index ce4711072a6d..ebe4d2a03d57 100644
--- a/llvm/test/CodeGen/EraVM/add.ll
+++ b/llvm/test/CodeGen/EraVM/add.ll
@@ -21,7 +21,7 @@ define i256 @addirr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: addcrr
 define i256 @addcrr(i256 %rs1) nounwind {
-; CHECK: add @val[0], r1, r1
+; CHECK: add code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = add i256 %rs1, %val
   ret i256 %res
@@ -57,7 +57,7 @@ define void @addirs(i256 %rs1) nounwind {
 ; CHECK-LABEL: addcrs
 define void @addcrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: add @val[0], r1, stack-[1]
+; CHECK: add code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = add i256 %rs1, %val
   store i256 %res, i256* %valptr
diff --git a/llvm/test/CodeGen/EraVM/addmod.ll b/llvm/test/CodeGen/EraVM/addmod.ll
index 862e00fe65c6..ea8512c32332 100644
--- a/llvm/test/CodeGen/EraVM/addmod.ll
+++ b/llvm/test/CodeGen/EraVM/addmod.ll
@@ -5,11 +5,11 @@ target triple = "eravm"
 
 define i256 @test(i256 %a) {
 ; CHECK-LABEL: test
-; CHECK:       sub.s! @CPI0_0[0], r1, r0
+; CHECK:       sub.s! code[@CPI0_0], r1, r0
 ; CHECK-NEXT:  add.ge 5, r1, r1
 ; CHECK-NEXT:  shl.s 1, r1, r4
 ; CHECK-NEXT:  add 5, r4, r2
-; CHECK-NEXT:  sub.s! @CPI0_0[0], r4, r0
+; CHECK-NEXT:  sub.s! code[@CPI0_0], r4, r0
 ; CHECK-NEXT:  add r2, r0, r3
 ; CHECK-NEXT:  add.lt r4, r0, r3
 ; CHECK-NEXT:  sub! r4, r1, r0
diff --git a/llvm/test/CodeGen/EraVM/and.ll b/llvm/test/CodeGen/EraVM/and.ll
index 541dc0c16033..719bc9cc2a98 100644
--- a/llvm/test/CodeGen/EraVM/and.ll
+++ b/llvm/test/CodeGen/EraVM/and.ll
@@ -21,7 +21,7 @@ define i256 @andirr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: andcrr
 define i256 @andcrr(i256 %rs1) nounwind {
-; CHECK: and @val[0], r1, r1
+; CHECK: and code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = and i256 %rs1, %val
   ret i256 %res
@@ -57,7 +57,7 @@ define void @andirs(i256 %rs1) nounwind {
 ; CHECK-LABEL: andcrs
 define void @andcrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: and @val[0], r1, stack-[1]
+; CHECK: and code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = and i256 %rs1, %val
   store i256 %res, i256* %valptr
diff --git a/llvm/test/CodeGen/EraVM/array.ll b/llvm/test/CodeGen/EraVM/array.ll
index 17b04d690021..5e570732a7ec 100644
--- a/llvm/test/CodeGen/EraVM/array.ll
+++ b/llvm/test/CodeGen/EraVM/array.ll
@@ -10,7 +10,7 @@ target triple = "eravm"
 ; CHECK-LABEL: consti_loadconst_neg_offset
 define i256 @consti_loadconst_neg_offset(i256 %idx) nounwind {
   ; CHECK: sub.s 1, r1, r1
-  ; CHECK: add @const[r1], r0, r1
+  ; CHECK: add code[@const+r1], r0, r1
   %sub = add nsw i256 %idx, -1
   %gep = getelementptr inbounds [10 x i256], ptr addrspace(4) @const, i256 0, i256 %sub
   %load = load i256, ptr addrspace(4) %gep, align 32
@@ -19,7 +19,7 @@ define i256 @consti_loadconst_neg_offset(i256 %idx) nounwind {
 
 ; CHECK-LABEL: consti_loadconst_storeglobal
 define void @consti_loadconst_storeglobal() nounwind {
-  ; CHECK: add @const[1], r0, stack[@val + 1]
+  ; CHECK: add code[@const+1], r0, stack[@val + 1]
   %1 = load i256, ptr addrspace(4) getelementptr inbounds ([10 x i256], ptr addrspace(4) @const, i256 0, i256 1), align 32
   store i256 %1, ptr getelementptr inbounds ([10 x i256], ptr @val, i256 0, i256 1), align 32
   ret void
@@ -39,7 +39,7 @@ define void @vari_loadconst_storeglobal(i256 %i) nounwind {
   %addrg = getelementptr inbounds [10 x i256], ptr @val, i256 0, i256 %i
   %1 = load i256, ptr addrspace(4) %addrc, align 32
   ; CHECK-NOT: shr.s 5, r1, {{r[0-9]+}}
-  ; CHECK: add @const2[r1], r0, stack[@val + r1]
+  ; CHECK: add code[@const2+r1], r0, stack[@val + r1]
   store i256 %1, ptr %addrg, align 32
   ret void
 }
diff --git a/llvm/test/CodeGen/EraVM/brcc.ll b/llvm/test/CodeGen/EraVM/brcc.ll
index 30faa230bf9f..a21f36b6d6d3 100644
--- a/llvm/test/CodeGen/EraVM/brcc.ll
+++ b/llvm/test/CodeGen/EraVM/brcc.ll
@@ -122,7 +122,7 @@ l2:
 
 ; CHECK-LABEL: cmpcr
 define i256 @cmpcr(i256 %p1, i256 %p2) nounwind {
-; CHECK: sub.s! @val[0], r1, r0
+; CHECK: sub.s! code[@val], r1, r0
 ; CHECK-NEXT: add.le  72, r0, r1
 ; CHECK-NEXT: add.gt  42, r0, r1
 ; CHECK-NEXT: ret
@@ -164,7 +164,7 @@ l2:
 
 ; CHECK-LABEL: cmprc
 define i256 @cmprc(i256 %p1, i256 %p2) nounwind {
-; CHECK: sub! @val[0], r1, r0
+; CHECK: sub! code[@val], r1, r0
 ; CHECK-NEXT: add.le  72, r0, r1
 ; CHECK-NEXT: add.gt  42, r0, r1
 ; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/EraVM/cmp-signed.ll b/llvm/test/CodeGen/EraVM/cmp-signed.ll
index b55dae4c5361..ac03bdecfbd5 100644
--- a/llvm/test/CodeGen/EraVM/cmp-signed.ll
+++ b/llvm/test/CodeGen/EraVM/cmp-signed.ll
@@ -7,15 +7,15 @@ target triple = "eravm"
 define i1 @slt_not(i256 %a) {
 ; CHECK-LABEL: slt_not:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
 ; CHECK-NEXT:    add r0, r0, r2
-; CHECK-NEXT:    add.lt @CPI0_0[0], r0, r2
-; CHECK-NEXT:    and @CPI0_0[0], r1, r1
-; CHECK-NEXT:    xor @CPI0_0[0], r1, r3
-; CHECK-NEXT:    sub.s! @CPI0_0[0], r1, r0
+; CHECK-NEXT:    add.lt code[@CPI0_0], r0, r2
+; CHECK-NEXT:    and code[@CPI0_0], r1, r1
+; CHECK-NEXT:    xor code[@CPI0_0], r1, r3
+; CHECK-NEXT:    sub.s! code[@CPI0_0], r1, r0
 ; CHECK-NEXT:    add r0, r0, r1
-; CHECK-NEXT:    add.gt @CPI0_0[0], r0, r1
-; CHECK-NEXT:    sub.s! @CPI0_0[0], r3, r0
+; CHECK-NEXT:    add.gt code[@CPI0_0], r0, r1
+; CHECK-NEXT:    sub.s! code[@CPI0_0], r3, r0
 ; CHECK-NEXT:    add.ne r2, r0, r1
 ; CHECK-NEXT:    sub! r1, r0, r0
 ; CHECK-NEXT:    add 0, r0, r1
@@ -28,15 +28,15 @@ define i1 @slt_not(i256 %a) {
 define i1 @sgt_not(i256 %a) {
 ; CHECK-LABEL: sgt_not:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
 ; CHECK-NEXT:    add r0, r0, r2
-; CHECK-NEXT:    add.gt @CPI1_0[0], r0, r2
-; CHECK-NEXT:    and @CPI1_0[0], r1, r1
-; CHECK-NEXT:    xor @CPI1_0[0], r1, r3
-; CHECK-NEXT:    sub.s! @CPI1_0[0], r1, r0
+; CHECK-NEXT:    add.gt code[@CPI1_0], r0, r2
+; CHECK-NEXT:    and code[@CPI1_0], r1, r1
+; CHECK-NEXT:    xor code[@CPI1_0], r1, r3
+; CHECK-NEXT:    sub.s! code[@CPI1_0], r1, r0
 ; CHECK-NEXT:    add r0, r0, r1
-; CHECK-NEXT:    add.lt @CPI1_0[0], r0, r1
-; CHECK-NEXT:    sub.s! @CPI1_0[0], r3, r0
+; CHECK-NEXT:    add.lt code[@CPI1_0], r0, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_0], r3, r0
 ; CHECK-NEXT:    add.ne r2, r0, r1
 ; CHECK-NEXT:    sub! r1, r0, r0
 ; CHECK-NEXT:    add 0, r0, r1
@@ -129,7 +129,7 @@ define i1 @sgt_i8_3(i8 %a) {
 define i1 @slt_i256_1(i256 %a) {
 ; CHECK-LABEL: slt_i256_1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI8_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI8_0], r1, r0
 ; CHECK-NEXT:    add 0, r0, r1
 ; CHECK-NEXT:    add.gt 1, r0, r1
 ; CHECK-NEXT:    ret
@@ -143,7 +143,7 @@ define i1 @slt_i256_2(i256 %a) {
 ; CHECK-NEXT:    sub! r1, r0, r0
 ; CHECK-NEXT:    add 0, r0, r2
 ; CHECK-NEXT:    add.eq 1, r0, r2
-; CHECK-NEXT:    sub.s! @CPI9_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI9_0], r1, r0
 ; CHECK-NEXT:    or.gt 1, r2, r2
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    ret
@@ -157,7 +157,7 @@ define i1 @slt_i256_3(i256 %a) {
 ; CHECK-NEXT:    sub.s! 31, r1, r0
 ; CHECK-NEXT:    add 0, r0, r2
 ; CHECK-NEXT:    add.lt 1, r0, r2
-; CHECK-NEXT:    sub.s! @CPI10_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI10_0], r1, r0
 ; CHECK-NEXT:    or.gt 1, r2, r2
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    ret
@@ -168,7 +168,7 @@ define i1 @slt_i256_3(i256 %a) {
 define i1 @sgt_i256_1(i256 %a) {
 ; CHECK-LABEL: sgt_i256_1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI11_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI11_0], r1, r0
 ; CHECK-NEXT:    add 0, r0, r1
 ; CHECK-NEXT:    add.lt 1, r0, r1
 ; CHECK-NEXT:    ret
@@ -182,7 +182,7 @@ define i1 @sgt_i256_2(i256 %a) {
 ; CHECK-NEXT:    sub! r1, r0, r0
 ; CHECK-NEXT:    add 0, r0, r2
 ; CHECK-NEXT:    add.ne 1, r0, r2
-; CHECK-NEXT:    sub.s! @CPI12_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI12_0], r1, r0
 ; CHECK-NEXT:    add 0, r0, r1
 ; CHECK-NEXT:    add.lt 1, r0, r1
 ; CHECK-NEXT:    and r1, r2, r1
@@ -197,7 +197,7 @@ define i1 @sgt_i256_3(i256 %a) {
 ; CHECK-NEXT:    sub.s! 31, r1, r0
 ; CHECK-NEXT:    add 0, r0, r2
 ; CHECK-NEXT:    add.gt 1, r0, r2
-; CHECK-NEXT:    sub.s! @CPI13_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI13_0], r1, r0
 ; CHECK-NEXT:    add 0, r0, r1
 ; CHECK-NEXT:    add.lt 1, r0, r1
 ; CHECK-NEXT:    and r1, r2, r1
diff --git a/llvm/test/CodeGen/EraVM/combine-flag-setting.ll b/llvm/test/CodeGen/EraVM/combine-flag-setting.ll
index fbfb5d4cdedb..1d2a625dee6f 100644
--- a/llvm/test/CodeGen/EraVM/combine-flag-setting.ll
+++ b/llvm/test/CodeGen/EraVM/combine-flag-setting.ll
@@ -163,7 +163,7 @@ define i1 @DIVxrrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: ADDcrr_v:
 define i1 @ADDcrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: add! @val[0], r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: add! code[@val], r{{[0-9]+}}, r{{[0-9]+}}
   %p2 = add i256 %val, %p1
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
@@ -172,7 +172,7 @@ define i1 @ADDcrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: ANDcrr_v:
 define i1 @ANDcrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: and! @val[0], r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: and! code[@val], r{{[0-9]+}}, r{{[0-9]+}}
   %p2 = and i256 %val, %p1
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
@@ -181,7 +181,7 @@ define i1 @ANDcrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: ORcrr_v:
 define i1 @ORcrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: or! @val[0], r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: or! code[@val], r{{[0-9]+}}, r{{[0-9]+}}
   %p2 = or i256 %val, %p1
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
@@ -190,7 +190,7 @@ define i1 @ORcrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: XORcrr_v:
 define i1 @XORcrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: xor! @val[0], r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: xor! code[@val], r{{[0-9]+}}, r{{[0-9]+}}
   %p2 = xor i256 %val, %p1
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
@@ -199,7 +199,7 @@ define i1 @XORcrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: SHLcrr_v:
 define i1 @SHLcrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: shl! @val[0], r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: shl! code[@val], r{{[0-9]+}}, r{{[0-9]+}}
   %p2 = shl i256 %val, %p1
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
@@ -208,7 +208,7 @@ define i1 @SHLcrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: SHRcrr_v:
 define i1 @SHRcrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: shr! @val[0], r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: shr! code[@val], r{{[0-9]+}}, r{{[0-9]+}}
   %p2 = lshr i256 %val, %p1
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
@@ -217,7 +217,7 @@ define i1 @SHRcrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: SHLyrr_v:
 define i1 @SHLyrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: shl.s! @val[0], r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: shl.s! code[@val], r{{[0-9]+}}, r{{[0-9]+}}
   %p2 = shl i256 %p1, %val
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
@@ -226,7 +226,7 @@ define i1 @SHLyrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: SHRyrr_v:
 define i1 @SHRyrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: shr.s! @val[0], r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: shr.s! code[@val], r{{[0-9]+}}, r{{[0-9]+}}
   %p2 = lshr i256 %p1, %val
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
@@ -235,7 +235,7 @@ define i1 @SHRyrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: MULcrrr_v:
 define i1 @MULcrrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: mul! @val[0], r1, r{{[0-9]+}}
+; CHECK: mul! code[@val], r1, r{{[0-9]+}}
   %p2 = mul i256 %p1, %val
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
@@ -244,7 +244,7 @@ define i1 @MULcrrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: DIVcrrr_v:
 define i1 @DIVcrrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: div! @val[0], r1, r{{[0-9]+}}
+; CHECK: div! code[@val], r1, r{{[0-9]+}}
   %p2 = udiv i256 %val, %p1
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
@@ -253,7 +253,7 @@ define i1 @DIVcrrr_v(i256 %p1) nounwind {
 ; CHECK-LABEL: DIVyrrr_v:
 define i1 @DIVyrrr_v(i256 %p1) nounwind {
   %val = load i256, i256 addrspace(4)* @val
-; CHECK: div.s! @val[0], r1, r{{[0-9]+}}
+; CHECK: div.s! code[@val], r1, r{{[0-9]+}}
   %p2 = udiv i256 %p1, %val
   %cmp = icmp eq i256 %p2, 0
   ret i1 %cmp
diff --git a/llvm/test/CodeGen/EraVM/cse-sub-cmp.ll b/llvm/test/CodeGen/EraVM/cse-sub-cmp.ll
index 773c8cc5d8ea..269c8efcebaa 100644
--- a/llvm/test/CodeGen/EraVM/cse-sub-cmp.ll
+++ b/llvm/test/CodeGen/EraVM/cse-sub-cmp.ll
@@ -23,8 +23,8 @@ define i256 @test_small_imm(i256 %a) {
 define i256 @test_large_imm(i256 %a) {
 ; CHECK-LABEL: test_large_imm:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_0[0], r1, r2
-; CHECK-NEXT:    mul @CPI1_0[0], r1, r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI1_0], r1, r2
+; CHECK-NEXT:    mul code[@CPI1_0], r1, r1, r0
 ; CHECK-NEXT:    add.ge r2, r0, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 %a, 123456789
diff --git a/llvm/test/CodeGen/EraVM/def-spill.ll b/llvm/test/CodeGen/EraVM/def-spill.ll
index 05fd630189aa..f1fe152e6d73 100644
--- a/llvm/test/CodeGen/EraVM/def-spill.ll
+++ b/llvm/test/CodeGen/EraVM/def-spill.ll
@@ -28,7 +28,7 @@ define i256 @spill_addi(i256 %a) nounwind {
 
 ; CHECK-LABEL: spill_addc
 define i256 @spill_addc(i256 %a) nounwind {
-  ; TODO: CPR-1221 add @CPI2_0[0], r2, stack-[1]
+  ; TODO: CPR-1221 add code[@CPI2_0], r2, stack-[1]
   %x = add i256 %a, 4200000000000000
   %c = call i256 @foo()
   %res = add i256 %x, %c
@@ -66,7 +66,7 @@ define i256 @spill_subi(i256 %a) nounwind {
 
 ; CHECK-LABEL: spill_subc
 define i256 @spill_subc(i256 %a) nounwind {
-  ; TODO: CPR-1221 sub @CPI2_0[0], r2, stack-[1]
+  ; TODO: CPR-1221 sub code[@CPI2_0], r2, stack-[1]
   %x = sub i256 %a, 4200000000000000
   %c = call i256 @foo()
   %res = sub i256 %x, %c
@@ -104,7 +104,7 @@ define i256 @spill_muli(i256 %a) nounwind {
 
 ; CHECK-LABEL: spill_mulc
 define i256 @spill_mulc(i256 %a) nounwind {
-  ; TODO: CPR-1221 mul @CPI2_0[0], r2, stack-[1]
+  ; TODO: CPR-1221 mul code[@CPI2_0], r2, stack-[1]
   %x = mul i256 %a, 4200000000000000
   %c = call i256 @foo()
   %res = mul i256 %x, %c
@@ -142,7 +142,7 @@ define i256 @spill_divi(i256 %a) nounwind {
 
 ; CHECK-LABEL: spill_divc
 define i256 @spill_divc(i256 %a) nounwind {
-  ; CHECK: div.s @CPI{{[0-9]+}}_0[0], r1, stack-[1], r0
+  ; CHECK: div.s code[@CPI{{[0-9]+}}_0], r1, stack-[1], r0
   %x = udiv i256 %a, 4200000000000000
   %c = call i256 @foo()
   %res = udiv i256 %x, %c
@@ -180,7 +180,7 @@ define i256 @spill_andi(i256 %a) nounwind {
 
 ; CHECK-LABEL: spill_andc
 define i256 @spill_andc(i256 %a) nounwind {
-  ; TODO: CPR-1221 and @CPI2_0[0], r2, stack-[1]
+  ; TODO: CPR-1221 and code[@CPI2_0], r2, stack-[1]
   %x = and i256 %a, 4200000000000000
   %c = call i256 @foo()
   %res = and i256 %x, %c
@@ -218,7 +218,7 @@ define i256 @spill_ori(i256 %a) nounwind {
 
 ; CHECK-LABEL: spill_orc
 define i256 @spill_orc(i256 %a) nounwind {
-  ; TODO: CPR-1221 or @CPI2_0[0], r2, stack-[1]
+  ; TODO: CPR-1221 or code[@CPI2_0], r2, stack-[1]
   %x = or i256 %a, 4200000000000000
   %c = call i256 @foo()
   %res = or i256 %x, %c
@@ -256,7 +256,7 @@ define i256 @spill_xori(i256 %a) nounwind {
 
 ; CHECK-LABEL: spill_xorc
 define i256 @spill_xorc(i256 %a) nounwind {
-  ; TODO: CPR-1221 xor @CPI2_0[0], r2, stack-[1]
+  ; TODO: CPR-1221 xor code[@CPI2_0], r2, stack-[1]
   %x = xor i256 %a, 4200000000000000
   %c = call i256 @foo()
   %res = xor i256 %x, %c
@@ -352,7 +352,7 @@ define i8 addrspace(3)* @spill_ptraddi(i8 addrspace(3)* %a) nounwind {
 
 ; CHECK-LABEL: spill_ptraddc
 define i8 addrspace(3)* @spill_ptraddc(i8 addrspace(3)* %a) nounwind {
-  ; CHECK: ptr.add.s @CPI{{[0-9]+}}_0[0], r1, stack-[1]
+  ; CHECK: ptr.add.s code[@CPI{{[0-9]+}}_0], r1, stack-[1]
   %x = call i8 addrspace(3)* @llvm.eravm.ptr.add(i8 addrspace(3)* %a, i256 4200000000000000)
   %c = call i256 @foo()
   %res = call i8 addrspace(3)* @llvm.eravm.ptr.add(i8 addrspace(3)* %x, i256 %c)
@@ -390,7 +390,7 @@ define i8 addrspace(3)* @spill_ptrpacki(i8 addrspace(3)* %a) nounwind {
 
 ; CHECK-LABEL: spill_ptrpackc
 define i8 addrspace(3)* @spill_ptrpackc(i8 addrspace(3)* %a) nounwind {
-  ; CHECK: ptr.pack.s @CPI{{[0-9]+}}_0[0], r1, stack-[1]
+  ; CHECK: ptr.pack.s code[@CPI{{[0-9]+}}_0], r1, stack-[1]
   %x = call i8 addrspace(3)* @llvm.eravm.ptr.pack(i8 addrspace(3)* %a, i256 4200000000000000)
   %c = call i256 @foo()
   %res = call i8 addrspace(3)* @llvm.eravm.ptr.pack(i8 addrspace(3)* %x, i256 %c)
@@ -428,7 +428,7 @@ define i8 addrspace(3)* @spill_ptrshrinki(i8 addrspace(3)* %a) nounwind {
 
 ; CHECK-LABEL: spill_ptrshrinkc
 define i8 addrspace(3)* @spill_ptrshrinkc(i8 addrspace(3)* %a) nounwind {
-  ; CHECK: ptr.shrink.s @CPI{{[0-9]+}}_0[0], r1, stack-[1]
+  ; CHECK: ptr.shrink.s code[@CPI{{[0-9]+}}_0], r1, stack-[1]
   %x = call i8 addrspace(3)* @llvm.eravm.ptr.shrink(i8 addrspace(3)* %a, i256 4200000000000000)
   %c = call i256 @foo()
   %res = call i8 addrspace(3)* @llvm.eravm.ptr.shrink(i8 addrspace(3)* %x, i256 %c)
diff --git a/llvm/test/CodeGen/EraVM/fold-add-to-select.ll b/llvm/test/CodeGen/EraVM/fold-add-to-select.ll
index ecd4fdeed890..cdde446d32d4 100644
--- a/llvm/test/CodeGen/EraVM/fold-add-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-add-to-select.ll
@@ -11,8 +11,8 @@ declare { i256, i1 } @llvm.uadd.with.overflow.i256(i256, i256)
 define i256 @test_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    sub.s.lt @CPI0_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    sub.s.lt code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    ret
   %add = add i256 %a, 26959946660873538059280334323183841250350249843923952699046031785980
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -23,8 +23,8 @@ define i256 @test_large_imm1(i256 %a) {
 define i256 @test_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    sub.s.lt @CPI1_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    sub.s.lt code[@CPI1_0], r1, r1
 ; CHECK-NEXT:    ret
   %add = add i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
   %cmp = icmp ult i256 %a, 26959946660873538059280334323183841250350249843923952699046031785980
@@ -35,8 +35,8 @@ define i256 @test_large_imm2(i256 %a) {
 define i256 @test_large_imm3(i256 %a) {
 ; CHECK-LABEL: test_large_imm3:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_1[0], r1, r0
-; CHECK-NEXT:    sub.s.ge @CPI2_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI2_1], r1, r0
+; CHECK-NEXT:    sub.s.ge code[@CPI2_0], r1, r1
 ; CHECK-NEXT:    ret
   %add = add i256 %a, 26959946660873538059280334323183841250350249843923952699046031785980
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -47,8 +47,8 @@ define i256 @test_large_imm3(i256 %a) {
 define i256 @test_large_imm4(i256 %a) {
 ; CHECK-LABEL: test_large_imm4:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_1[0], r1, r0
-; CHECK-NEXT:    sub.s.ge @CPI3_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI3_1], r1, r0
+; CHECK-NEXT:    sub.s.ge code[@CPI3_0], r1, r1
 ; CHECK-NEXT:    ret
   %add = add i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
   %cmp = icmp ult i256 %a, 26959946660873538059280334323183841250350249843923952699046031785980
@@ -59,7 +59,7 @@ define i256 @test_large_imm4(i256 %a) {
 define i256 @test_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI4_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI4_0], r1, r0
 ; CHECK-NEXT:    add.lt 10, r1, r1
 ; CHECK-NEXT:    ret
   %add = add i256 %a, 10
@@ -71,7 +71,7 @@ define i256 @test_small_imm1(i256 %a) {
 define i256 @test_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI5_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI5_0], r1, r0
 ; CHECK-NEXT:    add.ge 10, r1, r1
 ; CHECK-NEXT:    ret
   %add = add i256 %a, 10
@@ -221,7 +221,7 @@ define i256 @test_code1(i256 %a) {
 ; CHECK-LABEL: test_code1:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub.s! 5, r1, r0
-; CHECK-NEXT:    add.lt @val[0], r1, r1
+; CHECK-NEXT:    add.lt code[@val], r1, r1
 ; CHECK-NEXT:    ret
   %b = load i256, i256 addrspace(4)* @val
   %add = add i256 %a, %b
@@ -234,7 +234,7 @@ define i256 @test_code2(i256 %a) {
 ; CHECK-LABEL: test_code2:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub.s! 5, r1, r0
-; CHECK-NEXT:    add.ge @val[0], r1, r1
+; CHECK-NEXT:    add.ge code[@val], r1, r1
 ; CHECK-NEXT:    ret
   %b = load i256, i256 addrspace(4)* @val
   %add = add i256 %a, %b
@@ -252,8 +252,8 @@ define i256 @test_use_in_other_bb(i256 %a, i1 %cond) {
 ; CHECK-NEXT:    add r0, r0, r1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .BB18_2: ; %else
-; CHECK-NEXT:    sub.s! @CPI18_1[0], r1, r0
-; CHECK-NEXT:    sub.s.lt @CPI18_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI18_1], r1, r0
+; CHECK-NEXT:    sub.s.lt code[@CPI18_0], r1, r1
 ; CHECK-NEXT:    ret
   %add = add i256 %a, 26959946660873538059280334323183841250350249843923952699046031785980
   br i1 %cond, label %then, label %else
diff --git a/llvm/test/CodeGen/EraVM/fold-and-to-select.ll b/llvm/test/CodeGen/EraVM/fold-and-to-select.ll
index d33215b305ab..d53ae9a0d9b7 100644
--- a/llvm/test/CodeGen/EraVM/fold-and-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-and-to-select.ll
@@ -7,8 +7,8 @@ target triple = "eravm"
 define i256 @test_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    and.lt @CPI0_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    and.lt code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    ret
   %and = and i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -19,8 +19,8 @@ define i256 @test_large_imm1(i256 %a) {
 define i256 @test_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    and.ge @CPI1_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    and.ge code[@CPI1_0], r1, r1
 ; CHECK-NEXT:    ret
   %and = and i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -31,7 +31,7 @@ define i256 @test_large_imm2(i256 %a) {
 define i256 @test_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI2_0], r1, r0
 ; CHECK-NEXT:    and.lt 10, r1, r1
 ; CHECK-NEXT:    ret
   %and = and i256 10, %a
@@ -43,7 +43,7 @@ define i256 @test_small_imm1(i256 %a) {
 define i256 @test_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI3_0], r1, r0
 ; CHECK-NEXT:    and.ge 10, r1, r1
 ; CHECK-NEXT:    ret
   %and = and i256 10, %a
diff --git a/llvm/test/CodeGen/EraVM/fold-div-to-select.ll b/llvm/test/CodeGen/EraVM/fold-div-to-select.ll
index 28a064ad06a5..3d7291167f7f 100644
--- a/llvm/test/CodeGen/EraVM/fold-div-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-div-to-select.ll
@@ -7,8 +7,8 @@ target triple = "eravm"
 define i256 @test_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    div.s.lt @CPI0_0[0], r1, r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    div.s.lt code[@CPI0_0], r1, r1, r0
 ; CHECK-NEXT:    ret
   %div = udiv i256 %a, 26959946660873538059280334323183841250350249843923952699046031785980
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -19,8 +19,8 @@ define i256 @test_large_imm1(i256 %a) {
 define i256 @test_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    div.s.ge @CPI1_0[0], r1, r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    div.s.ge code[@CPI1_0], r1, r1, r0
 ; CHECK-NEXT:    ret
   %div = udiv i256 %a, 26959946660873538059280334323183841250350249843923952699046031785980
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -31,7 +31,7 @@ define i256 @test_large_imm2(i256 %a) {
 define i256 @test_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI2_0], r1, r0
 ; CHECK-NEXT:    div.s.lt 10, r1, r1, r0
 ; CHECK-NEXT:    ret
   %div = udiv i256 %a, 10
@@ -43,7 +43,7 @@ define i256 @test_small_imm1(i256 %a) {
 define i256 @test_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI3_0], r1, r0
 ; CHECK-NEXT:    div.s.ge 10, r1, r1, r0
 ; CHECK-NEXT:    ret
   %div = udiv i256 %a, 10
diff --git a/llvm/test/CodeGen/EraVM/fold-move-imm.ll b/llvm/test/CodeGen/EraVM/fold-move-imm.ll
index e1223089746c..f047ff0d6c90 100644
--- a/llvm/test/CodeGen/EraVM/fold-move-imm.ll
+++ b/llvm/test/CodeGen/EraVM/fold-move-imm.ll
@@ -26,7 +26,7 @@ define i256 @test_pos(i256 %arg) {
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    sub.s! 3, r8, r0
 ; CHECK-NEXT:    add 100, r0, r9
-; CHECK-NEXT:    jump.le @JTI0_0[r8]
+; CHECK-NEXT:    jump.le code[@JTI0_0+r8]
 ; CHECK-NEXT:    jump @.BB0_9
 ; CHECK-NEXT:  .BB0_5: ; %loop-bb2
 ; CHECK-NEXT:    ; in Loop: Header=BB0_4 Depth=1
@@ -102,7 +102,7 @@ define i256 @test_neg(i256 %arg) {
 ; CHECK-NEXT:    jump @.BB1_4
 ; CHECK-NEXT:  .BB1_8: ; %loop-bb5
 ; CHECK-NEXT:    ; in Loop: Header=BB1_4 Depth=1
-; CHECK-NEXT:    add @CPI1_4[0], r0, r9
+; CHECK-NEXT:    add code[@CPI1_4], r0, r9
 ; CHECK-NEXT:  .BB1_9: ; %loop-bb6
 ; CHECK-NEXT:    ; in Loop: Header=BB1_4 Depth=1
 ; CHECK-NEXT:    add r2, r9, r2
@@ -112,20 +112,20 @@ define i256 @test_neg(i256 %arg) {
 ; CHECK-NEXT:  .BB1_4: ; %loop-bb1
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    sub.s! 3, r8, r0
-; CHECK-NEXT:    add @CPI1_0[0], r0, r9
-; CHECK-NEXT:    jump.le @JTI1_0[r8]
+; CHECK-NEXT:    add code[@CPI1_0], r0, r9
+; CHECK-NEXT:    jump.le code[@JTI1_0+r8]
 ; CHECK-NEXT:    jump @.BB1_9
 ; CHECK-NEXT:  .BB1_5: ; %loop-bb2
 ; CHECK-NEXT:    ; in Loop: Header=BB1_4 Depth=1
-; CHECK-NEXT:    add @CPI1_1[0], r0, r9
+; CHECK-NEXT:    add code[@CPI1_1], r0, r9
 ; CHECK-NEXT:    jump @.BB1_9
 ; CHECK-NEXT:  .BB1_6: ; %loop-bb3
 ; CHECK-NEXT:    ; in Loop: Header=BB1_4 Depth=1
-; CHECK-NEXT:    add @CPI1_2[0], r0, r9
+; CHECK-NEXT:    add code[@CPI1_2], r0, r9
 ; CHECK-NEXT:    jump @.BB1_9
 ; CHECK-NEXT:  .BB1_7: ; %loop-bb4
 ; CHECK-NEXT:    ; in Loop: Header=BB1_4 Depth=1
-; CHECK-NEXT:    add @CPI1_3[0], r0, r9
+; CHECK-NEXT:    add code[@CPI1_3], r0, r9
 ; CHECK-NEXT:    jump @.BB1_9
 ; CHECK-NEXT:  .BB1_1:
 ; CHECK-NEXT:    add r0, r0, r2
diff --git a/llvm/test/CodeGen/EraVM/fold-mul-to-select.ll b/llvm/test/CodeGen/EraVM/fold-mul-to-select.ll
index 50cda42c7389..be2efe068318 100644
--- a/llvm/test/CodeGen/EraVM/fold-mul-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-mul-to-select.ll
@@ -9,8 +9,8 @@ declare { i256, i1 } @llvm.umul.with.overflow.i256(i256, i256)
 define i256 @test_lo_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_lo_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    mul.lt @CPI0_0[0], r1, r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    mul.lt code[@CPI0_0], r1, r1, r0
 ; CHECK-NEXT:    ret
   %mul = mul i256 %a, 26959946660873538059280334323183841250350249843923952699046031785980
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -21,8 +21,8 @@ define i256 @test_lo_large_imm1(i256 %a) {
 define i256 @test_hi_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_hi_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    mul.lt @CPI1_0[0], r1, r0, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    mul.lt code[@CPI1_0], r1, r0, r1
 ; CHECK-NEXT:    ret
   %al = zext i256 %a to i512
   %mul = mul i512 %al, 26959946660873538059280334323183841250350249843923952699046031785980
@@ -36,8 +36,8 @@ define i256 @test_hi_large_imm1(i256 %a) {
 define i256 @test_lo_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_lo_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_1[0], r1, r0
-; CHECK-NEXT:    mul.ge @CPI2_0[0], r1, r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI2_1], r1, r0
+; CHECK-NEXT:    mul.ge code[@CPI2_0], r1, r1, r0
 ; CHECK-NEXT:    ret
   %mul = mul i256 %a, 26959946660873538059280334323183841250350249843923952699046031785980
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -48,8 +48,8 @@ define i256 @test_lo_large_imm2(i256 %a) {
 define i256 @test_hi_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_hi_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_1[0], r1, r0
-; CHECK-NEXT:    mul.ge @CPI3_0[0], r1, r0, r1
+; CHECK-NEXT:    sub.s! code[@CPI3_1], r1, r0
+; CHECK-NEXT:    mul.ge code[@CPI3_0], r1, r0, r1
 ; CHECK-NEXT:    ret
   %al = zext i256 %a to i512
   %mul = mul i512 %al, 26959946660873538059280334323183841250350249843923952699046031785980
@@ -63,7 +63,7 @@ define i256 @test_hi_large_imm2(i256 %a) {
 define i256 @test_lo_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_lo_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI4_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI4_0], r1, r0
 ; CHECK-NEXT:    mul.lt 10, r1, r1, r0
 ; CHECK-NEXT:    ret
   %mul = mul i256 %a, 10
@@ -75,7 +75,7 @@ define i256 @test_lo_small_imm1(i256 %a) {
 define i256 @test_hi_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_hi_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI5_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI5_0], r1, r0
 ; CHECK-NEXT:    mul.lt 10, r1, r0, r1
 ; CHECK-NEXT:    ret
   %al = zext i256 %a to i512
@@ -90,7 +90,7 @@ define i256 @test_hi_small_imm1(i256 %a) {
 define i256 @test_lo_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_lo_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI6_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI6_0], r1, r0
 ; CHECK-NEXT:    mul.ge 10, r1, r1, r0
 ; CHECK-NEXT:    ret
   %mul = mul i256 %a, 10
@@ -102,7 +102,7 @@ define i256 @test_lo_small_imm2(i256 %a) {
 define i256 @test_hi_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_hi_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI7_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI7_0], r1, r0
 ; CHECK-NEXT:    mul.ge 10, r1, r0, r1
 ; CHECK-NEXT:    ret
   %al = zext i256 %a to i512
diff --git a/llvm/test/CodeGen/EraVM/fold-or-to-select.ll b/llvm/test/CodeGen/EraVM/fold-or-to-select.ll
index 681477041e59..a2a1563d949e 100644
--- a/llvm/test/CodeGen/EraVM/fold-or-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-or-to-select.ll
@@ -7,8 +7,8 @@ target triple = "eravm"
 define i256 @test_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    or.lt @CPI0_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    or.lt code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    ret
   %or = or i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -19,8 +19,8 @@ define i256 @test_large_imm1(i256 %a) {
 define i256 @test_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    or.ge @CPI1_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    or.ge code[@CPI1_0], r1, r1
 ; CHECK-NEXT:    ret
   %or = or i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -31,7 +31,7 @@ define i256 @test_large_imm2(i256 %a) {
 define i256 @test_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI2_0], r1, r0
 ; CHECK-NEXT:    or.lt 10, r1, r1
 ; CHECK-NEXT:    ret
   %or = or i256 10, %a
@@ -43,7 +43,7 @@ define i256 @test_small_imm1(i256 %a) {
 define i256 @test_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI3_0], r1, r0
 ; CHECK-NEXT:    or.ge 10, r1, r1
 ; CHECK-NEXT:    ret
   %or = or i256 10, %a
diff --git a/llvm/test/CodeGen/EraVM/fold-rol-to-select.ll b/llvm/test/CodeGen/EraVM/fold-rol-to-select.ll
index 6329728fcbad..b4bbea43a029 100644
--- a/llvm/test/CodeGen/EraVM/fold-rol-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-rol-to-select.ll
@@ -7,8 +7,8 @@ target triple = "eravm"
 define i256 @test_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    rol.lt @CPI0_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    rol.lt code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 256, %a
   %shl = shl i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
@@ -22,8 +22,8 @@ define i256 @test_large_imm1(i256 %a) {
 define i256 @test_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    rol.ge @CPI1_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    rol.ge code[@CPI1_0], r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 256, %a
   %shl = shl i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
@@ -37,7 +37,7 @@ define i256 @test_large_imm2(i256 %a) {
 define i256 @test_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI2_0], r1, r0
 ; CHECK-NEXT:    rol.lt 10, r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 256, %a
@@ -52,7 +52,7 @@ define i256 @test_small_imm1(i256 %a) {
 define i256 @test_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI3_0], r1, r0
 ; CHECK-NEXT:    rol.ge 10, r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 256, %a
diff --git a/llvm/test/CodeGen/EraVM/fold-ror-to-select.ll b/llvm/test/CodeGen/EraVM/fold-ror-to-select.ll
index aee35c671e0c..417f4160cfb1 100644
--- a/llvm/test/CodeGen/EraVM/fold-ror-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-ror-to-select.ll
@@ -7,8 +7,8 @@ target triple = "eravm"
 define i256 @test_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    ror.lt @CPI0_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    ror.lt code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 256, %a
   %lshr = lshr i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
@@ -22,8 +22,8 @@ define i256 @test_large_imm1(i256 %a) {
 define i256 @test_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    ror.ge @CPI1_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    ror.ge code[@CPI1_0], r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 256, %a
   %lshr = lshr i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
@@ -37,7 +37,7 @@ define i256 @test_large_imm2(i256 %a) {
 define i256 @test_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI2_0], r1, r0
 ; CHECK-NEXT:    ror.lt 10, r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 256, %a
@@ -52,7 +52,7 @@ define i256 @test_small_imm1(i256 %a) {
 define i256 @test_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI3_0], r1, r0
 ; CHECK-NEXT:    ror.ge 10, r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 256, %a
diff --git a/llvm/test/CodeGen/EraVM/fold-shl-to-select.ll b/llvm/test/CodeGen/EraVM/fold-shl-to-select.ll
index 596e04011f0f..575c7f051ded 100644
--- a/llvm/test/CodeGen/EraVM/fold-shl-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-shl-to-select.ll
@@ -7,8 +7,8 @@ target triple = "eravm"
 define i256 @test_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    shl.lt @CPI0_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    shl.lt code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    ret
   %shl = shl i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -19,8 +19,8 @@ define i256 @test_large_imm1(i256 %a) {
 define i256 @test_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    shl.ge @CPI1_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    shl.ge code[@CPI1_0], r1, r1
 ; CHECK-NEXT:    ret
   %shl = shl i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -31,7 +31,7 @@ define i256 @test_large_imm2(i256 %a) {
 define i256 @test_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI2_0], r1, r0
 ; CHECK-NEXT:    shl.lt 10, r1, r1
 ; CHECK-NEXT:    ret
   %shl = shl i256 10, %a
@@ -43,7 +43,7 @@ define i256 @test_small_imm1(i256 %a) {
 define i256 @test_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI3_0], r1, r0
 ; CHECK-NEXT:    shl.ge 10, r1, r1
 ; CHECK-NEXT:    ret
   %shl = shl i256 10, %a
diff --git a/llvm/test/CodeGen/EraVM/fold-shr-to-select.ll b/llvm/test/CodeGen/EraVM/fold-shr-to-select.ll
index c09f4b40a37c..107707645c83 100644
--- a/llvm/test/CodeGen/EraVM/fold-shr-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-shr-to-select.ll
@@ -7,8 +7,8 @@ target triple = "eravm"
 define i256 @test_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    shr.lt @CPI0_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    shr.lt code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    ret
   %shr = lshr i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -19,8 +19,8 @@ define i256 @test_large_imm1(i256 %a) {
 define i256 @test_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    shr.ge @CPI1_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    shr.ge code[@CPI1_0], r1, r1
 ; CHECK-NEXT:    ret
   %shr = lshr i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -31,7 +31,7 @@ define i256 @test_large_imm2(i256 %a) {
 define i256 @test_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI2_0], r1, r0
 ; CHECK-NEXT:    shr.lt 10, r1, r1
 ; CHECK-NEXT:    ret
   %shr = lshr i256 10, %a
@@ -43,7 +43,7 @@ define i256 @test_small_imm1(i256 %a) {
 define i256 @test_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI3_0], r1, r0
 ; CHECK-NEXT:    shr.ge 10, r1, r1
 ; CHECK-NEXT:    ret
   %shr = lshr i256 10, %a
diff --git a/llvm/test/CodeGen/EraVM/fold-similar-instructions.ll b/llvm/test/CodeGen/EraVM/fold-similar-instructions.ll
index 63064ab02b16..3a1aaa7124a3 100644
--- a/llvm/test/CodeGen/EraVM/fold-similar-instructions.ll
+++ b/llvm/test/CodeGen/EraVM/fold-similar-instructions.ll
@@ -9,8 +9,8 @@ target triple = "eravm"
 define i256 @test_large_imm_no_fold1(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_large_imm_no_fold1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s @CPI0_0[0], r1, r3
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
+; CHECK-NEXT:    sub.s code[@CPI0_0], r1, r3
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
 ; CHECK-NEXT:    add.lt r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
@@ -25,8 +25,8 @@ define i256 @test_large_imm_no_fold1(i256 %a, i1 %cond) {
 define i256 @test_large_imm_no_fold2(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_large_imm_no_fold2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s @CPI1_0[0], r1, r3
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
+; CHECK-NEXT:    sub.s code[@CPI1_0], r1, r3
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
 ; CHECK-NEXT:    add.lt r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
@@ -57,7 +57,7 @@ define i256 @test_small_imm_no_fold(i256 %a, i1 %cond) {
 define i256 @test_large_imm_ult1(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_large_imm_ult1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_0[0], r1, r3
+; CHECK-NEXT:    sub.s! code[@CPI3_0], r1, r3
 ; CHECK-NEXT:    add.lt r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
@@ -72,7 +72,7 @@ define i256 @test_large_imm_ult1(i256 %a, i1 %cond) {
 define i256 @test_large_imm_ult2(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_large_imm_ult2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI4_0[0], r1, r3
+; CHECK-NEXT:    sub.s! code[@CPI4_0], r1, r3
 ; CHECK-NEXT:    add.lt r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
@@ -87,7 +87,7 @@ define i256 @test_large_imm_ult2(i256 %a, i1 %cond) {
 define i256 @test_large_imm_ule1(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_large_imm_ule1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI5_0[0], r1, r3
+; CHECK-NEXT:    sub.s! code[@CPI5_0], r1, r3
 ; CHECK-NEXT:    add.le r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
@@ -102,7 +102,7 @@ define i256 @test_large_imm_ule1(i256 %a, i1 %cond) {
 define i256 @test_large_imm_ule2(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_large_imm_ule2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI6_0[0], r1, r3
+; CHECK-NEXT:    sub.s! code[@CPI6_0], r1, r3
 ; CHECK-NEXT:    add.le r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
@@ -119,7 +119,7 @@ define i256 @test_small_large_imm_ule(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_small_large_imm_ule:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub.s 65535, r1, r3
-; CHECK-NEXT:    sub.s! @CPI7_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI7_0], r1, r0
 ; CHECK-NEXT:    add.lt r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
@@ -134,7 +134,7 @@ define i256 @test_small_large_imm_ule(i256 %a, i1 %cond) {
 define i256 @test_large_imm_uge1(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_large_imm_uge1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI8_0[0], r1, r3
+; CHECK-NEXT:    sub.s! code[@CPI8_0], r1, r3
 ; CHECK-NEXT:    add.ge r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
@@ -149,7 +149,7 @@ define i256 @test_large_imm_uge1(i256 %a, i1 %cond) {
 define i256 @test_large_imm_uge2(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_large_imm_uge2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI9_0[0], r1, r3
+; CHECK-NEXT:    sub.s! code[@CPI9_0], r1, r3
 ; CHECK-NEXT:    add.ge r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
@@ -165,7 +165,7 @@ define i256 @test_large_imm_uge2(i256 %a, i1 %cond) {
 define i256 @test_small_large_imm_uge(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_small_large_imm_uge:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s @CPI10_0[0], r1, r3
+; CHECK-NEXT:    sub.s code[@CPI10_0], r1, r3
 ; CHECK-NEXT:    sub.s! 65535, r1, r0
 ; CHECK-NEXT:    add.gt r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
@@ -292,7 +292,7 @@ define i256 @test_stack2(i256 %a, i1 %cond) {
 define i256 @test_code1(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_code1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @val[0], r1, r3
+; CHECK-NEXT:    sub.s! code[@val], r1, r3
 ; CHECK-NEXT:    add.lt r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
@@ -308,7 +308,7 @@ define i256 @test_code1(i256 %a, i1 %cond) {
 define i256 @test_code2(i256 %a, i1 %cond) {
 ; CHECK-LABEL: test_code2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub! @val[0], r1, r3
+; CHECK-NEXT:    sub! code[@val], r1, r3
 ; CHECK-NEXT:    add.lt r3, r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    add.eq r3, r0, r1
diff --git a/llvm/test/CodeGen/EraVM/fold-sub-to-select.ll b/llvm/test/CodeGen/EraVM/fold-sub-to-select.ll
index be98d80cf32f..a877f635d9df 100644
--- a/llvm/test/CodeGen/EraVM/fold-sub-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-sub-to-select.ll
@@ -9,8 +9,8 @@ declare { i256, i1 } @llvm.usub.with.overflow.i256(i256, i256)
 define i256 @test_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    sub.lt @CPI0_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    sub.lt code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -21,8 +21,8 @@ define i256 @test_large_imm1(i256 %a) {
 define i256 @test_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    sub.ge @CPI1_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    sub.ge code[@CPI1_0], r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -33,7 +33,7 @@ define i256 @test_large_imm2(i256 %a) {
 define i256 @test_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI2_0], r1, r0
 ; CHECK-NEXT:    sub.lt 10, r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 10, %a
@@ -45,7 +45,7 @@ define i256 @test_small_imm1(i256 %a) {
 define i256 @test_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI3_0], r1, r0
 ; CHECK-NEXT:    sub.ge 10, r1, r1
 ; CHECK-NEXT:    ret
   %sub = sub i256 10, %a
diff --git a/llvm/test/CodeGen/EraVM/fold-xor-to-select.ll b/llvm/test/CodeGen/EraVM/fold-xor-to-select.ll
index 0fc3e3e71d4a..c3d7fe420889 100644
--- a/llvm/test/CodeGen/EraVM/fold-xor-to-select.ll
+++ b/llvm/test/CodeGen/EraVM/fold-xor-to-select.ll
@@ -7,8 +7,8 @@ target triple = "eravm"
 define i256 @test_large_imm1(i256 %a) {
 ; CHECK-LABEL: test_large_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI0_1[0], r1, r0
-; CHECK-NEXT:    xor.lt @CPI0_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI0_1], r1, r0
+; CHECK-NEXT:    xor.lt code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    ret
   %xor = xor i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -19,8 +19,8 @@ define i256 @test_large_imm1(i256 %a) {
 define i256 @test_large_imm2(i256 %a) {
 ; CHECK-LABEL: test_large_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI1_1[0], r1, r0
-; CHECK-NEXT:    xor.ge @CPI1_0[0], r1, r1
+; CHECK-NEXT:    sub.s! code[@CPI1_1], r1, r0
+; CHECK-NEXT:    xor.ge code[@CPI1_0], r1, r1
 ; CHECK-NEXT:    ret
   %xor = xor i256 26959946660873538059280334323183841250350249843923952699046031785980, %a
   %cmp = icmp ult i256 %a, -26959946660873538059280334323183841250350249843923952699046031785985
@@ -31,7 +31,7 @@ define i256 @test_large_imm2(i256 %a) {
 define i256 @test_small_imm1(i256 %a) {
 ; CHECK-LABEL: test_small_imm1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI2_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI2_0], r1, r0
 ; CHECK-NEXT:    xor.lt 10, r1, r1
 ; CHECK-NEXT:    ret
   %xor = xor i256 10, %a
@@ -43,7 +43,7 @@ define i256 @test_small_imm1(i256 %a) {
 define i256 @test_small_imm2(i256 %a) {
 ; CHECK-LABEL: test_small_imm2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s! @CPI3_0[0], r1, r0
+; CHECK-NEXT:    sub.s! code[@CPI3_0], r1, r0
 ; CHECK-NEXT:    xor.ge 10, r1, r1
 ; CHECK-NEXT:    ret
   %xor = xor i256 10, %a
diff --git a/llvm/test/CodeGen/EraVM/frame_memory.ll b/llvm/test/CodeGen/EraVM/frame_memory.ll
index 782933281072..d5205b67cced 100644
--- a/llvm/test/CodeGen/EraVM/frame_memory.ll
+++ b/llvm/test/CodeGen/EraVM/frame_memory.ll
@@ -75,7 +75,7 @@ define void @store_to_frame.i64(i64 %par) nounwind {
   store i64 %par, i64* %1, align 32
   store i64 %par, i64* %2, align 32
 ; TODO: CPR-1003
-; CHECK: add @CPI5_0[0], r0, r2
+; CHECK: add code[@CPI5_0], r0, r2
 ; CHECK: and stack-[1], r2, r3
 ; CHECK: or  r1, r3, stack-[1]
 ; CHECK: and stack-[2], r2, r2
@@ -88,7 +88,7 @@ define i64 @load_from_frame.i64(i64 %par) nounwind {
   %1 = alloca i64, align 32
 ; TODO: CPR-1003
 ; store i64 to stack
-; CHECK: add   @CPI6_0[0], r0, r2
+; CHECK: add   code[@CPI6_0], r0, r2
 ; CHECK: and   stack-[1], r2, r2
 ; CHECK: shl.s 192, r1, r1
 ; CHECK: or    r1, r2, stack-[1]
diff --git a/llvm/test/CodeGen/EraVM/global_initializers.ll b/llvm/test/CodeGen/EraVM/global_initializers.ll
index e4e4f410f4aa..d99fab56c9c6 100644
--- a/llvm/test/CodeGen/EraVM/global_initializers.ll
+++ b/llvm/test/CodeGen/EraVM/global_initializers.ll
@@ -11,9 +11,9 @@ target triple = "eravm"
 
 ; CHECK-LABEL: .text
 ; CHECK-NEXT: nop	stack+=[10 + r0]
-; CHECK-NEXT: add	@glob_initializer_0[0], r0, stack[@glob]
-; CHECK-NEXT: add	@glob.arr_initializer_1[0], r0, stack[@glob.arr + 1]
-; CHECK-NEXT: add	@glob.arr_initializer_3[0], r0, stack[@glob.arr + 3]
+; CHECK-NEXT: add	code[@glob_initializer_0], r0, stack[@glob]
+; CHECK-NEXT: add	code[@glob.arr_initializer_1], r0, stack[@glob.arr + 1]
+; CHECK-NEXT: add	code[@glob.arr_initializer_3], r0, stack[@glob.arr + 3]
 
 
 ; CHECK-LABEL: glob_initializer_0:
diff --git a/llvm/test/CodeGen/EraVM/globals.ll b/llvm/test/CodeGen/EraVM/globals.ll
index 8f1c0fa8df3c..184ff2578d5e 100644
--- a/llvm/test/CodeGen/EraVM/globals.ll
+++ b/llvm/test/CodeGen/EraVM/globals.ll
@@ -57,7 +57,7 @@ define i256 @load.fromcodearray(i256 %i) nounwind {
   %elem = getelementptr [4 x i256], [4 x i256] addrspace(4)* @val.code.arr, i256 0, i256 1
   %elem2 = getelementptr i256, i256 addrspace(4)* %elem, i256 %i
 ; CHECK: add 1, r1, r[[REG:[0-9]+]]
-; CHECK: add @val.code.arr[r[[REG]]], r0, r1
+; CHECK: add code[@val.code.arr+r[[REG]]], r0, r1
   %res = load i256, i256 addrspace(4)* %elem2
   ret i256 %res
 }
diff --git a/llvm/test/CodeGen/EraVM/hoist-flag-setting.ll b/llvm/test/CodeGen/EraVM/hoist-flag-setting.ll
index ed6d41344144..452e7a13a7cc 100644
--- a/llvm/test/CodeGen/EraVM/hoist-flag-setting.ll
+++ b/llvm/test/CodeGen/EraVM/hoist-flag-setting.ll
@@ -75,8 +75,8 @@ define i256 @test_hoist_2(i256 %0, i256 %1, i256 addrspace(1)* %2, i256 addrspac
 define i256 @test_hoist_const(i256 %0) {
 ; CHECK-LABEL: test_hoist_const
 ; CHECK:      .BB2_2:
-; CHECK:        and! @CPI2_0[0], r1, r0
-; CHECK-NEXT:   mul @CPI2_0[0], r1, r1, r0
+; CHECK:        and! code[@CPI2_0], r1, r0
+; CHECK-NEXT:   mul code[@CPI2_0], r1, r1, r0
 ; CHECK-NEXT:   add 1, r2, r2
 ; CHECK-NEXT:   jump.ne @.BB2_2
 
diff --git a/llvm/test/CodeGen/EraVM/icmp.ll b/llvm/test/CodeGen/EraVM/icmp.ll
index 92c7054e812d..0a977a3e6719 100644
--- a/llvm/test/CodeGen/EraVM/icmp.ll
+++ b/llvm/test/CodeGen/EraVM/icmp.ll
@@ -23,7 +23,7 @@ define i256 @small_imm2(i256 %par) nounwind {
 
 ; CHECK-LABEL: large_imm1
 define i256 @large_imm1(i256 %par) nounwind {
-  ; CHECK: sub.s!  @CPI{{[0-9]+_[0-9]+}}[0], r{{[0-9]}}, r{{[0-9]}}
+  ; CHECK: sub.s!  code[@CPI{{[0-9]+_[0-9]+}}], r{{[0-9]}}, r{{[0-9]}}
   %1 = icmp ugt i256 %par, 1234567890123456789
   ; CHECK: add.gt 1, r{{[0-9]}}, r{{[0-9]}}
   %2 = zext i1 %1 to i256
@@ -32,7 +32,7 @@ define i256 @large_imm1(i256 %par) nounwind {
 
 ; CHECK-LABEL: large_imm2
 define i256 @large_imm2(i256 %par) nounwind {
-  ; CHECK: sub.s!  @CPI{{[0-9]+_[0-9]+}}[0], r{{[0-9]}}, r{{[0-9]}}
+  ; CHECK: sub.s!  code[@CPI{{[0-9]+_[0-9]+}}], r{{[0-9]}}, r{{[0-9]}}
   %1 = icmp ugt i256 1234567890123456789, %par
   ; CHECK: add.lt 1, r{{[0-9]}}, r{{[0-9]}}
   %2 = zext i1 %1 to i256
diff --git a/llvm/test/CodeGen/EraVM/immediate-remat.ll b/llvm/test/CodeGen/EraVM/immediate-remat.ll
index 0b1784b91568..bacf70caff03 100644
--- a/llvm/test/CodeGen/EraVM/immediate-remat.ll
+++ b/llvm/test/CodeGen/EraVM/immediate-remat.ll
@@ -33,9 +33,9 @@ entry:
 define i256 @test_large_imm_pos() {
 ; CHECK-LABEL: test_large_imm_pos:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    add @CPI2_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI2_0], r0, r1
 ; CHECK-NEXT:    near_call r0, @use, @DEFAULT_UNWIND
-; CHECK-NEXT:    add @CPI2_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI2_0], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   call void @use(i256 123456789)
@@ -45,9 +45,9 @@ entry:
 define i256 @test_large_imm_neg() {
 ; CHECK-LABEL: test_large_imm_neg:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    add @CPI3_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI3_0], r0, r1
 ; CHECK-NEXT:    near_call r0, @use, @DEFAULT_UNWIND
-; CHECK-NEXT:    add @CPI3_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI3_0], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   call void @use(i256 -123456789)
diff --git a/llvm/test/CodeGen/EraVM/immediate.ll b/llvm/test/CodeGen/EraVM/immediate.ll
index b7d47bfb4ffe..2287ce0414ec 100644
--- a/llvm/test/CodeGen/EraVM/immediate.ll
+++ b/llvm/test/CodeGen/EraVM/immediate.ll
@@ -19,7 +19,7 @@ define i256 @materialize_small_imm() nounwind {
 
 ; CHECK-LABEL: materialize_big_imm
 define i256 @materialize_big_imm() nounwind {
-  ; CHECK: add @CPI{{[0-9]}}_0[0], r0, r1
+  ; CHECK: add code[@CPI{{[0-9]}}_0], r0, r1
   ret i256 65536
 }
 
@@ -64,14 +64,14 @@ define i256 @materialize_small_negimm_in_operation_2(i256 %par) nounwind {
 
 ; CHECK-LABEL: materialize_bigimm_in_and_operation
 define i256 @materialize_bigimm_in_and_operation(i256 %par) nounwind {
-  ; CHECK: and @CPI9_0[0], r1, r1
+  ; CHECK: and code[@CPI9_0], r1, r1
   %res = and i256 %par, -42
   ret i256 %res
 }
 
 ; CHECK-LABEL: materialize_bigimm_in_xor_operation
 define i256 @materialize_bigimm_in_xor_operation(i256 %par) nounwind {
-  ; CHECK: xor @CPI10_0[0], r1, r1
+  ; CHECK: xor code[@CPI10_0], r1, r1
   %res = xor i256 -42, %par
   ret i256 %res
 }
@@ -85,7 +85,7 @@ define i256 @materialize_bigimm_in_sub_operation(i256 %par) nounwind {
 
 ; CHECK-LABEL: materialize_bigimm_in_sub_operation_2
 define i256 @materialize_bigimm_in_sub_operation_2(i256 %par) nounwind {
-  ; CHECK: sub @CPI12_0[0], r1, r1
+  ; CHECK: sub code[@CPI12_0], r1, r1
   %res = sub i256 -42, %par
   ret i256 %res
 }
@@ -100,14 +100,14 @@ define i256 @materialize_bigimm_in_sub_operation_2_minsize(i256 %par) nounwind m
 
 ; CHECK-LABEL: materialize_bigimm_1
 define i256 @materialize_bigimm_1(i256 %par) nounwind {
-  ; CHECK: sub @CPI14_0[0], r1, r1
+  ; CHECK: sub code[@CPI14_0], r1, r1
   %res = sub i256 12345678901234567890, %par
   ret i256 %res
 }
 
 ; CHECK-LABEL: materialize_bigimm_2
 define i256 @materialize_bigimm_2(i256 %par) nounwind {
-  ; CHECK: sub @CPI15_0[0], r1, r1
+  ; CHECK: sub code[@CPI15_0], r1, r1
   %res = sub i256 12345678901234567890, %par
   ret i256 %res
 }
diff --git a/llvm/test/CodeGen/EraVM/jumptable-block-placement-bug.ll b/llvm/test/CodeGen/EraVM/jumptable-block-placement-bug.ll
index 205472ba7f87..64444354eeee 100644
--- a/llvm/test/CodeGen/EraVM/jumptable-block-placement-bug.ll
+++ b/llvm/test/CodeGen/EraVM/jumptable-block-placement-bug.ll
@@ -6,7 +6,7 @@ target triple = "eravm"
 define i256 @test(i256 %cond) {
 ; CHECK-LABEL: test:
 ; CHECK:         sub.s! 3, r1, r0
-; CHECK-NEXT:    jump.le @JTI0_0[r1]
+; CHECK-NEXT:    jump.le code[@JTI0_0+r1]
 ; CHECK:       .BB0_1:
 ; CHECK-NEXT:    add r0, r0, r1
 ; CHECK-NEXT:    ret
diff --git a/llvm/test/CodeGen/EraVM/jumptable.ll b/llvm/test/CodeGen/EraVM/jumptable.ll
index f412363fdc1a..35caad7a648e 100644
--- a/llvm/test/CodeGen/EraVM/jumptable.ll
+++ b/llvm/test/CodeGen/EraVM/jumptable.ll
@@ -5,7 +5,7 @@ target triple = "eravm"
 
 define i256 @test(i256 %a, i256 %b, i256 %cond) {
 ; CHECK-LABEL: test:
-; CHECK:         jump.le @JTI0_0[r3]
+; CHECK:         jump.le code[@JTI0_0+r3]
 ; CHECK-NEXT:    jump @.BB0_6
 entry:
   switch i256 %cond, label %return [
diff --git a/llvm/test/CodeGen/EraVM/loadconst-ifcvt.ll b/llvm/test/CodeGen/EraVM/loadconst-ifcvt.ll
index b840a257c055..2719ce89a0c4 100644
--- a/llvm/test/CodeGen/EraVM/loadconst-ifcvt.ll
+++ b/llvm/test/CodeGen/EraVM/loadconst-ifcvt.ll
@@ -8,9 +8,9 @@ define i256 @test(i1 %cond) {
 ; CHECK-LABEL: test:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add r1, r0, r2
-; CHECK-NEXT:    add @CPI0_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI0_0], r0, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
-; CHECK-NEXT:    add.ne @CPI0_1[0], r0, r1
+; CHECK-NEXT:    add.ne code[@CPI0_1], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   br i1 %cond, label %bb1, label %exit
diff --git a/llvm/test/CodeGen/EraVM/machine-outliner-tail.mir b/llvm/test/CodeGen/EraVM/machine-outliner-tail.mir
index a7c68c2f264f..9d36b4a59cdf 100644
--- a/llvm/test/CodeGen/EraVM/machine-outliner-tail.mir
+++ b/llvm/test/CodeGen/EraVM/machine-outliner-tail.mir
@@ -28,11 +28,11 @@
 # CHECK-LABEL: foo
 # CHECK-LABEL: bb.0:
 # CHECK: NOPrrs $r0, $r0, $r0, $r0, 2, 0, implicit-def $sp, implicit $sp
-# CHECK-NEXT: ADDcrs_s target-flags(<unknown>) <mcsymbol >, 0, $r0, $sp, 0, -1, 0
+# CHECK-NEXT: ADDirs_s target-flags(<unknown>) <mcsymbol >, $r0, $sp, 0, -1, 0
 # CHECK-NEXT: JCALL @OUTLINED_FUNCTION_1, implicit-def $r1, implicit $sp, implicit $r1, implicit $r2, post-instr-symbol <mcsymbol >
 
 # CHECK-LABEL: bb.1:
-# CHECK: ADDcrs_s target-flags(<unknown>) <mcsymbol >, 0, $r0, $sp, 0, -1, 0
+# CHECK: ADDirs_s target-flags(<unknown>) <mcsymbol >, $r0, $sp, 0, -1, 0
 # CHECK-NEXT: JCALL @OUTLINED_FUNCTION_1, implicit-def $r1, implicit $sp, implicit $r1, implicit $r2, post-instr-symbol <mcsymbol >
 
 # CHECK-LABEL: bb.2:
diff --git a/llvm/test/CodeGen/EraVM/machine-outliner.mir b/llvm/test/CodeGen/EraVM/machine-outliner.mir
index 0e155003f593..11385ad19a19 100644
--- a/llvm/test/CodeGen/EraVM/machine-outliner.mir
+++ b/llvm/test/CodeGen/EraVM/machine-outliner.mir
@@ -19,12 +19,12 @@
 # CHECK-LABEL: foo
 # CHECK-LABEL: bb.0:
 # CHECK: NOPrrs $r0, $r0, $r0, $r0, 1, 0, implicit-def $sp, implicit $sp
-# CHECK-NEXT: ADDcrs_s target-flags(<unknown>) <mcsymbol >, 0, $r0, $sp, 0, -1, 0
+# CHECK-NEXT: ADDirs_s target-flags(<unknown>) <mcsymbol >, $r0, $sp, 0, -1, 0
 # CHECK-NEXT: JCALL @OUTLINED_FUNCTION_2, implicit-def $r1, implicit-def $flags, implicit $r2, implicit $r1, post-instr-symbol <mcsymbol >
 # CHECK-NEXT: $r1 = ADDirr_s i256 1, $r0, 2, implicit $flags
 
 # CHECK-LABEL: bb.1:
-# CHECK: ADDcrs_s target-flags(<unknown>) <mcsymbol >, 0, $r0, $sp, 0, -1, 0
+# CHECK: ADDirs_s target-flags(<unknown>) <mcsymbol >, $r0, $sp, 0, -1, 0
 # CHECK-NEXT: JCALL @OUTLINED_FUNCTION_2, implicit-def $r1, implicit-def $flags, implicit $r2, implicit $r1, post-instr-symbol <mcsymbol >
 # CHECK-NEXT: $r1 = ORrrr_s $r1, $r2, 0
 # CHECK-NEXT: $r1 = ADDirr_s i256 1, $r0, 2, implicit $flags
@@ -67,12 +67,12 @@ body:             |
 # CHECK-LABEL: bb.0:
 # CHECK: NOPrrs $r0, $r0, $r0, $r0, 1, 0, implicit-def $sp, implicit $sp
 # CHECK-NEXT: $r3 = CTXGasLeft i256 0
-# CHECK-NEXT: ADDcrs_s target-flags(<unknown>) <mcsymbol >, 0, $r0, $sp, 0, -1, 0
+# CHECK-NEXT: ADDirs_s target-flags(<unknown>) <mcsymbol >, $r0, $sp, 0, -1, 0
 # CHECK-NEXT: JCALL @OUTLINED_FUNCTION_1, implicit-def $r1, implicit $r2, implicit $r1, post-instr-symbol <mcsymbol >
 
 # CHECK-LABEL: bb.1:
 # CHECK: $r3 = CTXGasLeft i256 0
-# CHECK-NEXT: ADDcrs_s target-flags(<unknown>) <mcsymbol >, 0, $r0, $sp, 0, -1, 0
+# CHECK-NEXT: ADDirs_s target-flags(<unknown>) <mcsymbol >, $r0, $sp, 0, -1, 0
 # CHECK-NEXT: JCALL @OUTLINED_FUNCTION_1, implicit-def $r1, implicit $r2, implicit $r1, post-instr-symbol <mcsymbol >
 # CHECK-NEXT: RET
 name:            bar
@@ -114,11 +114,11 @@ body:             |
 # CHECK-NEXT: ADDsrs_s $sp, 0, -2, $r1, $sp, 0, -2, 0
 # CHECK-NEXT: SHRxrs_s i256 224, $r2, $sp, i256 0, -2, 0
 # CHECK-NEXT: $r1 = SUBzrr_s $sp, i256 0, -2, $r2, 0
-# CHECK-NEXT: ADDcrs_s target-flags(<unknown>) <mcsymbol >, 0, $r0, $sp, 0, -1, 0
+# CHECK-NEXT: ADDirs_s target-flags(<unknown>) <mcsymbol >, $r0, $sp, 0, -1, 0
 # CHECK-NEXT: JCALL @OUTLINED_FUNCTION_0, implicit-def $r2, implicit $sp, implicit $r0, implicit $r1, post-instr-symbol <mcsymbol >
 
 # CHECK-LABEL: bb.1:
-# CHECK: ADDcrs_s target-flags(<unknown>) <mcsymbol >, 0, $r0, $sp, 0, -1, 0
+# CHECK: ADDirs_s target-flags(<unknown>) <mcsymbol >, $r0, $sp, 0, -1, 0
 # CHECK-NEXT: JCALL @OUTLINED_FUNCTION_0, implicit-def $r2, implicit $sp, implicit $r0, implicit $r1, post-instr-symbol <mcsymbol >
 # CHECK-NEXT: RET
 name:            baz
diff --git a/llvm/test/CodeGen/EraVM/machinesink-inst-with-cp-operand.ll b/llvm/test/CodeGen/EraVM/machinesink-inst-with-cp-operand.ll
index aefd40369a5c..8bfe1db9eb21 100644
--- a/llvm/test/CodeGen/EraVM/machinesink-inst-with-cp-operand.ll
+++ b/llvm/test/CodeGen/EraVM/machinesink-inst-with-cp-operand.ll
@@ -12,7 +12,7 @@ define i256 @test(i256 %in, i1 %cond) {
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    jump.eq @.BB0_2
 ; CHECK-NEXT:  ; %bb.1: ; %bb1
-; CHECK-NEXT:    and @CPI0_0[0], r1, r1
+; CHECK-NEXT:    and code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    near_call r0, @use, @DEFAULT_UNWIND
 ; CHECK-NEXT:    add r0, r0, r1
 ; CHECK-NEXT:    ret
diff --git a/llvm/test/CodeGen/EraVM/memcpy-expansion-asm.ll b/llvm/test/CodeGen/EraVM/memcpy-expansion-asm.ll
index 9a498f0b0924..393e9b097091 100644
--- a/llvm/test/CodeGen/EraVM/memcpy-expansion-asm.ll
+++ b/llvm/test/CodeGen/EraVM/memcpy-expansion-asm.ll
@@ -10,7 +10,7 @@ declare void @llvm.memcpy.p1.p3.i256(ptr addrspace(1), ptr addrspace(3), i256, i
 define void @expand_unknown_p1_p3(ptr addrspace(1) %dest, ptr addrspace(3) %src, i256 %size) {
 ; CHECK-LABEL: expand_unknown_p1_p3:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    and! @CPI0_0[0], r3, r4
+; CHECK-NEXT:    and! code[@CPI0_0], r3, r4
 ; CHECK-NEXT:    and 31, r3, r5
 ; CHECK-NEXT:    add r1, r4, r3
 ; CHECK-NEXT:    jump.eq @.BB0_3
@@ -47,7 +47,7 @@ entry:
 define void @expand_unknown_p1_p1(ptr addrspace(1) %dest, ptr addrspace(1) %src, i256 %size) {
 ; CHECK-LABEL: expand_unknown_p1_p1:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    and! @CPI1_0[0], r3, r4
+; CHECK-NEXT:    and! code[@CPI1_0], r3, r4
 ; CHECK-NEXT:    and 31, r3, r5
 ; CHECK-NEXT:    add r1, r4, r3
 ; CHECK-NEXT:    jump.eq @.BB1_3
@@ -87,9 +87,9 @@ define void @expand_known_p1_p3_loop_iter1(ptr addrspace(1) %dest, ptr addrspace
 ; CHECK-NEXT:    ld.inc r2, r2, r3
 ; CHECK-NEXT:    st.1.inc r1, r2, r1
 ; CHECK-NEXT:    ld.1 r1, r2
-; CHECK-NEXT:    and @CPI2_0[0], r2, r2
+; CHECK-NEXT:    and code[@CPI2_0], r2, r2
 ; CHECK-NEXT:    ld r3, r3
-; CHECK-NEXT:    and @CPI2_1[0], r3, r3
+; CHECK-NEXT:    and code[@CPI2_1], r3, r3
 ; CHECK-NEXT:    or r3, r2, r2
 ; CHECK-NEXT:    st.1 r1, r2
 ; CHECK-NEXT:    ret
@@ -104,9 +104,9 @@ define void @expand_known_p1_p1_loop_iter1(ptr addrspace(1) %dest, ptr addrspace
 ; CHECK-NEXT:    ld.1.inc r2, r2, r3
 ; CHECK-NEXT:    st.1.inc r1, r2, r1
 ; CHECK-NEXT:    ld.1 r1, r2
-; CHECK-NEXT:    and @CPI3_0[0], r2, r2
+; CHECK-NEXT:    and code[@CPI3_0], r2, r2
 ; CHECK-NEXT:    ld.1 r3, r3
-; CHECK-NEXT:    and @CPI3_1[0], r3, r3
+; CHECK-NEXT:    and code[@CPI3_1], r3, r3
 ; CHECK-NEXT:    or r3, r2, r2
 ; CHECK-NEXT:    st.1 r1, r2
 ; CHECK-NEXT:    ret
@@ -128,10 +128,10 @@ define void @expand_known_p1_p3_loop_iter2(ptr addrspace(1) %dest, ptr addrspace
 ; CHECK-NEXT:    jump.ne @.BB4_1
 ; CHECK-NEXT:  ; %bb.2: ; %memcpy-split
 ; CHECK-NEXT:    ld.1 r3, r1
-; CHECK-NEXT:    and @CPI4_0[0], r1, r1
+; CHECK-NEXT:    and code[@CPI4_0], r1, r1
 ; CHECK-NEXT:    ptr.add.s 64, r2, r2
 ; CHECK-NEXT:    ld r2, r2
-; CHECK-NEXT:    and @CPI4_1[0], r2, r2
+; CHECK-NEXT:    and code[@CPI4_1], r2, r2
 ; CHECK-NEXT:    or r2, r1, r1
 ; CHECK-NEXT:    st.1 r3, r1
 ; CHECK-NEXT:    ret
@@ -153,10 +153,10 @@ define void @expand_known_p1_p1_loop_iter2(ptr addrspace(1) %dest, ptr addrspace
 ; CHECK-NEXT:    jump.ne @.BB5_1
 ; CHECK-NEXT:  ; %bb.2: ; %memcpy-split
 ; CHECK-NEXT:    ld.1 r3, r1
-; CHECK-NEXT:    and @CPI5_0[0], r1, r1
+; CHECK-NEXT:    and code[@CPI5_0], r1, r1
 ; CHECK-NEXT:    add 64, r2, r2
 ; CHECK-NEXT:    ld.1 r2, r2
-; CHECK-NEXT:    and @CPI5_1[0], r2, r2
+; CHECK-NEXT:    and code[@CPI5_1], r2, r2
 ; CHECK-NEXT:    or r2, r1, r1
 ; CHECK-NEXT:    st.1 r3, r1
 ; CHECK-NEXT:    ret
diff --git a/llvm/test/CodeGen/EraVM/memintrinsics.ll b/llvm/test/CodeGen/EraVM/memintrinsics.ll
index 677cd5317b6b..d714cc5dc8b7 100644
--- a/llvm/test/CodeGen/EraVM/memintrinsics.ll
+++ b/llvm/test/CodeGen/EraVM/memintrinsics.ll
@@ -10,7 +10,7 @@ declare void @llvm.memcpy.p2i256.p2i256.i256(i256 addrspace(2)* noalias nocaptur
 define fastcc void @huge_copysize0(i256 addrspace(0)* %dest, i256 addrspace(0)* %src) {
 ; CHECK-LABEL: huge_copysize0:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s @CPI0_0[0], r1, r3
+; CHECK-NEXT:    sub.s code[@CPI0_0], r1, r3
 ; CHECK-NEXT:  .BB0_1: ; %load-store-loop
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    shr.s 5, r2, r4
@@ -30,7 +30,7 @@ define fastcc void @huge_copysize0(i256 addrspace(0)* %dest, i256 addrspace(0)*
 define fastcc void @huge_copysize1(i256 addrspace(1)* %dest, i256 addrspace(1)* %src) {
 ; CHECK-LABEL: huge_copysize1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s @CPI1_0[0], r1, r3
+; CHECK-NEXT:    sub.s code[@CPI1_0], r1, r3
 ; CHECK-NEXT:    add r2, r0, r4
 ; CHECK-NEXT:  .BB1_1: ; %load-store-loop
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
@@ -40,10 +40,10 @@ define fastcc void @huge_copysize1(i256 addrspace(1)* %dest, i256 addrspace(1)*
 ; CHECK-NEXT:    jump.ne @.BB1_1
 ; CHECK-NEXT:  ; %bb.2: ; %memcpy-split
 ; CHECK-NEXT:    ld.1 r3, r1
-; CHECK-NEXT:    and @CPI1_1[0], r1, r1
-; CHECK-NEXT:    sub.s @CPI1_0[0], r2, r2
+; CHECK-NEXT:    and code[@CPI1_1], r1, r1
+; CHECK-NEXT:    sub.s code[@CPI1_0], r2, r2
 ; CHECK-NEXT:    ld.1 r2, r2
-; CHECK-NEXT:    and @CPI1_2[0], r2, r2
+; CHECK-NEXT:    and code[@CPI1_2], r2, r2
 ; CHECK-NEXT:    or r2, r1, r1
 ; CHECK-NEXT:    st.1 r3, r1
 ; CHECK-NEXT:    ret
@@ -54,7 +54,7 @@ define fastcc void @huge_copysize1(i256 addrspace(1)* %dest, i256 addrspace(1)*
 define fastcc void @huge_copysize2(i256 addrspace(2)* %dest, i256 addrspace(2)* %src) {
 ; CHECK-LABEL: huge_copysize2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.s @CPI2_0[0], r1, r3
+; CHECK-NEXT:    sub.s code[@CPI2_0], r1, r3
 ; CHECK-NEXT:    add r2, r0, r4
 ; CHECK-NEXT:  .BB2_1: ; %load-store-loop
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
@@ -64,10 +64,10 @@ define fastcc void @huge_copysize2(i256 addrspace(2)* %dest, i256 addrspace(2)*
 ; CHECK-NEXT:    jump.ne @.BB2_1
 ; CHECK-NEXT:  ; %bb.2: ; %memcpy-split
 ; CHECK-NEXT:    ld.2 r3, r1
-; CHECK-NEXT:    and @CPI2_1[0], r1, r1
-; CHECK-NEXT:    sub.s @CPI2_0[0], r2, r2
+; CHECK-NEXT:    and code[@CPI2_1], r1, r1
+; CHECK-NEXT:    sub.s code[@CPI2_0], r2, r2
 ; CHECK-NEXT:    ld.2 r2, r2
-; CHECK-NEXT:    and @CPI2_2[0], r2, r2
+; CHECK-NEXT:    and code[@CPI2_2], r2, r2
 ; CHECK-NEXT:    or r2, r1, r1
 ; CHECK-NEXT:    st.2 r3, r1
 ; CHECK-NEXT:    ret
@@ -112,10 +112,10 @@ define fastcc void @normal_known_size_2(i256* %dest, i256* %src) {
 ; CHECK-NEXT:    sub! r5, r3, r0
 ; CHECK-NEXT:    jump.ne @.BB4_1
 ; CHECK-NEXT:  ; %bb.2: ; %memcpy-split
-; CHECK-NEXT:    add @CPI4_0[0], r0, r3
+; CHECK-NEXT:    add code[@CPI4_0], r0, r3
 ; CHECK-NEXT:    shr.s 5, r2, r2
 ; CHECK-NEXT:    and stack[33 + r2], r3, r2
-; CHECK-NEXT:    add @CPI4_1[0], r0, r3
+; CHECK-NEXT:    add code[@CPI4_1], r0, r3
 ; CHECK-NEXT:    shr.s 5, r1, r1
 ; CHECK-NEXT:    and stack[33 + r1], r3, r3
 ; CHECK-NEXT:    or r2, r3, stack[33 + r1]
diff --git a/llvm/test/CodeGen/EraVM/memmove-expansion-asm.ll b/llvm/test/CodeGen/EraVM/memmove-expansion-asm.ll
index 5bffdb5c0b88..9b87ea081dbe 100644
--- a/llvm/test/CodeGen/EraVM/memmove-expansion-asm.ll
+++ b/llvm/test/CodeGen/EraVM/memmove-expansion-asm.ll
@@ -10,7 +10,7 @@ declare void @llvm.memmove.p1.p1.i256(ptr addrspace(1), ptr addrspace(1), i256,
 define i256 @expand_unknown(ptr addrspace(1) %dst, ptr addrspace(1) %src, i256 %size) {
 ; CHECK-LABEL: expand_unknown:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    and @CPI0_0[0], r3, r4
+; CHECK-NEXT:    and code[@CPI0_0], r3, r4
 ; CHECK-NEXT:    and 31, r3, r3
 ; CHECK-NEXT:    sub! r2, r1, r0
 ; CHECK-NEXT:    jump.ge @.BB0_5
@@ -86,7 +86,7 @@ define i256 @expand_known_backward() {
 ; CHECK-NEXT:    jump.ne @.BB1_1
 ; CHECK-NEXT:  ; %bb.2: ; %copy-backwards-residual-cond
 ; CHECK-NEXT:    ld.1 10, r2
-; CHECK-NEXT:    and @CPI1_0[0], r2, r1
+; CHECK-NEXT:    and code[@CPI1_0], r2, r1
 ; CHECK-NEXT:    ld.1 100, r2
 ; CHECK-NEXT:    and 255, r2, r2
 ; CHECK-NEXT:    or r1, r2, r1
@@ -114,9 +114,9 @@ define i256 @expand_known_loop_iter1(ptr addrspace(1) %dst, ptr addrspace(1) %sr
 ; CHECK-NEXT:    st.1.inc r1, r3, r1
 ; CHECK-NEXT:  .BB2_3: ; %memmove-residual
 ; CHECK-NEXT:    ld.1 r1, r3
-; CHECK-NEXT:    and @CPI2_0[0], r3, r3
+; CHECK-NEXT:    and code[@CPI2_0], r3, r3
 ; CHECK-NEXT:    ld.1 r2, r2
-; CHECK-NEXT:    and @CPI2_1[0], r2, r2
+; CHECK-NEXT:    and code[@CPI2_1], r2, r2
 ; CHECK-NEXT:    or r2, r3, r2
 ; CHECK-NEXT:    st.1 r1, r2
 ; CHECK-NEXT:    add r0, r0, r1
@@ -159,9 +159,9 @@ define i256 @expand_known_loop_iter2(ptr addrspace(1) %dst, ptr addrspace(1) %sr
 ; CHECK-NEXT:    add 64, r2, r2
 ; CHECK-NEXT:  .BB3_7: ; %memmove-residual
 ; CHECK-NEXT:    ld.1 r3, r1
-; CHECK-NEXT:    and @CPI3_0[0], r1, r1
+; CHECK-NEXT:    and code[@CPI3_0], r1, r1
 ; CHECK-NEXT:    ld.1 r2, r2
-; CHECK-NEXT:    and @CPI3_1[0], r2, r2
+; CHECK-NEXT:    and code[@CPI3_1], r2, r2
 ; CHECK-NEXT:    or r2, r1, r1
 ; CHECK-NEXT:    st.1 r3, r1
 ; CHECK-NEXT:    add r0, r0, r1
diff --git a/llvm/test/CodeGen/EraVM/mov.ll b/llvm/test/CodeGen/EraVM/mov.ll
index 1ee8cf9d7b6c..58c864c367b4 100644
--- a/llvm/test/CodeGen/EraVM/mov.ll
+++ b/llvm/test/CodeGen/EraVM/mov.ll
@@ -19,7 +19,7 @@ define i256 @movirr() nounwind {
 
 ; CHECK-LABEL: movcrr
 define i256 @movcrr() nounwind {
-; CHECK: add @val[0], r0, r1
+; CHECK: add code[@val], r0, r1
   %val = load i256, i256 addrspace(4)* @val
   ret i256 %val
 }
@@ -51,7 +51,7 @@ define void @movirs(i256 %rs1) nounwind {
 ; CHECK-LABEL: movcrs
 define void @movcrs() nounwind {
   %valptr = alloca i256
-; CHECK: add @val[0], r0, stack-[1]
+; CHECK: add code[@val], r0, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   store i256 %val, i256* %valptr
   ret void
diff --git a/llvm/test/CodeGen/EraVM/mul.ll b/llvm/test/CodeGen/EraVM/mul.ll
index 5041a35b13fe..926563c80920 100644
--- a/llvm/test/CodeGen/EraVM/mul.ll
+++ b/llvm/test/CodeGen/EraVM/mul.ll
@@ -21,7 +21,7 @@ define i256 @mulirr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: mulcrr
 define i256 @mulcrr(i256 %rs1) nounwind {
-; CHECK: mul @val[0], r1, r1, r{{[0-9]+}}
+; CHECK: mul code[@val], r1, r1, r{{[0-9]+}}
   %val = load i256, i256 addrspace(4)* @val
   %res = mul i256 %rs1, %val
   ret i256 %res
@@ -57,7 +57,7 @@ define void @mulirs(i256 %rs1) nounwind {
 ; CHECK-LABEL: mulcrs
 define void @mulcrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: mul @val[0], r1, stack-[1], r{{[0-9]+}}
+; CHECK: mul code[@val], r1, stack-[1], r{{[0-9]+}}
   %val = load i256, i256 addrspace(4)* @val
   %res = mul i256 %rs1, %val
   store i256 %res, i256* %valptr
@@ -107,7 +107,7 @@ define i256 @mulhicrr(i256 %rs1) nounwind {
   %rs1l = zext i256 %rs1 to i512
   %val = load i256, i256 addrspace(4)* @val
   %rs2l = zext i256 %val to i512
-; CHECK: mul @val[0], r1, r[[REG1:[0-9]+]], r[[REG2:[0-9]+]]
+; CHECK: mul code[@val], r1, r[[REG1:[0-9]+]], r[[REG2:[0-9]+]]
   %resl = mul i512 %rs1l, %rs2l
   %res1 = trunc i512 %resl to i256
   %res2l = lshr i512 %resl, 256
@@ -164,7 +164,7 @@ define i256 @umullohiirsr(i256 %rs1) nounwind {
 define i256 @umullohicrsr(i256 %rs1) nounwind {
   %rs1l = zext i256 %rs1 to i512
   %valptr = alloca i256
-; CHECK: mul @val[0], r1, stack-[1], r1
+; CHECK: mul code[@val], r1, stack-[1], r1
   %val = load i256, i256 addrspace(4)* @val
   %rs2l = zext i256 %val to i512
   %resl = mul i512 %rs1l, %rs2l
diff --git a/llvm/test/CodeGen/EraVM/or.ll b/llvm/test/CodeGen/EraVM/or.ll
index 762def23707d..99900a6d99ff 100644
--- a/llvm/test/CodeGen/EraVM/or.ll
+++ b/llvm/test/CodeGen/EraVM/or.ll
@@ -21,7 +21,7 @@ define i256 @orirr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: orcrr
 define i256 @orcrr(i256 %rs1) nounwind {
-; CHECK: or @val[0], r1, r1
+; CHECK: or code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = or i256 %rs1, %val
   ret i256 %res
@@ -57,7 +57,7 @@ define void @orirs(i256 %rs1) nounwind {
 ; CHECK-LABEL: orcrs
 define void @orcrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: or @val[0], r1, stack-[1]
+; CHECK: or code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = or i256 %rs1, %val
   store i256 %res, i256* %valptr
diff --git a/llvm/test/CodeGen/EraVM/overflow.ll b/llvm/test/CodeGen/EraVM/overflow.ll
index 9bac002af7e1..dfdd0e32a288 100644
--- a/llvm/test/CodeGen/EraVM/overflow.ll
+++ b/llvm/test/CodeGen/EraVM/overflow.ll
@@ -71,7 +71,7 @@ entry:
 define i256 @add_test_large_imm(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_large_imm:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    add! @CPI3_0[0], r3, r0
+; CHECK-NEXT:    add! code[@CPI3_0], r3, r0
 ; CHECK-NEXT:    add.lt r1, r0, r2
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    ret
@@ -86,7 +86,7 @@ define i256 @add_test_crr(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_crr:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r2
+; CHECK-NEXT:    add code[@val], r0, r2
 ; CHECK-NEXT:    add.lt r1, r0, r2
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    ret
@@ -103,7 +103,7 @@ define i256 @add_test_crr_zero_cp(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
 ; CHECK-NEXT:    add r0, r0, r1
-; CHECK-NEXT:    add.lt @CPI5_0[0], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI5_0], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   %res1 = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %x, i256 %y)
@@ -117,7 +117,7 @@ define i256 @add_test_crr_cp(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
 ; CHECK-NEXT:    add r0, r0, r1
-; CHECK-NEXT:    add.lt @CPI6_0[0], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI6_0], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   %res1 = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %x, i256 %y)
@@ -176,7 +176,7 @@ define i256 @add_test_cir(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
 ; CHECK-NEXT:    add 42, r0, r1
-; CHECK-NEXT:    add.lt @val[0], r0, r1
+; CHECK-NEXT:    add.lt code[@val], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   %res1 = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %x, i256 %y)
@@ -191,7 +191,7 @@ define i256 @add_test_cir_cp(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
 ; CHECK-NEXT:    add 42, r0, r1
-; CHECK-NEXT:    add.lt @CPI11_0[0], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI11_0], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   %res1 = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %x, i256 %y)
@@ -221,7 +221,7 @@ define i256 @add_test_rcr(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_rcr:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r2
+; CHECK-NEXT:    add code[@val], r0, r2
 ; CHECK-NEXT:    add.lt r1, r0, r2
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    ret
@@ -237,7 +237,7 @@ define i256 @add_test_rcr_zero_cp(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_rcr_zero_cp:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @CPI14_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI14_0], r0, r1
 ; CHECK-NEXT:    add.lt r0, r0, r1
 ; CHECK-NEXT:    ret
 entry:
@@ -251,7 +251,7 @@ define i256 @add_test_rcr_cp(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_rcr_cp:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @CPI15_0[0], r0, r2
+; CHECK-NEXT:    add code[@CPI15_0], r0, r2
 ; CHECK-NEXT:    add.lt r1, r0, r2
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    ret
@@ -266,7 +266,7 @@ define i256 @add_test_icr(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_icr:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
 ; CHECK-NEXT:    add.lt 42, r0, r1
 ; CHECK-NEXT:    ret
 entry:
@@ -281,7 +281,7 @@ define i256 @add_test_icr_cp(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_icr_cp:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @CPI17_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI17_0], r0, r1
 ; CHECK-NEXT:    add.lt 42, r0, r1
 ; CHECK-NEXT:    ret
 entry:
@@ -295,8 +295,8 @@ define i256 @add_test_ccr_cl_cl(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_ccr_cl_cl:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
-; CHECK-NEXT:    add.lt @val2[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
+; CHECK-NEXT:    add.lt code[@val2], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   %res1 = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %x, i256 %y)
@@ -311,8 +311,8 @@ define i256 @add_test_ccr_cl_cp(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_ccr_cl_cp:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @CPI19_0[0], r0, r1
-; CHECK-NEXT:    add.lt @val[0], r0, r1
+; CHECK-NEXT:    add code[@CPI19_0], r0, r1
+; CHECK-NEXT:    add.lt code[@val], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   %res1 = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %x, i256 %y)
@@ -326,8 +326,8 @@ define i256 @add_test_ccr_cp_cl(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_ccr_cp_cl:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
-; CHECK-NEXT:    add.lt @CPI20_0[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI20_0], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   %res1 = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %x, i256 %y)
@@ -341,8 +341,8 @@ define i256 @add_test_ccr_cp_cp(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: add_test_ccr_cp_cp:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @CPI21_1[0], r0, r1
-; CHECK-NEXT:    add.lt @CPI21_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI21_1], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI21_0], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   %res1 = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %x, i256 %y)
@@ -356,7 +356,7 @@ define i256 @add_test_scr(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
 ; CHECK-NEXT:    add.lt stack-[1], r0, r1
 ; CHECK-NEXT:    ret
 entry:
@@ -374,7 +374,7 @@ define i256 @add_test_scr_cp(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @CPI23_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI23_0], r0, r1
 ; CHECK-NEXT:    add.lt stack-[1], r0, r1
 ; CHECK-NEXT:    ret
 entry:
@@ -427,7 +427,7 @@ define i256 @add_test_csr(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    add! r3, r4, r0
 ; CHECK-NEXT:    add stack-[1], r0, r1
-; CHECK-NEXT:    add.lt @val[0], r0, r1
+; CHECK-NEXT:    add.lt code[@val], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   %data = alloca i256
@@ -445,7 +445,7 @@ define i256 @add_test_csr_cp(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    add! r3, r4, r0
 ; CHECK-NEXT:    add stack-[1], r0, r1
-; CHECK-NEXT:    add.lt @CPI27_0[0], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI27_0], r0, r1
 ; CHECK-NEXT:    ret
 entry:
   %data = alloca i256
@@ -517,7 +517,7 @@ define i256 @add_test_crs(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add.lt @val[0], r0, r1
+; CHECK-NEXT:    add.lt code[@val], r0, r1
 ; CHECK-NEXT:    add r1, r0, stack-[1]
 ; CHECK-NEXT:    ret
 entry:
@@ -593,7 +593,7 @@ define i256 @add_test_cis(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    add! r3, r4, r0
 ; CHECK-NEXT:    add 42, r0, r1
-; CHECK-NEXT:    add.lt @val[0], r0, r1
+; CHECK-NEXT:    add.lt code[@val], r0, r1
 ; CHECK-NEXT:    add r1, r0, stack-[1]
 ; CHECK-NEXT:    ret
 entry:
@@ -631,7 +631,7 @@ define i256 @add_test_rcs(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r2
+; CHECK-NEXT:    add code[@val], r0, r2
 ; CHECK-NEXT:    add.lt r1, r0, r2
 ; CHECK-NEXT:    add r2, r0, stack-[1]
 ; CHECK-NEXT:    add r2, r0, r1
@@ -651,7 +651,7 @@ define i256 @add_test_ics(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
 ; CHECK-NEXT:    add.lt 42, r0, r1
 ; CHECK-NEXT:    add r1, r0, stack-[1]
 ; CHECK-NEXT:    ret
@@ -670,8 +670,8 @@ define i256 @add_test_ccs(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
-; CHECK-NEXT:    add.lt @val2[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
+; CHECK-NEXT:    add.lt code[@val2], r0, r1
 ; CHECK-NEXT:    add r1, r0, stack-[1]
 ; CHECK-NEXT:    ret
 entry:
@@ -690,7 +690,7 @@ define i256 @add_test_scs(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[2 + r0]
 ; CHECK-NEXT:    add! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
 ; CHECK-NEXT:    add.lt stack-[1], r0, r1
 ; CHECK-NEXT:    add r1, r0, stack-[2]
 ; CHECK-NEXT:    ret
@@ -753,7 +753,7 @@ define i256 @add_test_css(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-NEXT:    nop stack+=[2 + r0]
 ; CHECK-NEXT:    add! r3, r4, r0
 ; CHECK-NEXT:    add stack-[1], r0, r1
-; CHECK-NEXT:    add.lt @val[0], r0, r1
+; CHECK-NEXT:    add.lt code[@val], r0, r1
 ; CHECK-NEXT:    add r1, r0, stack-[2]
 ; CHECK-NEXT:    ret
 entry:
@@ -806,7 +806,7 @@ entry:
 define i256 @sub_test_large_imm(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: sub_test_large_imm:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.s! @CPI46_0[0], r3, r0
+; CHECK-NEXT:    sub.s! code[@CPI46_0], r3, r0
 ; CHECK-NEXT:    add.ge r2, r0, r1
 ; CHECK-NEXT:    ret
 entry:
@@ -819,7 +819,7 @@ entry:
 define i256 @sub_test_large_immx(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: sub_test_large_immx:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub! @CPI47_0[0], r1, r0
+; CHECK-NEXT:    sub! code[@CPI47_0], r1, r0
 ; CHECK-NEXT:    add.ge r2, r0, r1
 ; CHECK-NEXT:    ret
 entry:
@@ -846,7 +846,7 @@ entry:
 define i256 @mul_test_large_imm(i256 %a, i256 %b, i256 %x, i256 %y) {
 ; CHECK-LABEL: mul_test_large_imm:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    mul! @CPI49_0[0], r3, r0, r0
+; CHECK-NEXT:    mul! code[@CPI49_0], r3, r0, r0
 ; CHECK-NEXT:    add.lt r1, r0, r2
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    ret
diff --git a/llvm/test/CodeGen/EraVM/ptradd.ll b/llvm/test/CodeGen/EraVM/ptradd.ll
index 09e1202a341c..f112534e4d17 100644
--- a/llvm/test/CodeGen/EraVM/ptradd.ll
+++ b/llvm/test/CodeGen/EraVM/ptradd.ll
@@ -31,7 +31,7 @@ define i8 addrspace(3)* @ptraddrsr(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptraddrcr
 define i8 addrspace(3)* @ptraddrcr(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: ptr.add.s @val[0], r1, r1
+; CHECK: ptr.add.s code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res1 = getelementptr i8, i8 addrspace(3)* %rs1, i256 %val
   ret i8 addrspace(3)* %res1
@@ -67,7 +67,7 @@ define i8 addrspace(3)* @ptraddgsr(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptraddgcr
 define i8 addrspace(3)* @ptraddgcr(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: add @val[0], r0, r1
+; CHECK: add code[@val], r0, r1
 ; CHECK: ptr.add stack[@ptr], r1, r1
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** @ptr
   %val = load i256, i256 addrspace(4)* @val
@@ -108,7 +108,7 @@ define i8 addrspace(3)* @ptraddssr(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptraddscr
 define i8 addrspace(3)* @ptraddscr(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: add @val[0], r0, r1
+; CHECK: add code[@val], r0, r1
 ; CHECK: ptr.add stack-[1], r1, r1
   %ptrptr = alloca i8 addrspace(3)*
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** %ptrptr
@@ -149,7 +149,7 @@ define void @ptraddrss(i8 addrspace(3)* %rs1) nounwind {
 ; CHECK-LABEL: ptraddrcs
 define void @ptraddrcs(i8 addrspace(3)* %rs1) nounwind {
   %result = alloca i8 addrspace(3)*
-; CHECK: ptr.add.s @val[0], r1, stack-[1]
+; CHECK: ptr.add.s code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res1 = getelementptr i8, i8 addrspace(3)* %rs1, i256 %val
   store i8 addrspace(3)* %res1, i8 addrspace(3)** %result
@@ -193,7 +193,7 @@ define void @ptraddgss(i8 addrspace(3)* %rs1) nounwind {
 ; CHECK-LABEL: ptraddgcs
 define void @ptraddgcs(i8 addrspace(3)* %rs1) nounwind {
   %result = alloca i8 addrspace(3)*
-  ; CHECK: add @val[0], r0, r1
+  ; CHECK: add code[@val], r0, r1
   ; CHECK: ptr.add stack[@ptr], r1, stack-[1]
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** @ptr
   %val = load i256, i256 addrspace(4)* @val
@@ -242,7 +242,7 @@ define void @ptraddsss(i8 addrspace(3)* %rs1) nounwind {
 ; CHECK-LABEL: ptraddscs
 define void @ptraddscs(i8 addrspace(3)* %rs1) nounwind {
   %result = alloca i8 addrspace(3)*
-  ; CHECK: add @val[0], r0, r1
+  ; CHECK: add code[@val], r0, r1
   ; CHECK: ptr.add stack-[1], r1, stack-[2]
   %ptrptr = alloca i8 addrspace(3)*
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** %ptrptr
@@ -285,7 +285,7 @@ define void @ptraddgsg(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptraddgcg
 define void @ptraddgcg(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: add @val[0], r0, r1
+; CHECK: add code[@val], r0, r1
 ; CHECK: ptr.add stack[@ptr], r1, stack[@ptr]
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** @ptr
   %val = load i256, i256 addrspace(4)* @val
@@ -330,7 +330,7 @@ define void @ptraddssg(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptraddscg
 define void @ptraddscg(i8 addrspace(3)* %rs1) nounwind {
-  ; CHECK: add @val[0], r0, r1
+  ; CHECK: add code[@val], r0, r1
   ; CHECK: ptr.add stack-[1], r1, stack[@ptr]
   %ptrptr = alloca i8 addrspace(3)*
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** %ptrptr
diff --git a/llvm/test/CodeGen/EraVM/ptrpack.ll b/llvm/test/CodeGen/EraVM/ptrpack.ll
index af1e3d187fc0..a298735356b0 100644
--- a/llvm/test/CodeGen/EraVM/ptrpack.ll
+++ b/llvm/test/CodeGen/EraVM/ptrpack.ll
@@ -31,7 +31,7 @@ define i8 addrspace(3)* @ptrpackrsr(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptrpackrcr
 define i8 addrspace(3)* @ptrpackrcr(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: ptr.pack.s @val[0], r1, r1
+; CHECK: ptr.pack.s code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res1 = call i8 addrspace(3)* @llvm.eravm.ptr.pack(i8 addrspace(3)* %rs1, i256 %val)
   ret i8 addrspace(3)* %res1
@@ -65,7 +65,7 @@ define i8 addrspace(3)* @ptrpackgsr(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptrpackgcr
 define i8 addrspace(3)* @ptrpackgcr(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: add @val[0], r0, r1
+; CHECK: add code[@val], r0, r1
 ; CHECK: ptr.pack stack[@ptr], r1, r1
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** @ptr
   %val = load i256, i256 addrspace(4)* @val
@@ -106,7 +106,7 @@ define i8 addrspace(3)* @ptrpackssr(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptrpackscr
 define i8 addrspace(3)* @ptrpackscr(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: add     @val[0], r0, r1
+; CHECK: add     code[@val], r0, r1
 ; CHECK: ptr.pack        stack-[1], r1, r1
   %ptrptr = alloca i8 addrspace(3)*
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** %ptrptr
@@ -147,7 +147,7 @@ define void @ptrpackrss(i8 addrspace(3)* %rs1) nounwind {
 ; CHECK-LABEL: ptrpackrcs
 define void @ptrpackrcs(i8 addrspace(3)* %rs1) nounwind {
   %result = alloca i8 addrspace(3)*
-; CHECK: ptr.pack.s @val[0], r1, stack-[1]
+; CHECK: ptr.pack.s code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res1 = call i8 addrspace(3)* @llvm.eravm.ptr.pack(i8 addrspace(3)* %rs1, i256 %val)
   store i8 addrspace(3)* %res1, i8 addrspace(3)** %result
@@ -191,7 +191,7 @@ define void @ptrpackgss(i8 addrspace(3)* %rs1) nounwind {
 ; CHECK-LABEL: ptrpackgcs
 define void @ptrpackgcs(i8 addrspace(3)* %rs1) nounwind {
   %result = alloca i8 addrspace(3)*
-  ; CHECK: add @val[0], r0, r1
+  ; CHECK: add code[@val], r0, r1
   ; CHECK: ptr.pack stack[@ptr], r1, stack-[1]
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** @ptr
   %val = load i256, i256 addrspace(4)* @val
@@ -240,7 +240,7 @@ define void @ptrpacksss(i8 addrspace(3)* %rs1) nounwind {
 ; CHECK-LABEL: ptrpackscs
 define void @ptrpackscs(i8 addrspace(3)* %rs1) nounwind {
   %result = alloca i8 addrspace(3)*
-  ; CHECK: add @val[0], r0, r1
+  ; CHECK: add code[@val], r0, r1
   ; CHECK: ptr.pack stack-[1], r1, stack-[2]
   %ptrptr = alloca i8 addrspace(3)*
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** %ptrptr
@@ -283,7 +283,7 @@ define void @ptrpackgsg(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptrpackgcg
 define void @ptrpackgcg(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: add @val[0], r0, r1
+; CHECK: add code[@val], r0, r1
 ; CHECK: ptr.pack stack[@ptr], r1, stack[@ptr]
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** @ptr
   %val = load i256, i256 addrspace(4)* @val
@@ -328,7 +328,7 @@ define void @ptrpackssg(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptrpackscg
 define void @ptrpackscg(i8 addrspace(3)* %rs1) nounwind {
-  ; CHECK: add @val[0], r0, r1
+  ; CHECK: add code[@val], r0, r1
   ; CHECK: ptr.pack stack-[1], r1, stack[@ptr]
   %ptrptr = alloca i8 addrspace(3)*
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** %ptrptr
diff --git a/llvm/test/CodeGen/EraVM/ptrshrink.ll b/llvm/test/CodeGen/EraVM/ptrshrink.ll
index 8db669f1616c..8b164957cd64 100644
--- a/llvm/test/CodeGen/EraVM/ptrshrink.ll
+++ b/llvm/test/CodeGen/EraVM/ptrshrink.ll
@@ -31,7 +31,7 @@ define i8 addrspace(3)* @ptrshrinkrsr(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptrshrinkrcr
 define i8 addrspace(3)* @ptrshrinkrcr(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: ptr.shrink.s @val[0], r1, r1
+; CHECK: ptr.shrink.s code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res1 = call i8 addrspace(3)* @llvm.eravm.ptr.shrink(i8 addrspace(3)* %rs1, i256 %val)
   ret i8 addrspace(3)* %res1
@@ -67,7 +67,7 @@ define i8 addrspace(3)* @ptrshrinkgsr(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptrshrinkgcr
 define i8 addrspace(3)* @ptrshrinkgcr(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: add     @val[0], r0, r1
+; CHECK: add     code[@val], r0, r1
 ; CHECK: ptr.shrink      stack[@ptr], r1, r1
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** @ptr
   %val = load i256, i256 addrspace(4)* @val
@@ -108,7 +108,7 @@ define i8 addrspace(3)* @ptrshrinkssr(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptrshrinkscr
 define i8 addrspace(3)* @ptrshrinkscr(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: add     @val[0], r0, r1
+; CHECK: add     code[@val], r0, r1
 ; CHECK: ptr.shrink      stack-[1], r1, r1
   %ptrptr = alloca i8 addrspace(3)*
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** %ptrptr
@@ -149,7 +149,7 @@ define void @ptrshrinkrss(i8 addrspace(3)* %rs1) nounwind {
 ; CHECK-LABEL: ptrshrinkrcs
 define void @ptrshrinkrcs(i8 addrspace(3)* %rs1) nounwind {
   %result = alloca i8 addrspace(3)*
-; CHECK: ptr.shrink.s @val[0], r1, stack-[1]
+; CHECK: ptr.shrink.s code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res1 = call i8 addrspace(3)* @llvm.eravm.ptr.shrink(i8 addrspace(3)* %rs1, i256 %val)
   store i8 addrspace(3)* %res1, i8 addrspace(3)** %result
@@ -193,7 +193,7 @@ define void @ptrshrinkgss(i8 addrspace(3)* %rs1) nounwind {
 ; CHECK-LABEL: ptrshrinkgcs
 define void @ptrshrinkgcs(i8 addrspace(3)* %rs1) nounwind {
   %result = alloca i8 addrspace(3)*
-  ; CHECK: add @val[0], r0, r1
+  ; CHECK: add code[@val], r0, r1
   ; CHECK: ptr.shrink stack[@ptr], r1, stack-[1]
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** @ptr
   %val = load i256, i256 addrspace(4)* @val
@@ -242,7 +242,7 @@ define void @ptrshrinksss(i8 addrspace(3)* %rs1) nounwind {
 ; CHECK-LABEL: ptrshrinkscs
 define void @ptrshrinkscs(i8 addrspace(3)* %rs1) nounwind {
   %result = alloca i8 addrspace(3)*
-  ; CHECK: add @val[0], r0, r1
+  ; CHECK: add code[@val], r0, r1
   ; CHECK: ptr.shrink stack-[1], r1, stack-[2]
   %ptrptr = alloca i8 addrspace(3)*
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** %ptrptr
@@ -285,7 +285,7 @@ define void @ptrshrinkgsg(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptrshrinkgcg
 define void @ptrshrinkgcg(i8 addrspace(3)* %rs1) nounwind {
-; CHECK: add @val[0], r0, r1
+; CHECK: add code[@val], r0, r1
 ; CHECK: ptr.shrink stack[@ptr], r1, stack[@ptr]
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** @ptr
   %val = load i256, i256 addrspace(4)* @val
@@ -330,7 +330,7 @@ define void @ptrshrinkssg(i8 addrspace(3)* %rs1) nounwind {
 
 ; CHECK-LABEL: ptrshrinkscg
 define void @ptrshrinkscg(i8 addrspace(3)* %rs1) nounwind {
-  ; CHECK: add @val[0], r0, r1
+  ; CHECK: add code[@val], r0, r1
   ; CHECK: ptr.shrink stack-[1], r1, stack[@ptr]
   %ptrptr = alloca i8 addrspace(3)*
   %ptr = load i8 addrspace(3)*, i8 addrspace(3)** %ptrptr
diff --git a/llvm/test/CodeGen/EraVM/ra_regress.ll b/llvm/test/CodeGen/EraVM/ra_regress.ll
index cc37486730d8..c62b6eed38ec 100644
--- a/llvm/test/CodeGen/EraVM/ra_regress.ll
+++ b/llvm/test/CodeGen/EraVM/ra_regress.ll
@@ -8,14 +8,14 @@ define i256 @test_length(i256 %arg1) {
 entry:
 ; CHECK:      sub.s!  36, r{{[0-9]+}}, r{{[[0-9]+}}
 ; CHECK-NEXT: add     r0, r{{[0-9]+}}, r{{[[0-9]+}}
-; CHECK-NEXT: add.lt  @CPI0_0[0], r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK-NEXT: add.lt  code[@CPI0_0], r{{[0-9]+}}, r{{[0-9]+}}
   %comparison_result24 = icmp slt i256 35, %arg1
   %comparison_result_extended25 = zext i1 %comparison_result24 to i256
 
-; CHECK:      and     @CPI0_0[0], r{{[0-9]+}}, r{{[[0-9]+}}
+; CHECK:      and     code[@CPI0_0], r{{[0-9]+}}, r{{[[0-9]+}}
 ; CHECK-NEXT: sub!    r{{[0-9]+}}, r0, r{{[[0-9]+}}
 ; CHECK-NEXT: add     r0, r0, r{{[[0-9]+}}
-; CHECK-NEXT: add.gt  @CPI0_0[0], r{{[0-9]+}}, r{{[[0-9]+}}
+; CHECK-NEXT: add.gt  code[@CPI0_0], r{{[0-9]+}}, r{{[[0-9]+}}
   %comparison_result26 = icmp eq i256 %comparison_result_extended25, 0
   %comparison_result_extended27 = zext i1 %comparison_result26 to i256
 
diff --git a/llvm/test/CodeGen/EraVM/rol.ll b/llvm/test/CodeGen/EraVM/rol.ll
index 21e9e9e4ba2e..ab1ff09b03fd 100644
--- a/llvm/test/CodeGen/EraVM/rol.ll
+++ b/llvm/test/CodeGen/EraVM/rol.ll
@@ -47,7 +47,7 @@ entry:
 define i256 @rolcrr(i256 %rs1) {
 ; CHECK-LABEL: rolcrr:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    rol @val[0], r1, r1
+; CHECK-NEXT:    rol code[@val], r1, r1
 ; CHECK-NEXT:    ret
 entry:
   %val = load i256, i256 addrspace(4)* @val
@@ -61,7 +61,7 @@ entry:
 define i256 @rolcrr_cp(i256 %rs1) {
 ; CHECK-LABEL: rolcrr_cp:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    rol @CPI4_0[0], r1, r1
+; CHECK-NEXT:    rol code[@CPI4_0], r1, r1
 ; CHECK-NEXT:    ret
 entry:
   %sub = sub i256 256, %rs1
@@ -74,7 +74,7 @@ entry:
 define i256 @rolyrr(i256 %rs1) {
 ; CHECK-LABEL: rolyrr:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    rol.s @val[0], r1, r1
+; CHECK-NEXT:    rol.s code[@val], r1, r1
 ; CHECK-NEXT:    ret
 entry:
   %val = load i256, i256 addrspace(4)* @val
@@ -168,7 +168,7 @@ define void @rolcrs(i256 %rs1) {
 ; CHECK-LABEL: rolcrs:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
-; CHECK-NEXT:    rol @val[0], r1, stack-[1]
+; CHECK-NEXT:    rol code[@val], r1, stack-[1]
 ; CHECK-NEXT:    ret
 entry:
   %destptr = alloca i256
@@ -185,7 +185,7 @@ define void @rolcrs_cp(i256 %rs1) {
 ; CHECK-LABEL: rolcrs_cp:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
-; CHECK-NEXT:    rol @CPI12_0[0], r1, stack-[1]
+; CHECK-NEXT:    rol code[@CPI12_0], r1, stack-[1]
 ; CHECK-NEXT:    ret
 entry:
   %destptr = alloca i256
@@ -201,7 +201,7 @@ define void @rolyrs(i256 %rs1) {
 ; CHECK-LABEL: rolyrs:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
-; CHECK-NEXT:    rol.s @val[0], r1, stack-[1]
+; CHECK-NEXT:    rol.s code[@val], r1, stack-[1]
 ; CHECK-NEXT:    ret
 entry:
   %destptr = alloca i256
diff --git a/llvm/test/CodeGen/EraVM/ror.ll b/llvm/test/CodeGen/EraVM/ror.ll
index 0e5851a04658..9e6d021c3b10 100644
--- a/llvm/test/CodeGen/EraVM/ror.ll
+++ b/llvm/test/CodeGen/EraVM/ror.ll
@@ -45,7 +45,7 @@ entry:
 define i256 @rorcrr(i256 %rs1) {
 ; CHECK-LABEL: rorcrr:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    ror @val[0], r1, r1
+; CHECK-NEXT:    ror code[@val], r1, r1
 ; CHECK-NEXT:    ret
 entry:
   %val = load i256, i256 addrspace(4)* @val
@@ -59,7 +59,7 @@ entry:
 define i256 @rorcrr_cp(i256 %rs1) {
 ; CHECK-LABEL: rorcrr_cp:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    ror @CPI4_0[0], r1, r1
+; CHECK-NEXT:    ror code[@CPI4_0], r1, r1
 ; CHECK-NEXT:    ret
 entry:
   %sub = sub i256 256, %rs1
@@ -72,7 +72,7 @@ entry:
 define i256 @roryrr(i256 %rs1) {
 ; CHECK-LABEL: roryrr:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    ror.s @val[0], r1, r1
+; CHECK-NEXT:    ror.s code[@val], r1, r1
 ; CHECK-NEXT:    ret
 entry:
   %val = load i256, i256 addrspace(4)* @val
@@ -164,7 +164,7 @@ define void @rorcrs(i256 %rs1) {
 ; CHECK-LABEL: rorcrs:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
-; CHECK-NEXT:    ror @val[0], r1, stack-[1]
+; CHECK-NEXT:    ror code[@val], r1, stack-[1]
 ; CHECK-NEXT:    ret
 entry:
   %destptr = alloca i256
@@ -181,7 +181,7 @@ define void @rorcrs_cp(i256 %rs1) {
 ; CHECK-LABEL: rorcrs_cp:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
-; CHECK-NEXT:    ror @CPI12_0[0], r1, stack-[1]
+; CHECK-NEXT:    ror code[@CPI12_0], r1, stack-[1]
 ; CHECK-NEXT:    ret
 entry:
   %destptr = alloca i256
@@ -197,7 +197,7 @@ define void @roryrs(i256 %rs1) {
 ; CHECK-LABEL: roryrs:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    nop stack+=[1 + r0]
-; CHECK-NEXT:    ror.s @val[0], r1, stack-[1]
+; CHECK-NEXT:    ror.s code[@val], r1, stack-[1]
 ; CHECK-NEXT:    ret
 entry:
   %destptr = alloca i256
diff --git a/llvm/test/CodeGen/EraVM/sdiv.ll b/llvm/test/CodeGen/EraVM/sdiv.ll
index f6248da4d35d..137c1b554d74 100644
--- a/llvm/test/CodeGen/EraVM/sdiv.ll
+++ b/llvm/test/CodeGen/EraVM/sdiv.ll
@@ -8,12 +8,12 @@ target triple = "eravm"
 define i256 @srem(i256 %rs1, i256 %rs2) nounwind {
 ; CHECK-LABEL: srem:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    div.s! @CPI0_0[0], r2, r0, r2
-; CHECK-NEXT:    sub.ne @CPI0_0[0], r2, r2
-; CHECK-NEXT:    div.s! @CPI0_0[0], r1, r0, r3
-; CHECK-NEXT:    sub.ne @CPI0_0[0], r3, r3
+; CHECK-NEXT:    div.s! code[@CPI0_0], r2, r0, r2
+; CHECK-NEXT:    sub.ne code[@CPI0_0], r2, r2
+; CHECK-NEXT:    div.s! code[@CPI0_0], r1, r0, r3
+; CHECK-NEXT:    sub.ne code[@CPI0_0], r3, r3
 ; CHECK-NEXT:    div r3, r2, r0, r2
-; CHECK-NEXT:    and! @CPI0_0[0], r1, r0
+; CHECK-NEXT:    and! code[@CPI0_0], r1, r0
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    sub.ne 0, r1, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
@@ -28,11 +28,11 @@ define i256 @srem(i256 %rs1, i256 %rs2) nounwind {
 define i256 @sdiv(i256 %rs1, i256 %rs2) nounwind {
 ; CHECK-LABEL: sdiv:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    div.s! @CPI1_0[0], r2, r2, r3
-; CHECK-NEXT:    sub.ne @CPI1_0[0], r3, r3
-; CHECK-NEXT:    div.s! @CPI1_0[0], r1, r1, r4
+; CHECK-NEXT:    div.s! code[@CPI1_0], r2, r2, r3
+; CHECK-NEXT:    sub.ne code[@CPI1_0], r3, r3
+; CHECK-NEXT:    div.s! code[@CPI1_0], r1, r1, r4
 ; CHECK-NEXT:    xor r1, r2, r2
-; CHECK-NEXT:    sub.ne @CPI1_0[0], r4, r4
+; CHECK-NEXT:    sub.ne code[@CPI1_0], r4, r4
 ; CHECK-NEXT:    div r4, r3, r1, r0
 ; CHECK-NEXT:    shl.s! 255, r2, r2
 ; CHECK-NEXT:    sub r2, r1, r3
@@ -49,17 +49,17 @@ define i256 @sdiv(i256 %rs1, i256 %rs2) nounwind {
 define i256 @sdivrem(i256 %rs1, i256 %rs2) nounwind {
 ; CHECK-LABEL: sdivrem:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    div.s! @CPI2_0[0], r2, r2, r3
-; CHECK-NEXT:    sub.ne @CPI2_0[0], r3, r3
-; CHECK-NEXT:    div.s! @CPI2_0[0], r1, r4, r5
+; CHECK-NEXT:    div.s! code[@CPI2_0], r2, r2, r3
+; CHECK-NEXT:    sub.ne code[@CPI2_0], r3, r3
+; CHECK-NEXT:    div.s! code[@CPI2_0], r1, r4, r5
 ; CHECK-NEXT:    xor r4, r2, r2
-; CHECK-NEXT:    sub.ne @CPI2_0[0], r5, r5
+; CHECK-NEXT:    sub.ne code[@CPI2_0], r5, r5
 ; CHECK-NEXT:    div r5, r3, r4, r3
 ; CHECK-NEXT:    shl.s! 255, r2, r2
 ; CHECK-NEXT:    sub r2, r4, r5
 ; CHECK-NEXT:    or r5, r2, r2
 ; CHECK-NEXT:    add.eq r4, r0, r2
-; CHECK-NEXT:    and! @CPI2_0[0], r1, r0
+; CHECK-NEXT:    and! code[@CPI2_0], r1, r0
 ; CHECK-NEXT:    add r3, r0, r1
 ; CHECK-NEXT:    sub.ne 0, r1, r1
 ; CHECK-NEXT:    sub! r3, r0, r0
diff --git a/llvm/test/CodeGen/EraVM/select-zero.ll b/llvm/test/CodeGen/EraVM/select-zero.ll
index 22cb4b3532f9..74a26e4e0e52 100644
--- a/llvm/test/CodeGen/EraVM/select-zero.ll
+++ b/llvm/test/CodeGen/EraVM/select-zero.ll
@@ -258,7 +258,7 @@ define i256 @select_zero_add_code(i256 %0, i256 %1) {
 ; CHECK-LABEL: select_zero_add_code:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    sub! r1, r2, r0
-; CHECK-NEXT:    add.eq @val[0], r2, r2
+; CHECK-NEXT:    add.eq code[@val], r2, r2
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    ret
 entry:
diff --git a/llvm/test/CodeGen/EraVM/select_fold.ll b/llvm/test/CodeGen/EraVM/select_fold.ll
index 26080a6ca967..961983219e08 100644
--- a/llvm/test/CodeGen/EraVM/select_fold.ll
+++ b/llvm/test/CodeGen/EraVM/select_fold.ll
@@ -18,7 +18,7 @@ define i256 @test_add_code(i256 %0, i256 %1) {
 ; CHECK-NEXT:  .BB0_2: ; %for_body
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    and! 1, r1, r0
-; CHECK-NEXT:    sub.s.ne @CPI0_0[0], r1, r1
+; CHECK-NEXT:    sub.s.ne code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    shr.s 1, r1, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    jump.eq @.BB0_2
@@ -264,7 +264,7 @@ define i256 @test_sub_code(i256 %0, i256 %1) {
 ; CHECK-NEXT:  .BB6_2: ; %for_body
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    and! 1, r1, r0
-; CHECK-NEXT:    sub.s.ne @CPI6_0[0], r1, r1
+; CHECK-NEXT:    sub.s.ne code[@CPI6_0], r1, r1
 ; CHECK-NEXT:    shr.s 1, r1, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    jump.eq @.BB6_2
@@ -305,7 +305,7 @@ define i256 @test_sub_code2(i256 %0, i256 %1) {
 ; CHECK-NEXT:  .BB7_2: ; %for_body
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    and! 1, r1, r0
-; CHECK-NEXT:    sub.ne @CPI7_0[0], r1, r1
+; CHECK-NEXT:    sub.ne code[@CPI7_0], r1, r1
 ; CHECK-NEXT:    shr.s 1, r1, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    jump.eq @.BB7_2
@@ -346,7 +346,7 @@ define i256 @test_sub_mul_code(i256 %0, i256 %1) {
 ; CHECK-NEXT:  .BB8_2: ; %for_body
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    and! 1, r1, r0
-; CHECK-NEXT:    mul.ne @CPI8_0[0], r1, r1, r0
+; CHECK-NEXT:    mul.ne code[@CPI8_0], r1, r1, r0
 ; CHECK-NEXT:    shr.s 1, r1, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    jump.eq @.BB8_2
@@ -551,7 +551,7 @@ define i256 @test_sub_div_code(i256 %0, i256 %1) {
 ; CHECK-NEXT:  .BB13_2: ; %for_body
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    and! 1, r1, r0
-; CHECK-NEXT:    div.ne @CPI13_0[0], r1, r1, r0
+; CHECK-NEXT:    div.ne code[@CPI13_0], r1, r1, r0
 ; CHECK-NEXT:    shr.s 1, r1, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    jump.eq @.BB13_2
@@ -592,7 +592,7 @@ define i256 @test_sub_div_code2(i256 %0, i256 %1) {
 ; CHECK-NEXT:  .BB14_2: ; %for_body
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    and! 1, r1, r0
-; CHECK-NEXT:    div.s.ne @CPI14_0[0], r1, r1, r0
+; CHECK-NEXT:    div.s.ne code[@CPI14_0], r1, r1, r0
 ; CHECK-NEXT:    shr.s 1, r1, r1
 ; CHECK-NEXT:    sub! r2, r0, r0
 ; CHECK-NEXT:    jump.eq @.BB14_2
diff --git a/llvm/test/CodeGen/EraVM/selectcc.ll b/llvm/test/CodeGen/EraVM/selectcc.ll
index 0fbd1f2885b4..5f9e5ed096ad 100644
--- a/llvm/test/CodeGen/EraVM/selectcc.ll
+++ b/llvm/test/CodeGen/EraVM/selectcc.ll
@@ -46,7 +46,7 @@ define i256 @selcrr(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    add r2, r0, r1
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add.gt @val[0], r0, r1
+; CHECK-NEXT:    add.gt code[@val], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ugt i256 %v3, %v4
   %const = load i256, i256 addrspace(4)* @val
@@ -59,7 +59,7 @@ define i256 @selcrr_zero_cp(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
 ; CHECK-NEXT:    add r0, r0, r1
-; CHECK-NEXT:    add.lt @CPI4_0[0], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI4_0], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
   %2 = select i1 %1, i256 123456789, i256 0
@@ -70,7 +70,7 @@ define i256 @selcrr_cp(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selcrr_cp:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add.lt @CPI5_0[0], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI5_0], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
   %2 = select i1 %1, i256 123456789, i256 %v1
@@ -119,7 +119,7 @@ define i256 @selcir(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
 ; CHECK-NEXT:    add 42, r0, r1
-; CHECK-NEXT:    add.gt @val[0], r0, r1
+; CHECK-NEXT:    add.gt code[@val], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ugt i256 %v3, %v4
   %const = load i256, i256 addrspace(4)* @val
@@ -132,7 +132,7 @@ define i256 @selcir_cp(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
 ; CHECK-NEXT:    add 42, r0, r1
-; CHECK-NEXT:    add.gt @CPI10_0[0], r0, r1
+; CHECK-NEXT:    add.gt code[@CPI10_0], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ugt i256 %v3, %v4
   %2 = select i1 %1, i256 123456789, i256 42
@@ -158,7 +158,7 @@ define i256 @selrcr(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selrcr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add.ge @val[0], r0, r1
+; CHECK-NEXT:    add.ge code[@val], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
   %const = load i256, i256 addrspace(4)* @val
@@ -170,7 +170,7 @@ define i256 @selrcr_zero_cp(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selrcr_zero_cp:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @CPI13_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI13_0], r0, r1
 ; CHECK-NEXT:    add.lt r0, r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
@@ -182,7 +182,7 @@ define i256 @selrcr_cp(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selrcr_cp:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add.ge @CPI14_0[0], r0, r1
+; CHECK-NEXT:    add.ge code[@CPI14_0], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
   %2 = select i1 %1, i256 %v1, i256 123456789
@@ -193,7 +193,7 @@ define i256 @selicr(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selicr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
 ; CHECK-NEXT:    add.lt 42, r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
@@ -206,7 +206,7 @@ define i256 @selicr_cp(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selicr_cp:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @CPI16_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI16_0], r0, r1
 ; CHECK-NEXT:    add.lt 42, r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
@@ -218,8 +218,8 @@ define i256 @selccr_cl_cl(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selccr_cl_cl:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
-; CHECK-NEXT:    add.lt @val2[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
+; CHECK-NEXT:    add.lt code[@val2], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
   %const = load i256, i256 addrspace(4)* @val
@@ -232,8 +232,8 @@ define i256 @selccr_cl_cp(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selccr_cl_cp:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @CPI18_0[0], r0, r1
-; CHECK-NEXT:    add.lt @val[0], r0, r1
+; CHECK-NEXT:    add code[@CPI18_0], r0, r1
+; CHECK-NEXT:    add.lt code[@val], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
   %const = load i256, i256 addrspace(4)* @val
@@ -245,8 +245,8 @@ define i256 @selccr_cp_cl(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selccr_cp_cl:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
-; CHECK-NEXT:    add.lt @CPI19_0[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI19_0], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
   %const = load i256, i256 addrspace(4)* @val
@@ -258,8 +258,8 @@ define i256 @selccr_cp_cp(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selccr_cp_cp:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @CPI20_1[0], r0, r1
-; CHECK-NEXT:    add.lt @CPI20_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI20_1], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI20_0], r0, r1
 ; CHECK-NEXT:    ret
   %1 = icmp ult i256 %v3, %v4
   %2 = select i1 %1, i256 12345678, i256 123456789
@@ -271,7 +271,7 @@ define i256 @selscr(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
 ; CHECK-NEXT:    add.lt stack-[1], r0, r1
 ; CHECK-NEXT:    ret
   %ptr = alloca i256
@@ -287,7 +287,7 @@ define i256 @selscr_cp(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @CPI22_0[0], r0, r1
+; CHECK-NEXT:    add code[@CPI22_0], r0, r1
 ; CHECK-NEXT:    add.lt stack-[1], r0, r1
 ; CHECK-NEXT:    ret
   %ptr = alloca i256
@@ -332,7 +332,7 @@ define i256 @selcsr(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    sub! r3, r4, r0
 ; CHECK-NEXT:    add stack-[1], r0, r1
-; CHECK-NEXT:    add.lt @val[0], r0, r1
+; CHECK-NEXT:    add.lt code[@val], r0, r1
 ; CHECK-NEXT:    ret
   %data = alloca i256
   %1 = icmp ult i256 %v3, %v4
@@ -348,7 +348,7 @@ define i256 @selcsr_cp(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    sub! r3, r4, r0
 ; CHECK-NEXT:    add stack-[1], r0, r1
-; CHECK-NEXT:    add.lt @CPI26_0[0], r0, r1
+; CHECK-NEXT:    add.lt code[@CPI26_0], r0, r1
 ; CHECK-NEXT:    ret
   %data = alloca i256
   %1 = icmp ult i256 %v3, %v4
@@ -412,7 +412,7 @@ define void @selcrs(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    sub! r3, r4, r0
 ; CHECK-NEXT:    add r2, r0, stack-[1]
-; CHECK-NEXT:    add.gt @val[0], r0, stack-[1]
+; CHECK-NEXT:    add.gt code[@val], r0, stack-[1]
 ; CHECK-NEXT:    ret
   %resptr = alloca i256
   %1 = icmp ugt i256 %v3, %v4
@@ -479,7 +479,7 @@ define void @selcis(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    sub! r3, r4, r0
 ; CHECK-NEXT:    add 42, r0, stack-[1]
-; CHECK-NEXT:    add.gt @val[0], r0, stack-[1]
+; CHECK-NEXT:    add.gt code[@val], r0, stack-[1]
 ; CHECK-NEXT:    ret
   %resptr = alloca i256
   %1 = icmp ugt i256 %v3, %v4
@@ -513,7 +513,7 @@ define void @selrcs(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, stack-[1]
+; CHECK-NEXT:    add code[@val], r0, stack-[1]
 ; CHECK-NEXT:    add.lt r1, r0, stack-[1]
 ; CHECK-NEXT:    ret
   %resptr = alloca i256
@@ -530,7 +530,7 @@ define void @selics(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    nop stack+=[1 + r0]
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, stack-[1]
+; CHECK-NEXT:    add code[@val], r0, stack-[1]
 ; CHECK-NEXT:    add.lt 42, r0, stack-[1]
 ; CHECK-NEXT:    ret
   %resptr = alloca i256
@@ -546,9 +546,9 @@ define void @selccs(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selccs:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    nop stack+=[1 + r0]
-; CHECK-NEXT:    add @val2[0], r0, r1
+; CHECK-NEXT:    add code[@val2], r0, r1
 ; CHECK-NEXT:    sub! r3, r4, r0
-; CHECK-NEXT:    add @val[0], r0, stack-[1]
+; CHECK-NEXT:    add code[@val], r0, stack-[1]
 ; CHECK-NEXT:    add.lt r1, r0, stack-[1]
 ; CHECK-NEXT:    ret
   %resptr = alloca i256
@@ -565,7 +565,7 @@ define void @selscs(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selscs:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    nop stack+=[2 + r0]
-; CHECK-NEXT:    add @val[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
 ; CHECK-NEXT:    sub! r3, r4, r0
 ; CHECK-NEXT:    add r1, r0, stack-[2]
 ; CHECK-NEXT:    add.lt stack-[1], r0, stack-[2]
@@ -621,7 +621,7 @@ define void @selcss(i256 %v1, i256 %v2, i256 %v3, i256 %v4) {
 ; CHECK-LABEL: selcss:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    nop stack+=[2 + r0]
-; CHECK-NEXT:    add @val[0], r0, r1
+; CHECK-NEXT:    add code[@val], r0, r1
 ; CHECK-NEXT:    sub! r3, r4, r0
 ; CHECK-NEXT:    add stack-[1], r0, stack-[2]
 ; CHECK-NEXT:    add.lt r1, r0, stack-[2]
diff --git a/llvm/test/CodeGen/EraVM/shl.ll b/llvm/test/CodeGen/EraVM/shl.ll
index 6e57db016b3d..1adb72ddbbfe 100644
--- a/llvm/test/CodeGen/EraVM/shl.ll
+++ b/llvm/test/CodeGen/EraVM/shl.ll
@@ -28,7 +28,7 @@ define i256 @shlxrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: shlcrr
 define i256 @shlcrr(i256 %rs1) nounwind {
-; CHECK: shl @val[0], r1, r1
+; CHECK: shl code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = shl i256 %val, %rs1
   ret i256 %res
@@ -36,14 +36,14 @@ define i256 @shlcrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: shlcrr_cp
 define i256 @shlcrr_cp(i256 %rs1) nounwind {
-; CHECK: shl @CPI4_0[0], r1, r1
+; CHECK: shl code[@CPI4_0], r1, r1
   %res = shl i256 123456789, %rs1
   ret i256 %res
 }
 
 ; CHECK-LABEL: shlyrr
 define i256 @shlyrr(i256 %rs1) nounwind {
-; CHECK: shl.s @val[0], r1, r1
+; CHECK: shl.s code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = shl i256 %rs1, %val
   ret i256 %res
@@ -97,7 +97,7 @@ define void @shlxrs(i256 %rs1) nounwind {
 ; CHECK-LABEL: shlcrs
 define void @shlcrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: shl @val[0], r1, stack-[1]
+; CHECK: shl code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = shl i256 %val, %rs1
   store i256 %res, i256* %valptr
@@ -107,7 +107,7 @@ define void @shlcrs(i256 %rs1) nounwind {
 ; CHECK-LABEL: shlcrs_cp
 define void @shlcrs_cp(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: shl @CPI12_0[0], r1, stack-[1]
+; CHECK: shl code[@CPI12_0], r1, stack-[1]
   %res = shl i256 123456789, %rs1
   store i256 %res, i256* %valptr
   ret void
@@ -116,7 +116,7 @@ define void @shlcrs_cp(i256 %rs1) nounwind {
 ; CHECK-LABEL: shlyrs
 define void @shlyrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: shl.s @val[0], r1, stack-[1]
+; CHECK: shl.s code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = shl i256 %rs1, %val
   store i256 %res, i256* %valptr
diff --git a/llvm/test/CodeGen/EraVM/shr.ll b/llvm/test/CodeGen/EraVM/shr.ll
index 0efac0d90d5b..6f16a2eabe89 100644
--- a/llvm/test/CodeGen/EraVM/shr.ll
+++ b/llvm/test/CodeGen/EraVM/shr.ll
@@ -28,7 +28,7 @@ define i256 @shrxrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: shrcrr
 define i256 @shrcrr(i256 %rs1) nounwind {
-; CHECK: shr @val[0], r1, r1
+; CHECK: shr code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = lshr i256 %val, %rs1
   ret i256 %res
@@ -36,14 +36,14 @@ define i256 @shrcrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: shrcrr_cp
 define i256 @shrcrr_cp(i256 %rs1) nounwind {
-; CHECK: shr @CPI4_0[0], r1, r1
+; CHECK: shr code[@CPI4_0], r1, r1
   %res = lshr i256 123456789, %rs1
   ret i256 %res
 }
 
 ; CHECK-LABEL: shryrr
 define i256 @shryrr(i256 %rs1) nounwind {
-; CHECK: shr.s @val[0], r1, r1
+; CHECK: shr.s code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = lshr i256 %rs1, %val
   ret i256 %res
@@ -97,7 +97,7 @@ define void @shrxrs(i256 %rs1) nounwind {
 ; CHECK-LABEL: shrcrs
 define void @shrcrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: shr @val[0], r1, stack-[1]
+; CHECK: shr code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = lshr i256 %val, %rs1
   store i256 %res, i256* %valptr
@@ -107,7 +107,7 @@ define void @shrcrs(i256 %rs1) nounwind {
 ; CHECK-LABEL: shrcrs_cp
 define void @shrcrs_cp(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: shr @CPI12_0[0], r1, stack-[1]
+; CHECK: shr code[@CPI12_0], r1, stack-[1]
   %res = lshr i256 123456789, %rs1
   store i256 %res, i256* %valptr
   ret void
@@ -116,7 +116,7 @@ define void @shrcrs_cp(i256 %rs1) nounwind {
 ; CHECK-LABEL: shryrs
 define void @shryrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: shr.s @val[0], r1, stack-[1]
+; CHECK: shr.s code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = lshr i256 %rs1, %val
   store i256 %res, i256* %valptr
diff --git a/llvm/test/CodeGen/EraVM/sub.ll b/llvm/test/CodeGen/EraVM/sub.ll
index 51efe8d4ab3f..90ecfb112e68 100644
--- a/llvm/test/CodeGen/EraVM/sub.ll
+++ b/llvm/test/CodeGen/EraVM/sub.ll
@@ -35,7 +35,7 @@ define i256 @sub2add(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: subcrr
 define i256 @subcrr(i256 %rs1) nounwind {
-; CHECK: sub @val[0], r1, r1
+; CHECK: sub code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = sub i256 %val, %rs1
   ret i256 %res
@@ -43,14 +43,14 @@ define i256 @subcrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: subcrr_cp
 define i256 @subcrr_cp(i256 %rs1) nounwind {
-; CHECK: sub @CPI5_0[0], r1, r1
+; CHECK: sub code[@CPI5_0], r1, r1
   %res = sub i256 123456789, %rs1
   ret i256 %res
 }
 
 ; CHECK-LABEL: subyrr
 define i256 @subyrr(i256 %rs1) nounwind {
-; CHECK: sub.s @val[0], r1, r1
+; CHECK: sub.s code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = sub i256 %rs1, %val
   ret i256 %res
@@ -104,7 +104,7 @@ define void @subxrs(i256 %rs1) nounwind {
 ; CHECK-LABEL: subcrs
 define void @subcrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: sub @val[0], r1, stack-[1]
+; CHECK: sub code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = sub i256 %val, %rs1
   store i256 %res, i256* %valptr
@@ -114,7 +114,7 @@ define void @subcrs(i256 %rs1) nounwind {
 ; CHECK-LABEL: subcrs_cp
 define void @subcrs_cp(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: sub @CPI13_0[0], r1, stack-[1]
+; CHECK: sub code[@CPI13_0], r1, stack-[1]
   %res = sub i256 123456789, %rs1
   store i256 %res, i256* %valptr
   ret void
@@ -123,7 +123,7 @@ define void @subcrs_cp(i256 %rs1) nounwind {
 ; CHECK-LABEL: subyrs
 define void @subyrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: sub.s @val[0], r1, stack-[1]
+; CHECK: sub.s code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = sub i256 %rs1, %val
   store i256 %res, i256* %valptr
diff --git a/llvm/test/CodeGen/EraVM/udiv.ll b/llvm/test/CodeGen/EraVM/udiv.ll
index 3fe7deee940c..47a12bd9d5a3 100644
--- a/llvm/test/CodeGen/EraVM/udiv.ll
+++ b/llvm/test/CodeGen/EraVM/udiv.ll
@@ -28,7 +28,7 @@ define i256 @uremxrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: uremcrr
 define i256 @uremcrr(i256 %rs1) nounwind {
-; CHECK: div @val[0], r1, r{{[0-9]+}}, r1
+; CHECK: div code[@val], r1, r{{[0-9]+}}, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = urem i256 %val, %rs1
   ret i256 %res
@@ -36,7 +36,7 @@ define i256 @uremcrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: uremyrr
 define i256 @uremyrr(i256 %rs1) nounwind {
-; CHECK: div.s @val[0], r1, r{{[0-9]+}}, r1
+; CHECK: div.s code[@val], r1, r{{[0-9]+}}, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = urem i256 %rs1, %val
   ret i256 %res
@@ -93,7 +93,7 @@ define void @uremxrs(i256 %rs1) nounwind {
 ; CHECK-LABEL: uremcrs
 define void @uremcrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: div @val[0], r1, r{{[0-9]+}}, r[[REG:[0-9]+]]
+; CHECK: div code[@val], r1, r{{[0-9]+}}, r[[REG:[0-9]+]]
 ; CHECK: add r[[REG]], r0, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = urem i256 %val, %rs1
@@ -104,7 +104,7 @@ define void @uremcrs(i256 %rs1) nounwind {
 ; CHECK-LABEL: uremyrs
 define void @uremyrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: div.s @val[0], r1, r{{[0-9]+}}, r[[REG:[0-9]+]]
+; CHECK: div.s code[@val], r1, r{{[0-9]+}}, r[[REG:[0-9]+]]
 ; CHECK: add r[[REG]], r0, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = urem i256 %rs1, %val
@@ -159,7 +159,7 @@ define i256 @udivxrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: udivcrr
 define i256 @udivcrr(i256 %rs1) nounwind {
-; CHECK: div @val[0], r1, r1, r{{[0-9]+}}
+; CHECK: div code[@val], r1, r1, r{{[0-9]+}}
   %val = load i256, i256 addrspace(4)* @val
   %res = udiv i256 %val, %rs1
   ret i256 %res
@@ -167,7 +167,7 @@ define i256 @udivcrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: udivyrr
 define i256 @udivyrr(i256 %rs1) nounwind {
-; CHECK: div.s @val[0], r1, r1, r{{[0-9]+}}
+; CHECK: div.s code[@val], r1, r1, r{{[0-9]+}}
   %val = load i256, i256 addrspace(4)* @val
   %res = udiv i256 %rs1, %val
   ret i256 %res
@@ -221,7 +221,7 @@ define void @udivxrs(i256 %rs1) nounwind {
 ; CHECK-LABEL: udivcrs
 define void @udivcrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: div @val[0], r1, stack-[1], r{{[0-9]+}}
+; CHECK: div code[@val], r1, stack-[1], r{{[0-9]+}}
   %val = load i256, i256 addrspace(4)* @val
   %res = udiv i256 %val, %rs1
   store i256 %res, i256* %valptr
@@ -231,7 +231,7 @@ define void @udivcrs(i256 %rs1) nounwind {
 ; CHECK-LABEL: udivyrs
 define void @udivyrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: div.s @val[0], r1, stack-[1], r{{[0-9]+}}
+; CHECK: div.s code[@val], r1, stack-[1], r{{[0-9]+}}
   %val = load i256, i256 addrspace(4)* @val
   %res = udiv i256 %rs1, %val
   store i256 %res, i256* %valptr
@@ -292,7 +292,7 @@ define i256 @udivremxrrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: udivremcrrr
 define i256 @udivremcrrr(i256 %rs1) nounwind {
-; CHECK: div @val[0], r1, r[[REG1:[0-9]+]], r[[REG2:[0-9]+]]
+; CHECK: div code[@val], r1, r[[REG1:[0-9]+]], r[[REG2:[0-9]+]]
 ; CHECK: add r[[REG2]], r[[REG1]], r1
   %val = load i256, i256 addrspace(4)* @val
   %res1 = urem i256 %val, %rs1
@@ -303,7 +303,7 @@ define i256 @udivremcrrr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: udivremyrrr
 define i256 @udivremyrrr(i256 %rs1) nounwind {
-; CHECK: div.s @val[0], r1, r[[REG1:[0-9]+]], r[[REG2:[0-9]+]]
+; CHECK: div.s code[@val], r1, r[[REG1:[0-9]+]], r[[REG2:[0-9]+]]
 ; CHECK: add r[[REG2]], r[[REG1]], r1
   %val = load i256, i256 addrspace(4)* @val
   %res1 = urem i256 %rs1, %val
@@ -369,7 +369,7 @@ define i256 @udivremxrsr(i256 %rs1) nounwind {
 ; CHECK-LABEL: udivremcrsr
 define i256 @udivremcrsr(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: div @val[0], r1, stack-[1], r1
+; CHECK: div code[@val], r1, stack-[1], r1
   %val = load i256, i256 addrspace(4)* @val
   %res = udiv i256 %val, %rs1
   %rem = urem i256 %val, %rs1
@@ -380,7 +380,7 @@ define i256 @udivremcrsr(i256 %rs1) nounwind {
 ; CHECK-LABEL: udivremyrsr
 define i256 @udivremyrsr(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: div.s @val[0], r1, stack-[1], r1
+; CHECK: div.s code[@val], r1, stack-[1], r1
   %val = load i256, i256 addrspace(4)* @val
   %res = udiv i256 %rs1, %val
   %rem = urem i256 %rs1, %val
diff --git a/llvm/test/CodeGen/EraVM/xor-opt-bug.ll b/llvm/test/CodeGen/EraVM/xor-opt-bug.ll
index 0fef8462c92d..273548ce02e1 100644
--- a/llvm/test/CodeGen/EraVM/xor-opt-bug.ll
+++ b/llvm/test/CodeGen/EraVM/xor-opt-bug.ll
@@ -10,7 +10,7 @@ define i256 @test(i256 %a) {
 ; CHECK-NEXT:    sub! r1, r0, r0
 ; CHECK-NEXT:    add 0, r0, r1
 ; CHECK-NEXT:    add.ne 1, r0, r1
-; CHECK-NEXT:    xor @CPI0_0[0], r1, r1
+; CHECK-NEXT:    xor code[@CPI0_0], r1, r1
 ; CHECK-NEXT:    ret
   %cmp = icmp ne i256 %a, 0
   %zext = zext i1 %cmp to i256
diff --git a/llvm/test/CodeGen/EraVM/xor.ll b/llvm/test/CodeGen/EraVM/xor.ll
index c5c620590621..a7d1f1a68e87 100644
--- a/llvm/test/CodeGen/EraVM/xor.ll
+++ b/llvm/test/CodeGen/EraVM/xor.ll
@@ -21,7 +21,7 @@ define i256 @xorirr(i256 %rs1) nounwind {
 
 ; CHECK-LABEL: xorcrr
 define i256 @xorcrr(i256 %rs1) nounwind {
-; CHECK: xor @val[0], r1, r1
+; CHECK: xor code[@val], r1, r1
   %val = load i256, i256 addrspace(4)* @val
   %res = xor i256 %rs1, %val
   ret i256 %res
@@ -57,7 +57,7 @@ define void @xorirs(i256 %rs1) nounwind {
 ; CHECK-LABEL: xorcrs
 define void @xorcrs(i256 %rs1) nounwind {
   %valptr = alloca i256
-; CHECK: xor @val[0], r1, stack-[1]
+; CHECK: xor code[@val], r1, stack-[1]
   %val = load i256, i256 addrspace(4)* @val
   %res = xor i256 %rs1, %val
   store i256 %res, i256* %valptr
diff --git a/llvm/test/MC/EraVM/asm-parser/arith-operands-errors.s b/llvm/test/MC/EraVM/asm-parser/arith-operands-errors.s
index 7ade56ca6ee9..3e46c4ff5dff 100644
--- a/llvm/test/MC/EraVM/asm-parser/arith-operands-errors.s
+++ b/llvm/test/MC/EraVM/asm-parser/arith-operands-errors.s
@@ -49,9 +49,9 @@
 ; CHECK:       <stdin>:{{[0-9]+}}:20: error: register name expected
 ; CHECK-NEXT:    add    stack[1 + 2], r1, r2
 ; CHECK-NEXT:                     ^
-; CHECK:       <stdin>:{{[0-9]+}}:8: error: two symbols in a single operand
+; CHECK:       <stdin>:{{[0-9]+}}:10: error: unexpected token
 ; CHECK-NEXT:    add  @a[@b + 1], r2, r3
-; CHECK-NEXT:         ^
+; CHECK-NEXT:           ^
 ; CHECK:       <stdin>:{{[0-9]+}}:32: error: global stack symbols only supported with absolute addressing
 ; CHECK-NEXT:    add  stack-[@global + 1 + r1], r2, r3
 ; CHECK-NEXT:                                 ^
diff --git a/llvm/test/MC/EraVM/asm-parser/jumptable.s b/llvm/test/MC/EraVM/asm-parser/jumptable.s
index 36718cf86ecb..b8b056b7fb9d 100644
--- a/llvm/test/MC/EraVM/asm-parser/jumptable.s
+++ b/llvm/test/MC/EraVM/asm-parser/jumptable.s
@@ -6,7 +6,7 @@ test:
   add  r1, r0, r4
   add  r0, r0, r1
   sub.s! 10, r3, r5
-  jump.le @JTI0_0[r3]
+  jump.le code[@JTI0_0 + r3]
   jump @.BB0_7
 .BB0_1:
   add r4, r2, r1
@@ -47,7 +47,7 @@ JTI0_0:
 ; CHECK:  	add	r1, r0, r4
 ; CHECK:  	add	r0, r0, r1
 ; CHECK:  	sub.s!	10, r3, r5
-; CHECK:  	jump.le	@JTI0_0[r3]
+; CHECK:  	jump.le	code[@JTI0_0+r3]
 ; CHECK:  	jump	@.BB0_7
 ; CHECK:  .BB0_1:
 ; CHECK:  	add	r4, r2, r1
diff --git a/llvm/test/MC/EraVM/asm-parser/near-jump.s b/llvm/test/MC/EraVM/asm-parser/near-jump.s
index f421d114029f..24ce2611293b 100644
--- a/llvm/test/MC/EraVM/asm-parser/near-jump.s
+++ b/llvm/test/MC/EraVM/asm-parser/near-jump.s
@@ -26,9 +26,9 @@ foo:
 
 ; do not confuse @jump_target and @indirect_via_const[1]
   jump       @label
-  jump       @jump_table[1]
+  jump       code[@jump_table + 1]
   jump       @label, r2
-  jump       @jump_table[1], r2
+  jump       code[@jump_table +1], r2
 
 ; COM: Autogenerated checks below, see README.md.
 ; CHECK:  .text
@@ -53,6 +53,6 @@ foo:
 ; CHECK:  jump code[r1+1], r2
 
 ; CHECK:  jump @label
-; CHECK:  jump @jump_table[1]
+; CHECK:  jump code[@jump_table+1]
 ; CHECK:  jump @label, r2
-; CHECK:  jump @jump_table[1], r2
+; CHECK:  jump code[@jump_table+1], r2
diff --git a/llvm/test/MC/EraVM/asm-parser/symbolic-operands.s b/llvm/test/MC/EraVM/asm-parser/symbolic-operands.s
index f99e1698ed79..9e6e045d9939 100644
--- a/llvm/test/MC/EraVM/asm-parser/symbolic-operands.s
+++ b/llvm/test/MC/EraVM/asm-parser/symbolic-operands.s
@@ -26,16 +26,17 @@ foo:
   add  code[@global - 1], r2, r3
   add  code[@global], r2, r3
 
-  ; special syntax for code[...]
-  add  @global[1], r1, r2
-  add  @global[-1], r1, r2
+  ; special syntax for add with immediate.
+  ; @global is treated as an offset instructions.
+  add  @global + 1, r1, r2
+  add  @global - 1, r1, r2
 
 
 ; COM: Autogenerated checks below, see README.md.
 ; CHECK:  .text
 ; CHECK:foo:
 
-; CHECK:  add  @global[r1+1], r1, r2
+; CHECK:  add  code[@global+r1+1], r1, r2
 ; CHECK:  add  stack[@global + 1 + r1], r1, r2
 ; CHECK:  add  stack[@global + 1 + r1], r1, r2
 
@@ -48,11 +49,11 @@ foo:
 ; CHECK:  add  stack[@global + 65535], r2, r3
 ; CHECK:  add  stack[@global], r2, r3
 
-; CHECK:  add  @global[r1+65535], r2, r3
-; CHECK:  add  @global[1], r2, r3
-; CHECK:  add  @global[r1], r2, r3
-; CHECK:  add  @global[65535], r2, r3
-; CHECK:  add  @global[0], r2, r3
+; CHECK:  add  code[@global+r1+65535], r2, r3
+; CHECK:  add  code[@global+1], r2, r3
+; CHECK:  add  code[@global+r1], r2, r3
+; CHECK:  add  code[@global+65535], r2, r3
+; CHECK:  add  code[@global], r2, r3
 
-; CHECK:  add  @global[1], r1, r2
-; CHECK:  add  @global[65535], r1, r2
+; CHECK:  add  @global+1, r1, r2
+; CHECK:  add  @global+65535, r1, r2
diff --git a/llvm/test/MC/EraVM/encoding/data.s b/llvm/test/MC/EraVM/encoding/data.s
index 0f67691f40ba..4d8505c720ff 100644
--- a/llvm/test/MC/EraVM/encoding/data.s
+++ b/llvm/test/MC/EraVM/encoding/data.s
@@ -44,7 +44,7 @@ local_var:
 foo:
   add code[@global_const], r2, stack[@global_var + 2]
   add code[@local_const], r2, stack[@local_var + 1]
-  jump @jump_table[1]
+  jump code[@jump_table + 1]
   ret
 
 ; CHECK:      Relocation section '.rela.text' at offset {{0x[0-9a-f]+}} contains 5 entries:
diff --git a/llvm/test/MC/EraVM/encoding/inst-fields.s b/llvm/test/MC/EraVM/encoding/inst-fields.s
index 9df6783dc597..ef18ad321b42 100644
--- a/llvm/test/MC/EraVM/encoding/inst-fields.s
+++ b/llvm/test/MC/EraVM/encoding/inst-fields.s
@@ -110,11 +110,11 @@ foo:
 ; CHECK:  add   r1, r2, stack[17185]              ; encoding: [0x43,0x21,0x00,0x00,0x00,0x21,0x00,0x1f]
 ; CHECK:  add   r1, r2, stack[17185 + r3]         ; encoding: [0x43,0x21,0x00,0x00,0x03,0x21,0x00,0x1f]
 
-; CHECK:  add   @constant[r1], r2, r3             ; encoding: [0x00,0x00,A,A,0x03,0x21,0x00,0x41]
+; CHECK:  add   code[@constant+r1], r2, r3             ; encoding: [0x00,0x00,A,A,0x03,0x21,0x00,0x41]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  add   @constant[17185], r2, r3          ; encoding: [0x00,0x00,0x43'A',0x21'A',0x03,0x20,0x00,0x41]
+; CHECK:  add   code[@constant+17185], r2, r3          ; encoding: [0x00,0x00,0x43'A',0x21'A',0x03,0x20,0x00,0x41]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  add   @constant[r1+17185], r2, r3       ; encoding: [0x00,0x00,0x43'A',0x21'A',0x03,0x21,0x00,0x41]
+; CHECK:  add   code[@constant+r1+17185], r2, r3       ; encoding: [0x00,0x00,0x43'A',0x21'A',0x03,0x21,0x00,0x41]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
 
 ; CHECK:  add   stack[@variable + r1], r2, r3         ; encoding: [0x00,0x00,A,A,0x03,0x21,0x00,0x31]
diff --git a/llvm/test/MC/EraVM/encoding/jump-table.ll b/llvm/test/MC/EraVM/encoding/jump-table.ll
index 3f2529f45a47..1836e5d931e5 100644
--- a/llvm/test/MC/EraVM/encoding/jump-table.ll
+++ b/llvm/test/MC/EraVM/encoding/jump-table.ll
@@ -31,7 +31,7 @@ default:
 ; CHECK:     foo:
 ; Make sure raw values from the jump table are used as-is, so R_ERAVM_16_SCALE_8
 ; is the right relocation to use for jump table entry emission.
-; CHECK:       jump.le @JTI0_0[r1]
+; CHECK:       jump.le code[@JTI0_0+r1]
 
 ; CHECK:       .rodata
 ; CHECK-NEXT:  .p2align 5, 0x0
diff --git a/llvm/test/MC/EraVM/encoding/jumps.s b/llvm/test/MC/EraVM/encoding/jumps.s
index 561d3f540089..e7a809455aaa 100644
--- a/llvm/test/MC/EraVM/encoding/jumps.s
+++ b/llvm/test/MC/EraVM/encoding/jumps.s
@@ -25,9 +25,9 @@ label:
 
 ; do not confuse @jump_target and @indirect_via_const[1]
   jump       @label
-  jump       @jump_table[1]
+  jump       code[@jump_table+1]
   jump       @label, r2
-  jump       @jump_table[1], r2
+  jump       code[@jump_table+1], r2
 
 ; CHECK:  .text
 ; CHECK:foo:
@@ -51,9 +51,9 @@ label:
 
 ; CHECK:  jump  @label                          ; encoding: [0x00,0x00,A,A,0x00,0x00,0x01,0x3d]
 ; CHECK:  ;   fixup A - offset: 2, value: @label, kind: fixup_16_scale_8
-; CHECK:  jump  @jump_table[1]                  ; encoding: [0x00,0x00,A,0x01'A',0x00,0x00,0x01,0x3e]
+; CHECK:  jump  code[@jump_table+1]             ; encoding: [0x00,0x00,A,0x01'A',0x00,0x00,0x01,0x3e]
 ; CHECK:  ;   fixup A - offset: 2, value: @jump_table, kind: fixup_16_scale_32
 ; CHECK:  jump  @label, r2                      ; encoding: [0x00,0x00,A,A,0x02,0x00,0x01,0x3d]
 ; CHECK:  ;   fixup A - offset: 2, value: @label, kind: fixup_16_scale_8
-; CHECK:  jump  @jump_table[1], r2              ; encoding: [0x00,0x00,A,0x01'A',0x02,0x00,0x01,0x3e]
+; CHECK:  jump  code[@jump_table+1], r2         ; encoding: [0x00,0x00,A,0x01'A',0x02,0x00,0x01,0x3e]
 ; CHECK:  ;   fixup A - offset: 2, value: @jump_table, kind: fixup_16_scale_32
diff --git a/llvm/test/MC/EraVM/encoding/named-constants.s b/llvm/test/MC/EraVM/encoding/named-constants.s
index 1577d783bcff..8374e1786d70 100644
--- a/llvm/test/MC/EraVM/encoding/named-constants.s
+++ b/llvm/test/MC/EraVM/encoding/named-constants.s
@@ -10,38 +10,38 @@
   .text
 foo:
   ; commutative
-  add    @constant[r1 + 42], r2, r3
-  add    @constant[r1 + 42], r2, stack[r3 + 123]
-  add    @constant[r1 + 42], r2, stack-[r3 + 123]
-  add    @constant[r1 + 42], r2, stack+=[r3 + 123]
+  add    code[@constant + r1 + 42], r2, r3
+  add    code[@constant + r1 + 42], r2, stack[r3 + 123]
+  add    code[@constant + r1 + 42], r2, stack-[r3 + 123]
+  add    code[@constant + r1 + 42], r2, stack+=[r3 + 123]
 
   ; commutative (2 outputs)
-  mul    @constant[r1 + 42], r2, r3, r4
-  mul    @constant[r1 + 42], r2, stack[r3 + 123], r4
-  mul    @constant[r1 + 42], r2, stack-[r3 + 123], r4
-  mul    @constant[r1 + 42], r2, stack+=[r3 + 123], r4
+  mul    code[@constant + r1 + 42], r2, r3, r4
+  mul    code[@constant + r1 + 42], r2, stack[r3 + 123], r4
+  mul    code[@constant + r1 + 42], r2, stack-[r3 + 123], r4
+  mul    code[@constant + r1 + 42], r2, stack+=[r3 + 123], r4
 
   ; non-commutative
-  sub    @constant[r1 + 42], r2, r3
-  sub    @constant[r1 + 42], r2, stack[r3 + 123]
-  sub    @constant[r1 + 42], r2, stack-[r3 + 123]
-  sub    @constant[r1 + 42], r2, stack+=[r3 + 123]
+  sub    code[@constant + r1 + 42], r2, r3
+  sub    code[@constant + r1 + 42], r2, stack[r3 + 123]
+  sub    code[@constant + r1 + 42], r2, stack-[r3 + 123]
+  sub    code[@constant + r1 + 42], r2, stack+=[r3 + 123]
 
   ; non-commutative (2 outputs)
-  div    @constant[r1 + 42], r2, r3, r4
-  div    @constant[r1 + 42], r2, stack[r3 + 123], r4
-  div    @constant[r1 + 42], r2, stack-[r3 + 123], r4
-  div    @constant[r1 + 42], r2, stack+=[r3 + 123], r4
+  div    code[@constant + r1 + 42], r2, r3, r4
+  div    code[@constant + r1 + 42], r2, stack[r3 + 123], r4
+  div    code[@constant + r1 + 42], r2, stack-[r3 + 123], r4
+  div    code[@constant + r1 + 42], r2, stack+=[r3 + 123], r4
 
   ; pointer arithmetics (only swapped version is supported)
-  ptr.add.s    @constant[r1 + 42], r2, r3
-  ptr.add.s    @constant[r1 + 42], r2, stack[r3 + 123]
-  ptr.add.s    @constant[r1 + 42], r2, stack-[r3 + 123]
-  ptr.add.s    @constant[r1 + 42], r2, stack+=[r3 + 123]
+  ptr.add.s    code[@constant + r1 + 42], r2, r3
+  ptr.add.s    code[@constant + r1 + 42], r2, stack[r3 + 123]
+  ptr.add.s    code[@constant + r1 + 42], r2, stack-[r3 + 123]
+  ptr.add.s    code[@constant + r1 + 42], r2, stack+=[r3 + 123]
 
   ; jumps
-  jump       @jump_table[42]
-  jump       @jump_table[r1+42]
+  jump       code[@jump_table + 42]
+  jump       code[@jump_table + r1 + 42]
 
 
 ; CHECK:  .text
@@ -50,52 +50,52 @@ foo:
 ; CHECK:jump_table:
 ; CHECK:  .text
 ; CHECK:foo:
-; CHECK:  add   @constant[r1+42], r2, r3        ; encoding: [0x00,0x00,A,0x2a'A',0x03,0x21,0x00,0x41]
+; CHECK:  add   code[@constant+r1+42], r2, r3        ; encoding: [0x00,0x00,A,0x2a'A',0x03,0x21,0x00,0x41]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  add   @constant[r1+42], r2, stack[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0x47]
+; CHECK:  add   code[@constant+r1+42], r2, stack[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0x47]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  add   @constant[r1+42], r2, stack-[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0x45]
+; CHECK:  add   code[@constant+r1+42], r2, stack-[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0x45]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  add   @constant[r1+42], r2, stack+=[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0x43]
+; CHECK:  add   code[@constant+r1+42], r2, stack+=[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0x43]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
 
-; CHECK:  mul   @constant[r1+42], r2, r3, r4    ; encoding: [0x00,0x00,A,0x2a'A',0x43,0x21,0x00,0xd1]
+; CHECK:  mul   code[@constant+r1+42], r2, r3, r4    ; encoding: [0x00,0x00,A,0x2a'A',0x43,0x21,0x00,0xd1]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  mul   @constant[r1+42], r2, stack[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x00,0xd7]
+; CHECK:  mul   code[@constant+r1+42], r2, stack[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x00,0xd7]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  mul   @constant[r1+42], r2, stack-[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x00,0xd5]
+; CHECK:  mul   code[@constant+r1+42], r2, stack-[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x00,0xd5]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  mul   @constant[r1+42], r2, stack+=[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x00,0xd3]
+; CHECK:  mul   code[@constant+r1+42], r2, stack+=[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x00,0xd3]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
 
-; CHECK:  sub   @constant[r1+42], r2, r3        ; encoding: [0x00,0x00,A,0x2a'A',0x03,0x21,0x00,0x99]
+; CHECK:  sub   code[@constant+r1+42], r2, r3        ; encoding: [0x00,0x00,A,0x2a'A',0x03,0x21,0x00,0x99]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  sub   @constant[r1+42], r2, stack[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0xa5]
+; CHECK:  sub   code[@constant+r1+42], r2, stack[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0xa5]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  sub   @constant[r1+42], r2, stack-[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0xa1]
+; CHECK:  sub   code[@constant+r1+42], r2, stack-[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0xa1]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  sub   @constant[r1+42], r2, stack+=[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0x9d]
+; CHECK:  sub   code[@constant+r1+42], r2, stack+=[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x00,0x9d]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
 
-; CHECK:  div   @constant[r1+42], r2, r3, r4    ; encoding: [0x00,0x00,A,0x2a'A',0x43,0x21,0x01,0x29]
+; CHECK:  div   code[@constant+r1+42], r2, r3, r4    ; encoding: [0x00,0x00,A,0x2a'A',0x43,0x21,0x01,0x29]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  div   @constant[r1+42], r2, stack[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x01,0x35]
+; CHECK:  div   code[@constant+r1+42], r2, stack[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x01,0x35]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  div   @constant[r1+42], r2, stack-[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x01,0x31]
+; CHECK:  div   code[@constant+r1+42], r2, stack-[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x01,0x31]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  div   @constant[r1+42], r2, stack+=[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x01,0x2d]
+; CHECK:  div   code[@constant+r1+42], r2, stack+=[123 + r3], r4 ; encoding: [0x00,0x7b,A,0x2a'A',0x43,0x21,0x01,0x2d]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
 
-; CHECK:  ptr.add.s     @constant[r1+42], r2, r3 ; encoding: [0x00,0x00,A,0x2a'A',0x03,0x21,0x03,0x78]
+; CHECK:  ptr.add.s     code[@constant+r1+42], r2, r3 ; encoding: [0x00,0x00,A,0x2a'A',0x03,0x21,0x03,0x78]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  ptr.add.s     @constant[r1+42], r2, stack[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x03,0x7e]
+; CHECK:  ptr.add.s     code[@constant+r1+42], r2, stack[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x03,0x7e]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  ptr.add.s     @constant[r1+42], r2, stack-[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x03,0x7c]
+; CHECK:  ptr.add.s     code[@constant+r1+42], r2, stack-[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x03,0x7c]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
-; CHECK:  ptr.add.s     @constant[r1+42], r2, stack+=[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x03,0x7a]
+; CHECK:  ptr.add.s     code[@constant+r1+42], r2, stack+=[123 + r3] ; encoding: [0x00,0x7b,A,0x2a'A',0x03,0x21,0x03,0x7a]
 ; CHECK:  ;   fixup A - offset: 2, value: @constant, kind: fixup_16_scale_32
 
-; CHECK:  jump  @jump_table[42]                 ; encoding: [0x00,0x00,A,0x2a'A',0x00,0x00,0x01,0x3e]
+; CHECK:  jump  code[@jump_table+42]                 ; encoding: [0x00,0x00,A,0x2a'A',0x00,0x00,0x01,0x3e]
 ; CHECK:  ;   fixup A - offset: 2, value: @jump_table, kind: fixup_16_scale_32
-; CHECK:  jump  @jump_table[r1+42]              ; encoding: [0x00,0x00,A,0x2a'A',0x00,0x01,0x01,0x3e]
+; CHECK:  jump  code[@jump_table+r1+42]              ; encoding: [0x00,0x00,A,0x2a'A',0x00,0x01,0x01,0x3e]
 ; CHECK:  ;   fixup A - offset: 2, value: @jump_table, kind: fixup_16_scale_32
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/eravm-basic.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/eravm-basic.ll.expected
index 8361c3c8a50c..022f3a317842 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/eravm-basic.ll.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/eravm-basic.ll.expected
@@ -7,7 +7,7 @@ define void @test1(i256 %rs1) {
 ; CHECK-LABEL: test1:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    nop stack+=[1 + r0]
-; CHECK-NEXT:    add @val[0], r1, stack-[1]
+; CHECK-NEXT:    add code[@val], r1, stack-[1]
 ; CHECK-NEXT:    ret
   %valptr = alloca i256
   %val = load i256, i256 addrspace(4)* @val