From 628e11564089a511e24b33971da93e0b0f708b8a Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko <atrosinenko@accesssoftek.com>
Date: Tue, 11 Jun 2024 14:29:10 +0300
Subject: [PATCH] [EraVM] Prepare for removing repeated operand definitions in
 *.td files

Perform a few preparations before removing repeated definitions of
operands in `EraVMInstrInfo.td`:
* move the definitions of EraVM-specific `AsmOperandClass`es and
  `Operand`s, so that they can be used in `EraVMInstrFormats.td`
* define tablegen classes to be mixed into `Ixx_x` instruction classes
---
 llvm/lib/Target/EraVM/EraVMInstrFormats.td | 219 ++++++++++++++-------
 llvm/lib/Target/EraVM/EraVMInstrInfo.td    |  82 --------
 2 files changed, 143 insertions(+), 158 deletions(-)

diff --git a/llvm/lib/Target/EraVM/EraVMInstrFormats.td b/llvm/lib/Target/EraVM/EraVMInstrFormats.td
index de4142dae5a5..1a61c87171c3 100644
--- a/llvm/lib/Target/EraVM/EraVMInstrFormats.td
+++ b/llvm/lib/Target/EraVM/EraVMInstrFormats.td
@@ -108,6 +108,88 @@ def withRegisterResult : WithDifferentResult<"ToStack", "ToReg">;
 
 include "EraVMOpcodes.td"
 
+//===----------------------------------------------------------------------===//
+// EraVM Operand Definitions.
+//===----------------------------------------------------------------------===//
+
+def UImm16Operand : AsmOperandClass {
+  let Name = "UImm16";
+  let ParserMethod = "tryParseUImm16Operand";
+  let PredicateMethod = "isImm";
+  let RenderMethod = "addImmOperands";
+}
+
+def imm16 : Operand<i256>, IntImmLeaf<i256, [{
+  return Imm.isIntN(16);
+}]> {
+  let ParserMatchClass = UImm16Operand;
+}
+
+def neg_imm16 : Operand<i256>, IntImmLeaf<i256, [{
+  return Imm.isNegative() && Imm.abs().isIntN(16);
+}]> {}
+
+def large_imm : Operand<i256>, IntImmLeaf<i256, [{
+  return !Imm.abs().isIntN(16);
+}]> {}
+
+// This operand class represents those jump targets described
+// as imm_in operand in the spec.
+def JumpTargetOperand : AsmOperandClass {
+  let Name = "JumpTarget";
+  let ParserMethod = "tryParseJumpTargetOperand";
+  let PredicateMethod = "isImm";
+  let RenderMethod = "addImmOperands";
+}
+
+def jmptarget : Operand<OtherVT> {
+  let ParserMatchClass = JumpTargetOperand;
+  let EncoderMethod = "getJumpTargetValue";
+}
+
+// Address operands
+
+def CodeOperand : AsmOperandClass {
+  let Name = "CodeReference";
+  let ParserMethod = "tryParseCodeOperand";
+}
+
+def memop : Operand<i256> {
+  let PrintMethod = "printMemOperand";
+  let EncoderMethod = "getMemOpValue";
+  let ParserMatchClass = CodeOperand;
+  let DecoderMethod = "DecodeCodeOperand";
+  let MIOperandInfo = (ops GR256, i16imm);
+}
+
+let ParserMethod = "tryParseStackOperand",
+    RenderMethod = "addStackReferenceOperands" in {
+def StackInOperand : AsmOperandClass {
+  let Name = "StackInReference";
+  let PredicateMethod = "isStackReference<true>";
+}
+def StackOutOperand : AsmOperandClass {
+  let Name = "StackOutReference";
+  let PredicateMethod = "isStackReference<false>";
+}
+}
+
+def stackin : Operand<i256> {
+  let PrintMethod = "printStackOperand<true>";
+  let EncoderMethod = "getStackOpValue<true>";
+  let ParserMatchClass = StackInOperand;
+  let DecoderMethod = "DecodeStackOperand";
+  let MIOperandInfo = (ops GRStackRefMarker, GR256, i16imm);
+}
+
+def stackout : Operand<i256> {
+  let PrintMethod = "printStackOperand<false>";
+  let EncoderMethod = "getStackOpValue<false>";
+  let ParserMatchClass = StackOutOperand;
+  let DecoderMethod = "DecodeStackOperand";
+  let MIOperandInfo = (ops GRStackRefMarker, GR256, i16imm);
+}
+
 //===----------------------------------------------------------------------===//
 // EraVM Instructions
 //===----------------------------------------------------------------------===//
@@ -346,21 +428,59 @@ class IBinaryS<EraVMOpcode opcode,
   let Imm1 = dst0{19-4};
 }
 
-class Irr_r<EraVMOpcode opcode,
-            mod_swap swap_operands, mod_set_flags silent,
-            dag outs, dag ins,
-            string asmstr,
-            list<dag> pattern>
-  : IBinaryR<opcode, SrcReg, swap_operands, silent, outs, ins, asmstr, pattern> {
+// Mix-in classes to hook standard fields for different combinations
+// of input operands.
+
+class SrcOperandsRR {
+  SrcOperandMode OperandAddrMode = OpndRR;
+
   bits<4> rs0;
   bits<4> rs1;
 
-  let OperandAddrMode = OpndRR;
+  bits<4> Src0 = rs0;
+  bits<4> Src1 = rs1;
+}
+
+class SrcOperandsIR {
+  SrcOperandMode OperandAddrMode = OpndIR;
 
-  let Src0 = rs0;
-  let Src1 = rs1;
+  bits<16> imm;
+  bits<4>  rs1;
+
+  bits<16> Imm0 = imm;
+  bits<4>  Src1 = rs1;
+}
+
+class SrcOperandsMR {
+  SrcOperandMode OperandAddrMode = OpndCR;
+
+  bits<20> src0;
+  bits<4>  rs1;
+
+  bits<4>  Src0 = src0{3-0};
+  bits<16> Imm0 = src0{19-4};
+  bits<4>  Src1 = rs1;
+}
+
+class SrcOperandsSR {
+  SrcOperandMode OperandAddrMode = OpndSR;
+
+  bits<20> src0;
+  bits<4>  rs1;
+
+  bits<4>  Src0 = src0{3-0};
+  bits<16> Imm0 = src0{19-4};
+  bits<4>  Src1 = rs1;
 }
 
+class Irr_r<EraVMOpcode opcode,
+            mod_swap swap_operands, mod_set_flags silent,
+            dag outs, dag ins,
+            string asmstr,
+            list<dag> pattern>
+  : IBinaryR<opcode, SrcReg, swap_operands, silent, outs, ins, asmstr, pattern>,
+    SrcOperandsRR;
+
 class Irr_rr<EraVMOpcode opcode,
              mod_swap swap_operands, mod_set_flags silent,
              dag outs, dag ins,
@@ -377,15 +497,8 @@ class Iir_r<EraVMOpcode opcode,
             dag outs, dag ins,
             string asmstr,
             list<dag> pattern>
-  : IBinaryR<opcode, SrcImm, swap_operands, silent, outs, ins, asmstr, pattern> {
-  bits<4> rs1;
-  bits<16> imm;
-
-  let OperandAddrMode = OpndIR;
-
-  let Src1 = rs1;
-  let Imm0 = imm;
-}
+  : IBinaryR<opcode, SrcImm, swap_operands, silent, outs, ins, asmstr, pattern>,
+    SrcOperandsIR;
 
 class Iir_rr<EraVMOpcode opcode,
              mod_swap swap_operands, mod_set_flags silent,
@@ -403,32 +516,16 @@ class Imr_r<EraVMOpcode opcode,
             dag outs, dag ins,
             string asmstr,
             list<dag> pattern>
-  : IBinaryR<opcode, SrcCodeAddr, swap_operands, silent, outs, ins, asmstr, pattern> {
-  bits<20> src0;
-  bits<4> rs1;
-
-  let OperandAddrMode = OpndCR;
-
-  let Src0 = src0{3-0};
-  let Imm0 = src0{19-4};
-  let Src1 = rs1;
-}
+  : IBinaryR<opcode, SrcCodeAddr, swap_operands, silent, outs, ins, asmstr, pattern>,
+    SrcOperandsMR;
 
 class Isr_r<EraVMOpcode opcode,
             mod_swap swap_operands, mod_set_flags silent,
             dag outs, dag ins,
             string asmstr,
             list<dag> pattern>
-  : IBinaryR<opcode, SrcStackAbsolute, swap_operands, silent, outs, ins, asmstr, pattern> {
-  bits<20> src0;
-  bits<4> rs1;
-
-  let OperandAddrMode = OpndSR;
-
-  let Src0 = src0{3-0};
-  let Src1 = rs1;
-  let Imm0 = src0{19-4};
-}
+  : IBinaryR<opcode, SrcStackAbsolute, swap_operands, silent, outs, ins, asmstr, pattern>,
+    SrcOperandsSR;
 
 class Imr_rr<EraVMOpcode opcode,
              mod_swap swap_operands, mod_set_flags silent,
@@ -457,15 +554,8 @@ class Irr_s<EraVMOpcode opcode,
             dag outs, dag ins,
             string asmstr,
             list<dag> pattern>
-  : IBinaryS<opcode, SrcReg, swap_operands, silent, outs, ins, asmstr, pattern> {
-  bits<4> rs0;
-  bits<4> rs1;
-
-  let OperandAddrMode = OpndRR;
-
-  let Src0 = rs0;
-  let Src1 = rs1;
-}
+  : IBinaryS<opcode, SrcReg, swap_operands, silent, outs, ins, asmstr, pattern>,
+    SrcOperandsRR;
 
 class Irr_sr<EraVMOpcode opcode,
              mod_swap swap_operands, mod_set_flags silent,
@@ -483,15 +573,8 @@ class Iir_s<EraVMOpcode opcode,
             dag outs, dag ins,
             string asmstr,
             list<dag> pattern>
-  : IBinaryS<opcode, SrcImm, swap_operands, silent, outs, ins, asmstr, pattern> {
-  bits<16> imm;
-  bits<4> rs1;
-
-  let OperandAddrMode = OpndIR;
-
-  let Imm0 = imm;
-  let Src1 = rs1;
-}
+  : IBinaryS<opcode, SrcImm, swap_operands, silent, outs, ins, asmstr, pattern>,
+    SrcOperandsIR;
 
 class Iir_sr<EraVMOpcode opcode,
              mod_swap swap_operands, mod_set_flags silent,
@@ -509,32 +592,16 @@ class Imr_s<EraVMOpcode opcode,
             dag outs, dag ins,
             string asmstr,
             list<dag> pattern>
-  : IBinaryS<opcode, SrcCodeAddr, swap_operands, silent, outs, ins, asmstr, pattern> {
-  bits<20> src0;
-  bits<4> rs1;
-
-  let OperandAddrMode = OpndCR;
-
-  let Src0 = src0{3-0};
-  let Imm0 = src0{19-4};
-  let Src1 = rs1;
-}
+  : IBinaryS<opcode, SrcCodeAddr, swap_operands, silent, outs, ins, asmstr, pattern>,
+    SrcOperandsMR;
 
 class Isr_s<EraVMOpcode opcode,
             mod_swap swap_operands, mod_set_flags silent,
             dag outs, dag ins,
             string asmstr,
             list<dag> pattern>
-  : IBinaryS<opcode, SrcStackAbsolute, swap_operands, silent, outs, ins, asmstr, pattern> {
-  bits<20> src0;
-  bits<4> rs1;
-
-  let OperandAddrMode = OpndSR;
-
-  let Src0 = src0{3-0};
-  let Src1 = rs1;
-  let Imm0 = src0{19-4};
-}
+  : IBinaryS<opcode, SrcStackAbsolute, swap_operands, silent, outs, ins, asmstr, pattern>,
+    SrcOperandsSR;
 
 class Imr_sr<EraVMOpcode opcode,
              mod_swap swap_operands, mod_set_flags silent,
diff --git a/llvm/lib/Target/EraVM/EraVMInstrInfo.td b/llvm/lib/Target/EraVM/EraVMInstrInfo.td
index 293833af1149..7c7933e4f6cc 100644
--- a/llvm/lib/Target/EraVM/EraVMInstrInfo.td
+++ b/llvm/lib/Target/EraVM/EraVMInstrInfo.td
@@ -105,88 +105,6 @@ def EraVMAdd_v : SDNode<"EraVMISD::ADD_V", SDT_EraVMArith, [SDNPHasChain, SDNPOu
 def EraVMSub_v : SDNode<"EraVMISD::SUB_V", SDT_EraVMArith, [SDNPHasChain, SDNPOutGlue]>;
 def EraVMMul_v : SDNode<"EraVMISD::MUL_V", SDT_EraVMArith, [SDNPHasChain, SDNPOutGlue]>;
 
-//===----------------------------------------------------------------------===//
-// EraVM Operand Definitions.
-//===----------------------------------------------------------------------===//
-
-def UImm16Operand : AsmOperandClass {
-  let Name = "UImm16";
-  let ParserMethod = "tryParseUImm16Operand";
-  let PredicateMethod = "isImm";
-  let RenderMethod = "addImmOperands";
-}
-
-def imm16 : Operand<i256>, IntImmLeaf<i256, [{
-  return Imm.isIntN(16);
-}]> {
-  let ParserMatchClass = UImm16Operand;
-}
-
-def neg_imm16 : Operand<i256>, IntImmLeaf<i256, [{
-  return Imm.isNegative() && Imm.abs().isIntN(16);
-}]> {}
-
-def large_imm : Operand<i256>, IntImmLeaf<i256, [{
-  return !Imm.abs().isIntN(16);
-}]> {}
-
-// This operand class represents those jump targets described
-// as imm_in operand in the spec.
-def JumpTargetOperand : AsmOperandClass {
-  let Name = "JumpTarget";
-  let ParserMethod = "tryParseJumpTargetOperand";
-  let PredicateMethod = "isImm";
-  let RenderMethod = "addImmOperands";
-}
-
-def jmptarget : Operand<OtherVT> {
-  let ParserMatchClass = JumpTargetOperand;
-  let EncoderMethod = "getJumpTargetValue";
-}
-
-// Address operands
-
-def CodeOperand : AsmOperandClass {
-  let Name = "CodeReference";
-  let ParserMethod = "tryParseCodeOperand";
-}
-
-def memop : Operand<i256> {
-  let PrintMethod = "printMemOperand";
-  let EncoderMethod = "getMemOpValue";
-  let ParserMatchClass = CodeOperand;
-  let DecoderMethod = "DecodeCodeOperand";
-  let MIOperandInfo = (ops GR256, i16imm);
-}
-
-let ParserMethod = "tryParseStackOperand",
-    RenderMethod = "addStackReferenceOperands" in {
-def StackInOperand : AsmOperandClass {
-  let Name = "StackInReference";
-  let PredicateMethod = "isStackReference<true>";
-}
-def StackOutOperand : AsmOperandClass {
-  let Name = "StackOutReference";
-  let PredicateMethod = "isStackReference<false>";
-}
-}
-
-def stackin : Operand<i256> {
-  let PrintMethod = "printStackOperand<true>";
-  let EncoderMethod = "getStackOpValue<true>";
-  let ParserMatchClass = StackInOperand;
-  let DecoderMethod = "DecodeStackOperand";
-  let MIOperandInfo = (ops GRStackRefMarker, GR256, i16imm);
-}
-
-def stackout : Operand<i256> {
-  let PrintMethod = "printStackOperand<false>";
-  let EncoderMethod = "getStackOpValue<false>";
-  let ParserMatchClass = StackOutOperand;
-  let DecoderMethod = "DecodeStackOperand";
-  let MIOperandInfo = (ops GRStackRefMarker, GR256, i16imm);
-}
-
 //===----------------------------------------------------------------------===//
 // Custom DAG Selection Operations.
 //===----------------------------------------------------------------------===//