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masatakemasatake
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Verilog: fill typeref fields of instances
This one is conceptually based on universal-ctags/ctags@master...my2817:ctags:master reported and written by @my2817 at universal-ctags#3469. The test case is also taken from universal-ctags#3469 submitted by @my2817. This commit does two things: * fill typeref fields of instances with module names, and * extract the module names used for defining instances as defInstance role of module kind. TODO: Update ctags-lang-verilog(7).
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5 files changed

+80
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‎Units/parser-verilog.r/verilog-instance.d/expected.tags

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -14,22 +14,22 @@ b input.v /^ input b; \/\/ To uut3 of foo.
1414
top.b input.v /^ input b; \/\/ To uut3 of foo.v$/;" p module:top
1515
unused_pin input.v /^ wire unused_pin;$/;" n module:top
1616
top.unused_pin input.v /^ wire unused_pin;$/;" n module:top
17-
uut1 input.v /^ foo uut1 ($/;" i module:top
18-
top.uut1 input.v /^ foo uut1 ($/;" i module:top
19-
uut2 input.v /^ uut2 ($/;" i module:top
20-
top.uut2 input.v /^ uut2 ($/;" i module:top
21-
uut3 input.v /^ foo uut3 (\/*AUTOINST*\/$/;" i module:top
22-
top.uut3 input.v /^ foo uut3 (\/*AUTOINST*\/$/;" i module:top
23-
uut4 input.v /^ uut4 (\/*AUTOINST*\/$/;" i module:top
24-
top.uut4 input.v /^ uut4 (\/*AUTOINST*\/$/;" i module:top
25-
uut5 input.v /^ uut5 (\/*AUTOINST*\/$/;" i module:top
26-
top.uut5 input.v /^ uut5 (\/*AUTOINST*\/$/;" i module:top
27-
uut6 input.v /^ foo uut6 [10:0]();$/;" i module:top
28-
top.uut6 input.v /^ foo uut6 [10:0]();$/;" i module:top
29-
uut7 input.v /^ foo uut7 [1:0][10:0]();$/;" i module:top
30-
top.uut7 input.v /^ foo uut7 [1:0][10:0]();$/;" i module:top
31-
uut8 input.v /^ foo uut8 () ;$/;" i module:top
32-
top.uut8 input.v /^ foo uut8 () ;$/;" i module:top
17+
uut1 input.v /^ foo uut1 ($/;" i module:top typeref:module:foo
18+
top.uut1 input.v /^ foo uut1 ($/;" i module:top typeref:module:foo
19+
uut2 input.v /^ uut2 ($/;" i module:top typeref:module:foo
20+
top.uut2 input.v /^ uut2 ($/;" i module:top typeref:module:foo
21+
uut3 input.v /^ foo uut3 (\/*AUTOINST*\/$/;" i module:top typeref:module:foo
22+
top.uut3 input.v /^ foo uut3 (\/*AUTOINST*\/$/;" i module:top typeref:module:foo
23+
uut4 input.v /^ uut4 (\/*AUTOINST*\/$/;" i module:top typeref:module:foo
24+
top.uut4 input.v /^ uut4 (\/*AUTOINST*\/$/;" i module:top typeref:module:foo
25+
uut5 input.v /^ uut5 (\/*AUTOINST*\/$/;" i module:top typeref:module:foo
26+
top.uut5 input.v /^ uut5 (\/*AUTOINST*\/$/;" i module:top typeref:module:foo
27+
uut6 input.v /^ foo uut6 [10:0]();$/;" i module:top typeref:module:foo
28+
top.uut6 input.v /^ foo uut6 [10:0]();$/;" i module:top typeref:module:foo
29+
uut7 input.v /^ foo uut7 [1:0][10:0]();$/;" i module:top typeref:module:foo
30+
top.uut7 input.v /^ foo uut7 [1:0][10:0]();$/;" i module:top typeref:module:foo
31+
uut8 input.v /^ foo uut8 () ;$/;" i module:top typeref:module:foo
32+
top.uut8 input.v /^ foo uut8 () ;$/;" i module:top typeref:module:foo
3333
func_foo input.v /^ function void func_foo(int a);$/;" f module:top
3434
top.func_foo input.v /^ function void func_foo(int a);$/;" f module:top
3535
a input.v /^ function void func_foo(int a);$/;" p function:top.func_foo

‎Units/parser-verilog.r/verilog-module-ref.d/args.ctags

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
--sort=no
2+
--extras=+r
3+
--fields=+r

‎Units/parser-verilog.r/verilog-module-ref.d/expected.tags

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
test input.v /^module test (\/*AUTOARG*\/);$/;" m roles:def
2+
i_a input.v /^ input i_a, i_b;$/;" p module:test roles:def
3+
i_b input.v /^ input i_a, i_b;$/;" p module:test roles:def
4+
o_c input.v /^ output o_c;$/;" p module:test roles:def
5+
ref1 input.v /^ ref1 int1 ();$/;" m module:test roles:defInstance
6+
int1 input.v /^ ref1 int1 ();$/;" i module:test typeref:module:ref1 roles:def
7+
ref1 input.v /^ ref1 int2 ();$/;" m module:test roles:defInstance
8+
int2 input.v /^ ref1 int2 ();$/;" i module:test typeref:module:ref1 roles:def
9+
ref3 input.v /^ ref3 # (.A (aaa),$/;" m module:test roles:defInstance
10+
int3 input.v /^ int3 ();$/;" i module:test typeref:module:ref3 roles:def

‎Units/parser-verilog.r/verilog-module-ref.d/input.v

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
// Taken from #3469 submitted by @my2817
2+
module test (/*AUTOARG*/);
3+
input i_a, i_b;
4+
output o_c;
5+
6+
ref1 int1 ();
7+
ref1 int2 ();
8+
ref3 # (.A (aaa),
9+
.B (bbb))
10+
int3 ();
11+
12+
endmodule // test

‎parsers/verilog.c

Lines changed: 39 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,10 @@ typedef enum {
108108
K_NETTYPE,
109109
} verilogKind;
110110

111+
typedef enum {
112+
R_MODULE_DEFINSTANCE,
113+
} verilogModuleRole;
114+
111115
typedef struct {
112116
const char *keyword;
113117
verilogKind kind;
@@ -141,11 +145,16 @@ static int Ungetc;
141145
static int Lang_verilog;
142146
static int Lang_systemverilog;
143147

148+
static roleDefinition VerilogModuleRoles [] = {
149+
{ true, "defInstance", "defining instances" },
150+
};
151+
144152
static kindDefinition VerilogKinds [] = {
145153
{ true, 'c', "constant", "constants (define, parameter, specparam)" },
146154
{ true, 'e', "event", "events" },
147155
{ true, 'f', "function", "functions" },
148-
{ true, 'm', "module", "modules" },
156+
{ true, 'm', "module", "modules",
157+
.referenceOnly = false, ATTACH_ROLES(VerilogModuleRoles)},
149158
{ true, 'n', "net", "net data types" },
150159
{ true, 'p', "port", "ports" },
151160
{ true, 'r', "register", "variable data types" },
@@ -406,6 +415,7 @@ static fieldDefinition SystemVerilogFields[] = {
406415
* PROTOTYPE DEFINITIONS
407416
*/
408417

418+
static void createTagFull (tokenInfo *const token, verilogKind kind, int role, tokenInfo *const typeref);
409419
static bool isIdentifier (tokenInfo* token);
410420
static int processDefine (tokenInfo *const token, int c);
411421
static int processType (tokenInfo* token, int c, verilogKind* kind, bool* with);
@@ -950,6 +960,11 @@ static int dropEndContext (tokenInfo *const token, int c)
950960

951961

952962
static void createTag (tokenInfo *const token, verilogKind kind)
963+
{
964+
createTagFull (token, kind, ROLE_DEFINITION_INDEX, NULL);
965+
}
966+
967+
static void createTagFull (tokenInfo *const token, verilogKind kind, int role, tokenInfo *const typeref)
953968
{
954969
tagEntryInfo tag;
955970

@@ -981,7 +996,10 @@ static void createTag (tokenInfo *const token, verilogKind kind)
981996
}
982997

983998
/* Create tag */
984-
initTagEntry (&tag, vStringValue (token->name), kind);
999+
if (role == ROLE_DEFINITION_INDEX)
1000+
initTagEntry (&tag, vStringValue (token->name), kind);
1001+
else
1002+
initRefTagEntry (&tag, vStringValue (token->name), kind, role);
9851003
tag.lineNumber = token->lineNumber;
9861004
tag.filePosition = token->filePosition;
9871005

@@ -1000,12 +1018,19 @@ static void createTag (tokenInfo *const token, verilogKind kind)
10001018
verbose ("Class %s extends %s\n", vStringValue (token->name), tag.extensionFields.inheritance);
10011019
}
10021020

1021+
if (typeref)
1022+
{
1023+
tag.extensionFields.typeRef [0] = getNameForKind (typeref->kind);
1024+
tag.extensionFields.typeRef [1] = vStringValue (typeref->name);
1025+
}
1026+
10031027
if (token->parameter)
10041028
attachParserField (&tag, false, fieldTable [F_PARAMETER].ftype, "");
10051029

10061030
makeTagEntry (&tag);
10071031

1008-
if (isXtagEnabled (XTAG_QUALIFIED_TAGS) && currentContext->kind != K_UNDEFINED)
1032+
if (isXtagEnabled (XTAG_QUALIFIED_TAGS) && currentContext->kind != K_UNDEFINED
1033+
&& role == ROLE_DEFINITION_INDEX)
10091034
{
10101035
vString *const scopedName = vStringNew ();
10111036

@@ -1021,7 +1046,7 @@ static void createTag (tokenInfo *const token, verilogKind kind)
10211046
}
10221047

10231048
/* Push token as context if it is a container */
1024-
if (container)
1049+
if (container && role == ROLE_DEFINITION_INDEX)
10251050
{
10261051
createContext (kind, token->name);
10271052

@@ -1409,7 +1434,7 @@ static int processAssertion (tokenInfo *const token, int c)
14091434

14101435
// data_declaration ::=
14111436
// ...
1412-
// import < package_identifier :: identifier | package_identifier :: * > ;
1437+
// import < package_identifier :: identifier | package_identifier :: * > ;
14131438
// dpi_import_export ::=
14141439
// import ( "DPI-C" | "DPI" ) [ context | pure ] [ c_identifier = ] function data_type_or_void function_identifier [ ( [ tf_port_list ] ) ] ;
14151440
// | import ( "DPI-C" | "DPI" ) [ context ] [ c_identifier = ] task task_identifier [ ( [ tf_port_list ] ) ] ;
@@ -1824,16 +1849,19 @@ static int tagIdsInPort (tokenInfo *const token, int c, verilogKind kind, bool m
18241849
// Tag a list of identifiers in a data declaration
18251850
static int tagIdsInDataDecl (tokenInfo* token, int c, verilogKind kind)
18261851
{
1852+
tokenInfo *module = dupToken(token);
1853+
module->kind = K_MODULE;
1854+
18271855
c = skipClassType (token, c);
18281856
if (c == ';')
1829-
return c;
1857+
goto out;
18301858

18311859
// skip drive|charge strength or type_reference, dimensions, and delay for net
18321860
if (c == '(')
18331861
c = skipPastMatch ("()");
18341862
c = skipDimension (c);
18351863
if (c == '.')
1836-
return c; // foo[...].bar = ..;
1864+
goto out; // foo[...].bar = ..;
18371865
c = skipDelay (token, c); // ## (cycle delay)
18381866

18391867
while (c != EOF)
@@ -1859,7 +1887,8 @@ static int tagIdsInDataDecl (tokenInfo* token, int c, verilogKind kind)
18591887
if (c == ';' || c == ',')
18601888
{
18611889
verbose ("find instance: %s with kind %s\n", vStringValue (token->name), getNameForKind (K_INSTANCE));
1862-
createTag (token, K_INSTANCE);
1890+
createTagFull (module, module->kind, R_MODULE_DEFINSTANCE, NULL);
1891+
createTagFull (token, K_INSTANCE, ROLE_DEFINITION_INDEX, module);
18631892
}
18641893
}
18651894
c = skipMacro (c, token); // `ifdef, `else, `endif, etc. (before comma)
@@ -1868,6 +1897,8 @@ static int tagIdsInDataDecl (tokenInfo* token, int c, verilogKind kind)
18681897
c = skipWhite (vGetc ()); // skip ','
18691898
c = skipMacro (c, token); // `ifdef, `else, `endif, etc. (after comma)
18701899
}
1900+
out:
1901+
deleteToken (module);
18711902
return c;
18721903
}
18731904

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