Description
While looking through the Hyperstone E1XS core, a few things have hit me as odd and potentially wrong, however I haven't investigated these well enough to go changing them yet. I want to keep track of the stuff I find, and allow other people who may understand Hyperstone better than me to chime in.
Register pairs and wrapping
When the source or destination is G15 and the instruction operates on a register pair, what is Rdf or Rsf? Is it the reserved G16 or does it wrap around to G0 aka PC? It doesn't really make sense for it to access G16 as writing upper global registers is a privileged operation and it would mean any instruction that writes to a register pair could cause a privilege exception. The documentation all states that only mov/movi with the H bit set can access upper global registers.
When the source or destination is L15 and the instruction operates on a register pair, what is Rdf or Rsf? Does it wrap around to L0 or does it escape the frame's register window? I honestly don't know what a real E1XS chip does in this case.
Negate optimisation
It should be possible to optimise the flag calculation and eliminate the 64-bit temporary: C flag will just indicate non-zero source, and V flag will just indicate that source is equal to 0x80000000 (the only 32-bit value that can cause an overflow when subtracted from zero).
SR as destination
Quoting from page 1-10 of the E1XS manual (page 14 of the PDF):
A result placed in the SR overrules any setting or clearing of the condition flags as a result of an instruction.
This means that setting the destination register needs to happen after any flag calculation. However, right now a lot of op handlers are calculating zero flag and sometimes other flags after setting the destination register. This will cause incorrect behaviour when the destination is SR.