Update SPI host

[rivos-eblot]

Update SPI host implementation to support V3 features:

• single CONFIGOPTS register
• larger transfert width and refactored COMMAND register
• SPI event signalling (from edge to level) and INTR_STATE behavior
• initial TX issue has been fixed

Check:

• STATUS.active management?
• TXFIFO length? (HW discrepancy in reported depth was not emulated in QEMU, so likely no change to support)

[rivos-eblot]

Done in #120

Waiting for feedback on STATUS.active bit behavior (from wave observation), shall this PR need more work to change this bit emulation, i.e. whether it beats between each command handling.

[rivos-eblot]

The STATUS.active bit does not seem to flicker between each command, so QEMU needs to be updated accordingly:

[rivos-eblot]

Second (and hopefully) last round of changes: #139

All tests now pass, with a couple of workarounds: with spi_host_irq_test

1. ready_event_irq only passes is the SPI clock is speed up, otherwise the test times out: DeadlineExceeded:["SPI",178].
2. cmd_busy_error_irq only passes if the SPI clock is reduced. Due to lack of synchronization between QEMU vCPU (Ibex) and the emulated HW, QEMU pops and executes the first pushed commands before the Ibex core is able to push new ones when the SPI clock is fast enough. This makes the test fails, as it pushes 6 commands in a row and expects to saturate the command FIFO, which does not happen with QEMU as QEMU SPI HOST HW has already started to pop out the commands.
   If the SPI HOST clock is reduced, QEMU does not pop out the commands fast enough for freeing space in the command FIFO and the test passes.

[rivos-eblot]

After observing the Command FIFO waves, it appeared that the command management in QEMU has wrong from the early beginning. The Command FIFO is 4 command deep, however each command is popped out of the FIFO before being executed. This means that there may be up to 4 commands in the FIFO + 1 executing, i.e. up to 5 pushed commands before the READY bit goes low, and the SPI Host does not accept command anymore.

Reworking the Command FIFO management to follow the SPI HOST HW makes all the SPI HOST SW test pass. Note that other bugs after the FIFO rework remained unnoticed through the OpenTitan SW tests, but some of our baremetal tests triggered those issues, which have also been addressed.

[rivos-eblot]

Done in #139.

Behavior on error is not yet fully validated