[csrng/rtl] Remove the rcstage FIFO from ctr_drbg_gen

Removal of this FIFO requires two additional states in the FSM in
ctr_drbg_gen to handle the data path bifurcation to the update unit,
depending on the `glast` field.

Signed-off-by: Florian Glaser <[email protected]>

Author: glaserf

hw/ip/csrng/data/csrng.hjson

@@ -749,15 +749,6 @@
                 This bit will stay set until the next reset.
                 '''
         }
-        { bits: "11",
-          name: "SFIFO_GRCSTAGE_ERR",
-          desc: '''
-                This bit will be set to one when an error has been detected for the
-                grcstage FIFO. The type of error is reflected in the type status
-                bits (bits 28 through 30 of this register).
-                This bit will stay set until the next reset.
-                '''
-        }
         { bits: "13",
           name: "SFIFO_GADSTAGE_ERR",
           desc: '''

hw/ip/csrng/doc/registers.md

@@ -555,12 +555,12 @@ Writing a zero resets this status bit.
 Hardware detection of error conditions status register
 - Offset: `0x54`
 - Reset default: `0x0`
-- Reset mask: `0x7ff0ee03`
+- Reset mask: `0x7ff0e603`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 7}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_CMD_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 7}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_CMD_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
 ```
 
 |  Bits  |  Type  |  Reset  | Name                                                |
@@ -581,8 +581,7 @@ Hardware detection of error conditions status register
 |   15   |   ro   |   0x0   | [SFIFO_CMDID_ERR](#err_code--sfifo_cmdid_err)       |
 |   14   |   ro   |   0x0   | [SFIFO_GGENBITS_ERR](#err_code--sfifo_ggenbits_err) |
 |   13   |   ro   |   0x0   | [SFIFO_GADSTAGE_ERR](#err_code--sfifo_gadstage_err) |
-|   12   |        |         | Reserved                                            |
-|   11   |   ro   |   0x0   | [SFIFO_GRCSTAGE_ERR](#err_code--sfifo_grcstage_err) |
+| 12:11  |        |         | Reserved                                            |
 |   10   |   ro   |   0x0   | [SFIFO_GBENCACK_ERR](#err_code--sfifo_gbencack_err) |
 |   9    |   ro   |   0x0   | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err)       |
 |  8:2   |        |         | Reserved                                            |
@@ -674,12 +673,6 @@ gadstage FIFO. The type of error is reflected in the type status
 bits (bits 28 through 30 of this register).
 This bit will stay set until the next reset.
 
-### ERR_CODE . SFIFO_GRCSTAGE_ERR
-This bit will be set to one when an error has been detected for the
-grcstage FIFO. The type of error is reflected in the type status
-bits (bits 28 through 30 of this register).
-This bit will stay set until the next reset.
-
 ### ERR_CODE . SFIFO_GBENCACK_ERR
 This bit will be set to one when an error has been detected for the
 gbencack FIFO. The type of error is reflected in the type status

hw/ip/csrng/dv/env/csrng_env_pkg.sv

@@ -60,7 +60,6 @@ package csrng_env_pkg;
     sfifo_genbits_error  = 1,
     sfifo_final_error    = 3,
     sfifo_gbencack_error = 4,
-    sfifo_grcstage_error = 5,
     sfifo_gadstage_error = 7,
     sfifo_ggenbits_error = 8,
     sfifo_cmdid_error    = 9,
@@ -83,7 +82,6 @@ package csrng_env_pkg;
     sfifo_genbits_err       = 1,
     sfifo_final_err         = 3,
     sfifo_gbencack_err      = 4,
-    sfifo_grcstage_err      = 5,
     sfifo_gadstage_err      = 7,
     sfifo_ggenbits_err      = 8,
     sfifo_cmdid_err         = 9,
@@ -103,7 +101,6 @@ package csrng_env_pkg;
     sfifo_genbits_err_test  = 22,
     sfifo_final_err_test    = 24,
     sfifo_gbencack_err_test = 25,
-    sfifo_grcstage_err_test = 26,
     sfifo_gadstage_err_test = 28,
     sfifo_ggenbits_err_test = 29,
     sfifo_cmdid_err_test    = 30,
@@ -127,7 +124,6 @@ package csrng_env_pkg;
     SFIFO_GENBITS_ERR  = 1,
     SFIFO_FINAL_ERR    = 9,
     SFIFO_GBENCACK_ERR = 10,
-    SFIFO_GRCSTAGE_ERR = 11,
     SFIFO_GADSTAGE_ERR = 13,
     SFIFO_GGENBITS_ERR = 14,
     SFIFO_CMDID_ERR    = 15,
@@ -159,7 +155,6 @@ package csrng_env_pkg;
     sfifo_cmdid    = 0,
     sfifo_ggenbits = 1,
     sfifo_gadstage = 2,
-    sfifo_grcstage = 4,
     sfifo_gbencack = 5,
     sfifo_final    = 6,
     sfifo_genbits  = 7,

hw/ip/csrng/dv/env/csrng_path_if.sv

@@ -18,7 +18,7 @@ interface csrng_path_if
       "sfifo_cmd", "sfifo_genbits": return {core_path, $sformatf(".gen_cmd_stage[%0d]", app),
                                             ".u_csrng_cmd_stage.", fifo_name, "_", which_path};
       "sfifo_final": return {core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path};
-      "sfifo_gbencack", "sfifo_grcstage", "sfifo_gadstage", "sfifo_ggenbits":
+      "sfifo_gbencack", "sfifo_gadstage", "sfifo_ggenbits":
         return {core_path,".u_csrng_ctr_drbg_gen.sfifo_", fifo_name.substr(7, fifo_name.len()-1),
                 "_", which_path};
       "sfifo_cmdid": return {core_path, ".u_csrng_block_encrypt.", fifo_name, "_", which_path};

hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv

@@ -100,8 +100,8 @@ class csrng_err_vseq extends csrng_base_vseq;
                               cfg.which_app_err_alert, fld_name), UVM_MEDIUM)
 
     case (cfg.which_err_code) inside
-      sfifo_cmd_err, sfifo_genbits_err, sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
-      sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err: begin
+      sfifo_cmd_err, sfifo_genbits_err, sfifo_final_err, sfifo_gbencack_err, sfifo_gadstage_err,
+      sfifo_ggenbits_err, sfifo_cmdid_err: begin
         fld = csr.get_field_by_name(fld_name);
         fifo_base_path = fld_name.substr(0, last_index-1);
 
@@ -289,9 +289,8 @@ class csrng_err_vseq extends csrng_base_vseq;
         cov_vif.cg_err_code_sample(.err_code(backdoor_err_code_val));
       end
       sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_final_err_test,
-      sfifo_gbencack_err_test, sfifo_grcstage_err_test, sfifo_gadstage_err_test,
-      sfifo_ggenbits_err_test, sfifo_cmdid_err_test,
-      cmd_stage_sm_err_test, main_sm_err_test, drbg_cmd_sm_err_test,
+      sfifo_gbencack_err_test, sfifo_gadstage_err_test, sfifo_ggenbits_err_test,
+      sfifo_cmdid_err_test, cmd_stage_sm_err_test, main_sm_err_test, drbg_cmd_sm_err_test,
       drbg_gen_sm_err_test, drbg_updbe_sm_err_test, drbg_updob_sm_err_test, aes_cipher_sm_err_test,
       cmd_gen_cnt_err_test, fifo_write_err_test, fifo_read_err_test, fifo_state_err_test: begin
         fld = csr.get_field_by_name(fld_name.substr(0, last_index-1));

hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv

@@ -220,8 +220,8 @@ class csrng_intr_vseq extends csrng_base_vseq;
     last_index = find_index("_", fld_name, "last");
 
     case (cfg.which_fatal_err) inside
-      sfifo_cmd_error, sfifo_genbits_error, sfifo_final_error, sfifo_gbencack_error,
-      sfifo_grcstage_error, sfifo_gadstage_error, sfifo_ggenbits_error, sfifo_cmdid_error: begin
+      sfifo_cmd_error, sfifo_genbits_error, sfifo_final_error, sfifo_cmdid_error,
+      sfifo_gadstage_error, sfifo_ggenbits_error, sfifo_gbencack_error: begin
         fifo_base_path = fld_name.substr(0, last_index-1);
 
         foreach (path_exts[i]) begin

hw/ip/csrng/rtl/csrng_core.sv

@@ -134,8 +134,6 @@ module csrng_core import csrng_pkg::*; #(
   logic [2:0]                  ctr_drbg_upd_sfifo_final_err;
   logic                        ctr_drbg_gen_sfifo_gbencack_err_sum;
   logic [2:0]                  ctr_drbg_gen_sfifo_gbencack_err;
-  logic                        ctr_drbg_gen_sfifo_grcstage_err_sum;
-  logic [2:0]                  ctr_drbg_gen_sfifo_grcstage_err;
   logic                        ctr_drbg_gen_sfifo_gadstage_err_sum;
   logic [2:0]                  ctr_drbg_gen_sfifo_gadstage_err;
   logic                        ctr_drbg_gen_sfifo_ggenbits_err_sum;
@@ -417,7 +415,6 @@ module csrng_core import csrng_pkg::*; #(
          (|cmd_stage_sfifo_genbits_err_sum) ||
          ctr_drbg_upd_sfifo_final_err_sum ||
          ctr_drbg_gen_sfifo_gbencack_err_sum ||
-         ctr_drbg_gen_sfifo_grcstage_err_sum ||
          ctr_drbg_gen_sfifo_gadstage_err_sum ||
          ctr_drbg_gen_sfifo_ggenbits_err_sum ||
          block_encrypt_sfifo_cmdid_err_sum ||
@@ -433,8 +430,6 @@ module csrng_core import csrng_pkg::*; #(
          err_code_test_bit[9];
   assign ctr_drbg_gen_sfifo_gbencack_err_sum = (|ctr_drbg_gen_sfifo_gbencack_err) ||
          err_code_test_bit[10];
-  assign ctr_drbg_gen_sfifo_grcstage_err_sum = (|ctr_drbg_gen_sfifo_grcstage_err) ||
-         err_code_test_bit[11];
   assign ctr_drbg_gen_sfifo_gadstage_err_sum = (|ctr_drbg_gen_sfifo_gadstage_err) ||
          err_code_test_bit[13];
   assign ctr_drbg_gen_sfifo_ggenbits_err_sum = (|ctr_drbg_gen_sfifo_ggenbits_err) ||
@@ -454,7 +449,6 @@ module csrng_core import csrng_pkg::*; #(
          block_encrypt_sfifo_cmdid_err[2] ||
          ctr_drbg_gen_sfifo_ggenbits_err[2] ||
          ctr_drbg_gen_sfifo_gadstage_err[2] ||
-         ctr_drbg_gen_sfifo_grcstage_err[2] ||
          ctr_drbg_gen_sfifo_gbencack_err[2] ||
          ctr_drbg_upd_sfifo_final_err[2] ||
          (|cmd_stage_sfifo_genbits_err_wr) ||
@@ -464,7 +458,6 @@ module csrng_core import csrng_pkg::*; #(
          block_encrypt_sfifo_cmdid_err[1] ||
          ctr_drbg_gen_sfifo_ggenbits_err[1] ||
          ctr_drbg_gen_sfifo_gadstage_err[1] ||
-         ctr_drbg_gen_sfifo_grcstage_err[1] ||
          ctr_drbg_gen_sfifo_gbencack_err[1] ||
          ctr_drbg_upd_sfifo_final_err[1] ||
          (|cmd_stage_sfifo_genbits_err_rd) ||
@@ -474,7 +467,6 @@ module csrng_core import csrng_pkg::*; #(
          block_encrypt_sfifo_cmdid_err[0] ||
          ctr_drbg_gen_sfifo_ggenbits_err[0] ||
          ctr_drbg_gen_sfifo_gadstage_err[0] ||
-         ctr_drbg_gen_sfifo_grcstage_err[0] ||
          ctr_drbg_gen_sfifo_gbencack_err[0] ||
          ctr_drbg_upd_sfifo_final_err[0] ||
          (|cmd_stage_sfifo_genbits_err_st) ||
@@ -498,10 +490,6 @@ module csrng_core import csrng_pkg::*; #(
   assign hw2reg.err_code.sfifo_gbencack_err.de = cs_enable_fo[12] &&
          ctr_drbg_gen_sfifo_gbencack_err_sum;
 
-  assign hw2reg.err_code.sfifo_grcstage_err.d = 1'b1;
-  assign hw2reg.err_code.sfifo_grcstage_err.de = cs_enable_fo[13] &&
-         ctr_drbg_gen_sfifo_grcstage_err_sum;
-
   assign hw2reg.err_code.sfifo_gadstage_err.d = 1'b1;
   assign hw2reg.err_code.sfifo_gadstage_err.de = cs_enable_fo[15] &&
          ctr_drbg_gen_sfifo_gadstage_err_sum;
@@ -1390,7 +1378,6 @@ module csrng_core import csrng_pkg::*; #(
     .sm_err_o (drbg_gen_sm_err),
 
     .fifo_gbencack_err_o(ctr_drbg_gen_sfifo_gbencack_err),
-    .fifo_grcstage_err_o(ctr_drbg_gen_sfifo_grcstage_err),
     .fifo_gadstage_err_o(ctr_drbg_gen_sfifo_gadstage_err),
     .fifo_ggenbits_err_o(ctr_drbg_gen_sfifo_ggenbits_err)
   );
@@ -1427,9 +1414,9 @@ module csrng_core import csrng_pkg::*; #(
   logic [SeedLen-1:0] unused_gen_rsp_pdata;
   logic               unused_state_db_inst_state;
 
-  assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || err_code_test_bit[12] ||
+  assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || (|err_code_test_bit[12:11]) ||
                                     (|err_code_test_bit[8:2]);
-  assign unused_enable_fo = cs_enable_fo[42] || cs_enable_fo[14] || (|cs_enable_fo[9:4]);
+  assign unused_enable_fo = cs_enable_fo[42] || (|cs_enable_fo[14:13]) || (|cs_enable_fo[9:4]);
   assign unused_reg2hw_genbits = (|reg2hw.genbits.q);
   assign unused_int_state_val = (|reg2hw.int_state_val.q);
   assign unused_reseed_interval = reg2hw.reseed_interval.qe;