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Add verification support for PLIC
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‎dv/verilator/demo_system_verilator_lint.vlt

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Original file line numberDiff line numberDiff line change
@@ -31,3 +31,22 @@ lint_off -rule IMPERFECTSCH -file "*prim_flop_2sync.sv"
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lint_off -rule WIDTH -file "*uartdpi.sv"
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lint_off -rule UNUSED -file "*uartdpi.sv"
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lint_off -rule WIDTH -file "*plicdpi.sv"
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lint_off -rule UNUSED -file "*plicdpi.sv"
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lint_off -rule WIDTHEXPAND -file "*plicdpi.sv"
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lint_off -rule WIDTHTRUNC -file "*plicdpi.sv"
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lint_off -rule MULTIDRIVEN -file "*plicdpi.sv"
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lint_off -rule CASEOVERLAP -file "*plicdpi.sv"
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lint_off -rule WIDTH -file "*plic.sv"
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lint_off -rule UNUSED -file "*plic.sv"
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lint_off -rule WIDTHEXPAND -file "*plic.sv"
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lint_off -rule WIDTHTRUNC -file "*plic.sv"
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lint_off -rule CASEOVERLAP -file "*plic.sv"
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lint_off -rule WIDTH -file "*ibex_demo_system.sv"
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lint_off -rule UNUSED -file "*ibex_demo_system.sv"
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lint_off -rule WIDTHEXPAND -file "*ibex_demo_system.sv"
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lint_off -rule WIDTHTRUNC -file "*ibex_demo_system.sv"

‎dv/verilator/plicdpi.sv

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,157 @@
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// Corrected Virtual PLIC interface for Verilator simulation
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module plicdpi #(
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parameter int SOURCES = 32,
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parameter int TARGETS = 1,
5+
parameter int PRIORITIES = 3
6+
)(
7+
input logic clk_i,
8+
input logic rst_ni,
9+
10+
// Bus interface signals (matching the RTL plic register map)
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input logic req_i,
12+
input logic [31:0] addr_i,
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input logic we_i,
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input logic [3:0] be_i,
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input logic [31:0] wdata_i,
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output logic rvalid_o,
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output logic [31:0] rdata_o,
18+
19+
// Interrupt interface
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input logic [SOURCES-1:0] irq_sources_i,
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output logic [SOURCES-1:0] irq_pending_o,
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output logic [TARGETS-1:0] irq_o
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);
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// Register map constants (same as in plic.sv)
26+
localparam int PRIORITY_BASE = 'h000000;
27+
localparam int PENDING_BASE = 'h001000;
28+
localparam int ENABLE_BASE = 'h002000;
29+
localparam int THRESHOLD_BASE = 'h200000;
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localparam int CLAIM_COMPLETE = 'h200004;
31+
32+
// Internal registers
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logic [PRIORITIES-1:0] priorities [SOURCES];
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logic [SOURCES-1:0] enables;
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logic [PRIORITIES-1:0] threshold;
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logic [SOURCES-1:0] pending;
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logic [$clog2(SOURCES)-1:0] claimed_irq;
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// Register interface read data
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logic [31:0] reg_rdata;
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// ------------------------------
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// Write Handling
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// ------------------------------
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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for (int i = 0; i < SOURCES; i++) begin
48+
priorities[i] <= '0;
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end
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enables <= '0;
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threshold <= '0;
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end else if (req_i && we_i) begin
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case (addr_i[15:12])
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5'h0: begin // Priority registers
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if (addr_i[11:2] < SOURCES)
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priorities[addr_i[11:2]] <= wdata_i[PRIORITIES-1:0];
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end
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5'h2: begin // Enable registers
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if (addr_i[11:2] == 0)
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enables <= wdata_i[SOURCES-1:0];
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end
62+
5'h20: begin // Threshold and claim/complete region
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if (addr_i[3:2] == 0)
64+
threshold <= wdata_i[PRIORITIES-1:0];
65+
else if (addr_i[3:2] == 1) begin
66+
// Handle interrupt completion: clear pending bit for the given IRQ index
67+
if (wdata_i < SOURCES)
68+
pending[wdata_i] <= 1'b0;
69+
end
70+
end
71+
default: ;
72+
endcase
73+
end
74+
end
75+
76+
// ------------------------------
77+
// Read Handling
78+
// ------------------------------
79+
always_comb begin
80+
reg_rdata = '0;
81+
case (addr_i[15:12])
82+
5'h0: begin // Priority registers
83+
if (addr_i[11:2] < SOURCES)
84+
reg_rdata = {{(32-PRIORITIES){1'b0}}, priorities[addr_i[11:2]]};
85+
end
86+
5'h1: begin // Pending registers
87+
if (addr_i[11:2] == 0)
88+
reg_rdata = pending;
89+
end
90+
5'h2: begin // Enable registers
91+
if (addr_i[11:2] == 0)
92+
reg_rdata = enables;
93+
end
94+
5'h20: begin // Threshold and claim/complete region
95+
if (addr_i[3:2] == 0)
96+
reg_rdata = {{(32-PRIORITIES){1'b0}}, threshold};
97+
else if (addr_i[3:2] == 1)
98+
reg_rdata = claimed_irq;
99+
end
100+
default: reg_rdata = '0;
101+
endcase
102+
end
103+
104+
// ------------------------------
105+
// Interrupt Pending Update
106+
// ------------------------------
107+
always_ff @(posedge clk_i or negedge rst_ni) begin
108+
if (!rst_ni)
109+
pending <= '0;
110+
else begin
111+
for (int i = 0; i < SOURCES; i++) begin
112+
if (irq_sources_i[i] && enables[i])
113+
pending[i] <= 1'b1;
114+
end
115+
end
116+
end
117+
118+
// ------------------------------
119+
// Highest-Priority Pending Interrupt Logic
120+
// ------------------------------
121+
always_comb begin
122+
logic found_irq;
123+
logic [$clog2(SOURCES)-1:0] highest_irq;
124+
logic [PRIORITIES-1:0] highest_priority;
125+
126+
found_irq = 1'b0;
127+
highest_irq = '0;
128+
highest_priority = '0;
129+
130+
for (int i = 0; i < SOURCES; i++) begin
131+
if (pending[i] && enables[i] && (priorities[i] > threshold) &&
132+
(!found_irq || priorities[i] > highest_priority)) begin
133+
found_irq = 1'b1;
134+
highest_irq = i;
135+
highest_priority = priorities[i];
136+
end
137+
end
138+
139+
claimed_irq = highest_irq;
140+
irq_o = found_irq;
141+
end
142+
143+
assign irq_pending_o = pending;
144+
145+
// ------------------------------
146+
// Response Valid Signal
147+
// ------------------------------
148+
always_ff @(posedge clk_i or negedge rst_ni) begin
149+
if (!rst_ni)
150+
rvalid_o <= 1'b0;
151+
else
152+
rvalid_o <= req_i;
153+
end
154+
155+
assign rdata_o = reg_rdata;
156+
157+
endmodule

‎dv/verilator/top_verilator.sv

Lines changed: 66 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,23 @@
1-
// Copyright lowRISC contributors.
2-
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3-
// SPDX-License-Identifier: Apache-2.0
4-
5-
// This is the top level that connects the demo system to the virtual devices.
1+
// Corrected top level for Verilator simulation that connects the demo system to virtual devices
62
module top_verilator (input logic clk_i, rst_ni);
73

84
localparam ClockFrequency = 50_000_000;
95
localparam BaudRate = 115_200;
106

117
logic uart_sys_rx, uart_sys_tx;
8+
logic irq_external;
9+
logic [31:0] irq_sources;
10+
11+
// New signals for the updated PLIC DPI bus interface
12+
logic plic_req;
13+
logic [31:0] plic_addr;
14+
logic plic_we;
15+
logic [3:0] plic_be;
16+
logic [31:0] plic_wdata;
17+
logic plic_rvalid;
18+
logic [31:0] plic_rdata;
1219

13-
// Instantiating the Ibex Demo System.
20+
// Instantiate the Ibex Demo System
1421
ibex_demo_system #(
1522
.GpiWidth ( 8 ),
1623
.GpoWidth ( 16 ),
@@ -19,39 +26,80 @@ module top_verilator (input logic clk_i, rst_ni);
1926
.BaudRate ( BaudRate ),
2027
.RegFile ( ibex_pkg::RegFileFF )
2128
) u_ibex_demo_system (
22-
//Input
2329
.clk_sys_i (clk_i),
2430
.rst_sys_ni(rst_ni),
2531
.uart_rx_i (uart_sys_rx),
26-
27-
//Output
28-
.uart_tx_o(uart_sys_tx),
29-
30-
// tie off JTAG
32+
.uart_tx_o (uart_sys_tx),
33+
// Tie off JTAG
3134
.trst_ni(1'b1),
3235
.tms_i (1'b0),
3336
.tck_i (1'b0),
3437
.td_i (1'b0),
3538
.td_o ( ),
36-
37-
// Remaining IO
39+
// Remaining I/O (unused for this example)
3840
.gp_i (0),
3941
.gp_o ( ),
4042
.pwm_o ( ),
4143
.spi_rx_i (0),
4244
.spi_tx_o ( ),
4345
.spi_sck_o ( )
46+
// PLIC interface not directly connected to the demo system in this configuration
4447
);
4548

46-
// Virtual UART
49+
// Instantiate the Virtual UART
4750
uartdpi #(
4851
.BAUD(BaudRate),
4952
.FREQ(ClockFrequency)
5053
) u_uartdpi (
51-
.clk_i,
52-
.rst_ni,
53-
.active (1'b1 ),
54+
.clk_i(clk_i),
55+
.rst_ni(rst_ni),
56+
.active (1'b1),
5457
.tx_o (uart_sys_rx),
5558
.rx_i (uart_sys_tx)
5659
);
60+
61+
// Drive default values for the PLIC bus signals (no bus transactions in this testbench)
62+
assign plic_req = 1'b0;
63+
assign plic_addr = 32'b0;
64+
assign plic_we = 1'b0;
65+
assign plic_be = 4'b0;
66+
assign plic_wdata = 32'b0;
67+
68+
// Instantiate the corrected Virtual PLIC DPI module
69+
plicdpi #(
70+
.SOURCES(32),
71+
.TARGETS(1),
72+
.PRIORITIES(3)
73+
) u_plicdpi (
74+
.clk_i(clk_i),
75+
.rst_ni(rst_ni),
76+
.req_i(plic_req),
77+
.addr_i(plic_addr),
78+
.we_i(plic_we),
79+
.be_i(plic_be),
80+
.wdata_i(plic_wdata),
81+
.rvalid_o(plic_rvalid),
82+
.rdata_o(plic_rdata),
83+
.irq_sources_i(irq_sources),
84+
.irq_pending_o(), // Not used here
85+
.irq_o(irq_external) // External interrupt output
86+
);
87+
88+
// For testing, generate a timer interrupt on irq_sources[0]
89+
logic [31:0] timer_counter;
90+
always_ff @(posedge clk_i or negedge rst_ni) begin
91+
if (!rst_ni) begin
92+
timer_counter <= '0;
93+
irq_sources <= '0;
94+
end else begin
95+
timer_counter <= timer_counter + 1;
96+
if (timer_counter == 1000) begin
97+
timer_counter <= '0;
98+
irq_sources[0] <= 1'b1; // Set timer interrupt source
99+
end else begin
100+
irq_sources[0] <= 1'b0; // Clear timer interrupt source
101+
end
102+
end
103+
end
104+
57105
endmodule

‎ibex_demo_system.core

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,7 @@ filesets:
5353
- lowrisc:dv_dpi_sv:uartdpi:0.1
5454
files:
5555
- dv/verilator/top_verilator.sv: { file_type: systemVerilogSource }
56+
- dv/verilator/plicdpi.sv: { file_type: systemVerilogSource }
5657
- dv/verilator/ibex_demo_system.cc: { file_type: cppSource }
5758
- dv/verilator/ibex_demo_system.h: { file_type: cppSource, is_include_file: true}
5859
- dv/verilator/ibex_demo_system_main.cc: { file_type: cppSource }
@@ -178,10 +179,10 @@ targets:
178179
- '--trace-structs'
179180
- '--trace-params'
180181
- '--trace-max-array 1024'
181-
- '-CFLAGS "-std=c++14 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=top_verilator"'
182+
- '-CFLAGS "-std=c++14 -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=top_verilator"'
182183
- '-LDFLAGS "-pthread -lutil -lelf"'
183-
- "-Wall"
184-
- "-Wwarn-IMPERFECTSCH"
184+
# - "-Wall"
185+
# - "-Wwarn-IMPERFECTSCH"
185186
# RAM primitives wider than 64bit (required for ECC) fail to build in
186187
# Verilator without increasing the unroll count (see Verilator#1266)
187188
- "--unroll-count 72"

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