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lerwyslerwys
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Merge branch 'devel'
2 parents c63e829 + 4d1d059 commit 21fab0b

3 files changed

Lines changed: 71 additions & 38 deletions

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‎hdl/modules/position_calc/position_calc.vhd‎

Lines changed: 60 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -400,6 +400,9 @@ architecture rtl of position_calc is
400400
signal tbt_x_pre, tbt_y_pre, tbt_q_pre, tbt_sum_pre :
401401
std_logic_vector(g_tbt_decim_width-1 downto 0) := (others => '0');
402402

403+
signal monit1_pos_x_int, monit1_pos_y_int, monit1_pos_q_int, monit1_pos_sum_int :
404+
std_logic_vector(g_monit_decim_width-1 downto 0) := (others => '0');
405+
403406
signal monit_x_pre, monit_y_pre, monit_q_pre, monit_sum_pre :
404407
std_logic_vector(g_monit_decim_width-1 downto 0) := (others => '0');
405408

@@ -422,7 +425,7 @@ architecture rtl of position_calc is
422425
signal valid_tbt, valid_tbt_cordic, valid_fofb, valid_fofb_cordic, valid_monit1, valid_monit2 : ce_sl := (others => '0');
423426
signal ce_adc, ce_monit1, ce_monit2, ce_tbt_cordic, ce_fofb_cordic : ce_sl := (others => '0');
424427

425-
signal valid_fofb_ds, valid_tbt_ds : std_logic;
428+
signal valid_monit1_ds, valid_fofb_ds, valid_tbt_ds : std_logic;
426429

427430
attribute max_fanout : string;
428431
attribute max_fanout of ce_adc, ce_monit1, ce_monit2 : signal is "50";
@@ -798,28 +801,58 @@ begin
798801
-- fractional length = g_width - (integer length)
799802
cmp_fofb_ds : delta_sigma
800803
generic map (
801-
g_width => g_fofb_decim_width,
802-
g_k_width => g_k_width,
804+
g_width => g_fofb_decim_width,
805+
g_k_width => g_k_width,
806+
g_offset_width => g_offset_width)
807+
port map (
808+
a_i => fofb_mag(0),
809+
b_i => fofb_mag(1),
810+
c_i => fofb_mag(2),
811+
d_i => fofb_mag(3),
812+
kx_i => kx_i,
813+
ky_i => ky_i,
814+
ksum_i => ksum_i,
815+
offset_x_i => offset_x_i,
816+
offset_y_i => offset_y_i,
817+
clk_i => clk_i,
818+
ce_i => ce_fofb_cordic(0),
819+
valid_i => valid_fofb_cordic(0),
820+
valid_o => valid_fofb_ds,
821+
rst_i => rst_i,
822+
x_o => fofb_pos_x_int,
823+
y_o => fofb_pos_y_int,
824+
q_o => fofb_pos_q_int,
825+
sum_o => fofb_pos_sum_int);
826+
827+
-- x, y, and q are fixed point with:
828+
-- sign bit = MSB
829+
-- word length = g_width
830+
-- integer length = g_k_width + 1
831+
-- fractional length = g_width - (integer length)
832+
cmp_monit1_ds : delta_sigma
833+
generic map (
834+
g_width => g_monit_decim_width,
835+
g_k_width => g_k_width,
803836
g_offset_width => g_offset_width)
804837
port map (
805-
a_i => fofb_mag(0),
806-
b_i => fofb_mag(1),
807-
c_i => fofb_mag(2),
808-
d_i => fofb_mag(3),
809-
kx_i => kx_i,
810-
ky_i => ky_i,
811-
ksum_i => ksum_i,
812-
offset_x_i => offset_x_i,
813-
offset_y_i => offset_y_i,
814-
clk_i => clk_i,
815-
ce_i => ce_fofb_cordic(0),
816-
valid_i => valid_fofb_cordic(0),
817-
valid_o => valid_fofb_ds,
818-
rst_i => rst_i,
819-
x_o => fofb_pos_x_int,
820-
y_o => fofb_pos_y_int,
821-
q_o => fofb_pos_q_int,
822-
sum_o => fofb_pos_sum_int);
838+
a_i => monit1_mag(0),
839+
b_i => monit1_mag(1),
840+
c_i => monit1_mag(2),
841+
d_i => monit1_mag(3),
842+
kx_i => kx_i,
843+
ky_i => ky_i,
844+
ksum_i => ksum_i,
845+
offset_x_i => offset_x_i,
846+
offset_y_i => offset_y_i,
847+
clk_i => clk_i,
848+
ce_i => ce_monit1(0),
849+
valid_i => valid_monit1(0),
850+
valid_o => valid_monit1_ds,
851+
rst_i => rst_i,
852+
x_o => monit1_pos_x_int,
853+
y_o => monit1_pos_y_int,
854+
q_o => monit1_pos_q_int,
855+
sum_o => monit1_pos_sum_int);
823856

824857
-- desync counters. Use only one of the channels as a sample
825858
tbt_tag_desync_cnt_o <= tbt_tag_desync_cnt(0);
@@ -921,13 +954,13 @@ begin
921954
tbt_pos_q_o <= (others => '0');
922955
tbt_pos_sum_o <= (others => '0');
923956

924-
monit1_pos_valid_o <= '0';
925-
monit1_pos_ce_o <= '0';
957+
monit1_pos_valid_o <= valid_monit1_ds;
958+
monit1_pos_ce_o <= ce_monit1(0);
926959

927-
monit1_pos_x_o <= (others => '0');
928-
monit1_pos_y_o <= (others => '0');
929-
monit1_pos_q_o <= (others => '0');
930-
monit1_pos_sum_o <= (others => '0');
960+
monit1_pos_x_o <= std_logic_vector(shift_right(signed(monit1_pos_x_int), g_monit_decim_width-g_k_width));
961+
monit1_pos_y_o <= std_logic_vector(shift_right(signed(monit1_pos_y_int), g_monit_decim_width-g_k_width));
962+
monit1_pos_q_o <= std_logic_vector(shift_right(signed(monit1_pos_q_int), g_monit_decim_width-g_k_width));
963+
monit1_pos_sum_o <= monit1_pos_sum_int;
931964

932965
monit_pos_valid_o <= '0';
933966
monit_pos_ce_o <= '0';

‎hdl/modules/wb_position_calc/wb_position_calc_core.vhd‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2375,7 +2375,7 @@ begin
23752375
monit1_pos_y_o <= fifo_monit1_pos_out(2*g_monit_decim_width-1 downto g_monit_decim_width);
23762376
monit1_pos_x_o <= fifo_monit1_pos_out(g_monit_decim_width-1 downto 0);
23772377

2378-
monit1_pos_valid_o <= fifo_monit_pos_valid_out;
2378+
monit1_pos_valid_o <= fifo_monit1_pos_valid_out;
23792379

23802380
p_reg_monit1_pos_sync_wb : process(clk_i)
23812381
begin

‎hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4285,11 +4285,11 @@ begin
42854285
adc_ds_tag_i => dsp1_adc_tag,
42864286
adc_ds_swap_valid_i => dsp1_adc_valid,
42874287

4288-
decim_ds_pos_x_i => dsp1_fofb_pos_x,
4289-
decim_ds_pos_y_i => dsp1_fofb_pos_y,
4290-
decim_ds_pos_q_i => dsp1_fofb_pos_q,
4291-
decim_ds_pos_sum_i => dsp1_fofb_pos_sum,
4292-
decim_ds_pos_valid_i => dsp1_fofb_pos_valid,
4288+
decim_ds_pos_x_i => dsp1_monit1_pos_x,
4289+
decim_ds_pos_y_i => dsp1_monit1_pos_y,
4290+
decim_ds_pos_q_i => dsp1_monit1_pos_q,
4291+
decim_ds_pos_sum_i => dsp1_monit1_pos_sum,
4292+
decim_ds_pos_valid_i => dsp1_monit1_pos_valid,
42934293

42944294
-----------------------------
42954295
-- Upstream ADC and position signals
@@ -4304,11 +4304,11 @@ begin
43044304
adc_us_tag_i => dsp2_adc_tag,
43054305
adc_us_swap_valid_i => dsp2_adc_valid,
43064306

4307-
decim_us_pos_x_i => dsp2_fofb_pos_x,
4308-
decim_us_pos_y_i => dsp2_fofb_pos_y,
4309-
decim_us_pos_q_i => dsp2_fofb_pos_q,
4310-
decim_us_pos_sum_i => dsp2_fofb_pos_sum,
4311-
decim_us_pos_valid_i => dsp2_fofb_pos_valid,
4307+
decim_us_pos_x_i => dsp2_monit1_pos_x,
4308+
decim_us_pos_y_i => dsp2_monit1_pos_y,
4309+
decim_us_pos_q_i => dsp2_monit1_pos_q,
4310+
decim_us_pos_sum_i => dsp2_monit1_pos_sum,
4311+
decim_us_pos_valid_i => dsp2_monit1_pos_valid,
43124312

43134313
-----------------------------
43144314
-- Interlock outputs

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