Search results

[ISel/RISCV] Modernize loops (NFC)

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 147281

#147281 In llvm/llvm-project;

· artagnon opened on Jul 7, 2025

[RISCV] Add compress patterns for Xqcilia instructions with tied-operands

backend:RISC-V

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 147242

#147242 In llvm/llvm-project;

· svs-quic opened on Jul 7, 2025

MC: Store MCRelaxableFragment MCInst out-of-line

backend:AMDGPU

backend:ARM

backend:CSKY

backend:Hexagon

backend:m68k

backend:RISC-V

backend:X86

backend:Xtensa

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 147229

#147229 In llvm/llvm-project;

· MaskRay opened on Jul 7, 2025

[RISCV] Correct type lowering of struct of fixed-vector array in VLS

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.

Status: Open (in progress).

llvm/llvm-projectnumber 147173

#147173 In llvm/llvm-project;

· 4vtomat opened on Jul 6, 2025

MC: Centralize X86 PC-relative fixup adjustment in MCAssembler

backend:RISC-V

backend:X86

BOLT

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 147113

#147113 In llvm/llvm-project;

· MaskRay opened on Jul 4, 2025

[RISCV] Don't increase vslide or splat vl if +minimize-vl is present

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 147089

#147089 In llvm/llvm-project;

· lukel97 opened on Jul 4, 2025

[RISCV] Implement Clang Builtins for XAndesPerf Extension

backend:RISC-V

backend:X86

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.

clang:frontendLanguage frontend issues, e.g. anything involving "Sema"Language frontend issues, e.g. anything involving "Sema"

clang:headersHeaders provided by Clang, e.g. for intrinsicsHeaders provided by Clang, e.g. for intrinsics

llvm:ir

Status: Open (in progress).

llvm/llvm-projectnumber 147018

#147018 In llvm/llvm-project;

· tclin914 opened on Jul 4, 2025

[RISCV][CodeGen] Add CodeGen support of Zibi experimental extension

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:driver'clang' and 'clang++' user-facing binaries. Not 'clang-cl''clang' and 'clang++' user-facing binaries. Not 'clang-cl'

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 146858

#146858 In llvm/llvm-project;

· BoyaoWang430 opened on Jul 3, 2025

[RISCV] AddEdge between first mask producer and user of V0

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 146855

#146855 In llvm/llvm-project;

· ChunyuLiao opened on Jul 3, 2025

[RISCV][TTI] Model partial reduce of ext for zvqdotq

backend:RISC-V

llvm:transforms

Status: Open (in progress).

llvm/llvm-projectnumber 146788

#146788 In llvm/llvm-project;

· preames opened on Jul 2, 2025

[RISCV] Avoid vl toggles when lowering vector_splice/experimental_vp_splice and add +minimize-vl tuning feature

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 146746

#146746 In llvm/llvm-project;

· lukel97 opened on Jul 2, 2025

[RISCV] Add ISel patterns for Qualcomm uC Xqcics extension

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 146675

#146675 In llvm/llvm-project;

· hchandel opened on Jul 2, 2025