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[LoongArch] Incorrect register allocation for [G]CSRXCHG - rj must not be R0 ro R1 #140842

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heiher opened this issue May 21, 2025 · 1 comment · Fixed by #140862
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[LoongArch] Incorrect register allocation for [G]CSRXCHG - rj must not be R0 ro R1 #140842

heiher opened this issue May 21, 2025 · 1 comment · Fixed by #140862
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backend:loongarch miscompilation

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@heiher
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heiher commented May 21, 2025 •
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In the LoongArch target, the [G]CSRXCHG instruction has a special encoding constraint:

If the rj operand is assigned to register R0 or R1, the instruction encoding will be interpreted as [G]CSRRD or [G]CSRWR respectively, not [G]CSRXCHG.

Currently, LLVM’s register allocator may assign R0 or R1 to the rj operand of a [G]CSRXCHG instruction, which leads to incorrect code generation and unintended semantics.

Reproduce case:

declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg);

define dso_local i64 @csrxchg() {
entry:
  %0 = tail call i64 asm sideeffect "", "=r,r,i,{$r4},{$r5},{$r6},{$r7},{$r8},{$r9},{$r10},{$r11},{$r12},{$r13},{$r14},{$r15},{$r16},{$r17},{$r18},{$r19},{$r20},{$r23},{$r24},{$r25},{$r26},{$r27},{$r28},{$r29},{$r30},{$r31},0,~{memory}"(i32 4, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i64 0)
  %1 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %0, i64 4, i32 0)
  %2 = tail call i64 asm sideeffect "", "=r,r,i,{$r4},{$r5},{$r6},{$r7},{$r8},{$r9},{$r10},{$r11},{$r12},{$r13},{$r14},{$r15},{$r16},{$r17},{$r18},{$r19},{$r20},{$r23},{$r24},{$r25},{$r26},{$r27},{$r28},{$r29},{$r30},{$r31},0,~{memory}"(i32 4, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i64 %1)
  ret i64 %2
}
@llvmbot
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llvmbot commented May 21, 2025

@llvm/issue-subscribers-backend-loongarch

Author: hev (heiher)

In the LoongArch target, the `{G}CSRXCHG` instruction has a special encoding constraint:

If the rj operand is assigned to register R0 or R1, the instruction encoding will be interpreted as {G}CSRRD or {G}CSRWR respectively, not {G}CSRXCHG.

Currently, LLVM’s register allocator may assign R0 or R1 to the rj operand of a {G}CSRXCHG instruction, which leads to incorrect code generation and unintended semantics.

Reproduce case:

declare i64 @<!-- -->llvm.loongarch.csrxchg.d(i64, i64, i32 immarg);

define dso_local i64 @<!-- -->csrxchg() {
entry:
  %0 = tail call i64 asm sideeffect "", "=r,r,i,{$r4},{$r5},{$r6},{$r7},{$r8},{$r9},{$r10},{$r11},{$r12},{$r13},{$r14},{$r15},{$r16},{$r17},{$r18},{$r19},{$r20},{$r23},{$r24},{$r25},{$r26},{$r27},{$r28},{$r29},{$r30},{$r31},0,~{memory}"(i32 4, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i64 0)
  %1 = tail call i64 @<!-- -->llvm.loongarch.csrxchg.d(i64 %0, i64 4, i32 0)
  %2 = tail call i64 asm sideeffect "", "=r,r,i,{$r4},{$r5},{$r6},{$r7},{$r8},{$r9},{$r10},{$r11},{$r12},{$r13},{$r14},{$r15},{$r16},{$r17},{$r18},{$r19},{$r20},{$r23},{$r24},{$r25},{$r26},{$r27},{$r28},{$r29},{$r30},{$r31},0,~{memory}"(i32 4, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i64 %1)
  ret i64 %2
}

@heiher heiher self-assigned this May 21, 2025
heiher added a commit to heiher/llvm-project that referenced this issue May 21, 2025
@heiher
[LoongArch] Prevent R0/R1 allocation for rj operand of {G}CSRXCHG
02bc62c 
The {G}CSRXCHG instruction must not use R0 or R1 as the rj operand, as
encoding rj as 0 or 1 will be interpreted as {G}CSRRD OR {G}CSRWR,
respectively, rather than {G}CSRXCHG.

This patch introduces a new register class `GPRNoR0R1` and updates the
{G}CSRXCHG instruction definition to use it for the rj operand, ensuring
the register allocator avoids assigning R0 or R1.

Fixes llvm#140842
@heiher heiher mentioned this issue May 21, 2025
Merged
@heiher heiher changed the title [LoongArch] Incorrect register allocation for {G}CSRXCHG - rj must not be R0 ro R1 [LoongArch] Incorrect register allocation for [G]CSRXCHG - rj must not be R0 ro R1 May 22, 2025
heiher added a commit that referenced this issue May 22, 2025
@heiher
[LoongArch] Prevent R0/R1 allocation for rj operand of [G]CSRXCHG (#1…
bd8578c 
…40862)

The `[G]CSRXCHG` instruction must not use R0 or R1 as the `rj` operand,
as encoding `rj` as 0 or 1 will be interpreted as `[G]CSRRD` OR
`[G]CSRWR`, respectively, rather than `[G]CSRXCHG`.

This patch introduces a new register class `GPRNoR0R1` and updates the
`[G]CSRXCHG` instruction definition to use it for the `rj` operand,
ensuring the register allocator avoids assigning R0 or R1.

Fixes #140842
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[LoongArch] Prevent R0/R1 allocation for rj operand of [G]CSRXCHG heiher/llvm-project
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