Commit 3fd53f7
committed
update submodules
update submodules
Signed-off-by: Fin Maaß <[email protected]>1 parent be2af1e commit 3fd53f7
8 files changed
+8
-8
lines changed- liteeth/mac/core.py+136-36
- liteeth/mac/crc.py+117-4
- liteeth/mac/sram.py+12-11
- liteeth/phy/rmii.py+13
- liteeth/phy/titanium_lvds_1000basex.py+327-277
- liteeth/phy/titaniumrgmii.py+52-53
- liteeth/phy/trionrgmii.py+14-107
- setup.py+1-1
- test/test_1000basex.py+8-8
- test/test_crc.py+114
- test/test_packet.py+1-11
- test/test_stream.py+11
- CHANGES.md+143
- litex/build/altera/common.py+172-35
- litex/build/altera/platform.py+1-1
- litex/build/altera/quartus.py+18-7
- litex/build/colognechip/common.py+58-16
- litex/build/colognechip/peppercorn.py-1
- litex/build/efinix/common.py+224-28
- litex/build/efinix/dbparser.py+12-4
- litex/build/efinix/ifacewriter.py+13-19
- litex/build/generic_platform.py+2-1
- litex/build/generic_toolchain.py+1-1
- litex/build/gowin/common.py+5-2
- litex/build/gowin/gowin.py+1-3
- litex/build/io.py+35-21
- litex/build/lattice/common.py+38-2
- litex/build/lattice/radiant.py+8-2
- litex/build/lattice/trellis.py+5-1
- litex/build/sim/core/Makefile+4-2
- litex/build/sim/core/modules/clocker/clocker.c+1-1
- litex/build/sim/core/modules/spdeeprom/spdeeprom.c+2-2
- litex/build/sim/core/veril.cpp+47-1
- litex/build/sim/core/veril.h+1-1
- litex/build/sim/verilator.py+19-9
- litex/build/vhd2v_converter.py+13-2
- litex/build/xilinx/common.py+8-5
- litex/build/xilinx/platform.py+4-2
- litex/build/xilinx/vivado.py+65-4
- litex/gen/fhdl/memory.py+29-20
- litex/soc/cores/clock/__init__.py+4
- litex/soc/cores/clock/efinix.py+23-17
- litex/soc/cores/clock/intel_agilex.py+428
- litex/soc/cores/code_8b10b.py+7-4
- litex/soc/cores/cpu/coreblocks/core.py+38-9
- litex/soc/cores/cpu/naxriscv/core.py+2-2
- litex/soc/cores/cpu/vexiiriscv/core.py+8-2
- litex/soc/cores/cpu/vexiiriscv/system.h+40-1
- litex/soc/cores/cpu/zynq7000/core.py+298-3
- litex/soc/cores/prbs.py+8-9
- litex/soc/cores/ram/efinix_hyperram.py+26-12
- litex/soc/cores/uart.py+3-3
- litex/soc/cores/video.py+8-3
- litex/soc/doc/__init__.py+2-1
- litex/soc/doc/csr.py+10-6
- litex/soc/integration/builder.py+1
- litex/soc/integration/export.py+15-11
- litex/soc/integration/soc.py+122-93
- litex/soc/integration/soc_core.py+3-2
- litex/soc/interconnect/ahb.py+3-1
- litex/soc/interconnect/axi/axi_common.py+48-4
- litex/soc/interconnect/axi/axi_full.py+10-5
- litex/soc/interconnect/axi/axi_lite.py+91-54
- litex/soc/interconnect/wishbone.py+14-4
- litex/soc/software/bios/boot.c+11-6
- litex/soc/software/bios/boot.h+7
- litex/soc/software/bios/cmds/cmd_bios.c+1-1
- litex/soc/software/bios/cmds/cmd_boot.c+1-1
- litex/soc/software/bios/cmds/cmd_liteeth.c+20
- litex/soc/software/bios/cmds/cmd_litesdcard.c+5-5
- litex/soc/software/bios/main.c+9-2
- litex/soc/software/bios/readline.c+19-4
- litex/soc/software/bios/readline.h+3
- litex/soc/software/bios/readline_simple.c+15
- litex/soc/software/include/hw/common.h+29-18
- litex/soc/software/include/system.h+33
- litex/soc/software/libbase/isr.c+2
- litex/soc/software/libbase/memtest.c+5-5
- litex/soc/software/libbase/uart.c+14-8
- litex/soc/software/liblitedram/sdram.c+11-11
- litex/soc/software/libliteeth/udp.c+191-5
- litex/soc/software/libliteeth/udp.h+2
- litex/soc/software/liblitesdcard/sdcard.c+38-37
- litex/soc/software/liblitesdcard/sdcard.h+7-2
- litex/soc/software/liblitespi/spiflash.c+13-4
- litex/soc/software/liblitespi/spiram.c+2-2
- litex/tools/litex_json2dts_linux.py+18-14
- litex/tools/litex_json2dts_zephyr.py+3-28
- litex/tools/litex_sim.py+8-7
- litex/tools/litex_term.py+6-3
- litex/tools/remote/comm_pcie.py+25-10
- litex_setup.py+80-14
- setup.py+1-1
Submodule litex-boards updated 77 files
- .github/workflows/ci.yml+3-3
- CONTRIBUTORS+20-4
- LICENSE+1-1
- README.md+13-3
- litex_boards/platforms/alibaba_vu13p.py+427
- litex_boards/platforms/aliexpress_xc7k70t.py+2-2
- litex_boards/platforms/alinx_ax7010.py+7-5
- litex_boards/platforms/alinx_ax7020.py+130
- litex_boards/platforms/alinx_ax7203.py+151
- litex_boards/platforms/arrow_axe5000.py+178
- litex_boards/platforms/berkeleylab_marble.py+9-8
- litex_boards/platforms/berkeleylab_obsidian.py+247
- litex_boards/platforms/bochenjingxin_kintex7_basec.py+68
- litex_boards/platforms/colognechip_gatemate_evb.py+21-4
- litex_boards/platforms/colorlight_5a_75b.py+4-4
- litex_boards/platforms/colorlight_5a_75e.py+110-4
- litex_boards/platforms/digilent_nexys_video.py+19
- litex_boards/platforms/efinix_ti375_c529_dev_kit.py+90-1
- litex_boards/platforms/efinix_tz170_j484_dev_kit.py+224
- litex_boards/platforms/hyvision_pcie_opt01_revf.py+210
- litex_boards/platforms/icepi_zero.py+143
- litex_boards/platforms/intergalaktik_ulx5m_gs.py+107
- litex_boards/platforms/lckfb_ljpi.py+180
- litex_boards/platforms/machdyne_kolsch.py+100
- litex_boards/platforms/marble.py-347
- litex_boards/platforms/marblemini.py-273
- litex_boards/platforms/mlkpai_fs01_dr1v90m.py+64
- litex_boards/platforms/myir_myc_j7a100t.py+279
- litex_boards/platforms/olimex_gatemate_a1_evb.py+21
- litex_boards/platforms/puzhi_pz_a7xxt_kfb.py+313
- litex_boards/platforms/qmtech_cyclone10_starterkit.py+234
- litex_boards/platforms/qmtech_xc7k325t.py+2-2
- litex_boards/platforms/radiona_ulx3s.py+2-2
- litex_boards/platforms/radiona_ulx4m_ls_v2.py+365
- litex_boards/platforms/sipeed_tang_console.py+333
- litex_boards/platforms/sipeed_tang_nano_20k.py+30-1
- litex_boards/platforms/sqrl_acorn.py+9-4
- litex_boards/platforms/xilinx_kcu116.py+354
- litex_boards/platforms/xilinx_zcu106.py+1-1
- litex_boards/platforms/ypcb_00338_1p1.py+205
- litex_boards/targets/alibaba_vu13p.py+224
- litex_boards/targets/alinx_ax7010.py+3-1
- litex_boards/targets/alinx_ax7020.py+113
- litex_boards/targets/alinx_ax7203.py+172
- litex_boards/targets/arrow_axe5000.py+149
- litex_boards/targets/berkeleylab_marble.py+8-6
- litex_boards/targets/berkeleylab_obsidian.py+255
- litex_boards/targets/bochenjingxin_kintex7_basec.py+80
- litex_boards/targets/colognechip_gatemate_evb.py+66-5
- litex_boards/targets/colorlight_5a_75x.py+2-2
- litex_boards/targets/digilent_genesys2.py+3-2
- litex_boards/targets/digilent_nexys_video.py+30
- litex_boards/targets/digilent_zedboard.py+12-3
- litex_boards/targets/efinix_ti375_c529_dev_kit.py+311-392
- litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py+6
- litex_boards/targets/efinix_tz170_j484_dev_kit.py+326
- litex_boards/targets/hyvision_pcie_opt01_revf.py+175
- litex_boards/targets/icepi_zero.py+186
- litex_boards/targets/intergalaktik_ulx5m_gs.py+122
- litex_boards/targets/lattice_certuspro_nx_versa.py+126
- litex_boards/targets/lckfb_ljpi.py+204
- litex_boards/targets/litex_acorn_baseboard_mini.py+8-19
- litex_boards/targets/machdyne_kolsch.py+171
- litex_boards/targets/mlkpai_fs01_dr1v90m.py+78
- litex_boards/targets/myir_myc_j7a100t.py+176
- litex_boards/targets/olimex_gatemate_a1_evb.py+58-2
- litex_boards/targets/puzhi_pz_a7xxt_kfb.py+242
- litex_boards/targets/qmtech_cyclone10_starterkit.py+133
- litex_boards/targets/radiona_ulx4m_ls_v2.py+262
- litex_boards/targets/sipeed_tang_console.py+246
- litex_boards/targets/sipeed_tang_mega_138k_pro.py+22-1
- litex_boards/targets/sipeed_tang_nano_20k.py+46-3
- litex_boards/targets/trenz_te0890.py
- litex_boards/targets/xilinx_kcu116.py+192
- litex_boards/targets/ypcb_00338_1p1.py+142
- setup.py+1-1
- test/test_targets.py+2
0 commit comments