pads are not driven in simulation

[betz-engineering]

Hi,

I ran into this problem trying to simulate the LiteSPISDRPHYCore in the Python simulator.

Here is a minimal example

from litex.gen import LiteXModule, Record, run_simulation
from litespi.phy.generic import LiteSPISDRPHYCore


class SdrIoBug(LiteXModule):
    def __init__(self):
        self.pads = Record([("clk", 1), ("cs_n", 1), ("mosi", 1), ("miso", 1)])
        self.phy = LiteSPISDRPHYCore(
            pads=self.pads,
            flash=None,
            device=None,
            clock_domain="sys",
            default_divisor=1,
            cs_delay=1,
        )


def dut_gen(dut):
    yield dut.phy.cs.eq(1)
    yield dut.phy.sink.data.eq(0xF1)
    yield dut.phy.sink.len.eq(8)
    yield dut.phy.sink.width.eq(1)
    yield dut.phy.sink.mask.eq(1)
    yield dut.phy.sink.valid.eq(1)
    yield

    print("cs_n, clk, mosi")
    while not (yield dut.phy.sink.ready):
        yield
        print((yield dut.pads.cs_n), (yield dut.pads.clk), (yield dut.pads.mosi))

    yield dut.phy.cs.eq(0)
    yield
    yield


if __name__ == "__main__":
    dut = SdrIoBug()
    tb = dut_gen(dut)
    run_simulation(dut, tb, vcd_name="sdr_io_bug.vcd")

Output

python sdr_io_bug.py 
cs_n, clk, mosi
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0

I would have expected the printed values of dut.pads.* to change.

If I open the .vcd file, I see the expected waveforms inside the PHY (the clk, cs_n and dq_o signals). But after passing through the SDROutput module, I only get zeros on all pads_* signals.

Changing the following in litex/build/io.py seems to fix it, but with potential serious side effects when more than one clock domain is present.

class InferedSDRIO(Module):
    def __init__(self, i, o, clk):
        self.sync += o.eq(i)

Any hints appreciated :)

My litex version is commit 9a52a3a4 (Wed Feb 11 11:43:26 2026 +0100)

As a background info, I'm trying to communicate with 2 SPI devices (IO extender and a OLED display) with shared clock and data-lines. Maybe I'm mis-using litespi, which seems to be primarily targeted at flash chips, but the crossbar interface is a very nice fit for my use-case.

All the best,
Michael