Add DDR support for Fomu

[tcal-x]

I tried getting DDR SPI on Fomu by editing https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/kosagi_fomu.py:

-        self.add_spi_flash(mode="4x", module=spi_flash_modules[spi_flash_module](), with_master=False)
+        self.add_spi_flash(mode="4x", module=spi_flash_modules[spi_flash_module](), with_master=False, rate='1:2')

The build attempt gave me the error

Info: Placed 14 cells based on constraints.
ERROR: Unable to find a placement location for cell 'SB_IO_13'
0 warnings, 1 error

Looking at the generated SoC rtl build/kosagi_fomu_pvt/gateware/kosagi_fomu_pvt.v I saw this pattern:

SB_IO #(
        .IO_STANDARD("SB_LVCMOS"),
        .PIN_TYPE(6'd0)
) SB_IO_13 (
        .CLOCK_ENABLE(1'd1),
        .INPUT_CLK(sys_clk),
        .PACKAGE_PIN(builder_inferedddrtristate2__i),
        .D_IN_0(main_basesoc_litespiddrphycore2[2]),
        .D_IN_1(main_basesoc_litespiddrphycore3[2])
);

SB_IO #(
        .PIN_TYPE(6'd41)
) SB_IO_14 (
        .D_OUT_0(builder_inferedddrtristate2__o),
        .OUTPUT_ENABLE(builder_inferedddrtristate2_oe),
        .PACKAGE_PIN(spiflash4x_dq[2]),
        .D_IN_0(builder_inferedddrtristate2__i)
);

These two IOs are connected by wire builder_inferedddrtristate2__i. I suspect this is not quite correct, in particular the connection to PACKAGE_PIN of the first IO.