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UefiCpuPkg/CpuCacheInfoLib: Collect cache associative type
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3265 Support collecting cache associative type in CpuCacheInfoLib. This prevents the user from using additional code to obtain the same information. Signed-off-by: Jason Lou <[email protected]> Reviewed-by: Ray Ni <[email protected]> Reviewed-by: Eric Dong <[email protected]> Cc: Laszlo Ersek <[email protected]> Cc: Rahul Kumar <[email protected]>
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‎UefiCpuPkg/Include/Library/CpuCacheInfoLib.h

+13-2
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/** @file
22
Header file for CPU Cache info Library.
33
4-
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
4+
Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
55
SPDX-License-Identifier: BSD-2-Clause-Patent
66
77
**/
@@ -33,7 +33,18 @@ typedef struct {
3333
// Ways of associativity.
3434
// Value = CPUID.04h:EBX[31:22]
3535
//
36-
UINT16 CacheWays;
36+
UINT16 CacheWays : 10;
37+
//
38+
// Fully associative cache.
39+
// Value = CPUID.04h:EAX[09]
40+
//
41+
UINT16 FullyAssociativeCache : 1;
42+
//
43+
// Direct mapped cache.
44+
// Value = CPUID.04h:EDX[02]
45+
//
46+
UINT16 DirectMappedCache : 1;
47+
UINT16 Reserved : 4;
3748
//
3849
// Size of single cache that this package's this type of logical processor corresponds to.
3950
// Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) *

‎UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c

+27-22
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/** @file
22
Provides cache info for each package, core type, cache level and cache type.
33
4-
Copyright (c) 2020 Intel Corporation. All rights reserved.<BR>
4+
Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
55
SPDX-License-Identifier: BSD-2-Clause-Patent
66
77
**/
@@ -23,18 +23,18 @@ CpuCacheInfoPrintCpuCacheInfoTable (
2323
{
2424
UINTN Index;
2525

26-
DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------------------------------+\n"));
27-
DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType CacheWays CacheSizeinKB CacheCount |\n"));
28-
DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------------------------------+\n"));
26+
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
27+
DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType CacheWays (FA|DM) CacheSizeinKB CacheCount |\n"));
28+
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
2929

3030
for (Index = 0; Index < CpuCacheInfoCount; Index++) {
31-
DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x %4x %8x %4x |\n", Index,
32-
CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel,
33-
CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].CacheSizeinKB,
34-
CpuCacheInfo[Index].CacheCount));
31+
DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n",
32+
Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel,
33+
CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].FullyAssociativeCache,
34+
CpuCacheInfo[Index].DirectMappedCache, CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount));
3535
}
3636

37-
DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------------------------------+\n"));
37+
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
3838
}
3939

4040
/**
@@ -160,6 +160,7 @@ CpuCacheInfoCollectCoreAndCacheData (
160160
CPUID_CACHE_PARAMS_EAX CacheParamEax;
161161
CPUID_CACHE_PARAMS_EBX CacheParamEbx;
162162
UINT32 CacheParamEcx;
163+
CPUID_CACHE_PARAMS_EDX CacheParamEdx;
163164
CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax;
164165
COLLECT_CPUID_CACHE_DATA_CONTEXT *Context;
165166
CPUID_CACHE_DATA *CacheData;
@@ -185,17 +186,19 @@ CpuCacheInfoCollectCoreAndCacheData (
185186
CacheParamLeafIndex = 0;
186187

187188
while (CacheParamLeafIndex < MAX_NUM_OF_CACHE_PARAMS_LEAF) {
188-
AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex, &CacheParamEax.Uint32, &CacheParamEbx.Uint32, &CacheParamEcx, NULL);
189+
AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex, &CacheParamEax.Uint32, &CacheParamEbx.Uint32, &CacheParamEcx, &CacheParamEdx.Uint32);
189190

190191
if (CacheParamEax.Bits.CacheType == 0) {
191192
break;
192193
}
193194

194-
CacheData[CacheParamLeafIndex].CacheLevel = (UINT8)CacheParamEax.Bits.CacheLevel;
195-
CacheData[CacheParamLeafIndex].CacheType = (UINT8)CacheParamEax.Bits.CacheType;
196-
CacheData[CacheParamLeafIndex].CacheWays = (UINT16)CacheParamEbx.Bits.Ways;
197-
CacheData[CacheParamLeafIndex].CacheShareBits = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;
198-
CacheData[CacheParamLeafIndex].CacheSizeinKB = (CacheParamEbx.Bits.Ways + 1) *
195+
CacheData[CacheParamLeafIndex].CacheLevel = (UINT8)CacheParamEax.Bits.CacheLevel;
196+
CacheData[CacheParamLeafIndex].CacheType = (UINT8)CacheParamEax.Bits.CacheType;
197+
CacheData[CacheParamLeafIndex].CacheWays = (UINT16)CacheParamEbx.Bits.Ways;
198+
CacheData[CacheParamLeafIndex].FullyAssociativeCache = (UINT8)CacheParamEax.Bits.FullyAssociativeCache;
199+
CacheData[CacheParamLeafIndex].DirectMappedCache = (UINT8)CacheParamEdx.Bits.ComplexCacheIndexing;
200+
CacheData[CacheParamLeafIndex].CacheShareBits = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;
201+
CacheData[CacheParamLeafIndex].CacheSizeinKB = (CacheParamEbx.Bits.Ways + 1) *
199202
(CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB;
200203

201204
CacheParamLeafIndex++;
@@ -305,13 +308,15 @@ CpuCacheInfoCollectCpuCacheInfoData (
305308
if (CacheInfoIndex == LocalCacheInfoCount) {
306309
ASSERT (LocalCacheInfoCount < MaxCacheInfoCount);
307310

308-
LocalCacheInfo[LocalCacheInfoCount].Package = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package;
309-
LocalCacheInfo[LocalCacheInfoCount].CoreType = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType;
310-
LocalCacheInfo[LocalCacheInfoCount].CacheLevel = CacheData[Index].CacheLevel;
311-
LocalCacheInfo[LocalCacheInfoCount].CacheType = CacheData[Index].CacheType;
312-
LocalCacheInfo[LocalCacheInfoCount].CacheWays = CacheData[Index].CacheWays;
313-
LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB = CacheData[Index].CacheSizeinKB;
314-
LocalCacheInfo[LocalCacheInfoCount].CacheCount = 1;
311+
LocalCacheInfo[LocalCacheInfoCount].Package = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package;
312+
LocalCacheInfo[LocalCacheInfoCount].CoreType = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType;
313+
LocalCacheInfo[LocalCacheInfoCount].CacheLevel = CacheData[Index].CacheLevel;
314+
LocalCacheInfo[LocalCacheInfoCount].CacheType = CacheData[Index].CacheType;
315+
LocalCacheInfo[LocalCacheInfoCount].CacheWays = CacheData[Index].CacheWays;
316+
LocalCacheInfo[LocalCacheInfoCount].FullyAssociativeCache = CacheData[Index].FullyAssociativeCache;
317+
LocalCacheInfo[LocalCacheInfoCount].DirectMappedCache = CacheData[Index].DirectMappedCache;
318+
LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB = CacheData[Index].CacheSizeinKB;
319+
LocalCacheInfo[LocalCacheInfoCount].CacheCount = 1;
315320

316321
LocalCacheInfoCount++;
317322
}

‎UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h

+13-2
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/** @file
22
Internal header file for CPU Cache info Library.
33
4-
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
4+
Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
55
SPDX-License-Identifier: BSD-2-Clause-Patent
66
77
**/
@@ -52,7 +52,18 @@ typedef struct {
5252
// Ways of associativity.
5353
// Value = CPUID.04h:EBX[31:22]
5454
//
55-
UINT16 CacheWays;
55+
UINT16 CacheWays : 10;
56+
//
57+
// Fully associative cache.
58+
// Value = CPUID.04h:EAX[09]
59+
//
60+
UINT16 FullyAssociativeCache : 1;
61+
//
62+
// Direct mapped cache.
63+
// Value = CPUID.04h:EDX[02]
64+
//
65+
UINT16 DirectMappedCache : 1;
66+
UINT16 Reserved : 4;
5667
//
5768
// Cache share bits.
5869
// Value = CPUID.04h:EAX[25:14]

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