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Verilog: extract module names used for declaring instances as reference tags
This one is conceptually based on universal-ctags/ctags@master...my2817:ctags:master reported and written by @my2817 at universal-ctags#3469. The test case is also taken from universal-ctags#3469 submitted by @my2817.
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7 files changed

Lines changed: 109 additions & 7 deletions

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‎Tmain/list-roles.d/stdout-expected.txt‎

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@@ -92,6 +92,7 @@ Ruby L/library required on loaded by "require"
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Ruby L/library requiredRel on loaded by "require_relative" method
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Sh h/heredoc endmarker on end marker
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Sh s/script loaded on loaded
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SystemVerilog m/module decl on declaring instances
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SystemdUnit u/unit After on referred in After key
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SystemdUnit u/unit Before on referred in Before key
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SystemdUnit u/unit RequiredBy on referred in RequiredBy key
@@ -108,6 +109,7 @@ Vera d/macro condition off used in part of #if/
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Vera d/macro undef on undefined
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Vera h/header local on local header
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Vera h/header system on system header
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Verilog m/module decl on declaring instances
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#
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# all.*
@@ -202,6 +204,7 @@ Ruby L/library required on loaded by "require"
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Ruby L/library requiredRel on loaded by "require_relative" method
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Sh h/heredoc endmarker on end marker
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Sh s/script loaded on loaded
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SystemVerilog m/module decl on declaring instances
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SystemdUnit u/unit After on referred in After key
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SystemdUnit u/unit Before on referred in Before key
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SystemdUnit u/unit RequiredBy on referred in RequiredBy key
@@ -218,6 +221,7 @@ Vera d/macro condition off used in part of #if/
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Vera d/macro undef on undefined
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Vera h/header local on local header
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Vera h/header system on system header
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Verilog m/module decl on declaring instances
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#
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# C.*

‎Units/parser-verilog.r/verilog-module-ref.d/args.ctags‎

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@@ -0,0 +1,3 @@
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--sort=no
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--extras=+r
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--fields=+r

‎Units/parser-verilog.r/verilog-module-ref.d/expected.tags‎

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test input.v /^module test (\/*AUTOARG*\/);$/;" m roles:def
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i_a input.v /^ input i_a, i_b;$/;" p module:test roles:def
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i_b input.v /^ input i_a, i_b;$/;" p module:test roles:def
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o_c input.v /^ output o_c;$/;" p module:test roles:def
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int1 input.v /^ ref1 int1 ();$/;" i module:test typeref:module:ref1 roles:def
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ref1 input.v /^ ref1 int1 ();$/;" m module:test roles:decl
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int2 input.v /^ ref1 int2 ();$/;" i module:test typeref:module:ref1 roles:def
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ref1 input.v /^ ref1 int2 ();$/;" m module:test roles:decl
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int3 input.v /^ int3 ();$/;" i module:test typeref:module:ref3 roles:def
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ref3 input.v /^ ref3 # (.A (aaa),$/;" m module:test roles:decl

‎Units/parser-verilog.r/verilog-module-ref.d/input.v‎

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// Taken from #3469 submitted by @my2817
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module test (/*AUTOARG*/);
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input i_a, i_b;
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output o_c;
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ref1 int1 ();
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ref1 int2 ();
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ref3 # (.A (aaa),
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.B (bbb))
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int3 ();
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endmodule // test

‎docs/man/ctags-lang-verilog.7.rst‎

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@@ -162,6 +162,28 @@ because they cannot be overridden.
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P3 input.sv /^ parameter P3 = "parameter";$/;" c module:no_parameter_port_list parameter:
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L7 input.sv /^ localparam L7 = "localparam";$/;" c module:no_parameter_port_list
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Supported Roles
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~~~~~~~~~~~~~~~
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.. code-block:: console
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$ ./ctags --list-roles=SystemVerilog
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#KIND(L/N) NAME ENABLED DESCRIPTION
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m/module decl on declaring instances
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$ ./ctags --list-roles=Verilog
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#KIND(L/N) NAME ENABLED DESCRIPTION
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m/module decl on declaring instances
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The parser extracts names of modules used in instance declarations as
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reference tags. ``decl`` is the role for the tags. See "TAG ENTRIES"
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section of :ref:`ctags(1) <ctags(1)>` about reference tags and roles.
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.. warning::
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The support for references in Universal Ctags is still
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experimental; the names of the roles may be changed in the future.
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TIPS
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~~~~
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‎man/ctags-lang-verilog.7.rst.in‎

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@@ -162,6 +162,28 @@ because they cannot be overridden.
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P3 input.sv /^ parameter P3 = "parameter";$/;" c module:no_parameter_port_list parameter:
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L7 input.sv /^ localparam L7 = "localparam";$/;" c module:no_parameter_port_list
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Supported Roles
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~~~~~~~~~~~~~~~
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.. code-block:: console
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$ ./ctags --list-roles=SystemVerilog
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#KIND(L/N) NAME ENABLED DESCRIPTION
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m/module decl on declaring instances
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$ ./ctags --list-roles=Verilog
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#KIND(L/N) NAME ENABLED DESCRIPTION
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m/module decl on declaring instances
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The parser extracts names of modules used in instance declarations as
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reference tags. ``decl`` is the role for the tags. See "TAG ENTRIES"
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section of ctags(1) about reference tags and roles.
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.. warning::
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The support for references in Universal Ctags is still
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experimental; the names of the roles may be changed in the future.
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TIPS
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~~~~
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‎parsers/verilog.c‎

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Original file line numberDiff line numberDiff line change
@@ -108,6 +108,10 @@ typedef enum {
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K_NETTYPE,
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} verilogKind;
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typedef enum {
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R_MODULE_DECL,
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} verilogModuleRole;
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typedef struct {
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const char *keyword;
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verilogKind kind;
@@ -141,11 +145,20 @@ static int Ungetc;
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static int Lang_verilog;
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static int Lang_systemverilog;
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static roleDefinition VerilogModuleRoles [] = {
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{ true, "decl", "declaring instances" },
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};
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static roleDefinition SystemVerilogModuleRoles [] = {
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{ true, "decl", "declaring instances" },
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};
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static kindDefinition VerilogKinds [] = {
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{ true, 'c', "constant", "constants (define, parameter, specparam)" },
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{ true, 'e', "event", "events" },
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{ true, 'f', "function", "functions" },
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{ true, 'm', "module", "modules" },
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{ true, 'm', "module", "modules",
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.referenceOnly = false, ATTACH_ROLES(VerilogModuleRoles) },
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{ true, 'n', "net", "net data types" },
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{ true, 'p', "port", "ports" },
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{ true, 'r', "register", "variable data types" },
@@ -158,7 +171,8 @@ static kindDefinition SystemVerilogKinds [] = {
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{ true, 'c', "constant", "constants (define, parameter, specparam, enum values)" },
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{ true, 'e', "event", "events" },
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{ true, 'f', "function", "functions" },
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{ true, 'm', "module", "modules" },
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{ true, 'm', "module", "modules",
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.referenceOnly = false, ATTACH_ROLES(SystemVerilogModuleRoles) },
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{ true, 'n', "net", "net data types" },
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{ true, 'p', "port", "ports" },
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{ true, 'r', "register", "variable data types" },
@@ -949,7 +963,7 @@ static int dropEndContext (tokenInfo *const token, int c)
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}
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952-
static void createTagWithTypeRef (tokenInfo *const token, verilogKind kind, tokenInfo *const typeref)
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static void createTagFull (tokenInfo *const token, verilogKind kind, int role, tokenInfo *const typeref)
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{
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tagEntryInfo tag;
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@@ -981,7 +995,10 @@ static void createTagWithTypeRef (tokenInfo *const token, verilogKind kind, toke
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}
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/* Create tag */
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initTagEntry (&tag, vStringValue (token->name), kind);
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if (role == ROLE_DEFINITION_INDEX)
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initTagEntry (&tag, vStringValue (token->name), kind);
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else
1001+
initRefTagEntry (&tag, vStringValue (token->name), kind, role);
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tag.lineNumber = token->lineNumber;
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tag.filePosition = token->filePosition;
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@@ -1011,7 +1028,8 @@ static void createTagWithTypeRef (tokenInfo *const token, verilogKind kind, toke
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10121029
makeTagEntry (&tag);
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if (isXtagEnabled (XTAG_QUALIFIED_TAGS) && currentContext->kind != K_UNDEFINED)
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if (isXtagEnabled (XTAG_QUALIFIED_TAGS) && currentContext->kind != K_UNDEFINED
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&& role == ROLE_DEFINITION_INDEX)
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{
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vString *const scopedName = vStringNew ();
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@@ -1027,7 +1045,7 @@ static void createTagWithTypeRef (tokenInfo *const token, verilogKind kind, toke
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}
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/* Push token as context if it is a container */
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if (container)
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if (container && role == ROLE_DEFINITION_INDEX)
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{
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createContext (kind, token->name);
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@@ -1037,7 +1055,7 @@ static void createTagWithTypeRef (tokenInfo *const token, verilogKind kind, toke
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for (unsigned int i = 0; i < ptrArrayCount (tagContents); i++)
10381056
{
10391057
tokenInfo *content = ptrArrayItem (tagContents, i);
1040-
createTagWithTypeRef (content, content->kind, NULL);
1058+
createTagFull (content, content->kind, ROLE_DEFINITION_INDEX, NULL);
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}
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/* Drop temporary contexts */
@@ -1049,11 +1067,21 @@ static void createTagWithTypeRef (tokenInfo *const token, verilogKind kind, toke
10491067
vStringClear (token->inheritance);
10501068
}
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static void createTagWithTypeRef (tokenInfo *const token, verilogKind kind, tokenInfo *const typeref)
1071+
{
1072+
createTagFull (token, kind, ROLE_DEFINITION_INDEX, typeref);
1073+
}
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static void createTag (tokenInfo *const token, verilogKind kind)
10531076
{
10541077
createTagWithTypeRef (token, kind, NULL);
10551078
}
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1080+
static void createRefTag (tokenInfo *const token, verilogKind kind, int role)
1081+
{
1082+
createTagFull (token, kind, role, NULL);
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}
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10571085
static int skipBlockName (tokenInfo *const token, int c)
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{
10591087
if (c == ':')
@@ -1873,6 +1901,7 @@ static int tagIdsInDataDecl (tokenInfo* token, int c, verilogKind kind)
18731901
tokenSaved->kind = K_MODULE; // for typeRef field
18741902
verbose ("find instance: %s with kind %s\n", vStringValue (token->name), getNameForKind (K_INSTANCE));
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createTagWithTypeRef (token, K_INSTANCE, tokenSaved);
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createRefTag (tokenSaved, K_MODULE, R_MODULE_DECL);
18761905
}
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}
18781907
c = skipMacro (c, token); // `ifdef, `else, `endif, etc. (before comma)

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