Error in parsing the last Output

Error in parsing the last Output in a module
```
module dut(

       input clk,rst,
       output reg [2:0]S1,
       output reg [2:0]S2,
       output reg [2:0]S3,
       output reg [2:0]S4
       );
```
### Parsing the above code gives number of ports for S4 as 1.
