From 9d322068133d7cd8487114aaebe6bf013f43f87c Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Fri, 31 May 2013 11:10:36 +0200 Subject: [PATCH 01/41] Almost compiling FMU config --- nuttx/.gitignore | 1 + nuttx/arch/arm/include/math.h | 612 +++++++++++++++++++++++ nuttx/configs/Kconfig | 11 + nuttx/configs/px4fmu-v1/common/Make.defs | 184 +++++++ nuttx/configs/px4fmu-v1/common/ld.script | 149 ++++++ nuttx/configs/px4fmu-v1/usbnsh/Make.defs | 110 +--- nuttx/configs/px4fmu-v1/usbnsh/defconfig | 147 ++++-- nuttx/configs/px4fmu-v1/usbnsh/setenv.sh | 4 +- 8 files changed, 1055 insertions(+), 163 deletions(-) create mode 100644 nuttx/arch/arm/include/math.h create mode 100644 nuttx/configs/px4fmu-v1/common/Make.defs create mode 100644 nuttx/configs/px4fmu-v1/common/ld.script diff --git a/nuttx/.gitignore b/nuttx/.gitignore index f594f36735..69b7bdb80e 100644 --- a/nuttx/.gitignore +++ b/nuttx/.gitignore @@ -1,5 +1,6 @@ /.config /.config.old +/.config-e /.version /Make.defs /setenv.sh diff --git a/nuttx/arch/arm/include/math.h b/nuttx/arch/arm/include/math.h new file mode 100644 index 0000000000..9de10c58b4 --- /dev/null +++ b/nuttx/arch/arm/include/math.h @@ -0,0 +1,612 @@ +#ifndef _MATH_H_ + +#define _MATH_H_ + +//#include +#include +#include "_ansi.h" + +//#define _PARAMS(_x) _x + +_BEGIN_STD_C + +#if 0 +/* __dmath, __fmath, and __ldmath are only here for backwards compatibility + * in case any code used them. They are no longer used by Newlib, itself, + * other than legacy. */ +union __dmath +{ + double d; + __ULong i[2]; +}; + +union __fmath +{ + float f; + __ULong i[1]; +}; + +#if defined(_HAVE_LONG_DOUBLE) +union __ldmath +{ + long double ld; + __ULong i[4]; +}; +#endif +#endif + +/* Natural log of 2 */ +#define _M_LN2 0.693147180559945309417 + +#if defined(__GNUC__) && \ + ( (__GNUC__ >= 4) || \ + ( (__GNUC__ >= 3) && defined(__GNUC_MINOR__) && (__GNUC_MINOR__ >= 3) ) ) + + /* gcc >= 3.3 implicitly defines builtins for HUGE_VALx values. */ + +# ifndef HUGE_VAL +# define HUGE_VAL (__builtin_huge_val()) +# endif + +# ifndef HUGE_VALF +# define HUGE_VALF (__builtin_huge_valf()) +# endif + +# ifndef HUGE_VALL +# define HUGE_VALL (__builtin_huge_vall()) +# endif + +# ifndef INFINITY +# define INFINITY (__builtin_inff()) +# endif + +# ifndef NAN +# define NAN (__builtin_nanf("")) +# endif + +#else /* !gcc >= 3.3 */ + + /* No builtins. Use fixed defines instead. (All 3 HUGE plus the INFINITY + * and NAN macros are required to be constant expressions. Using a variable-- + * even a static const--does not meet this requirement, as it cannot be + * evaluated at translation time.) + * The infinities are done using numbers that are far in excess of + * something that would be expected to be encountered in a floating-point + * implementation. (A more certain way uses values from float.h, but that is + * avoided because system includes are not supposed to include each other.) + * This method might produce warnings from some compilers. (It does in + * newer GCCs, but not for ones that would hit this #else.) If this happens, + * please report details to the Newlib mailing list. */ + + #ifndef HUGE_VAL + #define HUGE_VAL (1.0e999999999) + #endif + + #ifndef HUGE_VALF + #define HUGE_VALF (1.0e999999999F) + #endif + + #if !defined(HUGE_VALL) && defined(_HAVE_LONG_DOUBLE) + #define HUGE_VALL (1.0e999999999L) + #endif + + #if !defined(INFINITY) + #define INFINITY (HUGE_VALF) + #endif + + #if !defined(NAN) + #if defined(__GNUC__) && defined(__cplusplus) + /* Exception: older g++ versions warn about the divide by 0 used in the + * normal case (even though older gccs do not). This trick suppresses the + * warning, but causes errors for plain gcc, so is only used in the one + * special case. */ + static const union { __ULong __i[1]; float __d; } __Nanf = {0x7FC00000}; + #define NAN (__Nanf.__d) + #else + #define NAN (0.0F/0.0F) + #endif + #endif + +#endif /* !gcc >= 3.3 */ + +/* Reentrant ANSI C functions. */ + +#ifndef __math_68881 +extern double atan _PARAMS((double)); +extern double cos _PARAMS((double)); +extern double sin _PARAMS((double)); +extern double tan _PARAMS((double)); +extern double tanh _PARAMS((double)); +extern double frexp _PARAMS((double, int *)); +extern double modf _PARAMS((double, double *)); +extern double ceil _PARAMS((double)); +extern double fabs _PARAMS((double)); +extern double floor _PARAMS((double)); +#endif /* ! defined (__math_68881) */ + +/* Non reentrant ANSI C functions. */ + +#ifndef _REENT_ONLY +#ifndef __math_68881 +extern double acos _PARAMS((double)); +extern double asin _PARAMS((double)); +extern double atan2 _PARAMS((double, double)); +extern double cosh _PARAMS((double)); +extern double sinh _PARAMS((double)); +extern double exp _PARAMS((double)); +extern double ldexp _PARAMS((double, int)); +extern double log _PARAMS((double)); +extern double log10 _PARAMS((double)); +extern double pow _PARAMS((double, double)); +extern double sqrt _PARAMS((double)); +extern double fmod _PARAMS((double, double)); +#endif /* ! defined (__math_68881) */ +#endif /* ! defined (_REENT_ONLY) */ + +#if !defined(__STRICT_ANSI__) || defined(__cplusplus) || __STDC_VERSION__ >= 199901L + +/* ISO C99 types and macros. */ + +#ifndef FLT_EVAL_METHOD +#define FLT_EVAL_METHOD 0 +typedef float float_t; +typedef double double_t; +#endif /* FLT_EVAL_METHOD */ + +#define FP_NAN 0 +#define FP_INFINITE 1 +#define FP_ZERO 2 +#define FP_SUBNORMAL 3 +#define FP_NORMAL 4 + +#ifndef FP_ILOGB0 +# define FP_ILOGB0 (-INT_MAX) +#endif +#ifndef FP_ILOGBNAN +# define FP_ILOGBNAN INT_MAX +#endif + +#ifndef MATH_ERRNO +# define MATH_ERRNO 1 +#endif +#ifndef MATH_ERREXCEPT +# define MATH_ERREXCEPT 2 +#endif +#ifndef math_errhandling +# define math_errhandling MATH_ERRNO +#endif + +extern int __isinff (float x); +extern int __isinfd (double x); +extern int __isnanf (float x); +extern int __isnand (double x); +extern int __fpclassifyf (float x); +extern int __fpclassifyd (double x); +extern int __signbitf (float x); +extern int __signbitd (double x); + +#define fpclassify(__x) \ + ((sizeof(__x) == sizeof(float)) ? __fpclassifyf(__x) : \ + __fpclassifyd(__x)) + +#ifndef isfinite + #define isfinite(__y) \ + (__extension__ ({int __cy = fpclassify(__y); \ + __cy != FP_INFINITE && __cy != FP_NAN;})) +#endif + +/* Note: isinf and isnan were once functions in newlib that took double + * arguments. C99 specifies that these names are reserved for macros + * supporting multiple floating point types. Thus, they are + * now defined as macros. Implementations of the old functions + * taking double arguments still exist for compatibility purposes + * (prototypes for them are in ). */ +#ifndef isinf + #define isinf(y) (fpclassify(y) == FP_INFINITE) +#endif + +#ifndef isnan + #define isnan(y) (fpclassify(y) == FP_NAN) +#endif + +#define isnormal(y) (fpclassify(y) == FP_NORMAL) +#define signbit(__x) \ + ((sizeof(__x) == sizeof(float)) ? __signbitf(__x) : \ + __signbitd(__x)) + +#define isgreater(x,y) \ + (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \ + !isunordered(__x,__y) && (__x > __y);})) +#define isgreaterequal(x,y) \ + (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \ + !isunordered(__x,__y) && (__x >= __y);})) +#define isless(x,y) \ + (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \ + !isunordered(__x,__y) && (__x < __y);})) +#define islessequal(x,y) \ + (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \ + !isunordered(__x,__y) && (__x <= __y);})) +#define islessgreater(x,y) \ + (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \ + !isunordered(__x,__y) && (__x < __y || __x > __y);})) + +#define isunordered(a,b) \ + (__extension__ ({__typeof__(a) __a = (a); __typeof__(b) __b = (b); \ + fpclassify(__a) == FP_NAN || fpclassify(__b) == FP_NAN;})) + +/* Non ANSI double precision functions. */ + +extern double infinity _PARAMS((void)); +extern double nan _PARAMS((const char *)); +extern int finite _PARAMS((double)); +extern double copysign _PARAMS((double, double)); +extern double logb _PARAMS((double)); +extern int ilogb _PARAMS((double)); + +extern double asinh _PARAMS((double)); +extern double cbrt _PARAMS((double)); +extern double nextafter _PARAMS((double, double)); +extern double rint _PARAMS((double)); +extern double scalbn _PARAMS((double, int)); + +extern double exp2 _PARAMS((double)); +extern double scalbln _PARAMS((double, long int)); +extern double tgamma _PARAMS((double)); +extern double nearbyint _PARAMS((double)); +extern long int lrint _PARAMS((double)); +extern _LONG_LONG_TYPE int llrint _PARAMS((double)); +extern double round _PARAMS((double)); +extern long int lround _PARAMS((double)); +extern long long int llround _PARAMS((double)); +extern double trunc _PARAMS((double)); +extern double remquo _PARAMS((double, double, int *)); +extern double fdim _PARAMS((double, double)); +extern double fmax _PARAMS((double, double)); +extern double fmin _PARAMS((double, double)); +extern double fma _PARAMS((double, double, double)); + +#ifndef __math_68881 +extern double log1p _PARAMS((double)); +extern double expm1 _PARAMS((double)); +#endif /* ! defined (__math_68881) */ + +#ifndef _REENT_ONLY +extern double acosh _PARAMS((double)); +extern double atanh _PARAMS((double)); +extern double remainder _PARAMS((double, double)); +extern double gamma _PARAMS((double)); +extern double lgamma _PARAMS((double)); +extern double erf _PARAMS((double)); +extern double erfc _PARAMS((double)); +extern double log2 _PARAMS((double)); +#if !defined(__cplusplus) +#define log2(x) (log (x) / _M_LN2) +#endif + +#ifndef __math_68881 +extern double hypot _PARAMS((double, double)); +#endif + +#endif /* ! defined (_REENT_ONLY) */ + +/* Single precision versions of ANSI functions. */ + +extern float atanf _PARAMS((float)); +extern float cosf _PARAMS((float)); +extern float sinf _PARAMS((float)); +extern float tanf _PARAMS((float)); +extern float tanhf _PARAMS((float)); +extern float frexpf _PARAMS((float, int *)); +extern float modff _PARAMS((float, float *)); +extern float ceilf _PARAMS((float)); +extern float fabsf _PARAMS((float)); +extern float floorf _PARAMS((float)); + +#ifndef _REENT_ONLY +extern float acosf _PARAMS((float)); +extern float asinf _PARAMS((float)); +extern float atan2f _PARAMS((float, float)); +extern float coshf _PARAMS((float)); +extern float sinhf _PARAMS((float)); +extern float expf _PARAMS((float)); +extern float ldexpf _PARAMS((float, int)); +extern float logf _PARAMS((float)); +extern float log10f _PARAMS((float)); +extern float powf _PARAMS((float, float)); +extern float sqrtf _PARAMS((float)); +extern float fmodf _PARAMS((float, float)); +#endif /* ! defined (_REENT_ONLY) */ + +/* Other single precision functions. */ + +extern float exp2f _PARAMS((float)); +extern float scalblnf _PARAMS((float, long int)); +extern float tgammaf _PARAMS((float)); +extern float nearbyintf _PARAMS((float)); +extern long int lrintf _PARAMS((float)); +extern _LONG_LONG_TYPE llrintf _PARAMS((float)); +extern float roundf _PARAMS((float)); +extern long int lroundf _PARAMS((float)); +extern long long int llroundf _PARAMS((float)); +extern float truncf _PARAMS((float)); +extern float remquof _PARAMS((float, float, int *)); +extern float fdimf _PARAMS((float, float)); +extern float fmaxf _PARAMS((float, float)); +extern float fminf _PARAMS((float, float)); +extern float fmaf _PARAMS((float, float, float)); + +extern float infinityf _PARAMS((void)); +extern float nanf _PARAMS((const char *)); +extern int finitef _PARAMS((float)); +extern float copysignf _PARAMS((float, float)); +extern float logbf _PARAMS((float)); +extern int ilogbf _PARAMS((float)); + +extern float asinhf _PARAMS((float)); +extern float cbrtf _PARAMS((float)); +extern float nextafterf _PARAMS((float, float)); +extern float rintf _PARAMS((float)); +extern float scalbnf _PARAMS((float, int)); +extern float log1pf _PARAMS((float)); +extern float expm1f _PARAMS((float)); + +#ifndef _REENT_ONLY +extern float acoshf _PARAMS((float)); +extern float atanhf _PARAMS((float)); +extern float remainderf _PARAMS((float, float)); +extern float gammaf _PARAMS((float)); +extern float lgammaf _PARAMS((float)); +extern float erff _PARAMS((float)); +extern float erfcf _PARAMS((float)); +extern float log2f _PARAMS((float)); +#if !defined(__cplusplus) +#define log2f(x) (logf (x) / (float_t) _M_LN2) +#endif +extern float hypotf _PARAMS((float, float)); +#endif /* ! defined (_REENT_ONLY) */ + +/* On platforms where long double equals double. */ +#ifdef _LDBL_EQ_DBL +/* Reentrant ANSI C functions. */ +#ifndef __math_68881 +extern long double atanl _PARAMS((long double)); +extern long double cosl _PARAMS((long double)); +extern long double sinl _PARAMS((long double)); +extern long double tanl _PARAMS((long double)); +extern long double tanhl _PARAMS((long double)); +extern long double frexpl _PARAMS((long double value, int *)); +extern long double modfl _PARAMS((long double, long double *)); +extern long double ceill _PARAMS((long double)); +extern long double fabsl _PARAMS((long double)); +extern long double floorl _PARAMS((long double)); +extern long double log1pl _PARAMS((long double)); +extern long double expm1l _PARAMS((long double)); +#endif /* ! defined (__math_68881) */ +/* Non reentrant ANSI C functions. */ +#ifndef _REENT_ONLY +#ifndef __math_68881 +extern long double acosl _PARAMS((long double)); +extern long double asinl _PARAMS((long double)); +extern long double atan2l _PARAMS((long double, long double)); +extern long double coshl _PARAMS((long double)); +extern long double sinhl _PARAMS((long double)); +extern long double expl _PARAMS((long double)); +extern long double ldexpl _PARAMS((long double, int)); +extern long double logl _PARAMS((long double)); +extern long double log10l _PARAMS((long double)); +extern long double powl _PARAMS((long double, long double)); +extern long double sqrtl _PARAMS((long double)); +extern long double fmodl _PARAMS((long double, long double)); +extern long double hypotl _PARAMS((long double, long double)); +#endif /* ! defined (__math_68881) */ +#endif /* ! defined (_REENT_ONLY) */ +extern long double copysignl _PARAMS((long double, long double)); +extern long double nanl _PARAMS((const char *)); +extern int ilogbl _PARAMS((long double)); +extern long double asinhl _PARAMS((long double)); +extern long double cbrtl _PARAMS((long double)); +extern long double nextafterl _PARAMS((long double, long double)); +extern long double rintl _PARAMS((long double)); +extern long double scalbnl _PARAMS((long double, int)); +extern long double exp2l _PARAMS((long double)); +extern long double scalblnl _PARAMS((long double, long)); +extern long double tgammal _PARAMS((long double)); +extern long double nearbyintl _PARAMS((long double)); +extern long int lrintl _PARAMS((long double)); +extern long long int llrintl _PARAMS((long double)); +extern long double roundl _PARAMS((long double)); +extern long lroundl _PARAMS((long double)); +extern _LONG_LONG_TYPE int llroundl _PARAMS((long double)); +extern long double truncl _PARAMS((long double)); +extern long double remquol _PARAMS((long double, long double, int *)); +extern long double fdiml _PARAMS((long double, long double)); +extern long double fmaxl _PARAMS((long double, long double)); +extern long double fminl _PARAMS((long double, long double)); +extern long double fmal _PARAMS((long double, long double, long double)); +#ifndef _REENT_ONLY +extern long double acoshl _PARAMS((long double)); +extern long double atanhl _PARAMS((long double)); +extern long double remainderl _PARAMS((long double, long double)); +extern long double lgammal _PARAMS((long double)); +extern long double erfl _PARAMS((long double)); +extern long double erfcl _PARAMS((long double)); +#endif /* ! defined (_REENT_ONLY) */ +#else /* !_LDBL_EQ_DBL */ +#ifdef __i386__ +/* Other long double precision functions. */ +extern _LONG_DOUBLE rintl _PARAMS((_LONG_DOUBLE)); +extern long int lrintl _PARAMS((_LONG_DOUBLE)); +extern _LONG_LONG_TYPE llrintl _PARAMS((_LONG_DOUBLE)); +#endif /* __i386__ */ +#endif /* !_LDBL_EQ_DBL */ + +#endif /* !defined (__STRICT_ANSI__) || defined(__cplusplus) || __STDC_VERSION__ >= 199901L */ + +#if !defined (__STRICT_ANSI__) || defined(__cplusplus) + +extern double drem _PARAMS((double, double)); +extern void sincos _PARAMS((double, double *, double *)); +extern double gamma_r _PARAMS((double, int *)); +extern double lgamma_r _PARAMS((double, int *)); + +extern double y0 _PARAMS((double)); +extern double y1 _PARAMS((double)); +extern double yn _PARAMS((int, double)); +extern double j0 _PARAMS((double)); +extern double j1 _PARAMS((double)); +extern double jn _PARAMS((int, double)); + +extern float dremf _PARAMS((float, float)); +extern void sincosf _PARAMS((float, float *, float *)); +extern float gammaf_r _PARAMS((float, int *)); +extern float lgammaf_r _PARAMS((float, int *)); + +extern float y0f _PARAMS((float)); +extern float y1f _PARAMS((float)); +extern float ynf _PARAMS((int, float)); +extern float j0f _PARAMS((float)); +extern float j1f _PARAMS((float)); +extern float jnf _PARAMS((int, float)); + +/* GNU extensions */ +# ifndef exp10 +extern double exp10 _PARAMS((double)); +# endif +# ifndef pow10 +extern double pow10 _PARAMS((double)); +# endif +# ifndef exp10f +extern float exp10f _PARAMS((float)); +# endif +# ifndef pow10f +extern float pow10f _PARAMS((float)); +# endif + +#endif /* !defined (__STRICT_ANSI__) || defined(__cplusplus) */ + +#ifndef __STRICT_ANSI__ + +/* The gamma functions use a global variable, signgam. */ +#ifndef _REENT_ONLY +#define signgam (*__signgam()) +extern int *__signgam _PARAMS((void)); +#endif /* ! defined (_REENT_ONLY) */ + +#define __signgam_r(ptr) _REENT_SIGNGAM(ptr) + +/* The exception structure passed to the matherr routine. */ +/* We have a problem when using C++ since `exception' is a reserved + name in C++. */ +#ifdef __cplusplus +struct __exception +#else +struct exception +#endif +{ + int type; + char *name; + double arg1; + double arg2; + double retval; + int err; +}; + +#ifdef __cplusplus +extern int matherr _PARAMS((struct __exception *e)); +#else +extern int matherr _PARAMS((struct exception *e)); +#endif + +/* Values for the type field of struct exception. */ + +#define DOMAIN 1 +#define SING 2 +#define OVERFLOW 3 +#define UNDERFLOW 4 +#define TLOSS 5 +#define PLOSS 6 + +/* Useful constants. */ + +#define MAXFLOAT 3.40282347e+38F + +#define M_E 2.7182818284590452354 +#define M_LOG2E 1.4426950408889634074 +#define M_LOG10E 0.43429448190325182765 +#define M_LN2 _M_LN2 +#define M_LN10 2.30258509299404568402 +#define M_PI 3.14159265358979323846 +#define M_TWOPI (M_PI * 2.0) +#define M_PI_2 1.57079632679489661923 +#define M_PI_4 0.78539816339744830962 +#define M_3PI_4 2.3561944901923448370E0 +#define M_SQRTPI 1.77245385090551602792981 +#define M_1_PI 0.31830988618379067154 +#define M_2_PI 0.63661977236758134308 +#define M_2_SQRTPI 1.12837916709551257390 +#define M_DEG_TO_RAD 0.01745329251994 +#define M_RAD_TO_DEG 57.2957795130823 +#define M_SQRT2 1.41421356237309504880 +#define M_SQRT1_2 0.70710678118654752440 +#define M_LN2LO 1.9082149292705877000E-10 +#define M_LN2HI 6.9314718036912381649E-1 +#define M_SQRT3 1.73205080756887719000 +#define M_IVLN10 0.43429448190325182765 /* 1 / log(10) */ +#define M_LOG2_E _M_LN2 +#define M_INVLN2 1.4426950408889633870E0 /* 1 / log(2) */ + + +#define M_E_F 2.7182818284590452354f +#define M_LOG2E_F 1.4426950408889634074f +#define M_LOG10E_F 0.43429448190325182765f +#define M_LN2_F _M_LN2_F +#define M_LN10_F 2.30258509299404568402f +#define M_PI_F 3.14159265358979323846f +#define M_TWOPI_F (M_PI_F * 2.0f) +#define M_PI_2_F 1.57079632679489661923f +#define M_PI_4_F 0.78539816339744830962f +#define M_3PI_4_F 2.3561944901923448370E0f +#define M_SQRTPI_F 1.77245385090551602792981f +#define M_1_PI_F 0.31830988618379067154f +#define M_2_PI_F 0.63661977236758134308f +#define M_2_SQRTPI_F 1.12837916709551257390f +#define M_DEG_TO_RAD_F 0.01745329251994f +#define M_RAD_TO_DEG_F 57.2957795130823f +#define M_SQRT2_F 1.41421356237309504880f +#define M_SQRT1_2_F 0.70710678118654752440f +#define M_LN2LO_F 1.9082149292705877000E-10f +#define M_LN2HI_F 6.9314718036912381649E-1f +#define M_SQRT3_F 1.73205080756887719000f +#define M_IVLN10_F 0.43429448190325182765f /* 1 / log(10) */ +#define M_LOG2_E_F _M_LN2_F +#define M_INVLN2_F 1.4426950408889633870E0f /* 1 / log(2) */ + +/* Global control over fdlibm error handling. */ + +enum __fdlibm_version +{ + __fdlibm_ieee = -1, + __fdlibm_svid, + __fdlibm_xopen, + __fdlibm_posix +}; + +#define _LIB_VERSION_TYPE enum __fdlibm_version +#define _LIB_VERSION __fdlib_version + +extern __IMPORT _LIB_VERSION_TYPE _LIB_VERSION; + +#define _IEEE_ __fdlibm_ieee +#define _SVID_ __fdlibm_svid +#define _XOPEN_ __fdlibm_xopen +#define _POSIX_ __fdlibm_posix + +#endif /* ! defined (__STRICT_ANSI__) */ + +_END_STD_C + +#ifdef __FAST_MATH__ +#include +#endif + +#endif /* _MATH_H_ */ diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig index f7ee6d9c0f..e2dad70cb7 100644 --- a/nuttx/configs/Kconfig +++ b/nuttx/configs/Kconfig @@ -535,6 +535,13 @@ config ARCH_BOARD_STM3240G_EVAL microcontroller (ARM Cortex-M4 with FPU). This port uses a GNU Cortex-M4 toolchain (such as CodeSourcery). +config ARCH_BOARD_PX4FMU_V1 + bool "PX4FMU v1.x" + depends on ARCH_CHIP_STM32F405RG + select ARCH_HAVE_LEDS + ---help--- + PX4 flight management unit v1.x + config ARCH_BOARD_STM32F100RC_GENERIC bool "STMicro STM32F100RC generic board" depends on ARCH_CHIP_STM32F100RC @@ -781,6 +788,7 @@ config ARCH_BOARD default "stm32f100rc_generic" if ARCH_BOARD_STM32F100RC_GENERIC default "stm32f3discovery" if ARCH_BOARD_STM32F3_DISCOVERY default "stm32f4discovery" if ARCH_BOARD_STM32F4_DISCOVERY + default "px4fmu-v1" if ARCH_BOARD_PX4FMU_V1 default "stm32ldiscovery" if ARCH_BOARD_STM32L_DISCOVERY default "mikroe-stm32f4" if ARCH_BOARD_MIKROE_STM32F4 default "sure-pic32mx" if ARCH_BOARD_SUREPIC32MX @@ -1016,6 +1024,9 @@ endif if ARCH_BOARD_STM32F4_DISCOVERY source "configs/stm32f4discovery/Kconfig" endif +if ARCH_BOARD_PX4FMU_V1 +source "configs/px4fmu-v1/Kconfig" +endif if ARCH_BOARD_STM32L_DISCOVERY source "configs/stm32ldiscovery/Kconfig" endif diff --git a/nuttx/configs/px4fmu-v1/common/Make.defs b/nuttx/configs/px4fmu-v1/common/Make.defs new file mode 100644 index 0000000000..756286ccb5 --- /dev/null +++ b/nuttx/configs/px4fmu-v1/common/Make.defs @@ -0,0 +1,184 @@ +############################################################################ +# configs/px4fmu/common/Make.defs +# +# Copyright (C) 2011 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# +# Generic Make.defs for the PX4FMU +# Do not specify/use this file directly - it is included by config-specific +# Make.defs in the per-config directories. +# + +include ${TOPDIR}/tools/Config.mk + +# +# We only support building with the ARM bare-metal toolchain from +# https://launchpad.net/gcc-arm-embedded on Windows, Linux or Mac OS. +# +CONFIG_ARMV7M_TOOLCHAIN := GNU_EABI + +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +MAXOPTIMIZATION = -O3 +ARCHCPUFLAGS = -mcpu=cortex-m4 \ + -mthumb \ + -march=armv7e-m \ + -mfpu=fpv4-sp-d16 \ + -mfloat-abi=hard + + +# enable precise stack overflow tracking +INSTRUMENTATIONDEFINES = -finstrument-functions \ + -ffixed-r10 + +# pull in *just* libm from the toolchain ... this is grody +LIBM = "${shell $(CC) $(ARCHCPUFLAGS) -print-file-name=libm.a}" +EXTRA_LIBS += $(LIBM) + +# use our linker script +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT)}" +else + ifeq ($(PX4_WINTOOL),y) + # Windows-native toolchains (MSYS) + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT) + else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT) + endif +endif + +# tool versions +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +# optimisation flags +ARCHOPTIMIZATION = $(MAXOPTIMIZATION) \ + -fno-strict-aliasing \ + -fno-strength-reduce \ + -fomit-frame-pointer \ + -funsafe-math-optimizations \ + -fno-builtin-printf \ + -ffunction-sections \ + -fdata-sections + +ifeq ("${CONFIG_DEBUG_SYMBOLS}","y") +ARCHOPTIMIZATION += -g +endif + +ARCHCFLAGS = -std=gnu99 +ARCHCXXFLAGS = -fno-exceptions -fno-rtti -std=gnu++0x +ARCHWARNINGS = -Wall \ + -Wextra \ + -Wdouble-promotion \ + -Wshadow \ + -Wfloat-equal \ + -Wframe-larger-than=1024 \ + -Wpointer-arith \ + -Wlogical-op \ + -Wmissing-declarations \ + -Wpacked \ + -Wno-unused-parameter +# -Wcast-qual - generates spurious noreturn attribute warnings, try again later +# -Wconversion - would be nice, but too many "risky-but-safe" conversions in the code +# -Wcast-align - would help catch bad casts in some cases, but generates too many false positives + +ARCHCWARNINGS = $(ARCHWARNINGS) \ + -Wbad-function-cast \ + -Wstrict-prototypes \ + -Wold-style-declaration \ + -Wmissing-parameter-type \ + -Wmissing-prototypes \ + -Wnested-externs \ + -Wunsuffixed-float-constants +ARCHWARNINGSXX = $(ARCHWARNINGS) \ + -Wno-psabi +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +# this seems to be the only way to add linker flags +EXTRA_LIBS += --warn-common \ + --gc-sections + +CFLAGS = $(ARCHCFLAGS) $(ARCHCWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -fno-common +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + + +# produce partially-linked $1 from files in $2 +define PRELINK + @echo "PRELINK: $1" + $(Q) $(LD) -Ur -o $1 $2 && $(OBJCOPY) --localize-hidden $1 +endef + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + diff --git a/nuttx/configs/px4fmu-v1/common/ld.script b/nuttx/configs/px4fmu-v1/common/ld.script new file mode 100644 index 0000000000..de8179e8db --- /dev/null +++ b/nuttx/configs/px4fmu-v1/common/ld.script @@ -0,0 +1,149 @@ +/**************************************************************************** + * configs/px4fmu/common/ld.script + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F405 has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of TCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The first 0x4000 of flash is reserved for the bootloader. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08004000, LENGTH = 1008K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + ccsram (rwx) : ORIGIN = 0x10000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) + +ENTRY(__start) /* treat __start as the anchor for dead code stripping */ +EXTERN(_vectors) /* force the vectors to be included in the output */ + +/* + * Ensure that abort() is present in the final object. The exception handling + * code pulled in by libgcc.a requires it (and that code cannot be easily avoided). + */ +EXTERN(abort) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + + /* + * This is a hack to make the newlib libm __errno() call + * use the NuttX get_errno_ptr() function. + */ + __errno = get_errno_ptr; + } > flash + + /* + * Init functions (static constructors and the like) + */ + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + /* + * Construction data for parameters. + */ + __param ALIGN(4): { + __param_start = ABSOLUTE(.); + KEEP(*(__param*)) + __param_end = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/px4fmu-v1/usbnsh/Make.defs b/nuttx/configs/px4fmu-v1/usbnsh/Make.defs index 8e75d971ed..81936334b3 100644 --- a/nuttx/configs/px4fmu-v1/usbnsh/Make.defs +++ b/nuttx/configs/px4fmu-v1/usbnsh/Make.defs @@ -1,111 +1,3 @@ -############################################################################ -# configs/stm32f4discovery/nsh/Make.defs -# -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mknulldeps.sh - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" - MAXOPTIMIZATION = -O2 -else - # Linux/Cygwin-native toolchain - MKDEP = $(TOPDIR)/tools/mkdeps.sh - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -else - ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -ARCHWARNINGSXX = -Wall -Wshadow -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe -HOSTLDFLAGS = +include $(TOPDIR)/configs/px4fmu-v1/common/Make.defs diff --git a/nuttx/configs/px4fmu-v1/usbnsh/defconfig b/nuttx/configs/px4fmu-v1/usbnsh/defconfig index 456ef55b1e..963d71a897 100644 --- a/nuttx/configs/px4fmu-v1/usbnsh/defconfig +++ b/nuttx/configs/px4fmu-v1/usbnsh/defconfig @@ -31,7 +31,7 @@ CONFIG_RAW_BINARY=y # Customize Header Files # # CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set +CONFIG_ARCH_MATH_H=y # CONFIG_ARCH_FLOAT_H is not set # CONFIG_ARCH_STDARG_H is not set @@ -65,6 +65,7 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_IMX is not set # CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set # CONFIG_ARCH_CHIP_LM is not set # CONFIG_ARCH_CHIP_LPC17XX is not set # CONFIG_ARCH_CHIP_LPC214X is not set @@ -95,6 +96,24 @@ CONFIG_SERIAL_TERMIOS=y # # STM32 Configuration Options # +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set # CONFIG_ARCH_CHIP_STM32F100C8 is not set # CONFIG_ARCH_CHIP_STM32F100CB is not set # CONFIG_ARCH_CHIP_STM32F100R8 is not set @@ -107,6 +126,8 @@ CONFIG_SERIAL_TERMIOS=y # CONFIG_ARCH_CHIP_STM32F100VC is not set # CONFIG_ARCH_CHIP_STM32F100VD is not set # CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set # CONFIG_ARCH_CHIP_STM32F103RET6 is not set # CONFIG_ARCH_CHIP_STM32F103VCT6 is not set # CONFIG_ARCH_CHIP_STM32F103VET6 is not set @@ -138,6 +159,17 @@ CONFIG_ARCH_CHIP_STM32F405RG=y # CONFIG_ARCH_CHIP_STM32F427V is not set # CONFIG_ARCH_CHIP_STM32F427Z is not set # CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F30XX is not set CONFIG_STM32_STM32F40XX=y # CONFIG_STM32_DFU is not set @@ -164,7 +196,6 @@ CONFIG_STM32_DMA2=y CONFIG_STM32_I2C1=y CONFIG_STM32_I2C2=y CONFIG_STM32_I2C3=y -# CONFIG_STM32_IWDG is not set CONFIG_STM32_OTGFS=y # CONFIG_STM32_OTGHS is not set CONFIG_STM32_PWR=y @@ -194,7 +225,8 @@ CONFIG_STM32_USART2=y # CONFIG_STM32_UART4 is not set CONFIG_STM32_UART5=y CONFIG_STM32_USART6=y -CONFIG_STM32_WWDG=y +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set CONFIG_STM32_ADC=y CONFIG_STM32_SPI=y CONFIG_STM32_I2C=y @@ -207,6 +239,7 @@ CONFIG_STM32_FLASH_PREFETCH=y # CONFIG_STM32_JTAG_FULL_ENABLE is not set # CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set # CONFIG_STM32_FORCEPOWER is not set # CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set # CONFIG_STM32_CCMEXCLUDE is not set @@ -234,7 +267,7 @@ CONFIG_UART5_RXDMA=y CONFIG_USART6_RXDMA=y # CONFIG_USART7_RXDMA is not set # CONFIG_USART8_RXDMA is not set -# CONFIG_STM32_USART_SINGLEWIRE is not set +CONFIG_STM32_USART_SINGLEWIRE=y # # SPI Configuration @@ -245,10 +278,10 @@ CONFIG_USART6_RXDMA=y # # I2C Configuration # -CONFIG_STM32_I2C_DYNTIMEO=y -CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=500 -CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=1000 +# CONFIG_STM32_I2C_DYNTIMEO is not set CONFIG_STM32_I2CTIMEOSEC=0 +CONFIG_STM32_I2CTIMEOMS=500 +CONFIG_STM32_I2CTIMEOTICKS=500 # CONFIG_STM32_I2C_DUTY16_9 is not set # @@ -312,7 +345,7 @@ CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y CONFIG_NSH_MMCSDMINOR=0 CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=3 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options @@ -323,9 +356,9 @@ CONFIG_NSH_MMCSDSPIPORTNO=3 # # CONFIG_BOARD_INITIALIZE is not set CONFIG_MSEC_PER_TICK=1 -CONFIG_RR_INTERVAL=10 +CONFIG_RR_INTERVAL=5 # CONFIG_SCHED_INSTRUMENTATION is not set -CONFIG_TASK_NAME_SIZE=16 +CONFIG_TASK_NAME_SIZE=24 # CONFIG_SCHED_HAVE_PARENT is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 @@ -345,7 +378,13 @@ CONFIG_SCHED_ATEXIT=y CONFIG_SCHED_ATEXIT_MAX=1 # CONFIG_SCHED_ONEXIT is not set CONFIG_USER_ENTRYPOINT="nsh_main" -# CONFIG_DISABLE_OS_API is not set +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set # # Signal Numbers @@ -360,7 +399,7 @@ CONFIG_SIG_SIGWORK=17 # Sizes of configurable things (0 disables) # CONFIG_MAX_TASKS=16 -CONFIG_MAX_TASK_ARGS=4 +CONFIG_MAX_TASK_ARGS=10 CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 @@ -374,7 +413,7 @@ CONFIG_PREALLOC_TIMERS=4 # # Stack and heap information # -CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_USERMAIN_STACKSIZE=2048 CONFIG_PTHREAD_STACK_MIN=256 CONFIG_PTHREAD_STACK_DEFAULT=2048 @@ -402,8 +441,9 @@ CONFIG_SPI=y CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_RTC is not set -CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set # CONFIG_LCD is not set @@ -411,7 +451,7 @@ CONFIG_MMCSD=y CONFIG_MMCSD_NSLOTS=1 # CONFIG_MMCSD_READONLY is not set # CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set -CONFIG_MMCSD_MMCSUPPORT=y +# CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_MMCSD_HAVECARDDETECT is not set CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SPICLOCK=20000000 @@ -421,9 +461,9 @@ CONFIG_PIPES=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set +CONFIG_SERIAL_REMOVABLE=y # CONFIG_16550_UART is not set CONFIG_ARCH_HAVE_UART5=y CONFIG_ARCH_HAVE_USART1=y @@ -431,11 +471,11 @@ CONFIG_ARCH_HAVE_USART2=y CONFIG_ARCH_HAVE_USART6=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y -CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_USART1_SERIAL_CONSOLE is not set # CONFIG_USART2_SERIAL_CONSOLE is not set # CONFIG_UART5_SERIAL_CONSOLE is not set # CONFIG_USART6_SERIAL_CONSOLE is not set -# CONFIG_NO_SERIAL_CONSOLE is not set +CONFIG_NO_SERIAL_CONSOLE=y # # USART1 Configuration @@ -479,14 +519,19 @@ CONFIG_USART6_2STOP=0 CONFIG_USBDEV=y # -# Device Controller Driver Options +# USB Device Controller Driver Options # # CONFIG_USBDEV_ISOCHRONOUS is not set # CONFIG_USBDEV_DUALSPEED is not set CONFIG_USBDEV_SELFPOWERED=y # CONFIG_USBDEV_BUSPOWERED is not set +CONFIG_USBDEV_MAXPOWER=500 # CONFIG_USBDEV_DMA is not set # CONFIG_USBDEV_TRACE is not set + +# +# USB Device Class Driver Options +# # CONFIG_USBDEV_COMPOSITE is not set # CONFIG_PL2303 is not set CONFIG_CDCACM=y @@ -505,20 +550,10 @@ CONFIG_CDCACM_NWRREQS=4 CONFIG_CDCACM_NRDREQS=4 CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_CDCACM_VENDORID=0x26AC +CONFIG_CDCACM_VENDORID=0x26ac CONFIG_CDCACM_PRODUCTID=0x10 CONFIG_CDCACM_VENDORSTR="3D Robotics" -CONFIG_CDCACM_PRODUCTSTR="PX4 FMU v1.x" -# CONFIG_USBMSC is not set -# CONFIG_USBHOST is not set -# CONFIG_WIRELESS is not set - -# -# USB Device Class Driver Options -# -# CONFIG_USBDEV_COMPOSITE is not set -# CONFIG_PL2303 is not set -# CONFIG_CDCACM is not set +CONFIG_CDCACM_PRODUCTSTR="PX4FMU v1.x" # CONFIG_USBMSC is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set @@ -546,23 +581,19 @@ CONFIG_CDCACM_PRODUCTSTR="PX4 FMU v1.x" # # CONFIG_DISABLE_MOUNTPOINT is not set # CONFIG_FS_RAMMAP is not set -CONFIG_FS_FAT=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=32 -# CONFIG_FS_FATTIME is not set -# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_FAT is not set # CONFIG_FS_NXFFS is not set -CONFIG_FS_ROMFS=y -CONFIG_FS_BINFS=y +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set # # System Logging # -CONFIG_SYSLOG_ENABLE=y +# CONFIG_SYSLOG_ENABLE is not set CONFIG_SYSLOG=y CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/syslog" +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" # # Graphics Support @@ -579,6 +610,11 @@ CONFIG_GRAN=y CONFIG_GRAN_SINGLE=y CONFIG_GRAN_INTR=y +# +# Audio Support +# +# CONFIG_AUDIO is not set + # # Binary Formats # @@ -601,9 +637,9 @@ CONFIG_STDIO_BUFFER_SIZE=64 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 CONFIG_LIB_HOMEDIR="/" -CONFIG_LIBM=y # CONFIG_NOPRINTF_FIELDWIDTH is not set CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set # CONFIG_EOL_IS_BOTH_CRLF is not set @@ -632,6 +668,7 @@ CONFIG_SCHED_LPWORKPRIORITY=50 CONFIG_SCHED_LPWORKPERIOD=50000 CONFIG_SCHED_LPWORKSTACKSIZE=2048 # CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set # # Basic CXX Support @@ -660,6 +697,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set # CONFIG_EXAMPLES_COMPOSITE is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -674,8 +712,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_IGMP is not set # CONFIG_EXAMPLES_LCDRW is not set # CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MOUNT is not set # CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set # CONFIG_EXAMPLES_NX is not set @@ -695,6 +733,10 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_THTTPD is not set # CONFIG_EXAMPLES_TIFF is not set @@ -791,6 +833,11 @@ CONFIG_NSH_BUILTIN_APPS=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 # CONFIG_NSH_STRERROR is not set @@ -798,7 +845,6 @@ CONFIG_NSH_LINELEN=64 CONFIG_NSH_NESTDEPTH=3 # CONFIG_NSH_DISABLESCRIPT is not set # CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_ROMFSETC is not set CONFIG_NSH_CONSOLE=y # CONFIG_NSH_USBCONSOLE is not set @@ -824,20 +870,17 @@ CONFIG_NSH_ARCHINIT=y # # I2C tool # -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_I2CTOOL_BUILTIN=y -CONFIG_I2CTOOL_MINBUS=0 -CONFIG_I2CTOOL_MAXBUS=3 -CONFIG_I2CTOOL_MINADDR=0x03 -CONFIG_I2CTOOL_MAXADDR=0x77 -CONFIG_I2CTOOL_MAXREGADDR=0xff -CONFIG_I2CTOOL_DEFFREQ=4000000 +# CONFIG_SYSTEM_I2CTOOL is not set # # FLASH Program Installation # # CONFIG_SYSTEM_INSTALL is not set +# +# FLASH Erase-all Command +# + # # readline() # diff --git a/nuttx/configs/px4fmu-v1/usbnsh/setenv.sh b/nuttx/configs/px4fmu-v1/usbnsh/setenv.sh index 2476845b64..db372217cd 100755 --- a/nuttx/configs/px4fmu-v1/usbnsh/setenv.sh +++ b/nuttx/configs/px4fmu-v1/usbnsh/setenv.sh @@ -1,7 +1,7 @@ #!/bin/bash -# configs/stm32f4discovery/nsh/setenv.sh +# configs/px4fmu-v1/usbnsh/setenv.sh # -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without From 3faa01af062a46732149d35221c656e0e7f04323 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Fri, 31 May 2013 23:44:38 +0200 Subject: [PATCH 02/41] Added stack checking --- nuttx/configs/px4fmu-v1/src/Makefile | 2 +- nuttx/configs/px4fmu-v1/src/up_spi.c | 2 +- nuttx/configs/px4fmu-v1/src/up_stackcheck.c | 40 +++++++++++++++++++++ 3 files changed, 42 insertions(+), 2 deletions(-) create mode 100644 nuttx/configs/px4fmu-v1/src/up_stackcheck.c diff --git a/nuttx/configs/px4fmu-v1/src/Makefile b/nuttx/configs/px4fmu-v1/src/Makefile index 07ae4ecff4..9b914e52ab 100644 --- a/nuttx/configs/px4fmu-v1/src/Makefile +++ b/nuttx/configs/px4fmu-v1/src/Makefile @@ -40,7 +40,7 @@ CFLAGS += -I$(TOPDIR)/sched ASRCS = AOBJS = $(ASRCS:.S=$(OBJEXT)) -CSRCS = up_boot.c up_spi.c +CSRCS = up_boot.c up_spi.c up_stackcheck.c ifeq ($(CONFIG_HAVE_CXX),y) CSRCS += up_cxxinitialize.c diff --git a/nuttx/configs/px4fmu-v1/src/up_spi.c b/nuttx/configs/px4fmu-v1/src/up_spi.c index db4d1e9de0..63d1b85203 100644 --- a/nuttx/configs/px4fmu-v1/src/up_spi.c +++ b/nuttx/configs/px4fmu-v1/src/up_spi.c @@ -93,7 +93,7 @@ * ************************************************************************************/ -void weak_function stm32_spiinitialize(void) +void stm32_spiinitialize(void) { #ifdef CONFIG_STM32_SPI1 stm32_configgpio(GPIO_SPI_CS_GYRO); diff --git a/nuttx/configs/px4fmu-v1/src/up_stackcheck.c b/nuttx/configs/px4fmu-v1/src/up_stackcheck.c new file mode 100644 index 0000000000..e8f02a863b --- /dev/null +++ b/nuttx/configs/px4fmu-v1/src/up_stackcheck.c @@ -0,0 +1,40 @@ + + +void __cyg_profile_func_enter(void *func, void *caller) __attribute__((naked, no_instrument_function)); +void __cyg_profile_func_exit(void *func, void *caller) __attribute__((naked, no_instrument_function)); +void __stack_overflow_trap(void) __attribute__((naked, no_instrument_function)); + +void +__stack_overflow_trap(void) +{ + /* if we get here, the stack has overflowed */ + asm ( "b ."); +} + +void +__cyg_profile_func_enter(void *func, void *caller) +{ + asm volatile ( + " mrs r2, ipsr \n" /* Check whether we are in interrupt mode */ + " cmp r2, #0 \n" /* since we don't switch r10 on interrupt entry, we */ + " bne 2f \n" /* can't detect overflow of the interrupt stack. */ + " \n" + " sub r2, sp, #68 \n" /* compute stack pointer as though we just stacked a full frame */ + " mrs r1, control \n" /* Test CONTROL.FPCA to see whether we also need room for the FP */ + " tst r1, #4 \n" /* context. */ + " beq 1f \n" + " sub r2, r2, #136 \n" /* subtract FP context frame size */ + "1: \n" + " cmp r2, r10 \n" /* compare stack with limit */ + " bgt 2f \n" /* stack is above limit and thus OK */ + " b __stack_overflow_trap\n" + "2: \n" + " bx lr \n" + ); +} + +void +__cyg_profile_func_exit(void *func, void *caller) +{ + asm volatile("bx lr"); +} From bdabaab5bb726e012ef841528fb89a7cb6e0101b Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sat, 1 Jun 2013 00:50:15 +0200 Subject: [PATCH 03/41] Updated FMU and IO configs --- nuttx/configs/Kconfig | 8 + nuttx/configs/px4fmu-v1/src/Makefile | 60 +- nuttx/configs/px4fmu-v1/src/empty.c | 4 + .../px4fmu-v1/src/px4fmu-v1-internal.h | 137 --- nuttx/configs/px4fmu-v1/src/up_autoleds.c | 235 ----- nuttx/configs/px4fmu-v1/src/up_boot.c | 103 --- .../configs/px4fmu-v1/src/up_cxxinitialize.c | 155 ---- nuttx/configs/px4fmu-v1/src/up_idle.c | 119 --- nuttx/configs/px4fmu-v1/src/up_nsh.c | 155 ---- nuttx/configs/px4fmu-v1/src/up_spi.c | 199 ----- nuttx/configs/px4fmu-v1/src/up_stackcheck.c | 40 - nuttx/configs/px4fmu-v1/src/up_usb.c | 124 --- nuttx/configs/px4fmu-v1/src/up_userleds.c | 134 --- nuttx/configs/px4fmu-v1/src/up_watchdog.c | 136 --- nuttx/configs/px4io-v1/Kconfig | 8 + nuttx/configs/px4io-v1/README.txt | 806 ++++++++++++++++++ nuttx/configs/px4io-v1/common/Make.defs | 175 ++++ nuttx/configs/px4io-v1/common/ld.script | 129 +++ nuttx/configs/px4io-v1/common/setenv.sh | 47 + nuttx/configs/px4io-v1/include/README.txt | 1 + nuttx/configs/px4io-v1/include/board.h | 172 ++++ .../configs/px4io-v1/include/drv_i2c_device.h | 42 + nuttx/configs/px4io-v1/io/Make.defs | 3 + nuttx/configs/px4io-v1/io/appconfig | 32 + nuttx/configs/px4io-v1/io/defconfig | 552 ++++++++++++ nuttx/configs/px4io-v1/io/setenv.sh | 47 + nuttx/configs/px4io-v1/nsh/Make.defs | 3 + nuttx/configs/px4io-v1/nsh/appconfig | 43 + nuttx/configs/px4io-v1/nsh/defconfig | 565 ++++++++++++ nuttx/configs/px4io-v1/nsh/setenv.sh | 47 + nuttx/configs/px4io-v1/src/Makefile | 84 ++ nuttx/configs/px4io-v1/src/README.txt | 1 + nuttx/configs/px4io-v1/src/drv_i2c_device.c | 618 ++++++++++++++ nuttx/configs/px4io-v1/src/empty.c | 4 + 34 files changed, 3406 insertions(+), 1582 deletions(-) create mode 100644 nuttx/configs/px4fmu-v1/src/empty.c delete mode 100644 nuttx/configs/px4fmu-v1/src/px4fmu-v1-internal.h delete mode 100644 nuttx/configs/px4fmu-v1/src/up_autoleds.c delete mode 100644 nuttx/configs/px4fmu-v1/src/up_boot.c delete mode 100644 nuttx/configs/px4fmu-v1/src/up_cxxinitialize.c delete mode 100644 nuttx/configs/px4fmu-v1/src/up_idle.c delete mode 100644 nuttx/configs/px4fmu-v1/src/up_nsh.c delete mode 100644 nuttx/configs/px4fmu-v1/src/up_spi.c delete mode 100644 nuttx/configs/px4fmu-v1/src/up_stackcheck.c delete mode 100644 nuttx/configs/px4fmu-v1/src/up_usb.c delete mode 100644 nuttx/configs/px4fmu-v1/src/up_userleds.c delete mode 100644 nuttx/configs/px4fmu-v1/src/up_watchdog.c create mode 100644 nuttx/configs/px4io-v1/Kconfig create mode 100755 nuttx/configs/px4io-v1/README.txt create mode 100644 nuttx/configs/px4io-v1/common/Make.defs create mode 100755 nuttx/configs/px4io-v1/common/ld.script create mode 100755 nuttx/configs/px4io-v1/common/setenv.sh create mode 100755 nuttx/configs/px4io-v1/include/README.txt create mode 100755 nuttx/configs/px4io-v1/include/board.h create mode 100644 nuttx/configs/px4io-v1/include/drv_i2c_device.h create mode 100644 nuttx/configs/px4io-v1/io/Make.defs create mode 100644 nuttx/configs/px4io-v1/io/appconfig create mode 100755 nuttx/configs/px4io-v1/io/defconfig create mode 100755 nuttx/configs/px4io-v1/io/setenv.sh create mode 100644 nuttx/configs/px4io-v1/nsh/Make.defs create mode 100644 nuttx/configs/px4io-v1/nsh/appconfig create mode 100755 nuttx/configs/px4io-v1/nsh/defconfig create mode 100755 nuttx/configs/px4io-v1/nsh/setenv.sh create mode 100644 nuttx/configs/px4io-v1/src/Makefile create mode 100644 nuttx/configs/px4io-v1/src/README.txt create mode 100644 nuttx/configs/px4io-v1/src/drv_i2c_device.c create mode 100644 nuttx/configs/px4io-v1/src/empty.c diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig index e2dad70cb7..30cf7a5b86 100644 --- a/nuttx/configs/Kconfig +++ b/nuttx/configs/Kconfig @@ -542,6 +542,13 @@ config ARCH_BOARD_PX4FMU_V1 ---help--- PX4 flight management unit v1.x +config ARCH_BOARD_PX4IO_V1 + bool "PX4IO v1.x" + depends on CONFIG_ARCH_CHIP_STM32F100C8 + select ARCH_HAVE_LEDS + ---help--- + PX4 input / output unit v1.x + config ARCH_BOARD_STM32F100RC_GENERIC bool "STMicro STM32F100RC generic board" depends on ARCH_CHIP_STM32F100RC @@ -789,6 +796,7 @@ config ARCH_BOARD default "stm32f3discovery" if ARCH_BOARD_STM32F3_DISCOVERY default "stm32f4discovery" if ARCH_BOARD_STM32F4_DISCOVERY default "px4fmu-v1" if ARCH_BOARD_PX4FMU_V1 + default "px4io-v1" if ARCH_BOARD_PX4IO_V1 default "stm32ldiscovery" if ARCH_BOARD_STM32L_DISCOVERY default "mikroe-stm32f4" if ARCH_BOARD_MIKROE_STM32F4 default "sure-pic32mx" if ARCH_BOARD_SUREPIC32MX diff --git a/nuttx/configs/px4fmu-v1/src/Makefile b/nuttx/configs/px4fmu-v1/src/Makefile index 9b914e52ab..6ef8b7d6af 100644 --- a/nuttx/configs/px4fmu-v1/src/Makefile +++ b/nuttx/configs/px4fmu-v1/src/Makefile @@ -1,7 +1,7 @@ ############################################################################ -# configs/stm32f4discovery/src/Makefile +# configs/px4fmu-v1/src/Makefile # -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -35,55 +35,24 @@ -include $(TOPDIR)/Make.defs -CFLAGS += -I$(TOPDIR)/sched +CFLAGS += -I$(TOPDIR)/sched -ASRCS = -AOBJS = $(ASRCS:.S=$(OBJEXT)) +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) -CSRCS = up_boot.c up_spi.c up_stackcheck.c +CSRCS = empty.c +COBJS = $(CSRCS:.c=$(OBJEXT)) -ifeq ($(CONFIG_HAVE_CXX),y) -CSRCS += up_cxxinitialize.c -endif +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += up_autoleds.c -else -CSRCS += up_userleds.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += up_usb.c -endif - -ifeq ($(CONFIG_WATCHDOG),y) -CSRCS += up_watchdog.c -endif - -ifeq ($(CONFIG_NSH_ARCHINIT),y) -CSRCS += up_nsh.c -endif - -ifeq ($(CONFIG_IDLE_CUSTOM),y) -CSRCS += up_idle.c -endif - -COBJS = $(CSRCS:.c=$(OBJEXT)) - -SRCS = $(ASRCS) $(CSRCS) -OBJS = $(AOBJS) $(COBJS) - -ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src -ifeq ($(CONFIG_WINDOWS_NATIVE),y) - CFLAGS += -I$(ARCH_SRCDIR)\chip -I$(ARCH_SRCDIR)\common -I$(ARCH_SRCDIR)\armv7-m -else +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src ifeq ($(WINTOOL),y) - CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \ - -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \ - -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}" else - CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m -endif + CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m endif all: libboard$(LIBEXT) @@ -112,3 +81,4 @@ distclean: clean $(call DELFILE, .depend) -include Make.dep + diff --git a/nuttx/configs/px4fmu-v1/src/empty.c b/nuttx/configs/px4fmu-v1/src/empty.c new file mode 100644 index 0000000000..ace900866c --- /dev/null +++ b/nuttx/configs/px4fmu-v1/src/empty.c @@ -0,0 +1,4 @@ +/* + * There are no source files here, but libboard.a can't be empty, so + * we have this empty source file to keep it company. + */ diff --git a/nuttx/configs/px4fmu-v1/src/px4fmu-v1-internal.h b/nuttx/configs/px4fmu-v1/src/px4fmu-v1-internal.h deleted file mode 100644 index 0639bbd558..0000000000 --- a/nuttx/configs/px4fmu-v1/src/px4fmu-v1-internal.h +++ /dev/null @@ -1,137 +0,0 @@ -/**************************************************************************************************** - * configs/stm32f4discovery/src/stm32f4discovery-internal.h - * arch/arm/src/board/stm32f4discovery-internal.n - * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************************/ - -#ifndef __CONFIGS_PX4FMU_V1_SRC_PX4FMU_V1_INTERNAL_H -#define __CONFIGS_PX4FMU_V1_SRC_PX4FMU_V1_INTERNAL_H - -/**************************************************************************************************** - * Included Files - ****************************************************************************************************/ - -#include -#include -#include - -/**************************************************************************************************** - * Definitions - ****************************************************************************************************/ -/* Configuration ************************************************************************************/ -/* How many SPI modules does this chip support? */ - -#if STM32_NSPI < 1 -# undef CONFIG_STM32_SPI1 -# undef CONFIG_STM32_SPI2 -# undef CONFIG_STM32_SPI3 -#elif STM32_NSPI < 2 -# undef CONFIG_STM32_SPI2 -# undef CONFIG_STM32_SPI3 -#elif STM32_NSPI < 3 -# undef CONFIG_STM32_SPI3 -#endif - -/* px4fmu-v1 GPIOs **************************************************************************/ -/* LEDs */ - -#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN15) -#define GPIO_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN14) - -/* SPI chip selects */ - -#define GPIO_SPI_CS_GYRO (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN14) -#define GPIO_SPI_CS_ACCEL (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN15) -#define GPIO_SPI_CS_MPU (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN0) -#define GPIO_SPI_CS_SDCARD (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4) - -/* USB OTG FS - * - * PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED) - */ - -#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) - -/**************************************************************************************************** - * Public Types - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public data - ****************************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ - -/**************************************************************************************************** - * Name: stm32_spiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f4discovery board. - * - ****************************************************************************************************/ - -void weak_function stm32_spiinitialize(void); - -/**************************************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in inialization to setup USB-related - * GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************************************/ - -#ifdef CONFIG_STM32_OTGFS -void weak_function stm32_usbinitialize(void); -#endif - -/**************************************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host functionality. This function will - * start a thread that will monitor for device connection/disconnection events. - * - ****************************************************************************************************/ - -#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) -int stm32_usbhost_initialize(void); -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_PX4FMU_V1_SRC_PX4FMU_V1_INTERNAL_H */ - diff --git a/nuttx/configs/px4fmu-v1/src/up_autoleds.c b/nuttx/configs/px4fmu-v1/src/up_autoleds.c deleted file mode 100644 index 440c0cfa9c..0000000000 --- a/nuttx/configs/px4fmu-v1/src/up_autoleds.c +++ /dev/null @@ -1,235 +0,0 @@ -/**************************************************************************** - * configs/stm32f4discovery/src/up_autoleds.c - * arch/arm/src/board/up_autoleds.c - * - * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" -#include "stm32.h" -#include "px4fmu-v1-internal.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Definitions - ****************************************************************************/ - -/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG - * with CONFIG_DEBUG_VERBOSE too) - */ - -#ifdef CONFIG_DEBUG_LEDS -# define leddbg lldbg -# define ledvdbg llvdbg -#else -# define leddbg(x...) -# define ledvdbg(x...) -#endif - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM32F4_LED1 (1 << 0) -#define STM32F4_LED2 (1 << 1) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM32F4_LED2) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM32F4_LED1) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM32F4_LED2) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM32F4_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM32F4_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM32F4_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM32F4_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM32F4_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_ledinit - ****************************************************************************/ - -void up_ledinit(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: up_ledon - ****************************************************************************/ - -void up_ledon(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: up_ledoff - ****************************************************************************/ - -void up_ledoff(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/nuttx/configs/px4fmu-v1/src/up_boot.c b/nuttx/configs/px4fmu-v1/src/up_boot.c deleted file mode 100644 index ee6f3d59f7..0000000000 --- a/nuttx/configs/px4fmu-v1/src/up_boot.c +++ /dev/null @@ -1,103 +0,0 @@ -/************************************************************************************ - * configs/stm32f4discovery/src/up_boot.c - * arch/arm/src/board/up_boot.c - * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include "up_arch.h" -#include "px4fmu-v1-internal.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spiinitialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) - if (stm32_spiinitialize) - { - stm32_spiinitialize(); - } -#endif - - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. - */ - -#ifdef CONFIG_STM32_OTGFS - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - up_ledinit(); -#endif -} diff --git a/nuttx/configs/px4fmu-v1/src/up_cxxinitialize.c b/nuttx/configs/px4fmu-v1/src/up_cxxinitialize.c deleted file mode 100644 index 402dfb1114..0000000000 --- a/nuttx/configs/px4fmu-v1/src/up_cxxinitialize.c +++ /dev/null @@ -1,155 +0,0 @@ -/************************************************************************************ - * configs/stm32f4discovery/src/up_cxxinitialize.c - * arch/arm/src/board/up_cxxinitialize.c - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include -#include "chip.h" - -#if defined(CONFIG_HAVE_CXX) && defined(CONFIG_HAVE_CXXINITIALIZE) - -/************************************************************************************ - * Definitions - ************************************************************************************/ -/* Debug ****************************************************************************/ -/* Non-standard debug that may be enabled just for testing the static constructors */ - -#ifndef CONFIG_DEBUG -# undef CONFIG_DEBUG_CXX -#endif - -#ifdef CONFIG_DEBUG_CXX -# define cxxdbg dbg -# define cxxlldbg lldbg -# ifdef CONFIG_DEBUG_VERBOSE -# define cxxvdbg vdbg -# define cxxllvdbg llvdbg -# else -# define cxxvdbg(x...) -# define cxxllvdbg(x...) -# endif -#else -# define cxxdbg(x...) -# define cxxlldbg(x...) -# define cxxvdbg(x...) -# define cxxllvdbg(x...) -#endif - -/************************************************************************************ - * Private Types - ************************************************************************************/ -/* This type defines one entry in initialization array */ - -typedef void (*initializer_t)(void); - -/************************************************************************************ - * External references - ************************************************************************************/ -/* _sinit and _einit are symbols exported by the linker script that mark the - * beginning and the end of the C++ initialization section. - */ - -extern initializer_t _sinit; -extern initializer_t _einit; - -/* _stext and _etext are symbols exported by the linker script that mark the - * beginning and the end of text. - */ - -extern uint32_t _stext; -extern uint32_t _etext; - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/**************************************************************************** - * Name: up_cxxinitialize - * - * Description: - * If C++ and C++ static constructors are supported, then this function - * must be provided by board-specific logic in order to perform - * initialization of the static C++ class instances. - * - * This function should then be called in the application-specific - * user_start logic in order to perform the C++ initialization. NOTE - * that no component of the core NuttX RTOS logic is involved; This - * function defintion only provides the 'contract' between application - * specific C++ code and platform-specific toolchain support - * - ***************************************************************************/ - -void up_cxxinitialize(void) -{ - initializer_t *initp; - - cxxdbg("_sinit: %p _einit: %p _stext: %p _etext: %p\n", - &_sinit, &_einit, &_stext, &_etext); - - /* Visit each entry in the initialzation table */ - - for (initp = &_sinit; initp != &_einit; initp++) - { - initializer_t initializer = *initp; - cxxdbg("initp: %p initializer: %p\n", initp, initializer); - - /* Make sure that the address is non-NULL and lies in the text region - * defined by the linker script. Some toolchains may put NULL values - * or counts in the initialization table - */ - - if ((void*)initializer > (void*)&_stext && (void*)initializer < (void*)&_etext) - { - cxxdbg("Calling %p\n", initializer); - initializer(); - } - } -} - -#endif /* CONFIG_HAVE_CXX && CONFIG_HAVE_CXXINITIALIZE */ - diff --git a/nuttx/configs/px4fmu-v1/src/up_idle.c b/nuttx/configs/px4fmu-v1/src/up_idle.c deleted file mode 100644 index 53caf97026..0000000000 --- a/nuttx/configs/px4fmu-v1/src/up_idle.c +++ /dev/null @@ -1,119 +0,0 @@ -/**************************************************************************** - * configs/stm32f4discovery/src/up_idle.c - * arch/arm/src/board/up_idle.c - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Diego Sanchez - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include -#include -#include - -#include "up_internal.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" - -#include "px4fmu-v1-internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() up_ledon(LED_IDLE) -# define END_IDLE() up_ledoff(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#define up_idlepm() - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - sched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - up_idlepm(); - END_IDLE(); -#endif -} - diff --git a/nuttx/configs/px4fmu-v1/src/up_nsh.c b/nuttx/configs/px4fmu-v1/src/up_nsh.c deleted file mode 100644 index c26a085398..0000000000 --- a/nuttx/configs/px4fmu-v1/src/up_nsh.c +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * config/stm32f4discovery/src/up_nsh.c - * arch/arm/src/board/up_nsh.c - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#ifdef CONFIG_SYSTEM_USBMONITOR -# include -#endif - -#ifdef CONFIG_STM32_SPI3 -# include -#endif - -#include "stm32.h" -#include "px4fmu-v1-internal.h" - -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_USBDEV 1 -#define HAVE_USBMONITOR 1 - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBMONITOR -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -# undef HAVE_USBMONITOR -#endif - -/* Check if we should enable the USB monitor before starting NSH */ - -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) -# undef HAVE_USBMONITOR -#endif - -/* Debug ********************************************************************/ - -#ifdef CONFIG_CPP_HAVE_VARARGS -# ifdef CONFIG_DEBUG -# define message(...) lowsyslog(__VA_ARGS__) -# else -# define message(...) printf(__VA_ARGS__) -# endif -#else -# ifdef CONFIG_DEBUG -# define message lowsyslog -# else -# define message printf -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: nsh_archinitialize - * - * Description: - * Perform architecture specific initialization - * - ****************************************************************************/ - -int nsh_archinitialize(void) -{ -#if defined(HAVE_USBMONITOR) || defined(CONFIG_STM32_SPI3) - int ret; -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(0, NULL); - if (ret != OK) - { - message("nsh_archinitialize: Start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_SPI3 - message("[boot] Initializing SPI port 3\n"); - struct spi_dev_s *spi3 = up_spiinitialize(3); - - if (!spi3) { - message("[boot] FAILED to initialize SPI port 3\n"); - return -ENODEV; - } - - message("[boot] Successfully initialized SPI port 3\n"); - - /* Now bind the SPI interface to the MMCSD driver */ - ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, CONFIG_NSH_MMCSDSLOTNO, spi3); - - if (ret != OK) { - message("[boot] FAILED to bind SPI port 3 to the MMCSD driver\n"); - return -ENODEV; - } - - message("[boot] Successfully bound SPI port 3 to the MMCSD driver\n"); -#endif - - return OK; -} diff --git a/nuttx/configs/px4fmu-v1/src/up_spi.c b/nuttx/configs/px4fmu-v1/src/up_spi.c deleted file mode 100644 index 63d1b85203..0000000000 --- a/nuttx/configs/px4fmu-v1/src/up_spi.c +++ /dev/null @@ -1,199 +0,0 @@ -/************************************************************************************ - * configs/stm32f4discovery/src/up_spi.c - * arch/arm/src/board/up_spi.c - * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "chip.h" -#include "stm32.h" -#include "px4fmu-v1-internal.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Enables debug output from this file (needs CONFIG_DEBUG too) */ - -#undef SPI_DEBUG /* Define to enable debug */ -#undef SPI_VERBOSE /* Define to enable verbose debug */ - -#ifdef SPI_DEBUG -# define spidbg lldbg -# ifdef SPI_VERBOSE -# define spivdbg lldbg -# else -# define spivdbg(x...) -# endif -#else -# undef SPI_VERBOSE -# define spidbg(x...) -# define spivdbg(x...) -#endif - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_spiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the px4fmu-v1 board. - * - ************************************************************************************/ - -void stm32_spiinitialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_SPI_CS_GYRO); - stm32_configgpio(GPIO_SPI_CS_ACCEL); - stm32_configgpio(GPIO_SPI_CS_MPU); - - /* De-activate all peripherals, - * required for some peripheral - * state machines - */ - stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1); - stm32_gpiowrite(GPIO_SPI_CS_ACCEL, 1); - stm32_gpiowrite(GPIO_SPI_CS_MPU, 1); -#endif - -#ifdef CONFIG_STM32_SPI3 - stm32_configgpio(GPIO_SPI_CS_SDCARD); - stm32_gpiowrite(GPIO_SPI_CS_SDCARD, 1); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi.h). All other methods (including up_spiinitialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to up_spiinitialize() in your low level application - * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) -{ - /* SPI select is active low, so write !selected to select the device */ - - switch (devid) { - case PX4_SPIDEV_GYRO: - /* Making sure the other peripherals are not selected */ - stm32_gpiowrite(GPIO_SPI_CS_GYRO, !selected); - stm32_gpiowrite(GPIO_SPI_CS_MPU, 1); - stm32_gpiowrite(GPIO_SPI_CS_ACCEL, 1); - break; - - case PX4_SPIDEV_ACCEL: - /* Making sure the other peripherals are not selected */ - stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1); - stm32_gpiowrite(GPIO_SPI_CS_ACCEL, !selected); - stm32_gpiowrite(GPIO_SPI_CS_MPU, 1); - break; - - case PX4_SPIDEV_MPU: - /* Making sure the other peripherals are not selected */ - stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1); - stm32_gpiowrite(GPIO_SPI_CS_MPU, !selected); - stm32_gpiowrite(GPIO_SPI_CS_ACCEL, 1); - break; - - default: - break; - } -} - -uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -# error SPI2 is not supported on this board. -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) -{ - /* there can only be one device on this bus, so always select it */ - stm32_gpiowrite(GPIO_SPI_CS_SDCARD, !selected); -} - -uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) -{ - /* this is actually bogus, but px4fmu-v1 has no way to sense the presence of an SD card */ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/nuttx/configs/px4fmu-v1/src/up_stackcheck.c b/nuttx/configs/px4fmu-v1/src/up_stackcheck.c deleted file mode 100644 index e8f02a863b..0000000000 --- a/nuttx/configs/px4fmu-v1/src/up_stackcheck.c +++ /dev/null @@ -1,40 +0,0 @@ - - -void __cyg_profile_func_enter(void *func, void *caller) __attribute__((naked, no_instrument_function)); -void __cyg_profile_func_exit(void *func, void *caller) __attribute__((naked, no_instrument_function)); -void __stack_overflow_trap(void) __attribute__((naked, no_instrument_function)); - -void -__stack_overflow_trap(void) -{ - /* if we get here, the stack has overflowed */ - asm ( "b ."); -} - -void -__cyg_profile_func_enter(void *func, void *caller) -{ - asm volatile ( - " mrs r2, ipsr \n" /* Check whether we are in interrupt mode */ - " cmp r2, #0 \n" /* since we don't switch r10 on interrupt entry, we */ - " bne 2f \n" /* can't detect overflow of the interrupt stack. */ - " \n" - " sub r2, sp, #68 \n" /* compute stack pointer as though we just stacked a full frame */ - " mrs r1, control \n" /* Test CONTROL.FPCA to see whether we also need room for the FP */ - " tst r1, #4 \n" /* context. */ - " beq 1f \n" - " sub r2, r2, #136 \n" /* subtract FP context frame size */ - "1: \n" - " cmp r2, r10 \n" /* compare stack with limit */ - " bgt 2f \n" /* stack is above limit and thus OK */ - " b __stack_overflow_trap\n" - "2: \n" - " bx lr \n" - ); -} - -void -__cyg_profile_func_exit(void *func, void *caller) -{ - asm volatile("bx lr"); -} diff --git a/nuttx/configs/px4fmu-v1/src/up_usb.c b/nuttx/configs/px4fmu-v1/src/up_usb.c deleted file mode 100644 index ab7d90c688..0000000000 --- a/nuttx/configs/px4fmu-v1/src/up_usb.c +++ /dev/null @@ -1,124 +0,0 @@ -/************************************************************************************ - * configs/stm32f4discovery/src/up_usbdev.c - * arch/arm/src/board/up_boot.c - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "up_arch.h" -#include "stm32.h" -#include "px4fmu-v1-internal.h" - -#ifdef CONFIG_STM32_OTGFS - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -#if defined(CONFIG_USBDEV) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but not CONFIG_USBDEV" -# undef HAVE_USB -#endif - -/************************************************************************************ - * Private Data - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in inialization to setup USB-related - * GPIO pins for the STM32F4Discovery board. - * - ************************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. No GPIO configuration is required */ - - /* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); -#endif -} - -/************************************************************************************ - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is - * used. This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. - * - ************************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) -{ - ulldbg("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ - - - diff --git a/nuttx/configs/px4fmu-v1/src/up_userleds.c b/nuttx/configs/px4fmu-v1/src/up_userleds.c deleted file mode 100644 index 32452120db..0000000000 --- a/nuttx/configs/px4fmu-v1/src/up_userleds.c +++ /dev/null @@ -1,134 +0,0 @@ -/**************************************************************************** - * configs/stm32f4discovery/src/up_leds.c - * arch/arm/src/board/up_leds.c - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" -#include "stm32.h" -#include "px4fmu-v1-internal.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Definitions - ****************************************************************************/ - -/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG - * with CONFIG_DEBUG_VERBOSE too) - */ - -#ifdef CONFIG_DEBUG_LEDS -# define leddbg lldbg -# define ledvdbg llvdbg -#else -# define leddbg(x...) -# define ledvdbg(x...) -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ledinit - ****************************************************************************/ - -void stm32_ledinit(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: stm32_setled - ****************************************************************************/ - -void stm32_setled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: stm32_setleds - ****************************************************************************/ - -void stm32_setleds(uint8_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/nuttx/configs/px4fmu-v1/src/up_watchdog.c b/nuttx/configs/px4fmu-v1/src/up_watchdog.c deleted file mode 100644 index 4bef40f783..0000000000 --- a/nuttx/configs/px4fmu-v1/src/up_watchdog.c +++ /dev/null @@ -1,136 +0,0 @@ -/************************************************************************************ - * configs/stm32f4discovery/src/up_watchdog.c - * arch/arm/src/board/up_watchdog.c - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_wdg.h" - -#ifdef CONFIG_WATCHDOG - -/************************************************************************************ - * Definitions - ************************************************************************************/ -/* Configuration *******************************************************************/ -/* Wathdog hardware should be enabled */ - -#if !defined(CONFIG_STM32_WWDG) && !defined(CONFIG_STM32_IWDG) -# warning "One of CONFIG_STM32_WWDG or CONFIG_STM32_IWDG must be defined" -#endif - -/* Select the path to the registered watchdog timer device */ - -#ifndef CONFIG_STM32_WDG_DEVPATH -# ifdef CONFIG_EXAMPLES_WATCHDOG_DEVPATH -# define CONFIG_STM32_WDG_DEVPATH CONFIG_EXAMPLES_WATCHDOG_DEVPATH -# else -# define CONFIG_STM32_WDG_DEVPATH "/dev/watchdog0" -# endif -#endif - -/* Use the un-calibrated LSI frequency if we have nothing better */ - -#if defined(CONFIG_STM32_IWDG) && !defined(CONFIG_STM32_LSIFREQ) -# define CONFIG_STM32_LSIFREQ STM32_LSI_FREQUENCY -#endif - -/* Debug ***************************************************************************/ -/* Non-standard debug that may be enabled just for testing the watchdog timer */ - -#ifndef CONFIG_DEBUG -# undef CONFIG_DEBUG_WATCHDOG -#endif - -#ifdef CONFIG_DEBUG_WATCHDOG -# define wdgdbg dbg -# define wdglldbg lldbg -# ifdef CONFIG_DEBUG_VERBOSE -# define wdgvdbg vdbg -# define wdgllvdbg llvdbg -# else -# define wdgvdbg(x...) -# define wdgllvdbg(x...) -# endif -#else -# define wdgdbg(x...) -# define wdglldbg(x...) -# define wdgvdbg(x...) -# define wdgllvdbg(x...) -#endif - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/**************************************************************************** - * Name: up_wdginitialize() - * - * Description: - * Perform architecuture-specific initialization of the Watchdog hardware. - * This interface must be provided by all configurations using - * apps/examples/watchdog - * - ****************************************************************************/ - -int up_wdginitialize(void) -{ - /* Initialize tha register the watchdog timer device */ - -#if defined(CONFIG_STM32_WWDG) - stm32_wwdginitialize(CONFIG_STM32_WDG_DEVPATH); - return OK; -#elif defined(CONFIG_STM32_IWDG) - stm32_iwdginitialize(CONFIG_STM32_WDG_DEVPATH, CONFIG_STM32_LSIFREQ); - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_WATCHDOG */ diff --git a/nuttx/configs/px4io-v1/Kconfig b/nuttx/configs/px4io-v1/Kconfig new file mode 100644 index 0000000000..6bd2e8e21e --- /dev/null +++ b/nuttx/configs/px4io-v1/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_PX4IO_V1 + +endif diff --git a/nuttx/configs/px4io-v1/README.txt b/nuttx/configs/px4io-v1/README.txt new file mode 100755 index 0000000000..9b1615f42d --- /dev/null +++ b/nuttx/configs/px4io-v1/README.txt @@ -0,0 +1,806 @@ +README +====== + +This README discusses issues unique to NuttX configurations for the +STMicro STM3210E-EVAL development board. + +Contents +======== + + - Development Environment + - GNU Toolchain Options + - IDEs + - NuttX buildroot Toolchain + - DFU and JTAG + - OpenOCD + - LEDs + - Temperature Sensor + - RTC + - STM3210E-EVAL-specific Configuration Options + - Configurations + +Development Environment +======================= + + Either Linux or Cygwin on Windows can be used for the development environment. + The source has been built only using the GNU toolchain (see below). Other + toolchains will likely cause problems. Testing was performed using the Cygwin + environment because the Raisonance R-Link emulatator and some RIDE7 development tools + were used and those tools works only under Windows. + +GNU Toolchain Options +===================== + + The NuttX make system has been modified to support the following different + toolchain options. + + 1. The CodeSourcery GNU toolchain, + 2. The devkitARM GNU toolchain, + 3. Raisonance GNU toolchain, or + 4. The NuttX buildroot Toolchain (see below). + + All testing has been conducted using the NuttX buildroot toolchain. However, + the make system is setup to default to use the devkitARM toolchain. To use + the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to + add one of the following configuration options to your .config (or defconfig) + file: + + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_STM32_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_STM32_DEVKITARM=y : devkitARM under Windows + CONFIG_STM32_RAISONANCE=y : Raisonance RIDE7 under Windows + CONFIG_STM32_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + + If you are not using CONFIG_STM32_BUILDROOT, then you may also have to modify + the PATH in the setenv.h file if your make cannot find the tools. + + NOTE: the CodeSourcery (for Windows), devkitARM, and Raisonance toolchains are + Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot + toolchains are Cygwin and/or Linux native toolchains. There are several limitations + to using a Windows based toolchain in a Cygwin environment. The three biggest are: + + 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are + performed automatically in the Cygwin makefiles using the 'cygpath' utility + but you might easily find some new path problems. If so, check out 'cygpath -w' + + 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links + are used in Nuttx (e.g., include/arch). The make system works around these + problems for the Windows tools by copying directories instead of linking them. + But this can also cause some confusion for you: For example, you may edit + a file in a "linked" directory and find that your changes had no effect. + That is because you are building the copy of the file in the "fake" symbolic + directory. If you use a Windows toolchain, you should get in the habit of + making like this: + + make clean_context all + + An alias in your .bashrc file might make that less painful. + + 3. Dependencies are not made when using Windows versions of the GCC. This is + because the dependencies are generated using Windows pathes which do not + work with the Cygwin make. + + Support has been added for making dependencies with the windows-native toolchains. + That support can be enabled by modifying your Make.defs file as follows: + + - MKDEP = $(TOPDIR)/tools/mknulldeps.sh + + MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)" + + If you have problems with the dependency build (for example, if you are not + building on C:), then you may need to modify tools/mkdeps.sh + + NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization + level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with + -Os. + + NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that + the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM + path or will get the wrong version of make. + +IDEs +==== + + NuttX is built using command-line make. It can be used with an IDE, but some + effort will be required to create the project (There is a simple RIDE project + in the RIDE subdirectory). + + Makefile Build + -------------- + Under Eclipse, it is pretty easy to set up an "empty makefile project" and + simply use the NuttX makefile to build the system. That is almost for free + under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty + makefile project in order to work with Windows (Google for "Eclipse Cygwin" - + there is a lot of help on the internet). + + Native Build + ------------ + Here are a few tips before you start that effort: + + 1) Select the toolchain that you will be using in your .config file + 2) Start the NuttX build at least one time from the Cygwin command line + before trying to create your project. This is necessary to create + certain auto-generated files and directories that will be needed. + 3) Set up include pathes: You will need include/, arch/arm/src/stm32, + arch/arm/src/common, arch/arm/src/armv7-m, and sched/. + 4) All assembly files need to have the definition option -D __ASSEMBLY__ + on the command line. + + Startup files will probably cause you some headaches. The NuttX startup file + is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX + one time from the Cygwin command line in order to obtain the pre-built + startup object needed by RIDE. + +NuttX buildroot Toolchain +========================= + + A GNU GCC-based toolchain is assumed. The files */setenv.sh should + be modified to point to the correct path to the Cortex-M3 GCC toolchain (if + different from the default in your PATH variable). + + If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX + SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573). + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in /nuttx. + + cd tools + ./configure.sh stm3210e-eval/ + + 2. Download the latest buildroot package into + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename /buildroot-x.y.z to /buildroot. + + 4. cd /buildroot + + 5. cp configs/cortexm3-defconfig-4.3.3 .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly built binaries. + + See the file configs/README.txt in the buildroot source tree. That has more + detailed PLUS some special instructions that you will need to follow if you are + building a Cortex-M3 toolchain for Cygwin under Windows. + +DFU and JTAG +============ + + Enbling Support for the DFU Bootloader + -------------------------------------- + The linker files in these projects can be configured to indicate that you + will be loading code using STMicro built-in USB Device Firmware Upgrade (DFU) + loader or via some JTAG emulator. You can specify the DFU bootloader by + adding the following line: + + CONFIG_STM32_DFU=y + + to your .config file. Most of the configurations in this directory are set + up to use the DFU loader. + + If CONFIG_STM32_DFU is defined, the code will not be positioned at the beginning + of FLASH (0x08000000) but will be offset to 0x08003000. This offset is needed + to make space for the DFU loader and 0x08003000 is where the DFU loader expects + to find new applications at boot time. If you need to change that origin for some + other bootloader, you will need to edit the file(s) ld.script.dfu for each + configuration. + + The DFU SE PC-based software is available from the STMicro website, + http://www.st.com. General usage instructions: + + 1. Convert the NuttX Intel Hex file (nuttx.ihx) into a special DFU + file (nuttx.dfu)... see below for details. + 2. Connect the STM3210E-EVAL board to your computer using a USB + cable. + 3. Start the DFU loader on the STM3210E-EVAL board. You do this by + resetting the board while holding the "Key" button. Windows should + recognize that the DFU loader has been installed. + 3. Run the DFU SE program to load nuttx.dfu into FLASH. + + What if the DFU loader is not in FLASH? The loader code is available + inside of the Demo dirctory of the USBLib ZIP file that can be downloaded + from the STMicro Website. You can build it using RIDE (or other toolchains); + you will need a JTAG emulator to burn it into FLASH the first time. + + In order to use STMicro's built-in DFU loader, you will have to get + the NuttX binary into a special format with a .dfu extension. The + DFU SE PC_based software installation includes a file "DFU File Manager" + conversion program that a file in Intel Hex format to the special DFU + format. When you successfully build NuttX, you will find a file called + nutt.ihx in the top-level directory. That is the file that you should + provide to the DFU File Manager. You will need to rename it to nuttx.hex + in order to find it with the DFU File Manager. You will end up with + a file called nuttx.dfu that you can use with the STMicro DFU SE program. + + Enabling JTAG + ------------- + If you are not using the DFU, then you will probably also need to enable + JTAG support. By default, all JTAG support is disabled but there NuttX + configuration options to enable JTAG in various different ways. + + These configurations effect the setting of the SWJ_CFG[2:0] bits in the AFIO + MAPR register. These bits are used to configure the SWJ and trace alternate function I/Os. The SWJ (SerialWire JTAG) supports JTAG or SWD access to the + Cortex debug port. The default state in this port is for all JTAG support + to be disable. + + CONFIG_STM32_JTAG_FULL_ENABLE - sets SWJ_CFG[2:0] to 000 which enables full + SWJ (JTAG-DP + SW-DP) + + CONFIG_STM32_JTAG_NOJNTRST_ENABLE - sets SWJ_CFG[2:0] to 001 which enable + full SWJ (JTAG-DP + SW-DP) but without JNTRST. + + CONFIG_STM32_JTAG_SW_ENABLE - sets SWJ_CFG[2:0] to 010 which would set JTAG-DP + disabled and SW-DP enabled + + The default setting (none of the above defined) is SWJ_CFG[2:0] set to 100 + which disable JTAG-DP and SW-DP. + +OpenOCD +======= + +I have also used OpenOCD with the STM3210E-EVAL. In this case, I used +the Olimex USB ARM OCD. See the script in configs/stm3210e-eval/tools/oocd.sh +for more information. Using the script: + +1) Start the OpenOCD GDB server + + cd + configs/stm3210e-eval/tools/oocd.sh $PWD + +2) Load Nuttx + + cd + arm-none-eabi-gdb nuttx + gdb> target remote localhost:3333 + gdb> mon reset + gdb> mon halt + gdb> load nuttx + +3) Running NuttX + + gdb> mon reset + gdb> c + +LEDs +==== + +The STM3210E-EVAL board has four LEDs labeled LD1, LD2, LD3 and LD4 on the +board.. These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is +defined. In that case, the usage by the board port is defined in +include/board.h and src/up_leds.c. The LEDs are used to encode OS-related +events as follows: + + SYMBOL Meaning LED1* LED2 LED3 LED4 + ---------------- ----------------------- ----- ----- ----- ----- + LED_STARTED NuttX has been started ON OFF OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF + LED_IRQSENABLED Interrupts enabled ON ON OFF OFF + LED_STACKCREATED Idle stack created OFF OFF ON OFF + LED_INIRQ In an interrupt** ON N/C N/C OFF + LED_SIGNAL In a signal handler*** N/C ON N/C OFF + LED_ASSERTION An assertion failed ON ON N/C OFF + LED_PANIC The system has crashed N/C N/C N/C ON + LED_IDLE STM32 is is sleep mode (Optional, not used) + + * If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot + and these LEDs will give you some indication of where the failure was + ** The normal state is LED3 ON and LED1 faintly glowing. This faint glow + is because of timer interupts that result in the LED being illuminated + on a small proportion of the time. +*** LED2 may also flicker normally if signals are processed. + +Temperature Sensor +================== + +Support for the on-board LM-75 temperature sensor is available. This supported +has been verified, but has not been included in any of the available the +configurations. To set up the temperature sensor, add the following to the +NuttX configuration file + + CONFIG_I2C=y + CONFIG_I2C_LM75=y + +Then you can implement logic like the following to use the temperature sensor: + + #include + #include + + ret = stm32_lm75initialize("/dev/temp"); /* Register the temperature sensor */ + fd = open("/dev/temp", O_RDONLY); /* Open the temperature sensor device */ + ret = ioctl(fd, SNIOC_FAHRENHEIT, 0); /* Select Fahrenheit */ + bytesread = read(fd, buffer, 8*sizeof(b16_t)); /* Read temperature samples */ + +More complex temperature sensor operations are also available. See the IOCTAL +commands enumerated in include/nuttx/sensors/lm75.h. Also read the descriptions +of the stm32_lm75initialize() and stm32_lm75attach() interfaces in the +arch/board/board.h file (sames as configs/stm3210e-eval/include/board.h). + +RTC +=== + + The STM32 RTC may configured using the following settings. + + CONFIG_RTC - Enables general support for a hardware RTC. Specific + architectures may require other specific settings. + CONFIG_RTC_HIRES - The typical RTC keeps time to resolution of 1 + second, usually supporting a 32-bit time_t value. In this case, + the RTC is used to "seed" the normal NuttX timer and the + NuttX timer provides for higher resoution time. If CONFIG_RTC_HIRES + is enabled in the NuttX configuration, then the RTC provides higher + resolution time and completely replaces the system timer for purpose of + date and time. + CONFIG_RTC_FREQUENCY - If CONFIG_RTC_HIRES is defined, then the + frequency of the high resolution RTC must be provided. If CONFIG_RTC_HIRES + is not defined, CONFIG_RTC_FREQUENCY is assumed to be one. + CONFIG_RTC_ALARM - Enable if the RTC hardware supports setting of an alarm. + A callback function will be executed when the alarm goes off + + In hi-res mode, the STM32 RTC operates only at 16384Hz. Overflow interrupts + are handled when the 32-bit RTC counter overflows every 3 days and 43 minutes. + A BKP register is incremented on each overflow interrupt creating, effectively, + a 48-bit RTC counter. + + In the lo-res mode, the RTC operates at 1Hz. Overflow interrupts are not handled + (because the next overflow is not expected until the year 2106. + + WARNING: Overflow interrupts are lost whenever the STM32 is powered down. The + overflow interrupt may be lost even if the STM32 is powered down only momentarily. + Therefore hi-res solution is only useful in systems where the power is always on. + +STM3210E-EVAL-specific Configuration Options +============================================ + + CONFIG_ARCH - Identifies the arch/ subdirectory. This should + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM3=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP=stm32 + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_STM32F103ZET6 + + CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock + configuration features. + + CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD=stm3210e_eval (for the STM3210E-EVAL development board) + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_STM3210E_EVAL=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case): + + CONFIG_DRAM_SIZE=0x00010000 (64Kb) + + CONFIG_DRAM_START - The start address of installed DRAM + + CONFIG_DRAM_START=0x20000000 + + CONFIG_DRAM_END - Last address+1 of installed RAM + + CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE) + + CONFIG_ARCH_IRQPRIO - The STM32F103Z supports interrupt prioritization + + CONFIG_ARCH_IRQPRIO=y + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibratre + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + AHB + --- + CONFIG_STM32_DMA1 + CONFIG_STM32_DMA2 + CONFIG_STM32_CRC + CONFIG_STM32_FSMC + CONFIG_STM32_SDIO + + APB1 + ---- + CONFIG_STM32_TIM2 + CONFIG_STM32_TIM3 + CONFIG_STM32_TIM4 + CONFIG_STM32_TIM5 + CONFIG_STM32_TIM6 + CONFIG_STM32_TIM7 + CONFIG_STM32_WWDG + CONFIG_STM32_SPI2 + CONFIG_STM32_SPI4 + CONFIG_STM32_USART2 + CONFIG_STM32_USART3 + CONFIG_STM32_UART4 + CONFIG_STM32_UART5 + CONFIG_STM32_I2C1 + CONFIG_STM32_I2C2 + CONFIG_STM32_USB + CONFIG_STM32_CAN + CONFIG_STM32_BKP + CONFIG_STM32_PWR + CONFIG_STM32_DAC1 + CONFIG_STM32_DAC2 + CONFIG_STM32_USB + + APB2 + ---- + CONFIG_STM32_ADC1 + CONFIG_STM32_ADC2 + CONFIG_STM32_TIM1 + CONFIG_STM32_SPI1 + CONFIG_STM32_TIM8 + CONFIG_STM32_USART1 + CONFIG_STM32_ADC3 + + Timer and I2C devices may need to the following to force power to be applied + unconditionally at power up. (Otherwise, the device is powered when it is + initialized). + + CONFIG_STM32_FORCEPOWER + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn + is defined (as above) then the following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation, ADC conversion, + or DAC conversion. Note that ADC/DAC require two definition: Not only do you have + to assign the timer (n) for used by the ADC or DAC, but then you also have to + configure which ADC or DAC (m) it is assigned to. + + CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,8 + CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,8 + CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,8, m=1,..,3 + CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,8 + CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,8, m=1,..,2 + + For each timer that is enabled for PWM usage, we need the following additional + configuration settings: + + CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} + + NOTE: The STM32 timers are each capable of generating different signals on + each of the four channels with different duty cycles. That capability is + not supported by this driver: Only one output channel per timer. + + Alternate pin mappings (should not be used with the STM3210E-EVAL board): + + CONFIG_STM32_TIM1_FULL_REMAP + CONFIG_STM32_TIM1_PARTIAL_REMAP + CONFIG_STM32_TIM2_FULL_REMAP + CONFIG_STM32_TIM2_PARTIAL_REMAP_1 + CONFIG_STM32_TIM2_PARTIAL_REMAP_2 + CONFIG_STM32_TIM3_FULL_REMAP + CONFIG_STM32_TIM3_PARTIAL_REMAP + CONFIG_STM32_TIM4_REMAP + CONFIG_STM32_USART1_REMAP + CONFIG_STM32_USART2_REMAP + CONFIG_STM32_USART3_FULL_REMAP + CONFIG_STM32_USART3_PARTIAL_REMAP + CONFIG_STM32_SPI1_REMAP + CONFIG_STM32_SPI3_REMAP + CONFIG_STM32_I2C1_REMAP + CONFIG_STM32_CAN1_FULL_REMAP + CONFIG_STM32_CAN1_PARTIAL_REMAP + CONFIG_STM32_CAN2_REMAP + + JTAG Enable settings (by default JTAG-DP and SW-DP are disabled): + CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) + CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) + but without JNTRST. + CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled + + STM32F103Z specific device driver settings + + CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART + m (m=4,5) for the console and ttys0 (default is the USART1). + CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be + CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8. + CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + CONFIG_U[S]ARTn_2STOP - Two stop bits + + CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI + support. Non-interrupt-driven, poll-waiting is recommended if the + interrupt rate would be to high in the interrupt driven case. + CONFIG_STM32_SPI_DMA - Use DMA to improve SPI transfer performance. + Cannot be used with CONFIG_STM32_SPI_INTERRUPT. + + CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32_SDIO + and CONFIG_STM32_DMA2. + CONFIG_SDIO_PRI - Select SDIO interrupt prority. Default: 128 + CONFIG_SDIO_DMAPRIO - Select SDIO DMA interrupt priority. + Default: Medium + CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default: + 4-bit transfer mode. + + STM3210E-EVAL CAN Configuration + + CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or + CONFIG_STM32_CAN2 must also be defined) + CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default + Standard 11-bit IDs. + CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages. + Default: 8 + CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests. + Default: 4 + CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback + mode for testing. The STM32 CAN driver does support loopback mode. + CONFIG_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. + CONFIG_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. + CONFIG_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 + CONFIG_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7 + CONFIG_CAN_REGDEBUG - If CONFIG_DEBUG is set, this will generate an + dump of all CAN registers. + + STM3210E-EVAL LCD Hardware Configuration + + CONFIG_LCD_LANDSCAPE - Define for 320x240 display "landscape" + support. Default is this 320x240 "landscape" orientation + (this setting is informative only... not used). + CONFIG_LCD_PORTRAIT - Define for 240x320 display "portrait" + orientation support. In this orientation, the STM3210E-EVAL's + LCD ribbon cable is at the bottom of the display. Default is + 320x240 "landscape" orientation. + CONFIG_LCD_RPORTRAIT - Define for 240x320 display "reverse + portrait" orientation support. In this orientation, the + STM3210E-EVAL's LCD ribbon cable is at the top of the display. + Default is 320x240 "landscape" orientation. + CONFIG_LCD_BACKLIGHT - Define to support a backlight. + CONFIG_LCD_PWM - If CONFIG_STM32_TIM1 is also defined, then an + adjustable backlight will be provided using timer 1 to generate + various pulse widthes. The granularity of the settings is + determined by CONFIG_LCD_MAXPOWER. If CONFIG_LCD_PWM (or + CONFIG_STM32_TIM1) is not defined, then a simple on/off backlight + is provided. + CONFIG_LCD_RDSHIFT - When reading 16-bit gram data, there appears + to be a shift in the returned data. This value fixes the offset. + Default 5. + + The LCD driver dynamically selects the LCD based on the reported LCD + ID value. However, code size can be reduced by suppressing support for + individual LCDs using: + + CONFIG_STM32_AM240320_DISABLE + CONFIG_STM32_SPFD5408B_DISABLE + CONFIG_STM32_R61580_DISABLE + +Configurations +============== + +Each STM3210E-EVAL configuration is maintained in a sudirectory and +can be selected as follow: + + cd tools + ./configure.sh stm3210e-eval/ + cd - + . ./setenv.sh + +Where is one of the following: + + buttons: + -------- + + Uses apps/examples/buttons to exercise STM3210E-EVAL buttons and + button interrupts. + + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + + composite + --------- + + This configuration exercises a composite USB interface consisting + of a CDC/ACM device and a USB mass storage device. This configuration + uses apps/examples/composite. + + nsh and nsh2: + ------------ + Configure the NuttShell (nsh) located at examples/nsh. + + Differences between the two NSH configurations: + + =========== ======================= ================================ + nsh nsh2 + =========== ======================= ================================ + Toolchain: NuttX buildroot for Codesourcery for Windows (1) + Linux or Cygwin (1,2) + ----------- ----------------------- -------------------------------- + Loader: DfuSe DfuSe + ----------- ----------------------- -------------------------------- + Serial Debug output: USART1 Debug output: USART1 + Console: NSH output: USART1 NSH output: USART1 (3) + ----------- ----------------------- -------------------------------- + microSD Yes Yes + Support + ----------- ----------------------- -------------------------------- + FAT FS CONFIG_FAT_LCNAME=y CONFIG_FAT_LCNAME=y + Config CONFIG_FAT_LFN=n CONFIG_FAT_LFN=y (4) + ----------- ----------------------- -------------------------------- + Support for No Yes + Built-in + Apps + ----------- ----------------------- -------------------------------- + Built-in None apps/examples/nx + Apps apps/examples/nxhello + apps/examples/usbstorage (5) + =========== ======================= ================================ + + (1) You will probably need to modify nsh/setenv.sh or nsh2/setenv.sh + to set up the correct PATH variable for whichever toolchain you + may use. + (2) Since DfuSe is assumed, this configuration may only work under + Cygwin without modification. + (3) When any other device other than /dev/console is used for a user + interface, (1) linefeeds (\n) will not be expanded to carriage return + / linefeeds \r\n). You will need to configure your terminal program + to account for this. And (2) input is not automatically echoed so + you will have to turn local echo on. + (4) Microsoft holds several patents related to the design of + long file names in the FAT file system. Please refer to the + details in the top-level COPYING file. Please do not use FAT + long file name unless you are familiar with these patent issues. + (5) When built as an NSH add-on command (CONFIG_EXAMPLES_USBMSC_BUILTIN=y), + Caution should be used to assure that the SD drive is not in use when + the USB storage device is configured. Specifically, the SD driver + should be unmounted like: + + nsh> mount -t vfat /dev/mmcsd0 /mnt/sdcard # Card is mounted in NSH + ... + nsh> umount /mnd/sdcard # Unmount before connecting USB!!! + nsh> msconn # Connect the USB storage device + ... + nsh> msdis # Disconnect USB storate device + nsh> mount -t vfat /dev/mmcsd0 /mnt/sdcard # Restore the mount + + Failure to do this could result in corruption of the SD card format. + + nx: + --- + An example using the NuttX graphics system (NX). This example + focuses on general window controls, movement, mouse and keyboard + input. + + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_LCD_RPORTRAIT=y : 240x320 reverse portrait + + nxlines: + ------ + Another example using the NuttX graphics system (NX). This + example focuses on placing lines on the background in various + orientations. + + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_LCD_RPORTRAIT=y : 240x320 reverse portrait + + nxtext: + ------ + Another example using the NuttX graphics system (NX). This + example focuses on placing text on the background while pop-up + windows occur. Text should continue to update normally with + or without the popup windows present. + + CONFIG_STM32_BUILDROOT=y : NuttX buildroot under Linux or Cygwin + CONFIG_LCD_RPORTRAIT=y : 240x320 reverse portrait + + NOTE: When I tried building this example with the CodeSourcery + tools, I got a hardfault inside of its libgcc. I haven't + retested since then, but beware if you choose to change the + toolchain. + + ostest: + ------ + This configuration directory, performs a simple OS test using + examples/ostest. By default, this project assumes that you are + using the DFU bootloader. + + CONFIG_STM32_BUILDROOT=y : NuttX buildroot under Linux or Cygwin + + RIDE + ---- + This configuration builds a trivial bring-up binary. It is + useful only because it words with the RIDE7 IDE and R-Link debugger. + + CONFIG_STM32_RAISONANCE=y : Raisonance RIDE7 under Windows + + usbserial: + --------- + This configuration directory exercises the USB serial class + driver at examples/usbserial. See examples/README.txt for + more information. + + CONFIG_STM32_BUILDROOT=y : NuttX buildroot under Linux or Cygwin + + USB debug output can be enabled as by changing the following + settings in the configuration file: + + -CONFIG_DEBUG=n + -CONFIG_DEBUG_VERBOSE=n + -CONFIG_DEBUG_USB=n + +CONFIG_DEBUG=y + +CONFIG_DEBUG_VERBOSE=y + +CONFIG_DEBUG_USB=y + + -CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n + -CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n + -CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n + -CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n + -CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n + +CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=y + +CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=y + +CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=y + +CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=y + +CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=y + + By default, the usbserial example uses the Prolific PL2303 + serial/USB converter emulation. The example can be modified + to use the CDC/ACM serial class by making the following changes + to the configuration file: + + -CONFIG_PL2303=y + +CONFIG_PL2303=n + + -CONFIG_CDCACM=n + +CONFIG_CDCACM=y + + The example can also be converted to use the alternative + USB serial example at apps/examples/usbterm by changing the + following: + + -CONFIGURED_APPS += examples/usbserial + +CONFIGURED_APPS += examples/usbterm + + In either the original appconfig file (before configuring) + or in the final apps/.config file (after configuring). + + usbstorage: + ---------- + This configuration directory exercises the USB mass storage + class driver at examples/usbstorage. See examples/README.txt for + more information. + + CONFIG_STM32_BUILDROOT=y : NuttX buildroot under Linux or Cygwin + diff --git a/nuttx/configs/px4io-v1/common/Make.defs b/nuttx/configs/px4io-v1/common/Make.defs new file mode 100644 index 0000000000..7f782b5b22 --- /dev/null +++ b/nuttx/configs/px4io-v1/common/Make.defs @@ -0,0 +1,175 @@ +############################################################################ +# configs/px4fmu/common/Make.defs +# +# Copyright (C) 2011 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# +# Generic Make.defs for the PX4FMU +# Do not specify/use this file directly - it is included by config-specific +# Make.defs in the per-config directories. +# + +include ${TOPDIR}/tools/Config.mk + +# +# We only support building with the ARM bare-metal toolchain from +# https://launchpad.net/gcc-arm-embedded on Windows, Linux or Mac OS. +# +CONFIG_ARMV7M_TOOLCHAIN := GNU_EABI + +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +MAXOPTIMIZATION = -O3 +ARCHCPUFLAGS = -mcpu=cortex-m3 \ + -mthumb \ + -march=armv7-m + +# enable precise stack overflow tracking +#INSTRUMENTATIONDEFINES = -finstrument-functions \ +# -ffixed-r10 + +# use our linker script +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT)}" +else + ifeq ($(PX4_WINTOOL),y) + # Windows-native toolchains (MSYS) + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT) + else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT) + endif +endif + +# tool versions +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +# optimisation flags +ARCHOPTIMIZATION = $(MAXOPTIMIZATION) \ + -fno-strict-aliasing \ + -fno-strength-reduce \ + -fomit-frame-pointer \ + -funsafe-math-optimizations \ + -fno-builtin-printf \ + -ffunction-sections \ + -fdata-sections + +ifeq ("${CONFIG_DEBUG_SYMBOLS}","y") +ARCHOPTIMIZATION += -g +endif + +ARCHCFLAGS = -std=gnu99 +ARCHCXXFLAGS = -fno-exceptions -fno-rtti -std=gnu++0x +ARCHWARNINGS = -Wall \ + -Wextra \ + -Wdouble-promotion \ + -Wshadow \ + -Wfloat-equal \ + -Wframe-larger-than=1024 \ + -Wpointer-arith \ + -Wlogical-op \ + -Wmissing-declarations \ + -Wpacked \ + -Wno-unused-parameter +# -Wcast-qual - generates spurious noreturn attribute warnings, try again later +# -Wconversion - would be nice, but too many "risky-but-safe" conversions in the code +# -Wcast-align - would help catch bad casts in some cases, but generates too many false positives + +ARCHCWARNINGS = $(ARCHWARNINGS) \ + -Wbad-function-cast \ + -Wstrict-prototypes \ + -Wold-style-declaration \ + -Wmissing-parameter-type \ + -Wmissing-prototypes \ + -Wnested-externs \ + -Wunsuffixed-float-constants +ARCHWARNINGSXX = $(ARCHWARNINGS) +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +# this seems to be the only way to add linker flags +EXTRA_LIBS += --warn-common \ + --gc-sections + +CFLAGS = $(ARCHCFLAGS) $(ARCHCWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -fno-common +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +# produce partially-linked $1 from files in $2 +define PRELINK + @echo "PRELINK: $1" + $(Q) $(LD) -Ur -o $1 $2 && $(OBJCOPY) --localize-hidden $1 +endef + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + diff --git a/nuttx/configs/px4io-v1/common/ld.script b/nuttx/configs/px4io-v1/common/ld.script new file mode 100755 index 0000000000..69c2f9cb2e --- /dev/null +++ b/nuttx/configs/px4io-v1/common/ld.script @@ -0,0 +1,129 @@ +/**************************************************************************** + * configs/stm3210e-eval/nsh/ld.script + * + * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F100C8 has 64Kb of FLASH beginning at address 0x0800:0000 and + * 8Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08001000, LENGTH = 60K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +OUTPUT_ARCH(arm) +ENTRY(__start) /* treat __start as the anchor for dead code stripping */ +EXTERN(_vectors) /* force the vectors to be included in the output */ + +/* + * Ensure that abort() is present in the final object. The exception handling + * code pulled in by libgcc.a requires it (and that code cannot be easily avoided). + */ +EXTERN(abort) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + /* + * Init functions (static constructors and the like) + */ + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + /* The STM32F100CB has 8Kb of SRAM beginning at the following address */ + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/px4io-v1/common/setenv.sh b/nuttx/configs/px4io-v1/common/setenv.sh new file mode 100755 index 0000000000..ff9a4bf8ae --- /dev/null +++ b/nuttx/configs/px4io-v1/common/setenv.sh @@ -0,0 +1,47 @@ +#!/bin/bash +# configs/stm3210e-eval/dfu/setenv.sh +# +# Copyright (C) 2009 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$(basename $0)" = "setenv.sh" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi + +WD=`pwd` +export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin" +export BUILDROOT_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" +export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/px4io-v1/include/README.txt b/nuttx/configs/px4io-v1/include/README.txt new file mode 100755 index 0000000000..2264a80aa8 --- /dev/null +++ b/nuttx/configs/px4io-v1/include/README.txt @@ -0,0 +1 @@ +This directory contains header files unique to the PX4IO board. diff --git a/nuttx/configs/px4io-v1/include/board.h b/nuttx/configs/px4io-v1/include/board.h new file mode 100755 index 0000000000..668602ea89 --- /dev/null +++ b/nuttx/configs/px4io-v1/include/board.h @@ -0,0 +1,172 @@ +/************************************************************************************ + * configs/px4io/include/board.h + * include/arch/board/board.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Copyright (C) 2012 PX4 Development Team. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_BOARD_BOARD_H +#define __ARCH_BOARD_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +# include +#endif +#include +#include +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ + +/* On-board crystal frequency is 24MHz (HSE) */ + +#define STM32_BOARD_XTAL 24000000ul + +/* Use the HSE output as the system clock */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_HSE +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_HSE +#define STM32_SYSCLK_FREQUENCY STM32_BOARD_XTAL + +/* AHB clock (HCLK) is SYSCLK (24MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ + +/* APB2 clock (PCLK2) is HCLK (24MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-4 */ + +/* APB2 timer 1 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK (24MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* All timers run off PCLK */ + +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) + +/* + * Some of the USART pins are not available; override the GPIO + * definitions with an invalid pin configuration. + */ +#undef GPIO_USART2_CTS +#define GPIO_USART2_CTS 0xffffffff +#undef GPIO_USART2_RTS +#define GPIO_USART2_RTS 0xffffffff +#undef GPIO_USART2_CK +#define GPIO_USART2_CK 0xffffffff +#undef GPIO_USART3_TX +#define GPIO_USART3_TX 0xffffffff +#undef GPIO_USART3_CK +#define GPIO_USART3_CK 0xffffffff +#undef GPIO_USART3_CTS +#define GPIO_USART3_CTS 0xffffffff +#undef GPIO_USART3_RTS +#define GPIO_USART3_RTS 0xffffffff + +/* + * High-resolution timer + */ +#ifdef CONFIG_HRT_TIMER +# define HRT_TIMER 1 /* use timer1 for the HRT */ +# define HRT_TIMER_CHANNEL 2 /* use capture/compare channel 2 */ +#endif + +/* + * PPM + * + * PPM input is handled by the HRT timer. + * + * Pin is PA8, timer 1, channel 1 + */ +#if defined(CONFIG_HRT_TIMER) && defined (CONFIG_HRT_PPM) +# define HRT_PPM_CHANNEL 1 /* use capture/compare channel 1 */ +# define GPIO_PPM_IN GPIO_TIM1_CH1IN +#endif + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +EXTERN void stm32_boardinitialize(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_BOARD_BOARD_H */ diff --git a/nuttx/configs/px4io-v1/include/drv_i2c_device.h b/nuttx/configs/px4io-v1/include/drv_i2c_device.h new file mode 100644 index 0000000000..02582bc092 --- /dev/null +++ b/nuttx/configs/px4io-v1/include/drv_i2c_device.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * + * Copyright (C) 2012 PX4 Development Team. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name PX4 nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + + /** + * @file A simple, polled I2C slave-mode driver. + * + * The master writes to and reads from a byte buffer, which the caller + * can update inbetween calls to the FSM. + */ + +extern void i2c_fsm_init(uint8_t *buffer, size_t buffer_size); +extern bool i2c_fsm(void); diff --git a/nuttx/configs/px4io-v1/io/Make.defs b/nuttx/configs/px4io-v1/io/Make.defs new file mode 100644 index 0000000000..c7f6effd9a --- /dev/null +++ b/nuttx/configs/px4io-v1/io/Make.defs @@ -0,0 +1,3 @@ +include ${TOPDIR}/.config + +include $(TOPDIR)/configs/px4io-v1/common/Make.defs diff --git a/nuttx/configs/px4io-v1/io/appconfig b/nuttx/configs/px4io-v1/io/appconfig new file mode 100644 index 0000000000..48a41bcdb8 --- /dev/null +++ b/nuttx/configs/px4io-v1/io/appconfig @@ -0,0 +1,32 @@ +############################################################################ +# +# Copyright (C) 2012 PX4 Development Team. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name PX4 nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ diff --git a/nuttx/configs/px4io-v1/io/defconfig b/nuttx/configs/px4io-v1/io/defconfig new file mode 100755 index 0000000000..43dd1b0e85 --- /dev/null +++ b/nuttx/configs/px4io-v1/io/defconfig @@ -0,0 +1,552 @@ +############################################################################ +# configs/px4io/nsh/defconfig +# +# Copyright (C) 2012 PX4 Development Team. All rights reserved. +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ +# +# architecture selection +# +# CONFIG_ARCH - identifies the arch subdirectory and, hence, the +# processor architecture. +# CONFIG_ARCH_family - for use in C code. This identifies the +# particular chip family that the architecture is implemented +# in. +# CONFIG_ARCH_architecture - for use in C code. This identifies the +# specific architecture within the chip family. +# CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory +# CONFIG_ARCH_CHIP_name - For use in C code +# CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence, +# the board that supports the particular chip or SoC. +# CONFIG_ARCH_BOARD_name - for use in C code +# CONFIG_ENDIAN_BIG - define if big endian (default is little endian) +# CONFIG_BOARD_LOOPSPERMSEC - for delay loops +# CONFIG_DRAM_SIZE - Describes the installed DRAM. +# CONFIG_DRAM_START - The start address of DRAM (physical) +# CONFIG_ARCH_IRQPRIO - The ST32F100CB supports interrupt prioritization +# CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt +# stack. If defined, this symbol is the size of the interrupt +# stack in bytes. If not defined, the user task stacks will be +# used during interrupt handling. +# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions +# CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader. +# CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. +# CONFIG_ARCH_BUTTONS - Enable support for buttons. Unique to board architecture. +# CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that +# cause a 100 second delay during boot-up. This 100 second delay +# serves no purpose other than it allows you to calibrate +# CONFIG_BOARD_LOOPSPERMSEC. You simply use a stop watch to measure +# the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until +# the delay actually is 100 seconds. +# CONFIG_ARCH_DMA - Support DMA initialization +# +CONFIG_ARCH="arm" +CONFIG_ARCH_ARM=y +CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32F100C8=y +# +# Board Selection +# +CONFIG_ARCH_BOARD_PX4IO_V1=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="px4io-v1" +CONFIG_BOARD_LOOPSPERMSEC=2000 +CONFIG_DRAM_SIZE=0x00002000 +CONFIG_DRAM_START=0x20000000 +CONFIG_ARCH_IRQPRIO=y +CONFIG_ARCH_INTERRUPTSTACK=n +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_BOOTLOADER=n +CONFIG_ARCH_LEDS=n +CONFIG_ARCH_BUTTONS=n +CONFIG_ARCH_CALIBRATION=n +CONFIG_ARCH_DMA=y +CONFIG_ARCH_MATH_H=y + +CONFIG_ARMV7M_CMNVECTOR=y + +# +# JTAG Enable settings (by default JTAG-DP and SW-DP are disabled): +# +# CONFIG_STM32_DFU - Use the DFU bootloader, not JTAG +# +# JTAG Enable options: +# +# CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) +# but without JNTRST. +# CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled +# +CONFIG_STM32_DFU=n +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n +CONFIG_STM32_JTAG_SW_ENABLE=n + +# +# Individual subsystems can be enabled: +# +# AHB: +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=n +CONFIG_STM32_CRC=n +# APB1: +# Timers 2,3 and 4 are owned by the PWM driver +CONFIG_STM32_TIM2=n +CONFIG_STM32_TIM3=n +CONFIG_STM32_TIM4=n +CONFIG_STM32_TIM5=n +CONFIG_STM32_TIM6=n +CONFIG_STM32_TIM7=n +CONFIG_STM32_WWDG=n +CONFIG_STM32_SPI2=n +CONFIG_STM32_USART2=y +CONFIG_STM32_USART3=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C2=n +CONFIG_STM32_BKP=n +CONFIG_STM32_PWR=n +CONFIG_STM32_DAC=n +# APB2: +# We use our own ADC driver, but leave this on for clocking purposes. +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC2=n +# TIM1 is owned by the HRT +CONFIG_STM32_TIM1=n +CONFIG_STM32_SPI1=n +CONFIG_STM32_TIM8=n +CONFIG_STM32_USART1=y +CONFIG_STM32_ADC3=n + + +# +# STM32F100 specific serial device driver settings +# +# CONFIG_USARTn_SERIAL_CONSOLE - selects the USARTn for the +# console and ttys0 (default is the USART1). +# CONFIG_USARTn_RXBUFSIZE - Characters are buffered as received. +# This specific the size of the receive buffer +# CONFIG_USARTn_TXBUFSIZE - Characters are buffered before +# being sent. This specific the size of the transmit buffer +# CONFIG_USARTn_BAUD - The configure BAUD of the UART. Must be +# CONFIG_USARTn_BITS - The number of bits. Must be either 7 or 8. +# CONFIG_USARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity +# CONFIG_USARTn_2STOP - Two stop bits +# +CONFIG_SERIAL_TERMIOS=y +CONFIG_STANDARD_SERIAL=y + +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART2_SERIAL_CONSOLE=n +CONFIG_USART3_SERIAL_CONSOLE=n + +CONFIG_USART1_TXBUFSIZE=64 +CONFIG_USART2_TXBUFSIZE=64 +CONFIG_USART3_TXBUFSIZE=64 + +CONFIG_USART1_RXBUFSIZE=64 +CONFIG_USART2_RXBUFSIZE=64 +CONFIG_USART3_RXBUFSIZE=64 + +CONFIG_USART1_BAUD=115200 +CONFIG_USART2_BAUD=115200 +CONFIG_USART3_BAUD=115200 + +CONFIG_USART1_BITS=8 +CONFIG_USART2_BITS=8 +CONFIG_USART3_BITS=8 + +CONFIG_USART1_PARITY=0 +CONFIG_USART2_PARITY=0 +CONFIG_USART3_PARITY=0 + +CONFIG_USART1_2STOP=0 +CONFIG_USART2_2STOP=0 +CONFIG_USART3_2STOP=0 + +CONFIG_USART1_RXDMA=y +SERIAL_HAVE_CONSOLE_DMA=y +# Conflicts with I2C1 DMA +CONFIG_USART2_RXDMA=n +CONFIG_USART3_RXDMA=y + +# +# PX4IO specific driver settings +# +# CONFIG_HRT_TIMER +# Enables the high-resolution timer. The board definition must +# set HRT_TIMER and HRT_TIMER_CHANNEL to the timer and capture/ +# compare channels to be used. +# CONFIG_HRT_PPM +# Enables R/C PPM input using the HRT. The board definition must +# set HRT_PPM_CHANNEL to the timer capture/compare channel to be +# used, and define GPIO_PPM_IN to configure the appropriate timer +# GPIO. +# CONFIG_PWM_SERVO +# Enables the PWM servo driver. The driver configuration must be +# supplied by the board support at initialisation time. +# Note that USART2 must be disabled on the PX4 board for this to +# be available. +# +# +CONFIG_HRT_TIMER=y +CONFIG_HRT_PPM=y + +# +# General build options +# +# CONFIG_RRLOAD_BINARY - make the rrload binary format used with +# BSPs from www.ridgerun.com using the tools/mkimage.sh script +# CONFIG_INTELHEX_BINARY - make the Intel HEX binary format +# used with many different loaders using the GNU objcopy program +# Should not be selected if you are not using the GNU toolchain. +# CONFIG_MOTOROLA_SREC - make the Motorola S-Record binary format +# used with many different loaders using the GNU objcopy program +# Should not be selected if you are not using the GNU toolchain. +# CONFIG_RAW_BINARY - make a raw binary format file used with many +# different loaders using the GNU objcopy program. This option +# should not be selected if you are not using the GNU toolchain. +# CONFIG_HAVE_LIBM - toolchain supports libm.a +# +CONFIG_RRLOAD_BINARY=n +CONFIG_INTELHEX_BINARY=n +CONFIG_MOTOROLA_SREC=n +CONFIG_RAW_BINARY=y +CONFIG_HAVE_LIBM=n + +# +# General OS setup +# +# CONFIG_APPS_DIR - Identifies the relative path to the directory +# that builds the application to link with NuttX. Default: ../apps +# CONFIG_DEBUG - enables built-in debug options +# CONFIG_DEBUG_VERBOSE - enables verbose debug output +# CONFIG_DEBUG_SYMBOLS - build without optimization and with +# debug symbols (needed for use with a debugger). +# CONFIG_HAVE_CXX - Enable support for C++ +# CONFIG_HAVE_CXXINITIALIZE - The platform-specific logic includes support +# for initialization of static C++ instances for this architecture +# and for the selected toolchain (via up_cxxinitialize()). +# CONFIG_MM_REGIONS - If the architecture includes multiple +# regions of memory to allocate from, this specifies the +# number of memory regions that the memory manager must +# handle and enables the API mm_addregion(start, end); +# CONFIG_ARCH_LOWPUTC - architecture supports low-level, boot +# time console output +# CONFIG_MSEC_PER_TICK - The default system timer is 100Hz +# or MSEC_PER_TICK=10. This setting may be defined to +# inform NuttX that the processor hardware is providing +# system timer interrupts at some interrupt interval other +# than 10 msec. +# CONFIG_RR_INTERVAL - The round robin timeslice will be set +# this number of milliseconds; Round robin scheduling can +# be disabled by setting this value to zero. +# CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in +# scheduler to monitor system performance +# CONFIG_TASK_NAME_SIZE - Spcifies that maximum size of a +# task name to save in the TCB. Useful if scheduler +# instrumentation is selected. Set to zero to disable. +# CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY - +# Used to initialize the internal time logic. +# CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions. +# You would only need this if you are concerned about accurate +# time conversions in the past or in the distant future. +# CONFIG_JULIAN_TIME - Enables Julian time conversions. You +# would only need this if you are concerned about accurate +# time conversion in the distand past. You must also define +# CONFIG_GREGORIAN_TIME in order to use Julian time. +# CONFIG_DEV_CONSOLE - Set if architecture-specific logic +# provides /dev/console. Enables stdout, stderr, stdin. +# CONFIG_DEV_LOWCONSOLE - Use the simple, low-level serial console +# driver (minimul support) +# CONFIG_MUTEX_TYPES: Set to enable support for recursive and +# errorcheck mutexes. Enables pthread_mutexattr_settype(). +# CONFIG_PRIORITY_INHERITANCE : Set to enable support for priority +# inheritance on mutexes and semaphores. +# CONFIG_SEM_PREALLOCHOLDERS: This setting is only used if priority +# inheritance is enabled. It defines the maximum number of +# different threads (minus one) that can take counts on a +# semaphore with priority inheritance support. This may be +# set to zero if priority inheritance is disabled OR if you +# are only using semaphores as mutexes (only one holder) OR +# if no more than two threads participate using a counting +# semaphore. +# CONFIG_SEM_NNESTPRIO. If priority inheritance is enabled, +# then this setting is the maximum number of higher priority +# threads (minus 1) than can be waiting for another thread +# to release a count on a semaphore. This value may be set +# to zero if no more than one thread is expected to wait for +# a semaphore. +# CONFIG_FDCLONE_DISABLE. Disable cloning of all file descriptors +# by task_create() when a new task is started. If set, all +# files/drivers will appear to be closed in the new task. +# CONFIG_FDCLONE_STDIO. Disable cloning of all but the first +# three file descriptors (stdin, stdout, stderr) by task_create() +# when a new task is started. If set, all files/drivers will +# appear to be closed in the new task except for stdin, stdout, +# and stderr. +# CONFIG_SDCLONE_DISABLE. Disable cloning of all socket +# desciptors by task_create() when a new task is started. If +# set, all sockets will appear to be closed in the new task. +# CONFIG_SCHED_WORKQUEUE. Create a dedicated "worker" thread to +# handle delayed processing from interrupt handlers. This feature +# is required for some drivers but, if there are not complaints, +# can be safely disabled. The worker thread also performs +# garbage collection -- completing any delayed memory deallocations +# from interrupt handlers. If the worker thread is disabled, +# then that clean will be performed by the IDLE thread instead +# (which runs at the lowest of priority and may not be appropriate +# if memory reclamation is of high priority). If CONFIG_SCHED_WORKQUEUE +# is enabled, then the following options can also be used: +# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker +# thread. Default: 50 +# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for +# work in units of microseconds. Default: 50*1000 (50 MS). +# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker +# thread. Default: CONFIG_IDLETHREAD_STACKSIZE. +# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up +# the worker thread. Default: 4 +# CONFIG_SCHED_WAITPID - Enable the waitpid() API +# CONFIG_SCHED_ATEXIT - Enabled the atexit() API +# +CONFIG_USER_ENTRYPOINT="user_start" +#CONFIG_APPS_DIR= +CONFIG_DEBUG=n +CONFIG_DEBUG_VERBOSE=n +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_FS=n +CONFIG_DEBUG_GRAPHICS=n +CONFIG_DEBUG_LCD=n +CONFIG_DEBUG_USB=n +CONFIG_DEBUG_NET=n +CONFIG_DEBUG_RTC=n +CONFIG_DEBUG_ANALOG=n +CONFIG_DEBUG_PWM=n +CONFIG_DEBUG_CAN=n +CONFIG_DEBUG_I2C=n +CONFIG_DEBUG_INPUT=n + +CONFIG_MSEC_PER_TICK=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_MM_REGIONS=1 +CONFIG_MM_SMALL=y +CONFIG_ARCH_LOWPUTC=y +CONFIG_RR_INTERVAL=0 +CONFIG_SCHED_INSTRUMENTATION=n +CONFIG_TASK_NAME_SIZE=8 +CONFIG_START_YEAR=1970 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=1 +CONFIG_GREGORIAN_TIME=n +CONFIG_JULIAN_TIME=n +# this eats ~1KiB of RAM ... work out why +CONFIG_DEV_CONSOLE=y +CONFIG_DEV_LOWCONSOLE=n +CONFIG_MUTEX_TYPES=n +CONFIG_PRIORITY_INHERITANCE=n +CONFIG_SEM_PREALLOCHOLDERS=0 +CONFIG_SEM_NNESTPRIO=0 +CONFIG_FDCLONE_DISABLE=y +CONFIG_FDCLONE_STDIO=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SCHED_WORKQUEUE=n +CONFIG_SCHED_WORKPRIORITY=50 +CONFIG_SCHED_WORKPERIOD=50000 +CONFIG_SCHED_WORKSTACKSIZE=1024 +CONFIG_SIG_SIGWORK=4 +CONFIG_SCHED_WAITPID=n +CONFIG_SCHED_ATEXIT=n + +# +# The following can be used to disable categories of +# APIs supported by the OS. If the compiler supports +# weak functions, then it should not be necessary to +# disable functions unless you want to restrict usage +# of those APIs. +# +# There are certain dependency relationships in these +# features. +# +# o mq_notify logic depends on signals to awaken tasks +# waiting for queues to become full or empty. +# o pthread_condtimedwait() depends on signals to wake +# up waiting tasks. +# +CONFIG_DISABLE_CLOCK=n +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_DISABLE_SIGNALS=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_POLL=y + +# +# Misc libc settings +# +# CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a +# little smaller if we do not support fieldwidthes +# +CONFIG_NOPRINTF_FIELDWIDTH=n + +# +# Allow for architecture optimized implementations +# +# The architecture can provide optimized versions of the +# following to improve system performance +# +CONFIG_ARCH_MEMCPY=n +CONFIG_ARCH_MEMCMP=n +CONFIG_ARCH_MEMMOVE=n +CONFIG_ARCH_MEMSET=n +CONFIG_ARCH_STRCMP=n +CONFIG_ARCH_STRCPY=n +CONFIG_ARCH_STRNCPY=n +CONFIG_ARCH_STRLEN=n +CONFIG_ARCH_STRNLEN=n +CONFIG_ARCH_BZERO=n + +# +# Sizes of configurable things (0 disables) +# +# CONFIG_MAX_TASKS - The maximum number of simultaneously +# active tasks. This value must be a power of two. +# CONFIG_MAX_TASK_ARGS - This controls the maximum number of +# of parameters that a task may receive (i.e., maxmum value +# of 'argc') +# CONFIG_NPTHREAD_KEYS - The number of items of thread- +# specific data that can be retained +# CONFIG_NFILE_DESCRIPTORS - The maximum number of file +# descriptors (one for each open) +# CONFIG_NFILE_STREAMS - The maximum number of streams that +# can be fopen'ed +# CONFIG_NAME_MAX - The maximum size of a file name. +# CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate +# on fopen. (Only if CONFIG_NFILE_STREAMS > 0) +# CONFIG_STDIO_LINEBUFFER - If standard C buffered I/O is enabled +# (CONFIG_STDIO_BUFFER_SIZE > 0), then this option may be added +# to force automatic, line-oriented flushing the output buffer +# for putc(), fputc(), putchar(), puts(), fputs(), printf(), +# fprintf(), and vfprintf(). When a newline is encountered in +# the output string, the output buffer will be flushed. This +# (slightly) increases the NuttX footprint but supports the kind +# of behavior that people expect for printf(). +# CONFIG_NUNGET_CHARS - Number of characters that can be +# buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0) +# CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message +# structures. The system manages a pool of preallocated +# message structures to minimize dynamic allocations +# CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with +# a fixed payload size given by this settin (does not include +# other message structure overhead. +# CONFIG_MAX_WDOGPARMS - Maximum number of parameters that +# can be passed to a watchdog handler +# CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog +# structures. The system manages a pool of preallocated +# watchdog structures to minimize dynamic allocations +# CONFIG_PREALLOC_TIMERS - The number of pre-allocated POSIX +# timer structures. The system manages a pool of preallocated +# timer structures to minimize dynamic allocations. Set to +# zero for all dynamic allocations. +# +CONFIG_MAX_TASKS=4 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=0 +CONFIG_NAME_MAX=12 +CONFIG_STDIO_BUFFER_SIZE=32 +CONFIG_STDIO_LINEBUFFER=n +CONFIG_NUNGET_CHARS=2 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=0 + + +# +# Settings for apps/nshlib +# +# CONFIG_NSH_BUILTIN_APPS - Support external registered, +# "named" applications that can be executed from the NSH +# command line (see apps/README.txt for more information). +# CONFIG_NSH_FILEIOSIZE - Size of a static I/O buffer +# CONFIG_NSH_STRERROR - Use strerror(errno) +# CONFIG_NSH_LINELEN - Maximum length of one command line +# CONFIG_NSH_NESTDEPTH - Max number of nested if-then[-else]-fi +# CONFIG_NSH_DISABLESCRIPT - Disable scripting support +# CONFIG_NSH_DISABLEBG - Disable background commands +# CONFIG_NSH_ROMFSETC - Use startup script in /etc +# CONFIG_NSH_CONSOLE - Use serial console front end +# CONFIG_NSH_TELNET - Use telnetd console front end +# CONFIG_NSH_ARCHINIT - Platform provides architecture +# specific initialization (nsh_archinitialize()). +# + +# Disable NSH completely +CONFIG_NSH_CONSOLE=n + +# +# Stack and heap information +# +# CONFIG_BOOT_RUNFROMFLASH - Some configurations support XIP +# operation from FLASH but must copy initialized .data sections to RAM. +# (should also be =n for the STM3210E-EVAL which always runs from flash) +# CONFIG_BOOT_COPYTORAM - Some configurations boot in FLASH +# but copy themselves entirely into RAM for better performance. +# CONFIG_CUSTOM_STACK - The up_ implementation will handle +# all stack operations outside of the nuttx model. +# CONFIG_STACK_POINTER - The initial stack pointer (arm7tdmi only) +# CONFIG_IDLETHREAD_STACKSIZE - The size of the initial stack. +# This is the thread that (1) performs the inital boot of the system up +# to the point where user_start() is spawned, and (2) there after is the +# IDLE thread that executes only when there is no other thread ready to +# run. +# CONFIG_USERMAIN_STACKSIZE - The size of the stack to allocate +# for the main user thread that begins at the user_start() entry point. +# CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size +# CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size +# CONFIG_HEAP_BASE - The beginning of the heap +# CONFIG_HEAP_SIZE - The size of the heap +# +CONFIG_BOOT_RUNFROMFLASH=n +CONFIG_BOOT_COPYTORAM=n +CONFIG_CUSTOM_STACK=n +CONFIG_STACK_POINTER= +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=1200 +CONFIG_PTHREAD_STACK_MIN=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_HEAP_BASE= +CONFIG_HEAP_SIZE= diff --git a/nuttx/configs/px4io-v1/io/setenv.sh b/nuttx/configs/px4io-v1/io/setenv.sh new file mode 100755 index 0000000000..ff9a4bf8ae --- /dev/null +++ b/nuttx/configs/px4io-v1/io/setenv.sh @@ -0,0 +1,47 @@ +#!/bin/bash +# configs/stm3210e-eval/dfu/setenv.sh +# +# Copyright (C) 2009 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$(basename $0)" = "setenv.sh" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi + +WD=`pwd` +export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin" +export BUILDROOT_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" +export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/px4io-v1/nsh/Make.defs b/nuttx/configs/px4io-v1/nsh/Make.defs new file mode 100644 index 0000000000..87508e22ec --- /dev/null +++ b/nuttx/configs/px4io-v1/nsh/Make.defs @@ -0,0 +1,3 @@ +include ${TOPDIR}/.config + +include $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/Make.defs diff --git a/nuttx/configs/px4io-v1/nsh/appconfig b/nuttx/configs/px4io-v1/nsh/appconfig new file mode 100644 index 0000000000..d5809a9391 --- /dev/null +++ b/nuttx/configs/px4io-v1/nsh/appconfig @@ -0,0 +1,43 @@ +############################################################################ +# configs/stm3210e-eval/nsh/appconfig +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Path to example in apps/examples containing the user_start entry point + +CONFIGURED_APPS += examples/nsh + +CONFIGURED_APPS += system/readline +CONFIGURED_APPS += nshlib +CONFIGURED_APPS += reboot + diff --git a/nuttx/configs/px4io-v1/nsh/defconfig b/nuttx/configs/px4io-v1/nsh/defconfig new file mode 100755 index 0000000000..6f4e208691 --- /dev/null +++ b/nuttx/configs/px4io-v1/nsh/defconfig @@ -0,0 +1,565 @@ +############################################################################ +# configs/px4io/nsh/defconfig +# +# Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ +# +# architecture selection +# +# CONFIG_ARCH - identifies the arch subdirectory and, hence, the +# processor architecture. +# CONFIG_ARCH_family - for use in C code. This identifies the +# particular chip family that the architecture is implemented +# in. +# CONFIG_ARCH_architecture - for use in C code. This identifies the +# specific architecture within the chip familyl. +# CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory +# CONFIG_ARCH_CHIP_name - For use in C code +# CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence, +# the board that supports the particular chip or SoC. +# CONFIG_ARCH_BOARD_name - for use in C code +# CONFIG_ENDIAN_BIG - define if big endian (default is little endian) +# CONFIG_BOARD_LOOPSPERMSEC - for delay loops +# CONFIG_DRAM_SIZE - Describes the installed DRAM. +# CONFIG_DRAM_START - The start address of DRAM (physical) +# CONFIG_DRAM_END - Last address+1 of installed RAM +# CONFIG_ARCH_IRQPRIO - The ST32F100CB supports interrupt prioritization +# CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt +# stack. If defined, this symbol is the size of the interrupt +# stack in bytes. If not defined, the user task stacks will be +# used during interrupt handling. +# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions +# CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader. +# CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. +# CONFIG_ARCH_BUTTONS - Enable support for buttons. Unique to board architecture. +# CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that +# cause a 100 second delay during boot-up. This 100 second delay +# serves no purpose other than it allows you to calibrate +# CONFIG_BOARD_LOOPSPERMSEC. You simply use a stop watch to measure +# the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until +# the delay actually is 100 seconds. +# CONFIG_ARCH_DMA - Support DMA initialization +# +CONFIG_ARCH=arm +CONFIG_ARCH_ARM=y +CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_CHIP=stm32 +CONFIG_ARCH_CHIP_STM32F100C8=y +CONFIG_ARCH_BOARD=px4io +CONFIG_ARCH_BOARD_PX4IO=y +CONFIG_BOARD_LOOPSPERMSEC=24000 +CONFIG_DRAM_SIZE=0x00002000 +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE) +CONFIG_ARCH_IRQPRIO=y +CONFIG_ARCH_INTERRUPTSTACK=n +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_BOOTLOADER=n +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CALIBRATION=n +CONFIG_ARCH_DMA=n +CONFIG_ARMV7M_CMNVECTOR=y + +# +# JTAG Enable settings (by default JTAG-DP and SW-DP are disabled): +# +# CONFIG_STM32_DFU - Use the DFU bootloader, not JTAG +# +# JTAG Enable options: +# +# CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) +# but without JNTRST. +# CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled +# +CONFIG_STM32_DFU=n +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n +CONFIG_STM32_JTAG_SW_ENABLE=n + +# +# Individual subsystems can be enabled: +# AHB: +CONFIG_STM32_DMA1=n +CONFIG_STM32_DMA2=n +CONFIG_STM32_CRC=n +# APB1: +# Timers 2,3 and 4 are owned by the PWM driver +CONFIG_STM32_TIM2=n +CONFIG_STM32_TIM3=n +CONFIG_STM32_TIM4=n +CONFIG_STM32_TIM5=n +CONFIG_STM32_TIM6=n +CONFIG_STM32_TIM7=n +CONFIG_STM32_WWDG=n +CONFIG_STM32_SPI2=n +CONFIG_STM32_USART2=y +CONFIG_STM32_USART3=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C2=n +CONFIG_STM32_BKP=n +CONFIG_STM32_PWR=n +CONFIG_STM32_DAC=n +# APB2: +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC2=n +# TIM1 is owned by the HRT +CONFIG_STM32_TIM1=n +CONFIG_STM32_SPI1=n +CONFIG_STM32_TIM8=n +CONFIG_STM32_USART1=y +CONFIG_STM32_ADC3=n + +# +# Timer and I2C devices may need to the following to force power to be applied: +# +#CONFIG_STM32_FORCEPOWER=y + +# +# STM32F100 specific serial device driver settings +# +# CONFIG_USARTn_SERIAL_CONSOLE - selects the USARTn for the +# console and ttys0 (default is the USART1). +# CONFIG_USARTn_RXBUFSIZE - Characters are buffered as received. +# This specific the size of the receive buffer +# CONFIG_USARTn_TXBUFSIZE - Characters are buffered before +# being sent. This specific the size of the transmit buffer +# CONFIG_USARTn_BAUD - The configure BAUD of the UART. Must be +# CONFIG_USARTn_BITS - The number of bits. Must be either 7 or 8. +# CONFIG_USARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity +# CONFIG_USARTn_2STOP - Two stop bits +# +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART2_SERIAL_CONSOLE=n +CONFIG_USART3_SERIAL_CONSOLE=n + +CONFIG_USART1_TXBUFSIZE=64 +CONFIG_USART2_TXBUFSIZE=64 +CONFIG_USART3_TXBUFSIZE=64 + +CONFIG_USART1_RXBUFSIZE=64 +CONFIG_USART2_RXBUFSIZE=64 +CONFIG_USART3_RXBUFSIZE=64 + +CONFIG_USART1_BAUD=57600 +CONFIG_USART2_BAUD=115200 +CONFIG_USART3_BAUD=115200 + +CONFIG_USART1_BITS=8 +CONFIG_USART2_BITS=8 +CONFIG_USART3_BITS=8 + +CONFIG_USART1_PARITY=0 +CONFIG_USART2_PARITY=0 +CONFIG_USART3_PARITY=0 + +CONFIG_USART1_2STOP=0 +CONFIG_USART2_2STOP=0 +CONFIG_USART3_2STOP=0 + +# +# PX4IO specific driver settings +# +# CONFIG_HRT_TIMER +# Enables the high-resolution timer. The board definition must +# set HRT_TIMER and HRT_TIMER_CHANNEL to the timer and capture/ +# compare channels to be used. +# CONFIG_HRT_PPM +# Enables R/C PPM input using the HRT. The board definition must +# set HRT_PPM_CHANNEL to the timer capture/compare channel to be +# used, and define GPIO_PPM_IN to configure the appropriate timer +# GPIO. +# CONFIG_PWM_SERVO +# Enables the PWM servo driver. The driver configuration must be +# supplied by the board support at initialisation time. +# Note that USART2 must be disabled on the PX4 board for this to +# be available. +# +# +CONFIG_HRT_TIMER=y +CONFIG_HRT_PPM=y +CONFIG_PWM_SERVO=y + +# +# General build options +# +# CONFIG_RRLOAD_BINARY - make the rrload binary format used with +# BSPs from www.ridgerun.com using the tools/mkimage.sh script +# CONFIG_INTELHEX_BINARY - make the Intel HEX binary format +# used with many different loaders using the GNU objcopy program +# Should not be selected if you are not using the GNU toolchain. +# CONFIG_MOTOROLA_SREC - make the Motorola S-Record binary format +# used with many different loaders using the GNU objcopy program +# Should not be selected if you are not using the GNU toolchain. +# CONFIG_RAW_BINARY - make a raw binary format file used with many +# different loaders using the GNU objcopy program. This option +# should not be selected if you are not using the GNU toolchain. +# CONFIG_HAVE_LIBM - toolchain supports libm.a +# +CONFIG_RRLOAD_BINARY=n +CONFIG_INTELHEX_BINARY=n +CONFIG_MOTOROLA_SREC=n +CONFIG_RAW_BINARY=y +CONFIG_HAVE_LIBM=n + +# +# General OS setup +# +# CONFIG_APPS_DIR - Identifies the relative path to the directory +# that builds the application to link with NuttX. Default: ../apps +# CONFIG_DEBUG - enables built-in debug options +# CONFIG_DEBUG_VERBOSE - enables verbose debug output +# CONFIG_DEBUG_SYMBOLS - build without optimization and with +# debug symbols (needed for use with a debugger). +# CONFIG_HAVE_CXX - Enable support for C++ +# CONFIG_HAVE_CXXINITIALIZE - The platform-specific logic includes support +# for initialization of static C++ instances for this architecture +# and for the selected toolchain (via up_cxxinitialize()). +# CONFIG_MM_REGIONS - If the architecture includes multiple +# regions of memory to allocate from, this specifies the +# number of memory regions that the memory manager must +# handle and enables the API mm_addregion(start, end); +# CONFIG_ARCH_LOWPUTC - architecture supports low-level, boot +# time console output +# CONFIG_MSEC_PER_TICK - The default system timer is 100Hz +# or MSEC_PER_TICK=10. This setting may be defined to +# inform NuttX that the processor hardware is providing +# system timer interrupts at some interrupt interval other +# than 10 msec. +# CONFIG_RR_INTERVAL - The round robin timeslice will be set +# this number of milliseconds; Round robin scheduling can +# be disabled by setting this value to zero. +# CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in +# scheduler to monitor system performance +# CONFIG_TASK_NAME_SIZE - Spcifies that maximum size of a +# task name to save in the TCB. Useful if scheduler +# instrumentation is selected. Set to zero to disable. +# CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY - +# Used to initialize the internal time logic. +# CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions. +# You would only need this if you are concerned about accurate +# time conversions in the past or in the distant future. +# CONFIG_JULIAN_TIME - Enables Julian time conversions. You +# would only need this if you are concerned about accurate +# time conversion in the distand past. You must also define +# CONFIG_GREGORIAN_TIME in order to use Julian time. +# CONFIG_DEV_CONSOLE - Set if architecture-specific logic +# provides /dev/console. Enables stdout, stderr, stdin. +# CONFIG_DEV_LOWCONSOLE - Use the simple, low-level serial console +# driver (minimul support) +# CONFIG_MUTEX_TYPES: Set to enable support for recursive and +# errorcheck mutexes. Enables pthread_mutexattr_settype(). +# CONFIG_PRIORITY_INHERITANCE : Set to enable support for priority +# inheritance on mutexes and semaphores. +# CONFIG_SEM_PREALLOCHOLDERS: This setting is only used if priority +# inheritance is enabled. It defines the maximum number of +# different threads (minus one) that can take counts on a +# semaphore with priority inheritance support. This may be +# set to zero if priority inheritance is disabled OR if you +# are only using semaphores as mutexes (only one holder) OR +# if no more than two threads participate using a counting +# semaphore. +# CONFIG_SEM_NNESTPRIO. If priority inheritance is enabled, +# then this setting is the maximum number of higher priority +# threads (minus 1) than can be waiting for another thread +# to release a count on a semaphore. This value may be set +# to zero if no more than one thread is expected to wait for +# a semaphore. +# CONFIG_FDCLONE_DISABLE. Disable cloning of all file descriptors +# by task_create() when a new task is started. If set, all +# files/drivers will appear to be closed in the new task. +# CONFIG_FDCLONE_STDIO. Disable cloning of all but the first +# three file descriptors (stdin, stdout, stderr) by task_create() +# when a new task is started. If set, all files/drivers will +# appear to be closed in the new task except for stdin, stdout, +# and stderr. +# CONFIG_SDCLONE_DISABLE. Disable cloning of all socket +# desciptors by task_create() when a new task is started. If +# set, all sockets will appear to be closed in the new task. +# CONFIG_NXFLAT. Enable support for the NXFLAT binary format. +# This format will support execution of NuttX binaries located +# in a ROMFS filesystem (see examples/nxflat). +# CONFIG_SCHED_WORKQUEUE. Create a dedicated "worker" thread to +# handle delayed processing from interrupt handlers. This feature +# is required for some drivers but, if there are not complaints, +# can be safely disabled. The worker thread also performs +# garbage collection -- completing any delayed memory deallocations +# from interrupt handlers. If the worker thread is disabled, +# then that clean will be performed by the IDLE thread instead +# (which runs at the lowest of priority and may not be appropriate +# if memory reclamation is of high priority). If CONFIG_SCHED_WORKQUEUE +# is enabled, then the following options can also be used: +# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker +# thread. Default: 50 +# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for +# work in units of microseconds. Default: 50*1000 (50 MS). +# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker +# thread. Default: CONFIG_IDLETHREAD_STACKSIZE. +# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up +# the worker thread. Default: 4 +# +#CONFIG_APPS_DIR= +CONFIG_DEBUG=n +CONFIG_DEBUG_VERBOSE=n +CONFIG_DEBUG_SYMBOLS=y +CONFIG_HAVE_CXX=n +CONFIG_HAVE_CXXINITIALIZE=n +CONFIG_MM_REGIONS=1 +CONFIG_MM_SMALL=y +CONFIG_ARCH_LOWPUTC=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_INSTRUMENTATION=n +CONFIG_TASK_NAME_SIZE=0 +CONFIG_START_YEAR=2009 +CONFIG_START_MONTH=9 +CONFIG_START_DAY=21 +CONFIG_GREGORIAN_TIME=n +CONFIG_JULIAN_TIME=n +CONFIG_DEV_CONSOLE=y +CONFIG_DEV_LOWCONSOLE=n +CONFIG_MUTEX_TYPES=n +CONFIG_PRIORITY_INHERITANCE=n +CONFIG_SEM_PREALLOCHOLDERS=0 +CONFIG_SEM_NNESTPRIO=0 +CONFIG_FDCLONE_DISABLE=n +CONFIG_FDCLONE_STDIO=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_NXFLAT=n +CONFIG_SCHED_WORKQUEUE=n +CONFIG_SCHED_WORKPRIORITY=50 +CONFIG_SCHED_WORKPERIOD=(50*1000) +CONFIG_SCHED_WORKSTACKSIZE=512 +CONFIG_SIG_SIGWORK=4 + +# +# The following can be used to disable categories of +# APIs supported by the OS. If the compiler supports +# weak functions, then it should not be necessary to +# disable functions unless you want to restrict usage +# of those APIs. +# +# There are certain dependency relationships in these +# features. +# +# o mq_notify logic depends on signals to awaken tasks +# waiting for queues to become full or empty. +# o pthread_condtimedwait() depends on signals to wake +# up waiting tasks. +# +CONFIG_DISABLE_CLOCK=n +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=n +CONFIG_DISABLE_SIGNALS=n +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_POLL=y + +# +# Misc libc settings +# +# CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a +# little smaller if we do not support fieldwidthes +# +CONFIG_NOPRINTF_FIELDWIDTH=n + +# +# Allow for architecture optimized implementations +# +# The architecture can provide optimized versions of the +# following to improve system performance +# +CONFIG_ARCH_MEMCPY=n +CONFIG_ARCH_MEMCMP=n +CONFIG_ARCH_MEMMOVE=n +CONFIG_ARCH_MEMSET=n +CONFIG_ARCH_STRCMP=n +CONFIG_ARCH_STRCPY=n +CONFIG_ARCH_STRNCPY=n +CONFIG_ARCH_STRLEN=n +CONFIG_ARCH_STRNLEN=n +CONFIG_ARCH_BZERO=n + +# +# Sizes of configurable things (0 disables) +# +# CONFIG_MAX_TASKS - The maximum number of simultaneously +# active tasks. This value must be a power of two. +# CONFIG_MAX_TASK_ARGS - This controls the maximum number of +# of parameters that a task may receive (i.e., maxmum value +# of 'argc') +# CONFIG_NPTHREAD_KEYS - The number of items of thread- +# specific data that can be retained +# CONFIG_NFILE_DESCRIPTORS - The maximum number of file +# descriptors (one for each open) +# CONFIG_NFILE_STREAMS - The maximum number of streams that +# can be fopen'ed +# CONFIG_NAME_MAX - The maximum size of a file name. +# CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate +# on fopen. (Only if CONFIG_NFILE_STREAMS > 0) +# CONFIG_NUNGET_CHARS - Number of characters that can be +# buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0) +# CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message +# structures. The system manages a pool of preallocated +# message structures to minimize dynamic allocations +# CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with +# a fixed payload size given by this settin (does not include +# other message structure overhead. +# CONFIG_MAX_WDOGPARMS - Maximum number of parameters that +# can be passed to a watchdog handler +# CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog +# structures. The system manages a pool of preallocated +# watchdog structures to minimize dynamic allocations +# CONFIG_PREALLOC_TIMERS - The number of pre-allocated POSIX +# timer structures. The system manages a pool of preallocated +# timer structures to minimize dynamic allocations. Set to +# zero for all dynamic allocations. +# +CONFIG_MAX_TASKS=4 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=2 +CONFIG_NFILE_DESCRIPTORS=6 +CONFIG_NFILE_STREAMS=4 +CONFIG_NAME_MAX=32 +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_NUNGET_CHARS=2 +CONFIG_PREALLOC_MQ_MSGS=1 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=3 +CONFIG_PREALLOC_TIMERS=1 + + +# +# Settings for apps/nshlib +# +# CONFIG_NSH_BUILTIN_APPS - Support external registered, +# "named" applications that can be executed from the NSH +# command line (see apps/README.txt for more information). +# CONFIG_NSH_FILEIOSIZE - Size of a static I/O buffer +# CONFIG_NSH_STRERROR - Use strerror(errno) +# CONFIG_NSH_LINELEN - Maximum length of one command line +# CONFIG_NSH_NESTDEPTH - Max number of nested if-then[-else]-fi +# CONFIG_NSH_DISABLESCRIPT - Disable scripting support +# CONFIG_NSH_DISABLEBG - Disable background commands +# CONFIG_NSH_ROMFSETC - Use startup script in /etc +# CONFIG_NSH_CONSOLE - Use serial console front end +# CONFIG_NSH_TELNET - Use telnetd console front end +# CONFIG_NSH_ARCHINIT - Platform provides architecture +# specific initialization (nsh_archinitialize()). +# +# If CONFIG_NSH_TELNET is selected: +# CONFIG_NSH_IOBUFFER_SIZE -- Telnetd I/O buffer size +# CONFIG_NSH_DHCPC - Obtain address using DHCP +# CONFIG_NSH_IPADDR - Provides static IP address +# CONFIG_NSH_DRIPADDR - Provides static router IP address +# CONFIG_NSH_NETMASK - Provides static network mask +# CONFIG_NSH_NOMAC - Use a bogus MAC address +# +# If CONFIG_NSH_ROMFSETC is selected: +# CONFIG_NSH_ROMFSMOUNTPT - ROMFS mountpoint +# CONFIG_NSH_INITSCRIPT - Relative path to init script +# CONFIG_NSH_ROMFSDEVNO - ROMFS RAM device minor +# CONFIG_NSH_ROMFSSECTSIZE - ROMF sector size +# CONFIG_NSH_FATDEVNO - FAT FS RAM device minor +# CONFIG_NSH_FATSECTSIZE - FAT FS sector size +# CONFIG_NSH_FATNSECTORS - FAT FS number of sectors +# CONFIG_NSH_FATMOUNTPT - FAT FS mountpoint +# +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_STRERROR=n +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_NESTDEPTH=1 +CONFIG_NSH_DISABLESCRIPT=y +CONFIG_NSH_DISABLEBG=n +CONFIG_NSH_ROMFSETC=n +CONFIG_NSH_CONSOLE=y +CONFIG_NSH_TELNET=n +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_IOBUFFER_SIZE=256 +#CONFIG_NSH_STACKSIZE=1024 +CONFIG_NSH_DHCPC=n +CONFIG_NSH_NOMAC=n +CONFIG_NSH_IPADDR=(10<<24|0<<16|0<<8|2) +CONFIG_NSH_DRIPADDR=(10<<24|0<<16|0<<8|1) +CONFIG_NSH_NETMASK=(255<<24|255<<16|255<<8|0) +CONFIG_NSH_ROMFSMOUNTPT="/etc" +CONFIG_NSH_INITSCRIPT="init.d/rcS" +CONFIG_NSH_ROMFSDEVNO=0 +CONFIG_NSH_ROMFSSECTSIZE=64 +CONFIG_NSH_FATDEVNO=1 +CONFIG_NSH_FATSECTSIZE=512 +CONFIG_NSH_FATNSECTORS=1024 +CONFIG_NSH_FATMOUNTPT=/tmp + +# +# Architecture-specific NSH options +# +CONFIG_NSH_MMCSDSPIPORTNO=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDMINOR=0 + +# +# Stack and heap information +# +# CONFIG_BOOT_RUNFROMFLASH - Some configurations support XIP +# operation from FLASH but must copy initialized .data sections to RAM. +# (should also be =n for the STM3210E-EVAL which always runs from flash) +# CONFIG_BOOT_COPYTORAM - Some configurations boot in FLASH +# but copy themselves entirely into RAM for better performance. +# CONFIG_CUSTOM_STACK - The up_ implementation will handle +# all stack operations outside of the nuttx model. +# CONFIG_STACK_POINTER - The initial stack pointer (arm7tdmi only) +# CONFIG_IDLETHREAD_STACKSIZE - The size of the initial stack. +# This is the thread that (1) performs the inital boot of the system up +# to the point where user_start() is spawned, and (2) there after is the +# IDLE thread that executes only when there is no other thread ready to +# run. +# CONFIG_USERMAIN_STACKSIZE - The size of the stack to allocate +# for the main user thread that begins at the user_start() entry point. +# CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size +# CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size +# CONFIG_HEAP_BASE - The beginning of the heap +# CONFIG_HEAP_SIZE - The size of the heap +# +CONFIG_BOOT_RUNFROMFLASH=n +CONFIG_BOOT_COPYTORAM=n +CONFIG_CUSTOM_STACK=n +CONFIG_STACK_POINTER= +CONFIG_IDLETHREAD_STACKSIZE=800 +CONFIG_USERMAIN_STACKSIZE=1024 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=512 +CONFIG_HEAP_BASE= +CONFIG_HEAP_SIZE= diff --git a/nuttx/configs/px4io-v1/nsh/setenv.sh b/nuttx/configs/px4io-v1/nsh/setenv.sh new file mode 100755 index 0000000000..d836851921 --- /dev/null +++ b/nuttx/configs/px4io-v1/nsh/setenv.sh @@ -0,0 +1,47 @@ +#!/bin/bash +# configs/stm3210e-eval/dfu/setenv.sh +# +# Copyright (C) 2009 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$(basename $0)" = "setenv.sh" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi + +WD=`pwd` +export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin" +export BUILDROOT_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" +export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/px4io-v1/src/Makefile b/nuttx/configs/px4io-v1/src/Makefile new file mode 100644 index 0000000000..bb9539d16a --- /dev/null +++ b/nuttx/configs/px4io-v1/src/Makefile @@ -0,0 +1,84 @@ +############################################################################ +# configs/stm3210e-eval/src/Makefile +# +# Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +CFLAGS += -I$(TOPDIR)/sched + +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = empty.c + +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(WINTOOL),y) + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}" +else + CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m +endif + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + @$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + @touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/nuttx/configs/px4io-v1/src/README.txt b/nuttx/configs/px4io-v1/src/README.txt new file mode 100644 index 0000000000..d4eda82fd7 --- /dev/null +++ b/nuttx/configs/px4io-v1/src/README.txt @@ -0,0 +1 @@ +This directory contains drivers unique to the STMicro STM3210E-EVAL development board. diff --git a/nuttx/configs/px4io-v1/src/drv_i2c_device.c b/nuttx/configs/px4io-v1/src/drv_i2c_device.c new file mode 100644 index 0000000000..1f5931ae5e --- /dev/null +++ b/nuttx/configs/px4io-v1/src/drv_i2c_device.c @@ -0,0 +1,618 @@ +/**************************************************************************** + * + * Copyright (C) 2012 PX4 Development Team. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name PX4 nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + + /** + * @file A simple, polled I2C slave-mode driver. + * + * The master writes to and reads from a byte buffer, which the caller + * can update inbetween calls to the FSM. + */ + +#include + +#include "stm32_i2c.h" + +#include + +/* + * I2C register definitions. + */ +#define I2C_BASE STM32_I2C1_BASE + +#define REG(_reg) (*(volatile uint32_t *)(I2C_BASE + _reg)) + +#define rCR1 REG(STM32_I2C_CR1_OFFSET) +#define rCR2 REG(STM32_I2C_CR2_OFFSET) +#define rOAR1 REG(STM32_I2C_OAR1_OFFSET) +#define rOAR2 REG(STM32_I2C_OAR2_OFFSET) +#define rDR REG(STM32_I2C_DR_OFFSET) +#define rSR1 REG(STM32_I2C_SR1_OFFSET) +#define rSR2 REG(STM32_I2C_SR2_OFFSET) +#define rCCR REG(STM32_I2C_CCR_OFFSET) +#define rTRISE REG(STM32_I2C_TRISE_OFFSET) + +/* + * "event" values (cr2 << 16 | cr1) as described in the ST DriverLib + */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +/** + * States implemented by the I2C FSM. + */ +enum fsm_state { + BAD_PHASE, // must be zero, default exit on a bad state transition + + WAIT_FOR_MASTER, + + /* write from master */ + WAIT_FOR_COMMAND, + RECEIVE_COMMAND, + RECEIVE_DATA, + HANDLE_COMMAND, + + /* read from master */ + WAIT_TO_SEND, + SEND_STATUS, + SEND_DATA, + + NUM_STATES +}; + +/** + * Events recognised by the I2C FSM. + */ +enum fsm_event { + /* automatic transition */ + AUTO, + + /* write from master */ + ADDRESSED_WRITE, + BYTE_RECEIVED, + STOP_RECEIVED, + + /* read from master */ + ADDRESSED_READ, + BYTE_SENDABLE, + ACK_FAILED, + + NUM_EVENTS +}; + +/** + * Context for the I2C FSM + */ +static struct fsm_context { + enum fsm_state state; + + /* XXX want to eliminate these */ + uint8_t command; + uint8_t status; + + uint8_t *data_ptr; + uint32_t data_count; + + size_t buffer_size; + uint8_t *buffer; +} context; + +/** + * Structure defining one FSM state and its outgoing transitions. + */ +struct fsm_transition { + void (*handler)(void); + enum fsm_state next_state[NUM_EVENTS]; +}; + +static bool i2c_command_received; + +static void fsm_event(enum fsm_event event); + +static void go_bad(void); +static void go_wait_master(void); + +static void go_wait_command(void); +static void go_receive_command(void); +static void go_receive_data(void); +static void go_handle_command(void); + +static void go_wait_send(void); +static void go_send_status(void); +static void go_send_buffer(void); + +/** + * The FSM state graph. + */ +static const struct fsm_transition fsm[NUM_STATES] = { + [BAD_PHASE] = { + .handler = go_bad, + .next_state = { + [AUTO] = WAIT_FOR_MASTER, + }, + }, + + [WAIT_FOR_MASTER] = { + .handler = go_wait_master, + .next_state = { + [ADDRESSED_WRITE] = WAIT_FOR_COMMAND, + [ADDRESSED_READ] = WAIT_TO_SEND, + }, + }, + + /* write from master*/ + [WAIT_FOR_COMMAND] = { + .handler = go_wait_command, + .next_state = { + [BYTE_RECEIVED] = RECEIVE_COMMAND, + [STOP_RECEIVED] = WAIT_FOR_MASTER, + }, + }, + [RECEIVE_COMMAND] = { + .handler = go_receive_command, + .next_state = { + [BYTE_RECEIVED] = RECEIVE_DATA, + [STOP_RECEIVED] = HANDLE_COMMAND, + }, + }, + [RECEIVE_DATA] = { + .handler = go_receive_data, + .next_state = { + [BYTE_RECEIVED] = RECEIVE_DATA, + [STOP_RECEIVED] = HANDLE_COMMAND, + }, + }, + [HANDLE_COMMAND] = { + .handler = go_handle_command, + .next_state = { + [AUTO] = WAIT_FOR_MASTER, + }, + }, + + /* buffer send */ + [WAIT_TO_SEND] = { + .handler = go_wait_send, + .next_state = { + [BYTE_SENDABLE] = SEND_STATUS, + }, + }, + [SEND_STATUS] = { + .handler = go_send_status, + .next_state = { + [BYTE_SENDABLE] = SEND_DATA, + [ACK_FAILED] = WAIT_FOR_MASTER, + }, + }, + [SEND_DATA] = { + .handler = go_send_buffer, + .next_state = { + [BYTE_SENDABLE] = SEND_DATA, + [ACK_FAILED] = WAIT_FOR_MASTER, + }, + }, +}; + + +/* debug support */ +#if 1 +struct fsm_logentry { + char kind; + uint32_t code; +}; + +#define LOG_ENTRIES 32 +static struct fsm_logentry fsm_log[LOG_ENTRIES]; +int fsm_logptr; +#define LOG_NEXT(_x) (((_x) + 1) % LOG_ENTRIES) +#define LOGx(_kind, _code) \ + do { \ + fsm_log[fsm_logptr].kind = _kind; \ + fsm_log[fsm_logptr].code = _code; \ + fsm_logptr = LOG_NEXT(fsm_logptr); \ + fsm_log[fsm_logptr].kind = 0; \ + } while(0) + +#define LOG(_kind, _code) \ + do {\ + if (fsm_logptr < LOG_ENTRIES) { \ + fsm_log[fsm_logptr].kind = _kind; \ + fsm_log[fsm_logptr].code = _code; \ + fsm_logptr++;\ + }\ + }while(0) + +#else +#define LOG(_kind, _code) +#endif + + +static void i2c_setclock(uint32_t frequency); + +/** + * Initialise I2C + * + */ +void +i2c_fsm_init(uint8_t *buffer, size_t buffer_size) +{ + /* save the buffer */ + context.buffer = buffer; + context.buffer_size = buffer_size; + + // initialise the FSM + context.status = 0; + context.command = 0; + context.state = BAD_PHASE; + fsm_event(AUTO); + +#if 0 + // enable the i2c block clock and reset it + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_I2C1EN); + modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_I2C1RST); + modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST, 0); + + // configure the i2c GPIOs + stm32_configgpio(GPIO_I2C1_SCL); + stm32_configgpio(GPIO_I2C1_SDA); + + // set the peripheral clock to match the APB clock + rCR2 = STM32_PCLK1_FREQUENCY / 1000000; + + // configure for 100kHz operation + i2c_setclock(100000); + + // enable i2c + rCR1 = I2C_CR1_PE; +#endif +} + +/** + * Run the I2C FSM for some period. + * + * @return True if the buffer has been updated by a command. + */ +bool +i2c_fsm(void) +{ + uint32_t event; + int idle_iterations = 0; + + for (;;) { + // handle bus error states by discarding the current operation + if (rSR1 & I2C_SR1_BERR) { + context.state = WAIT_FOR_MASTER; + rSR1 = ~I2C_SR1_BERR; + } + + // we do not anticipate over/underrun errors as clock-stretching is enabled + + // fetch the most recent event + event = ((rSR2 << 16) | rSR1) & 0x00ffffff; + + // generate FSM events based on I2C events + switch (event) { + case I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: + LOG('w', 0); + fsm_event(ADDRESSED_WRITE); + break; + + case I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: + LOG('r', 0); + fsm_event(ADDRESSED_READ); + break; + + case I2C_EVENT_SLAVE_BYTE_RECEIVED: + LOG('R', 0); + fsm_event(BYTE_RECEIVED); + break; + + case I2C_EVENT_SLAVE_STOP_DETECTED: + LOG('s', 0); + fsm_event(STOP_RECEIVED); + break; + + case I2C_EVENT_SLAVE_BYTE_TRANSMITTING: + //case I2C_EVENT_SLAVE_BYTE_TRANSMITTED: + LOG('T', 0); + fsm_event(BYTE_SENDABLE); + break; + + case I2C_EVENT_SLAVE_ACK_FAILURE: + LOG('a', 0); + fsm_event(ACK_FAILED); + break; + + default: + idle_iterations++; +// if ((event) && (event != 0x00020000)) +// LOG('e', event); + break; + } + + /* if we have just received something, drop out and let the caller handle it */ + if (i2c_command_received) { + i2c_command_received = false; + return true; + } + + /* if we have done nothing recently, drop out and let the caller have a slice */ + if (idle_iterations > 1000) + return false; + } +} + +/** + * Update the FSM with an event + * + * @param event New event. + */ +static void +fsm_event(enum fsm_event event) +{ + // move to the next state + context.state = fsm[context.state].next_state[event]; + + LOG('f', context.state); + + // call the state entry handler + if (fsm[context.state].handler) { + fsm[context.state].handler(); + } +} + +static void +go_bad() +{ + LOG('B', 0); + fsm_event(AUTO); +} + +/** + * Wait for the master to address us. + * + */ +static void +go_wait_master() +{ + // We currently don't have a command byte. + // + context.command = '\0'; + + // The data pointer starts pointing to the start of the data buffer. + // + context.data_ptr = context.buffer; + + // The data count is either: + // - the size of the data buffer + // - some value less than or equal the size of the data buffer during a write or a read + // + context.data_count = context.buffer_size; + + // (re)enable the peripheral, clear the stop event flag in + // case we just finished receiving data + rCR1 |= I2C_CR1_PE; + + // clear the ACK failed flag in case we just finished sending data + rSR1 = ~I2C_SR1_AF; +} + +/** + * Prepare to receive a command byte. + * + */ +static void +go_wait_command() +{ + // NOP +} + +/** + * Command byte has been received, save it and prepare to handle the data. + * + */ +static void +go_receive_command() +{ + + // fetch the command byte + context.command = (uint8_t)rDR; + LOG('c', context.command); + +} + +/** + * Receive a data byte. + * + */ +static void +go_receive_data() +{ + uint8_t d; + + // fetch the byte + d = (uint8_t)rDR; + LOG('d', d); + + // if we have somewhere to put it, do so + if (context.data_count) { + *context.data_ptr++ = d; + context.data_count--; + } +} + +/** + * Handle a command once the host is done sending it to us. + * + */ +static void +go_handle_command() +{ + // presume we are happy with the command + context.status = 0; + + // make a note that the buffer contains a fresh command + i2c_command_received = true; + + // kick along to the next state + fsm_event(AUTO); +} + +/** + * Wait to be able to send the status byte. + * + */ +static void +go_wait_send() +{ + // NOP +} + +/** + * Send the status byte. + * + */ +static void +go_send_status() +{ + rDR = context.status; + LOG('?', context.status); +} + +/** + * Send a data or pad byte. + * + */ +static void +go_send_buffer() +{ + if (context.data_count) { + LOG('D', *context.data_ptr); + rDR = *(context.data_ptr++); + context.data_count--; + } else { + LOG('-', 0); + rDR = 0xff; + } +} + +/* cribbed directly from the NuttX master driver */ +static void +i2c_setclock(uint32_t frequency) +{ + uint16_t cr1; + uint16_t ccr; + uint16_t trise; + uint16_t freqmhz; + uint16_t speed; + + /* Disable the selected I2C peripheral to configure TRISE */ + + cr1 = rCR1; + rCR1 &= ~I2C_CR1_PE; + + /* Update timing and control registers */ + + freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000); + ccr = 0; + + /* Configure speed in standard mode */ + + if (frequency <= 100000) { + /* Standard mode speed calculation */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1)); + + /* The CCR fault must be >= 4 */ + + if (speed < 4) { + /* Set the minimum allowed value */ + + speed = 4; + } + ccr |= speed; + + /* Set Maximum Rise Time for standard mode */ + + trise = freqmhz + 1; + + /* Configure speed in fast mode */ + } else { /* (frequency <= 400000) */ + /* Fast mode speed calculation with Tlow/Thigh = 16/9 */ + +#ifdef CONFIG_I2C_DUTY16_9 + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25)); + + /* Set DUTY and fast speed bits */ + + ccr |= (I2C_CCR_DUTY|I2C_CCR_FS); +#else + /* Fast mode speed calculation with Tlow/Thigh = 2 */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3)); + + /* Set fast speed bit */ + + ccr |= I2C_CCR_FS; +#endif + + /* Verify that the CCR speed value is nonzero */ + + if (speed < 1) { + /* Set the minimum allowed value */ + + speed = 1; + } + ccr |= speed; + + /* Set Maximum Rise Time for fast mode */ + + trise = (uint16_t)(((freqmhz * 300) / 1000) + 1); + } + + /* Write the new values of the CCR and TRISE registers */ + + rCCR = ccr; + rTRISE = trise; + + /* Bit 14 of OAR1 must be configured and kept at 1 */ + + rOAR1 = I2C_OAR1_ONE); + + /* Re-enable the peripheral (or not) */ + + rCR1 = cr1; +} diff --git a/nuttx/configs/px4io-v1/src/empty.c b/nuttx/configs/px4io-v1/src/empty.c new file mode 100644 index 0000000000..ace900866c --- /dev/null +++ b/nuttx/configs/px4io-v1/src/empty.c @@ -0,0 +1,4 @@ +/* + * There are no source files here, but libboard.a can't be empty, so + * we have this empty source file to keep it company. + */ From 3fb9aafb384fad9c27eeef93d7344104fed0e5b7 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sat, 1 Jun 2013 01:02:20 +0200 Subject: [PATCH 04/41] Config updates --- nuttx/configs/px4fmu-v1/nsh/Make.defs | 110 +------------------ nuttx/configs/px4fmu-v1/nsh/defconfig | 150 +++++++++++++++++++------- nuttx/configs/px4fmu-v1/nsh/setenv.sh | 4 +- 3 files changed, 112 insertions(+), 152 deletions(-) diff --git a/nuttx/configs/px4fmu-v1/nsh/Make.defs b/nuttx/configs/px4fmu-v1/nsh/Make.defs index 8e75d971ed..81936334b3 100644 --- a/nuttx/configs/px4fmu-v1/nsh/Make.defs +++ b/nuttx/configs/px4fmu-v1/nsh/Make.defs @@ -1,111 +1,3 @@ -############################################################################ -# configs/stm32f4discovery/nsh/Make.defs -# -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mknulldeps.sh - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" - MAXOPTIMIZATION = -O2 -else - # Linux/Cygwin-native toolchain - MKDEP = $(TOPDIR)/tools/mkdeps.sh - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -else - ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -ARCHWARNINGSXX = -Wall -Wshadow -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe -HOSTLDFLAGS = +include $(TOPDIR)/configs/px4fmu-v1/common/Make.defs diff --git a/nuttx/configs/px4fmu-v1/nsh/defconfig b/nuttx/configs/px4fmu-v1/nsh/defconfig index 444f296cfc..963d71a897 100644 --- a/nuttx/configs/px4fmu-v1/nsh/defconfig +++ b/nuttx/configs/px4fmu-v1/nsh/defconfig @@ -31,7 +31,7 @@ CONFIG_RAW_BINARY=y # Customize Header Files # # CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set +CONFIG_ARCH_MATH_H=y # CONFIG_ARCH_FLOAT_H is not set # CONFIG_ARCH_STDARG_H is not set @@ -65,6 +65,7 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_IMX is not set # CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set # CONFIG_ARCH_CHIP_LM is not set # CONFIG_ARCH_CHIP_LPC17XX is not set # CONFIG_ARCH_CHIP_LPC214X is not set @@ -95,6 +96,24 @@ CONFIG_SERIAL_TERMIOS=y # # STM32 Configuration Options # +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set # CONFIG_ARCH_CHIP_STM32F100C8 is not set # CONFIG_ARCH_CHIP_STM32F100CB is not set # CONFIG_ARCH_CHIP_STM32F100R8 is not set @@ -107,6 +126,8 @@ CONFIG_SERIAL_TERMIOS=y # CONFIG_ARCH_CHIP_STM32F100VC is not set # CONFIG_ARCH_CHIP_STM32F100VD is not set # CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set # CONFIG_ARCH_CHIP_STM32F103RET6 is not set # CONFIG_ARCH_CHIP_STM32F103VCT6 is not set # CONFIG_ARCH_CHIP_STM32F103VET6 is not set @@ -138,6 +159,17 @@ CONFIG_ARCH_CHIP_STM32F405RG=y # CONFIG_ARCH_CHIP_STM32F427V is not set # CONFIG_ARCH_CHIP_STM32F427Z is not set # CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F30XX is not set CONFIG_STM32_STM32F40XX=y # CONFIG_STM32_DFU is not set @@ -164,7 +196,6 @@ CONFIG_STM32_DMA2=y CONFIG_STM32_I2C1=y CONFIG_STM32_I2C2=y CONFIG_STM32_I2C3=y -# CONFIG_STM32_IWDG is not set CONFIG_STM32_OTGFS=y # CONFIG_STM32_OTGHS is not set CONFIG_STM32_PWR=y @@ -194,7 +225,8 @@ CONFIG_STM32_USART2=y # CONFIG_STM32_UART4 is not set CONFIG_STM32_UART5=y CONFIG_STM32_USART6=y -CONFIG_STM32_WWDG=y +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set CONFIG_STM32_ADC=y CONFIG_STM32_SPI=y CONFIG_STM32_I2C=y @@ -207,6 +239,7 @@ CONFIG_STM32_FLASH_PREFETCH=y # CONFIG_STM32_JTAG_FULL_ENABLE is not set # CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set # CONFIG_STM32_FORCEPOWER is not set # CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set # CONFIG_STM32_CCMEXCLUDE is not set @@ -234,7 +267,7 @@ CONFIG_UART5_RXDMA=y CONFIG_USART6_RXDMA=y # CONFIG_USART7_RXDMA is not set # CONFIG_USART8_RXDMA is not set -# CONFIG_STM32_USART_SINGLEWIRE is not set +CONFIG_STM32_USART_SINGLEWIRE=y # # SPI Configuration @@ -245,10 +278,10 @@ CONFIG_USART6_RXDMA=y # # I2C Configuration # -CONFIG_STM32_I2C_DYNTIMEO=y -CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=500 -CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=1000 +# CONFIG_STM32_I2C_DYNTIMEO is not set CONFIG_STM32_I2CTIMEOSEC=0 +CONFIG_STM32_I2CTIMEOMS=500 +CONFIG_STM32_I2CTIMEOTICKS=500 # CONFIG_STM32_I2C_DUTY16_9 is not set # @@ -312,7 +345,7 @@ CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y CONFIG_NSH_MMCSDMINOR=0 CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=3 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options @@ -323,15 +356,15 @@ CONFIG_NSH_MMCSDSPIPORTNO=3 # # CONFIG_BOARD_INITIALIZE is not set CONFIG_MSEC_PER_TICK=1 -CONFIG_RR_INTERVAL=10 +CONFIG_RR_INTERVAL=5 # CONFIG_SCHED_INSTRUMENTATION is not set -CONFIG_TASK_NAME_SIZE=16 +CONFIG_TASK_NAME_SIZE=24 # CONFIG_SCHED_HAVE_PARENT is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 CONFIG_START_MONTH=12 CONFIG_START_DAY=6 -CONFIG_DEV_CONSOLE=y +# CONFIG_DEV_CONSOLE is not set # CONFIG_MUTEX_TYPES is not set CONFIG_PRIORITY_INHERITANCE=y CONFIG_SEM_PREALLOCHOLDERS=16 @@ -345,7 +378,13 @@ CONFIG_SCHED_ATEXIT=y CONFIG_SCHED_ATEXIT_MAX=1 # CONFIG_SCHED_ONEXIT is not set CONFIG_USER_ENTRYPOINT="nsh_main" -# CONFIG_DISABLE_OS_API is not set +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set # # Signal Numbers @@ -360,7 +399,7 @@ CONFIG_SIG_SIGWORK=17 # Sizes of configurable things (0 disables) # CONFIG_MAX_TASKS=16 -CONFIG_MAX_TASK_ARGS=4 +CONFIG_MAX_TASK_ARGS=10 CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 @@ -374,7 +413,7 @@ CONFIG_PREALLOC_TIMERS=4 # # Stack and heap information # -CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_USERMAIN_STACKSIZE=2048 CONFIG_PTHREAD_STACK_MIN=256 CONFIG_PTHREAD_STACK_DEFAULT=2048 @@ -402,8 +441,9 @@ CONFIG_SPI=y CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_RTC is not set -CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set # CONFIG_LCD is not set @@ -411,7 +451,7 @@ CONFIG_MMCSD=y CONFIG_MMCSD_NSLOTS=1 # CONFIG_MMCSD_READONLY is not set # CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set -CONFIG_MMCSD_MMCSUPPORT=y +# CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_MMCSD_HAVECARDDETECT is not set CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SPICLOCK=20000000 @@ -421,9 +461,9 @@ CONFIG_PIPES=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set +CONFIG_SERIAL_REMOVABLE=y # CONFIG_16550_UART is not set CONFIG_ARCH_HAVE_UART5=y CONFIG_ARCH_HAVE_USART1=y @@ -431,11 +471,11 @@ CONFIG_ARCH_HAVE_USART2=y CONFIG_ARCH_HAVE_USART6=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y -CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_USART1_SERIAL_CONSOLE is not set # CONFIG_USART2_SERIAL_CONSOLE is not set # CONFIG_UART5_SERIAL_CONSOLE is not set # CONFIG_USART6_SERIAL_CONSOLE is not set -# CONFIG_NO_SERIAL_CONSOLE is not set +CONFIG_NO_SERIAL_CONSOLE=y # # USART1 Configuration @@ -485,6 +525,7 @@ CONFIG_USBDEV=y # CONFIG_USBDEV_DUALSPEED is not set CONFIG_USBDEV_SELFPOWERED=y # CONFIG_USBDEV_BUSPOWERED is not set +CONFIG_USBDEV_MAXPOWER=500 # CONFIG_USBDEV_DMA is not set # CONFIG_USBDEV_TRACE is not set @@ -493,7 +534,26 @@ CONFIG_USBDEV_SELFPOWERED=y # # CONFIG_USBDEV_COMPOSITE is not set # CONFIG_PL2303 is not set -# CONFIG_CDCACM is not set +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_EP0MAXPACKET=64 +CONFIG_CDCACM_EPINTIN=1 +CONFIG_CDCACM_EPINTIN_FSSIZE=64 +CONFIG_CDCACM_EPINTIN_HSSIZE=64 +CONFIG_CDCACM_EPBULKOUT=3 +CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 +CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 +CONFIG_CDCACM_EPBULKIN=2 +CONFIG_CDCACM_EPBULKIN_FSSIZE=64 +CONFIG_CDCACM_EPBULKIN_HSSIZE=512 +CONFIG_CDCACM_NWRREQS=4 +CONFIG_CDCACM_NRDREQS=4 +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_CDCACM_VENDORID=0x26ac +CONFIG_CDCACM_PRODUCTID=0x10 +CONFIG_CDCACM_VENDORSTR="3D Robotics" +CONFIG_CDCACM_PRODUCTSTR="PX4FMU v1.x" # CONFIG_USBMSC is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set @@ -521,23 +581,19 @@ CONFIG_USBDEV_SELFPOWERED=y # # CONFIG_DISABLE_MOUNTPOINT is not set # CONFIG_FS_RAMMAP is not set -CONFIG_FS_FAT=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=32 -# CONFIG_FS_FATTIME is not set -# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_FAT is not set # CONFIG_FS_NXFFS is not set -CONFIG_FS_ROMFS=y -CONFIG_FS_BINFS=y +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set # # System Logging # -CONFIG_SYSLOG_ENABLE=y +# CONFIG_SYSLOG_ENABLE is not set CONFIG_SYSLOG=y CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/syslog" +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" # # Graphics Support @@ -554,6 +610,11 @@ CONFIG_GRAN=y CONFIG_GRAN_SINGLE=y CONFIG_GRAN_INTR=y +# +# Audio Support +# +# CONFIG_AUDIO is not set + # # Binary Formats # @@ -576,9 +637,9 @@ CONFIG_STDIO_BUFFER_SIZE=64 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 CONFIG_LIB_HOMEDIR="/" -CONFIG_LIBM=y # CONFIG_NOPRINTF_FIELDWIDTH is not set CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set # CONFIG_EOL_IS_BOTH_CRLF is not set @@ -607,6 +668,7 @@ CONFIG_SCHED_LPWORKPRIORITY=50 CONFIG_SCHED_LPWORKPERIOD=50000 CONFIG_SCHED_LPWORKSTACKSIZE=2048 # CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set # # Basic CXX Support @@ -635,6 +697,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set # CONFIG_EXAMPLES_COMPOSITE is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -649,8 +712,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_IGMP is not set # CONFIG_EXAMPLES_LCDRW is not set # CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MOUNT is not set # CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set # CONFIG_EXAMPLES_NX is not set @@ -670,6 +733,10 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_THTTPD is not set # CONFIG_EXAMPLES_TIFF is not set @@ -766,6 +833,11 @@ CONFIG_NSH_BUILTIN_APPS=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 # CONFIG_NSH_STRERROR is not set @@ -773,7 +845,6 @@ CONFIG_NSH_LINELEN=64 CONFIG_NSH_NESTDEPTH=3 # CONFIG_NSH_DISABLESCRIPT is not set # CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_ROMFSETC is not set CONFIG_NSH_CONSOLE=y # CONFIG_NSH_USBCONSOLE is not set @@ -799,20 +870,17 @@ CONFIG_NSH_ARCHINIT=y # # I2C tool # -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_I2CTOOL_BUILTIN=y -CONFIG_I2CTOOL_MINBUS=0 -CONFIG_I2CTOOL_MAXBUS=3 -CONFIG_I2CTOOL_MINADDR=0x03 -CONFIG_I2CTOOL_MAXADDR=0x77 -CONFIG_I2CTOOL_MAXREGADDR=0xff -CONFIG_I2CTOOL_DEFFREQ=4000000 +# CONFIG_SYSTEM_I2CTOOL is not set # # FLASH Program Installation # # CONFIG_SYSTEM_INSTALL is not set +# +# FLASH Erase-all Command +# + # # readline() # diff --git a/nuttx/configs/px4fmu-v1/nsh/setenv.sh b/nuttx/configs/px4fmu-v1/nsh/setenv.sh index 2476845b64..db372217cd 100755 --- a/nuttx/configs/px4fmu-v1/nsh/setenv.sh +++ b/nuttx/configs/px4fmu-v1/nsh/setenv.sh @@ -1,7 +1,7 @@ #!/bin/bash -# configs/stm32f4discovery/nsh/setenv.sh +# configs/px4fmu-v1/usbnsh/setenv.sh # -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without From c29153a4fa9f9e3ea0ef50e88dc3f82037daca40 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sat, 1 Jun 2013 01:52:10 +0200 Subject: [PATCH 05/41] Integration with main Firmware repo, adjusting new-style configs --- nuttx/configs/px4fmu-v1/include/board.h | 115 ++- nuttx/configs/px4fmu-v1/nsh/defconfig | 2 +- nuttx/configs/px4fmu-v1/usbnsh/Make.defs | 3 - nuttx/configs/px4fmu-v1/usbnsh/defconfig | 912 ----------------------- nuttx/configs/px4fmu-v1/usbnsh/setenv.sh | 75 -- nuttx/configs/px4io-v1/io/Make.defs | 3 - nuttx/configs/px4io-v1/io/appconfig | 32 - nuttx/configs/px4io-v1/io/defconfig | 552 -------------- nuttx/configs/px4io-v1/io/setenv.sh | 47 -- nuttx/configs/px4io-v1/nsh/Make.defs | 2 +- nuttx/configs/px4io-v1/nsh/appconfig | 15 +- nuttx/configs/px4io-v1/nsh/defconfig | 179 +++-- nuttx/configs/px4io-v1/nsh/setenv.sh | 4 +- 13 files changed, 185 insertions(+), 1756 deletions(-) delete mode 100644 nuttx/configs/px4fmu-v1/usbnsh/Make.defs delete mode 100644 nuttx/configs/px4fmu-v1/usbnsh/defconfig delete mode 100755 nuttx/configs/px4fmu-v1/usbnsh/setenv.sh delete mode 100644 nuttx/configs/px4io-v1/io/Make.defs delete mode 100644 nuttx/configs/px4io-v1/io/appconfig delete mode 100755 nuttx/configs/px4io-v1/io/defconfig delete mode 100755 nuttx/configs/px4io-v1/io/setenv.sh diff --git a/nuttx/configs/px4fmu-v1/include/board.h b/nuttx/configs/px4fmu-v1/include/board.h index 8d17488ffd..bf825a899c 100644 --- a/nuttx/configs/px4fmu-v1/include/board.h +++ b/nuttx/configs/px4fmu-v1/include/board.h @@ -149,12 +149,19 @@ #define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. + * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_TIM27_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY) + +/* High-resolution timer + */ +#ifdef CONFIG_HRT_TIMER +# define HRT_TIMER 1 /* use timer1 for the HRT */ +# define HRT_TIMER_CHANNEL 1 /* use capture/compare channel */ +#endif /* LED definitions ******************************************************************/ /* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any @@ -209,29 +216,45 @@ /* UART DMA configuration for USART1/6 */ #define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 #define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - + /* - * SPI + * PWM + * + * Four PWM outputs can be configured on pins otherwise shared with + * USART2; two can take the flow control pins if they are not being used. + * + * Pins: + * + * CTS - PA0 - TIM2CH1 + * RTS - PA1 - TIM2CH2 + * TX - PA2 - TIM2CH3 + * RX - PA3 - TIM2CH4 * - * There are sensors on SPI1, and SPI3 is connected to the microSD slot. */ -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 +#define GPIO_TIM2_CH1OUT GPIO_TIM2_CH1OUT_1 +#define GPIO_TIM2_CH2OUT GPIO_TIM2_CH2OUT_1 +#define GPIO_TIM2_CH3OUT GPIO_TIM2_CH3OUT_1 +#define GPIO_TIM2_CH4OUT GPIO_TIM2_CH4OUT_1 -#define GPIO_SPI3_MISO GPIO_SPI3_MISO_2 -#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_1 -#define GPIO_SPI3_SCK GPIO_SPI3_SCK_2 -#define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 +/* + * PPM + * + * PPM input is handled by the HRT timer. + */ +#if defined(CONFIG_HRT_TIMER) && defined (CONFIG_HRT_PPM) +# define HRT_PPM_CHANNEL 3 /* use capture/compare channel 3 */ +# define GPIO_PPM_IN (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN10) +#endif /* - * Use these in place of the spi_dev_e enumeration to - * select a specific SPI device on SPI1 + * CAN + * + * CAN2 is routed to the expansion connector. */ -#define PX4_SPIDEV_GYRO 1 -#define PX4_SPIDEV_ACCEL 2 -#define PX4_SPIDEV_MPU 3 - + +#define GPIO_CAN2_RX GPIO_CAN2_RX_2 +#define GPIO_CAN2_TX GPIO_CAN2_TX_2 + /* * I2C * @@ -254,6 +277,60 @@ #define GPIO_I2C3_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN8) #define GPIO_I2C3_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN9) +/* + * I2C busses + */ +#define PX4_I2C_BUS_ESC 1 +#define PX4_I2C_BUS_ONBOARD 2 +#define PX4_I2C_BUS_EXPANSION 3 + +/* + * Devices on the onboard bus. + * + * Note that these are unshifted addresses. + */ +#define PX4_I2C_OBDEV_HMC5883 0x1e +#define PX4_I2C_OBDEV_MS5611 0x76 +#define PX4_I2C_OBDEV_EEPROM NOTDEFINED + +#define PX4_I2C_OBDEV_PX4IO_BL 0x18 +#define PX4_I2C_OBDEV_PX4IO 0x1a + +/* + * SPI + * + * There are sensors on SPI1, and SPI3 is connected to the microSD slot. + */ +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +#define GPIO_SPI3_MISO GPIO_SPI3_MISO_2 +#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_1 +#define GPIO_SPI3_SCK GPIO_SPI3_SCK_2 +#define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 + +/* + * Use these in place of the spi_dev_e enumeration to + * select a specific SPI device on SPI1 + */ +#define PX4_SPIDEV_GYRO 1 +#define PX4_SPIDEV_ACCEL 2 +#define PX4_SPIDEV_MPU 3 + +/* + * Optional devices on IO's external port + */ +#define PX4_SPIDEV_ACCEL_MAG 2 + +/* + * Tone alarm output + */ +#define TONE_ALARM_TIMER 3 /* timer 3 */ +#define TONE_ALARM_CHANNEL 3 /* channel 3 */ +#define GPIO_TONE_ALARM_IDLE (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TONE_ALARM (GPIO_ALT|GPIO_AF2|GPIO_SPEED_2MHz|GPIO_FLOAT|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/nuttx/configs/px4fmu-v1/nsh/defconfig b/nuttx/configs/px4fmu-v1/nsh/defconfig index 963d71a897..732bd41e08 100644 --- a/nuttx/configs/px4fmu-v1/nsh/defconfig +++ b/nuttx/configs/px4fmu-v1/nsh/defconfig @@ -421,7 +421,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # # Device Drivers # -CONFIG_DISABLE_POLL=y +# CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set # CONFIG_LOOP is not set diff --git a/nuttx/configs/px4fmu-v1/usbnsh/Make.defs b/nuttx/configs/px4fmu-v1/usbnsh/Make.defs deleted file mode 100644 index 81936334b3..0000000000 --- a/nuttx/configs/px4fmu-v1/usbnsh/Make.defs +++ /dev/null @@ -1,3 +0,0 @@ -include ${TOPDIR}/.config - -include $(TOPDIR)/configs/px4fmu-v1/common/Make.defs diff --git a/nuttx/configs/px4fmu-v1/usbnsh/defconfig b/nuttx/configs/px4fmu-v1/usbnsh/defconfig deleted file mode 100644 index 963d71a897..0000000000 --- a/nuttx/configs/px4fmu-v1/usbnsh/defconfig +++ /dev/null @@ -1,912 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# -CONFIG_NUTTX_NEWCONFIG=y - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_HOST_LINUX is not set -CONFIG_HOST_OSX=y -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -CONFIG_APPS_DIR="../apps" -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y - -# -# Customize Header Files -# -# CONFIG_ARCH_STDBOOL_H is not set -CONFIG_ARCH_MATH_H=y -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG is not set -CONFIG_DEBUG_SYMBOLS=y - -# -# System Type -# -# CONFIG_ARCH_8051 is not set -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set -# CONFIG_ARCH_SH is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_IMX is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAM3U is not set -CONFIG_ARCH_CHIP_STM32=y -# CONFIG_ARCH_CHIP_STR71X is not set -CONFIG_ARCH_CORTEXM4=y -CONFIG_ARCH_FAMILY="armv7-m" -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARMV7M_USEBASEPRI=y -CONFIG_ARCH_HAVE_CMNVECTOR=y -CONFIG_ARMV7M_CMNVECTOR=y -CONFIG_ARCH_FPU=y -CONFIG_ARCH_HAVE_MPU=y -# CONFIG_ARMV7M_MPU is not set - -# -# ARMV7M Configuration Options -# -# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set -CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI=y -CONFIG_SERIAL_TERMIOS=y - -# -# STM32 Configuration Options -# -# CONFIG_ARCH_CHIP_STM32L151C6 is not set -# CONFIG_ARCH_CHIP_STM32L151C8 is not set -# CONFIG_ARCH_CHIP_STM32L151CB is not set -# CONFIG_ARCH_CHIP_STM32L151R6 is not set -# CONFIG_ARCH_CHIP_STM32L151R8 is not set -# CONFIG_ARCH_CHIP_STM32L151RB is not set -# CONFIG_ARCH_CHIP_STM32L151V6 is not set -# CONFIG_ARCH_CHIP_STM32L151V8 is not set -# CONFIG_ARCH_CHIP_STM32L151VB is not set -# CONFIG_ARCH_CHIP_STM32L152C6 is not set -# CONFIG_ARCH_CHIP_STM32L152C8 is not set -# CONFIG_ARCH_CHIP_STM32L152CB is not set -# CONFIG_ARCH_CHIP_STM32L152R6 is not set -# CONFIG_ARCH_CHIP_STM32L152R8 is not set -# CONFIG_ARCH_CHIP_STM32L152RB is not set -# CONFIG_ARCH_CHIP_STM32L152V6 is not set -# CONFIG_ARCH_CHIP_STM32L152V8 is not set -# CONFIG_ARCH_CHIP_STM32L152VB is not set -# CONFIG_ARCH_CHIP_STM32F100C8 is not set -# CONFIG_ARCH_CHIP_STM32F100CB is not set -# CONFIG_ARCH_CHIP_STM32F100R8 is not set -# CONFIG_ARCH_CHIP_STM32F100RB is not set -# CONFIG_ARCH_CHIP_STM32F100RC is not set -# CONFIG_ARCH_CHIP_STM32F100RD is not set -# CONFIG_ARCH_CHIP_STM32F100RE is not set -# CONFIG_ARCH_CHIP_STM32F100V8 is not set -# CONFIG_ARCH_CHIP_STM32F100VB is not set -# CONFIG_ARCH_CHIP_STM32F100VC is not set -# CONFIG_ARCH_CHIP_STM32F100VD is not set -# CONFIG_ARCH_CHIP_STM32F100VE is not set -# CONFIG_ARCH_CHIP_STM32F103C4 is not set -# CONFIG_ARCH_CHIP_STM32F103C8 is not set -# CONFIG_ARCH_CHIP_STM32F103RET6 is not set -# CONFIG_ARCH_CHIP_STM32F103VCT6 is not set -# CONFIG_ARCH_CHIP_STM32F103VET6 is not set -# CONFIG_ARCH_CHIP_STM32F103ZET6 is not set -# CONFIG_ARCH_CHIP_STM32F105VBT7 is not set -# CONFIG_ARCH_CHIP_STM32F107VC is not set -# CONFIG_ARCH_CHIP_STM32F207IG is not set -# CONFIG_ARCH_CHIP_STM32F302CB is not set -# CONFIG_ARCH_CHIP_STM32F302CC is not set -# CONFIG_ARCH_CHIP_STM32F302RB is not set -# CONFIG_ARCH_CHIP_STM32F302RC is not set -# CONFIG_ARCH_CHIP_STM32F302VB is not set -# CONFIG_ARCH_CHIP_STM32F302VC is not set -# CONFIG_ARCH_CHIP_STM32F303CB is not set -# CONFIG_ARCH_CHIP_STM32F303CC is not set -# CONFIG_ARCH_CHIP_STM32F303RB is not set -# CONFIG_ARCH_CHIP_STM32F303RC is not set -# CONFIG_ARCH_CHIP_STM32F303VB is not set -# CONFIG_ARCH_CHIP_STM32F303VC is not set -CONFIG_ARCH_CHIP_STM32F405RG=y -# CONFIG_ARCH_CHIP_STM32F405VG is not set -# CONFIG_ARCH_CHIP_STM32F405ZG is not set -# CONFIG_ARCH_CHIP_STM32F407VE is not set -# CONFIG_ARCH_CHIP_STM32F407VG is not set -# CONFIG_ARCH_CHIP_STM32F407ZE is not set -# CONFIG_ARCH_CHIP_STM32F407ZG is not set -# CONFIG_ARCH_CHIP_STM32F407IE is not set -# CONFIG_ARCH_CHIP_STM32F407IG is not set -# CONFIG_ARCH_CHIP_STM32F427V is not set -# CONFIG_ARCH_CHIP_STM32F427Z is not set -# CONFIG_ARCH_CHIP_STM32F427I is not set -# CONFIG_STM32_STM32L15XX is not set -# CONFIG_STM32_ENERGYLITE is not set -# CONFIG_STM32_STM32F10XX is not set -# CONFIG_STM32_VALUELINE is not set -# CONFIG_STM32_CONNECTIVITYLINE is not set -# CONFIG_STM32_PERFORMANCELINE is not set -# CONFIG_STM32_HIGHDENSITY is not set -# CONFIG_STM32_MEDIUMDENSITY is not set -# CONFIG_STM32_LOWDENSITY is not set -# CONFIG_STM32_STM32F20XX is not set -# CONFIG_STM32_STM32F30XX is not set -CONFIG_STM32_STM32F40XX=y -# CONFIG_STM32_DFU is not set - -# -# STM32 Peripheral Support -# -CONFIG_STM32_ADC1=y -# CONFIG_STM32_ADC2 is not set -# CONFIG_STM32_ADC3 is not set -# CONFIG_STM32_BKPSRAM is not set -# CONFIG_STM32_CAN1 is not set -# CONFIG_STM32_CAN2 is not set -CONFIG_STM32_CCMDATARAM=y -# CONFIG_STM32_CRC is not set -# CONFIG_STM32_CRYP is not set -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -# CONFIG_STM32_DAC1 is not set -# CONFIG_STM32_DAC2 is not set -# CONFIG_STM32_DCMI is not set -# CONFIG_STM32_ETHMAC is not set -# CONFIG_STM32_FSMC is not set -# CONFIG_STM32_HASH is not set -CONFIG_STM32_I2C1=y -CONFIG_STM32_I2C2=y -CONFIG_STM32_I2C3=y -CONFIG_STM32_OTGFS=y -# CONFIG_STM32_OTGHS is not set -CONFIG_STM32_PWR=y -# CONFIG_STM32_RNG is not set -# CONFIG_STM32_SDIO is not set -CONFIG_STM32_SPI1=y -# CONFIG_STM32_SPI2 is not set -CONFIG_STM32_SPI3=y -CONFIG_STM32_SYSCFG=y -# CONFIG_STM32_TIM1 is not set -# CONFIG_STM32_TIM2 is not set -# CONFIG_STM32_TIM3 is not set -CONFIG_STM32_TIM4=y -CONFIG_STM32_TIM5=y -CONFIG_STM32_TIM6=y -CONFIG_STM32_TIM7=y -# CONFIG_STM32_TIM8 is not set -# CONFIG_STM32_TIM9 is not set -# CONFIG_STM32_TIM10 is not set -# CONFIG_STM32_TIM11 is not set -CONFIG_STM32_TIM12=y -CONFIG_STM32_TIM13=y -CONFIG_STM32_TIM14=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -# CONFIG_STM32_USART3 is not set -# CONFIG_STM32_UART4 is not set -CONFIG_STM32_UART5=y -CONFIG_STM32_USART6=y -# CONFIG_STM32_IWDG is not set -# CONFIG_STM32_WWDG is not set -CONFIG_STM32_ADC=y -CONFIG_STM32_SPI=y -CONFIG_STM32_I2C=y - -# -# Alternate Pin Mapping -# -CONFIG_STM32_FLASH_PREFETCH=y -# CONFIG_STM32_JTAG_DISABLE is not set -# CONFIG_STM32_JTAG_FULL_ENABLE is not set -# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set -CONFIG_STM32_JTAG_SW_ENABLE=y -# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set -# CONFIG_STM32_FORCEPOWER is not set -# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set -# CONFIG_STM32_CCMEXCLUDE is not set -# CONFIG_STM32_TIM4_PWM is not set -# CONFIG_STM32_TIM5_PWM is not set -# CONFIG_STM32_TIM12_PWM is not set -# CONFIG_STM32_TIM13_PWM is not set -# CONFIG_STM32_TIM14_PWM is not set -# CONFIG_STM32_TIM4_ADC is not set -# CONFIG_STM32_TIM5_ADC is not set -CONFIG_STM32_USART=y - -# -# U[S]ART Configuration -# -# CONFIG_USART1_RS485 is not set -# CONFIG_USART1_RXDMA is not set -# CONFIG_USART2_RS485 is not set -CONFIG_USART2_RXDMA=y -# CONFIG_USART3_RXDMA is not set -# CONFIG_UART4_RXDMA is not set -# CONFIG_UART5_RS485 is not set -CONFIG_UART5_RXDMA=y -# CONFIG_USART6_RS485 is not set -CONFIG_USART6_RXDMA=y -# CONFIG_USART7_RXDMA is not set -# CONFIG_USART8_RXDMA is not set -CONFIG_STM32_USART_SINGLEWIRE=y - -# -# SPI Configuration -# -# CONFIG_STM32_SPI_INTERRUPTS is not set -# CONFIG_STM32_SPI_DMA is not set - -# -# I2C Configuration -# -# CONFIG_STM32_I2C_DYNTIMEO is not set -CONFIG_STM32_I2CTIMEOSEC=0 -CONFIG_STM32_I2CTIMEOMS=500 -CONFIG_STM32_I2CTIMEOTICKS=500 -# CONFIG_STM32_I2C_DUTY16_9 is not set - -# -# USB Host Configuration -# - -# -# USB Device Configuration -# - -# -# External Memory Configuration -# - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -CONFIG_ARCH_DMA=y -CONFIG_ARCH_IRQPRIO=y -# CONFIG_CUSTOM_STACK is not set -# CONFIG_ADDRENV is not set -CONFIG_ARCH_HAVE_VFORK=y -CONFIG_ARCH_STACKDUMP=y -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -CONFIG_ARCH_HAVE_RAMVECTORS=y -# CONFIG_ARCH_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=16717 -# CONFIG_ARCH_CALIBRATION is not set -CONFIG_DRAM_START=0x20000000 -CONFIG_DRAM_SIZE=114688 -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=0 - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_PX4FMU_V1=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="px4fmu-v1" - -# -# Common Board Options -# -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=0 - -# -# Board-Specific Options -# - -# -# RTOS Features -# -# CONFIG_BOARD_INITIALIZE is not set -CONFIG_MSEC_PER_TICK=1 -CONFIG_RR_INTERVAL=5 -# CONFIG_SCHED_INSTRUMENTATION is not set -CONFIG_TASK_NAME_SIZE=24 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=12 -CONFIG_START_DAY=6 -# CONFIG_DEV_CONSOLE is not set -# CONFIG_MUTEX_TYPES is not set -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_SEM_PREALLOCHOLDERS=16 -CONFIG_SEM_NNESTPRIO=16 -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_SCHED_WAITPID=y -# CONFIG_SCHED_STARTHOOK is not set -CONFIG_SCHED_ATEXIT=y -CONFIG_SCHED_ATEXIT_MAX=1 -# CONFIG_SCHED_ONEXIT is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_CLOCK is not set -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 -CONFIG_SIG_SIGWORK=17 - -# -# Sizes of configurable things (0 disables) -# -CONFIG_MAX_TASKS=16 -CONFIG_MAX_TASK_ARGS=10 -CONFIG_NPTHREAD_KEYS=4 -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 -CONFIG_PREALLOC_MQ_MSGS=4 -CONFIG_MQ_MAXMSGSIZE=32 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_PREALLOC_TIMERS=4 - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_LOOP is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_PWM is not set -CONFIG_I2C=y -# CONFIG_I2C_SLAVE is not set -CONFIG_I2C_TRANSFER=y -# CONFIG_I2C_WRITEREAD is not set -# CONFIG_I2C_POLLED is not set -# CONFIG_I2C_TRACE is not set -CONFIG_ARCH_HAVE_I2CRESET=y -# CONFIG_I2C_RESET is not set -CONFIG_SPI=y -# CONFIG_SPI_OWNBUS is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_LCD is not set -CONFIG_MMCSD=y -CONFIG_MMCSD_NSLOTS=1 -# CONFIG_MMCSD_READONLY is not set -# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SPICLOCK=20000000 -# CONFIG_MMCSD_SDIO is not set -# CONFIG_MTD is not set -CONFIG_PIPES=y -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -CONFIG_SERIAL_REMOVABLE=y -# CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART5=y -CONFIG_ARCH_HAVE_USART1=y -CONFIG_ARCH_HAVE_USART2=y -CONFIG_ARCH_HAVE_USART6=y -CONFIG_MCU_SERIAL=y -CONFIG_STANDARD_SERIAL=y -# CONFIG_USART1_SERIAL_CONSOLE is not set -# CONFIG_USART2_SERIAL_CONSOLE is not set -# CONFIG_UART5_SERIAL_CONSOLE is not set -# CONFIG_USART6_SERIAL_CONSOLE is not set -CONFIG_NO_SERIAL_CONSOLE=y - -# -# USART1 Configuration -# -CONFIG_USART1_RXBUFSIZE=256 -CONFIG_USART1_TXBUFSIZE=256 -CONFIG_USART1_BAUD=57600 -CONFIG_USART1_BITS=8 -CONFIG_USART1_PARITY=0 -CONFIG_USART1_2STOP=0 - -# -# USART2 Configuration -# -CONFIG_USART2_RXBUFSIZE=256 -CONFIG_USART2_TXBUFSIZE=256 -CONFIG_USART2_BAUD=115200 -CONFIG_USART2_BITS=8 -CONFIG_USART2_PARITY=0 -CONFIG_USART2_2STOP=0 - -# -# UART5 Configuration -# -CONFIG_UART5_RXBUFSIZE=256 -CONFIG_UART5_TXBUFSIZE=256 -CONFIG_UART5_BAUD=115200 -CONFIG_UART5_BITS=8 -CONFIG_UART5_PARITY=0 -CONFIG_UART5_2STOP=0 - -# -# USART6 Configuration -# -CONFIG_USART6_RXBUFSIZE=256 -CONFIG_USART6_TXBUFSIZE=256 -CONFIG_USART6_BAUD=115200 -CONFIG_USART6_BITS=8 -CONFIG_USART6_PARITY=0 -CONFIG_USART6_2STOP=0 -CONFIG_USBDEV=y - -# -# USB Device Controller Driver Options -# -# CONFIG_USBDEV_ISOCHRONOUS is not set -# CONFIG_USBDEV_DUALSPEED is not set -CONFIG_USBDEV_SELFPOWERED=y -# CONFIG_USBDEV_BUSPOWERED is not set -CONFIG_USBDEV_MAXPOWER=500 -# CONFIG_USBDEV_DMA is not set -# CONFIG_USBDEV_TRACE is not set - -# -# USB Device Class Driver Options -# -# CONFIG_USBDEV_COMPOSITE is not set -# CONFIG_PL2303 is not set -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_EP0MAXPACKET=64 -CONFIG_CDCACM_EPINTIN=1 -CONFIG_CDCACM_EPINTIN_FSSIZE=64 -CONFIG_CDCACM_EPINTIN_HSSIZE=64 -CONFIG_CDCACM_EPBULKOUT=3 -CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 -CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 -CONFIG_CDCACM_EPBULKIN=2 -CONFIG_CDCACM_EPBULKIN_FSSIZE=64 -CONFIG_CDCACM_EPBULKIN_HSSIZE=512 -CONFIG_CDCACM_NWRREQS=4 -CONFIG_CDCACM_NRDREQS=4 -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_CDCACM_VENDORID=0x26ac -CONFIG_CDCACM_PRODUCTID=0x10 -CONFIG_CDCACM_VENDORSTR="3D Robotics" -CONFIG_CDCACM_PRODUCTSTR="PX4FMU v1.x" -# CONFIG_USBMSC is not set -# CONFIG_USBHOST is not set -# CONFIG_WIRELESS is not set - -# -# System Logging Device Options -# - -# -# System Logging -# -# CONFIG_RAMLOG is not set - -# -# Networking Support -# -# CONFIG_NET is not set - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_BINFS is not set - -# -# System Logging -# -# CONFIG_SYSLOG_ENABLE is not set -CONFIG_SYSLOG=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_MULTIHEAP is not set -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 -CONFIG_GRAN=y -CONFIG_GRAN_SINGLE=y -CONFIG_GRAN_INTR=y - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Binary Formats -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -CONFIG_BUILTIN=y -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_NOPRINTF_FIELDWIDTH is not set -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -CONFIG_LIBC_STRERROR=y -# CONFIG_LIBC_STRERROR_SHORT is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set - -# -# Non-standard Library Support -# -CONFIG_SCHED_WORKQUEUE=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WORKPRIORITY=192 -CONFIG_SCHED_WORKPERIOD=50000 -CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=50 -CONFIG_SCHED_LPWORKPERIOD=50000 -CONFIG_SCHED_LPWORKSTACKSIZE=2048 -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -# CONFIG_CXX_NEWLONG is not set - -# -# uClibc++ Standard C++ Library -# -# CONFIG_UCLIBCXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# -CONFIG_BUILTIN_PROXY_STACKSIZE=1024 - -# -# Examples -# -# CONFIG_EXAMPLES_BUTTONS is not set -# CONFIG_EXAMPLES_CAN is not set -# CONFIG_EXAMPLES_CDCACM is not set -# CONFIG_EXAMPLES_COMPOSITE is not set -# CONFIG_EXAMPLES_CXXTEST is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_LCDRW is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXCONSOLE is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXFLAT is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PASHELLO is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set -# CONFIG_EXAMPLES_ROMFS is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART_TEST is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_THTTPD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_UDP is not set -# CONFIG_EXAMPLES_UIP is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBMSC is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# Network Utilities -# - -# -# Networking Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_DHCPC is not set -# CONFIG_NETUTILS_DHCPD is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_FTPD is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_RESOLV is not set -# CONFIG_NETUTILS_SMTP is not set -# CONFIG_NETUTILS_TELNETD is not set -# CONFIG_NETUTILS_TFTPC is not set -# CONFIG_NETUTILS_THTTPD is not set -# CONFIG_NETUTILS_UIPLIB is not set -# CONFIG_NETUTILS_WEBCLIENT is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_BUILTIN_APPS=y - -# -# Disable Individual commands -# -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_NSFMOUNT is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PING is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -# CONFIG_NSH_CMDOPT_DF_H is not set -CONFIG_NSH_CODECS_BUFSIZE=128 -CONFIG_NSH_FILEIOSIZE=512 -# CONFIG_NSH_STRERROR is not set -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLEBG is not set -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_USBCONSOLE is not set - -# -# USB Trace Support -# -# CONFIG_NSH_CONDEV is not set -CONFIG_NSH_ARCHINIT=y - -# -# NxWidgets/NxWM -# - -# -# System NSH Add-Ons -# - -# -# Custom Free Memory Command -# -# CONFIG_SYSTEM_FREE is not set - -# -# I2C tool -# -# CONFIG_SYSTEM_I2CTOOL is not set - -# -# FLASH Program Installation -# -# CONFIG_SYSTEM_INSTALL is not set - -# -# FLASH Erase-all Command -# - -# -# readline() -# -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y - -# -# Power Off -# -# CONFIG_SYSTEM_POWEROFF is not set - -# -# RAMTRON -# -# CONFIG_SYSTEM_RAMTRON is not set - -# -# SD Card -# -# CONFIG_SYSTEM_SDCARD is not set - -# -# Sysinfo -# -CONFIG_SYSTEM_SYSINFO=y - -# -# USB Monitor -# diff --git a/nuttx/configs/px4fmu-v1/usbnsh/setenv.sh b/nuttx/configs/px4fmu-v1/usbnsh/setenv.sh deleted file mode 100755 index db372217cd..0000000000 --- a/nuttx/configs/px4fmu-v1/usbnsh/setenv.sh +++ /dev/null @@ -1,75 +0,0 @@ -#!/bin/bash -# configs/px4fmu-v1/usbnsh/setenv.sh -# -# Copyright (C) 2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$_" = "$0" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -WD=`pwd` -if [ ! -x "setenv.sh" ]; then - echo "This script must be executed from the top-level NuttX build directory" - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then - export PATH_ORIG="${PATH}" -fi - -# This is the Cygwin path to the location where I installed the RIDE -# toolchain under windows. You will also have to edit this if you install -# the RIDE toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" - -# These are the Cygwin paths to the locations where I installed the Atollic -# toolchain under windows. You will also have to edit this if you install -# the Atollic toolchain in any other location. /usr/bin is added before -# the Atollic bin path because there is are binaries named gcc.exe and g++.exe -# at those locations as well. -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" - -# Add the path to the toolchain to the PATH varialble -export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/nuttx/configs/px4io-v1/io/Make.defs b/nuttx/configs/px4io-v1/io/Make.defs deleted file mode 100644 index c7f6effd9a..0000000000 --- a/nuttx/configs/px4io-v1/io/Make.defs +++ /dev/null @@ -1,3 +0,0 @@ -include ${TOPDIR}/.config - -include $(TOPDIR)/configs/px4io-v1/common/Make.defs diff --git a/nuttx/configs/px4io-v1/io/appconfig b/nuttx/configs/px4io-v1/io/appconfig deleted file mode 100644 index 48a41bcdb8..0000000000 --- a/nuttx/configs/px4io-v1/io/appconfig +++ /dev/null @@ -1,32 +0,0 @@ -############################################################################ -# -# Copyright (C) 2012 PX4 Development Team. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name PX4 nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ diff --git a/nuttx/configs/px4io-v1/io/defconfig b/nuttx/configs/px4io-v1/io/defconfig deleted file mode 100755 index 43dd1b0e85..0000000000 --- a/nuttx/configs/px4io-v1/io/defconfig +++ /dev/null @@ -1,552 +0,0 @@ -############################################################################ -# configs/px4io/nsh/defconfig -# -# Copyright (C) 2012 PX4 Development Team. All rights reserved. -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# architecture selection -# -# CONFIG_ARCH - identifies the arch subdirectory and, hence, the -# processor architecture. -# CONFIG_ARCH_family - for use in C code. This identifies the -# particular chip family that the architecture is implemented -# in. -# CONFIG_ARCH_architecture - for use in C code. This identifies the -# specific architecture within the chip family. -# CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory -# CONFIG_ARCH_CHIP_name - For use in C code -# CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence, -# the board that supports the particular chip or SoC. -# CONFIG_ARCH_BOARD_name - for use in C code -# CONFIG_ENDIAN_BIG - define if big endian (default is little endian) -# CONFIG_BOARD_LOOPSPERMSEC - for delay loops -# CONFIG_DRAM_SIZE - Describes the installed DRAM. -# CONFIG_DRAM_START - The start address of DRAM (physical) -# CONFIG_ARCH_IRQPRIO - The ST32F100CB supports interrupt prioritization -# CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt -# stack. If defined, this symbol is the size of the interrupt -# stack in bytes. If not defined, the user task stacks will be -# used during interrupt handling. -# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions -# CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader. -# CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. -# CONFIG_ARCH_BUTTONS - Enable support for buttons. Unique to board architecture. -# CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that -# cause a 100 second delay during boot-up. This 100 second delay -# serves no purpose other than it allows you to calibrate -# CONFIG_BOARD_LOOPSPERMSEC. You simply use a stop watch to measure -# the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until -# the delay actually is 100 seconds. -# CONFIG_ARCH_DMA - Support DMA initialization -# -CONFIG_ARCH="arm" -CONFIG_ARCH_ARM=y -CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F100C8=y -# -# Board Selection -# -CONFIG_ARCH_BOARD_PX4IO_V1=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="px4io-v1" -CONFIG_BOARD_LOOPSPERMSEC=2000 -CONFIG_DRAM_SIZE=0x00002000 -CONFIG_DRAM_START=0x20000000 -CONFIG_ARCH_IRQPRIO=y -CONFIG_ARCH_INTERRUPTSTACK=n -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_BOOTLOADER=n -CONFIG_ARCH_LEDS=n -CONFIG_ARCH_BUTTONS=n -CONFIG_ARCH_CALIBRATION=n -CONFIG_ARCH_DMA=y -CONFIG_ARCH_MATH_H=y - -CONFIG_ARMV7M_CMNVECTOR=y - -# -# JTAG Enable settings (by default JTAG-DP and SW-DP are disabled): -# -# CONFIG_STM32_DFU - Use the DFU bootloader, not JTAG -# -# JTAG Enable options: -# -# CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) -# CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) -# but without JNTRST. -# CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled -# -CONFIG_STM32_DFU=n -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n -CONFIG_STM32_JTAG_SW_ENABLE=n - -# -# Individual subsystems can be enabled: -# -# AHB: -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=n -CONFIG_STM32_CRC=n -# APB1: -# Timers 2,3 and 4 are owned by the PWM driver -CONFIG_STM32_TIM2=n -CONFIG_STM32_TIM3=n -CONFIG_STM32_TIM4=n -CONFIG_STM32_TIM5=n -CONFIG_STM32_TIM6=n -CONFIG_STM32_TIM7=n -CONFIG_STM32_WWDG=n -CONFIG_STM32_SPI2=n -CONFIG_STM32_USART2=y -CONFIG_STM32_USART3=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_I2C2=n -CONFIG_STM32_BKP=n -CONFIG_STM32_PWR=n -CONFIG_STM32_DAC=n -# APB2: -# We use our own ADC driver, but leave this on for clocking purposes. -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC2=n -# TIM1 is owned by the HRT -CONFIG_STM32_TIM1=n -CONFIG_STM32_SPI1=n -CONFIG_STM32_TIM8=n -CONFIG_STM32_USART1=y -CONFIG_STM32_ADC3=n - - -# -# STM32F100 specific serial device driver settings -# -# CONFIG_USARTn_SERIAL_CONSOLE - selects the USARTn for the -# console and ttys0 (default is the USART1). -# CONFIG_USARTn_RXBUFSIZE - Characters are buffered as received. -# This specific the size of the receive buffer -# CONFIG_USARTn_TXBUFSIZE - Characters are buffered before -# being sent. This specific the size of the transmit buffer -# CONFIG_USARTn_BAUD - The configure BAUD of the UART. Must be -# CONFIG_USARTn_BITS - The number of bits. Must be either 7 or 8. -# CONFIG_USARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity -# CONFIG_USARTn_2STOP - Two stop bits -# -CONFIG_SERIAL_TERMIOS=y -CONFIG_STANDARD_SERIAL=y - -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART2_SERIAL_CONSOLE=n -CONFIG_USART3_SERIAL_CONSOLE=n - -CONFIG_USART1_TXBUFSIZE=64 -CONFIG_USART2_TXBUFSIZE=64 -CONFIG_USART3_TXBUFSIZE=64 - -CONFIG_USART1_RXBUFSIZE=64 -CONFIG_USART2_RXBUFSIZE=64 -CONFIG_USART3_RXBUFSIZE=64 - -CONFIG_USART1_BAUD=115200 -CONFIG_USART2_BAUD=115200 -CONFIG_USART3_BAUD=115200 - -CONFIG_USART1_BITS=8 -CONFIG_USART2_BITS=8 -CONFIG_USART3_BITS=8 - -CONFIG_USART1_PARITY=0 -CONFIG_USART2_PARITY=0 -CONFIG_USART3_PARITY=0 - -CONFIG_USART1_2STOP=0 -CONFIG_USART2_2STOP=0 -CONFIG_USART3_2STOP=0 - -CONFIG_USART1_RXDMA=y -SERIAL_HAVE_CONSOLE_DMA=y -# Conflicts with I2C1 DMA -CONFIG_USART2_RXDMA=n -CONFIG_USART3_RXDMA=y - -# -# PX4IO specific driver settings -# -# CONFIG_HRT_TIMER -# Enables the high-resolution timer. The board definition must -# set HRT_TIMER and HRT_TIMER_CHANNEL to the timer and capture/ -# compare channels to be used. -# CONFIG_HRT_PPM -# Enables R/C PPM input using the HRT. The board definition must -# set HRT_PPM_CHANNEL to the timer capture/compare channel to be -# used, and define GPIO_PPM_IN to configure the appropriate timer -# GPIO. -# CONFIG_PWM_SERVO -# Enables the PWM servo driver. The driver configuration must be -# supplied by the board support at initialisation time. -# Note that USART2 must be disabled on the PX4 board for this to -# be available. -# -# -CONFIG_HRT_TIMER=y -CONFIG_HRT_PPM=y - -# -# General build options -# -# CONFIG_RRLOAD_BINARY - make the rrload binary format used with -# BSPs from www.ridgerun.com using the tools/mkimage.sh script -# CONFIG_INTELHEX_BINARY - make the Intel HEX binary format -# used with many different loaders using the GNU objcopy program -# Should not be selected if you are not using the GNU toolchain. -# CONFIG_MOTOROLA_SREC - make the Motorola S-Record binary format -# used with many different loaders using the GNU objcopy program -# Should not be selected if you are not using the GNU toolchain. -# CONFIG_RAW_BINARY - make a raw binary format file used with many -# different loaders using the GNU objcopy program. This option -# should not be selected if you are not using the GNU toolchain. -# CONFIG_HAVE_LIBM - toolchain supports libm.a -# -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=n -CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=y -CONFIG_HAVE_LIBM=n - -# -# General OS setup -# -# CONFIG_APPS_DIR - Identifies the relative path to the directory -# that builds the application to link with NuttX. Default: ../apps -# CONFIG_DEBUG - enables built-in debug options -# CONFIG_DEBUG_VERBOSE - enables verbose debug output -# CONFIG_DEBUG_SYMBOLS - build without optimization and with -# debug symbols (needed for use with a debugger). -# CONFIG_HAVE_CXX - Enable support for C++ -# CONFIG_HAVE_CXXINITIALIZE - The platform-specific logic includes support -# for initialization of static C++ instances for this architecture -# and for the selected toolchain (via up_cxxinitialize()). -# CONFIG_MM_REGIONS - If the architecture includes multiple -# regions of memory to allocate from, this specifies the -# number of memory regions that the memory manager must -# handle and enables the API mm_addregion(start, end); -# CONFIG_ARCH_LOWPUTC - architecture supports low-level, boot -# time console output -# CONFIG_MSEC_PER_TICK - The default system timer is 100Hz -# or MSEC_PER_TICK=10. This setting may be defined to -# inform NuttX that the processor hardware is providing -# system timer interrupts at some interrupt interval other -# than 10 msec. -# CONFIG_RR_INTERVAL - The round robin timeslice will be set -# this number of milliseconds; Round robin scheduling can -# be disabled by setting this value to zero. -# CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in -# scheduler to monitor system performance -# CONFIG_TASK_NAME_SIZE - Spcifies that maximum size of a -# task name to save in the TCB. Useful if scheduler -# instrumentation is selected. Set to zero to disable. -# CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY - -# Used to initialize the internal time logic. -# CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions. -# You would only need this if you are concerned about accurate -# time conversions in the past or in the distant future. -# CONFIG_JULIAN_TIME - Enables Julian time conversions. You -# would only need this if you are concerned about accurate -# time conversion in the distand past. You must also define -# CONFIG_GREGORIAN_TIME in order to use Julian time. -# CONFIG_DEV_CONSOLE - Set if architecture-specific logic -# provides /dev/console. Enables stdout, stderr, stdin. -# CONFIG_DEV_LOWCONSOLE - Use the simple, low-level serial console -# driver (minimul support) -# CONFIG_MUTEX_TYPES: Set to enable support for recursive and -# errorcheck mutexes. Enables pthread_mutexattr_settype(). -# CONFIG_PRIORITY_INHERITANCE : Set to enable support for priority -# inheritance on mutexes and semaphores. -# CONFIG_SEM_PREALLOCHOLDERS: This setting is only used if priority -# inheritance is enabled. It defines the maximum number of -# different threads (minus one) that can take counts on a -# semaphore with priority inheritance support. This may be -# set to zero if priority inheritance is disabled OR if you -# are only using semaphores as mutexes (only one holder) OR -# if no more than two threads participate using a counting -# semaphore. -# CONFIG_SEM_NNESTPRIO. If priority inheritance is enabled, -# then this setting is the maximum number of higher priority -# threads (minus 1) than can be waiting for another thread -# to release a count on a semaphore. This value may be set -# to zero if no more than one thread is expected to wait for -# a semaphore. -# CONFIG_FDCLONE_DISABLE. Disable cloning of all file descriptors -# by task_create() when a new task is started. If set, all -# files/drivers will appear to be closed in the new task. -# CONFIG_FDCLONE_STDIO. Disable cloning of all but the first -# three file descriptors (stdin, stdout, stderr) by task_create() -# when a new task is started. If set, all files/drivers will -# appear to be closed in the new task except for stdin, stdout, -# and stderr. -# CONFIG_SDCLONE_DISABLE. Disable cloning of all socket -# desciptors by task_create() when a new task is started. If -# set, all sockets will appear to be closed in the new task. -# CONFIG_SCHED_WORKQUEUE. Create a dedicated "worker" thread to -# handle delayed processing from interrupt handlers. This feature -# is required for some drivers but, if there are not complaints, -# can be safely disabled. The worker thread also performs -# garbage collection -- completing any delayed memory deallocations -# from interrupt handlers. If the worker thread is disabled, -# then that clean will be performed by the IDLE thread instead -# (which runs at the lowest of priority and may not be appropriate -# if memory reclamation is of high priority). If CONFIG_SCHED_WORKQUEUE -# is enabled, then the following options can also be used: -# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker -# thread. Default: 50 -# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for -# work in units of microseconds. Default: 50*1000 (50 MS). -# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker -# thread. Default: CONFIG_IDLETHREAD_STACKSIZE. -# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up -# the worker thread. Default: 4 -# CONFIG_SCHED_WAITPID - Enable the waitpid() API -# CONFIG_SCHED_ATEXIT - Enabled the atexit() API -# -CONFIG_USER_ENTRYPOINT="user_start" -#CONFIG_APPS_DIR= -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEBUG_FS=n -CONFIG_DEBUG_GRAPHICS=n -CONFIG_DEBUG_LCD=n -CONFIG_DEBUG_USB=n -CONFIG_DEBUG_NET=n -CONFIG_DEBUG_RTC=n -CONFIG_DEBUG_ANALOG=n -CONFIG_DEBUG_PWM=n -CONFIG_DEBUG_CAN=n -CONFIG_DEBUG_I2C=n -CONFIG_DEBUG_INPUT=n - -CONFIG_MSEC_PER_TICK=1 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MM_REGIONS=1 -CONFIG_MM_SMALL=y -CONFIG_ARCH_LOWPUTC=y -CONFIG_RR_INTERVAL=0 -CONFIG_SCHED_INSTRUMENTATION=n -CONFIG_TASK_NAME_SIZE=8 -CONFIG_START_YEAR=1970 -CONFIG_START_MONTH=1 -CONFIG_START_DAY=1 -CONFIG_GREGORIAN_TIME=n -CONFIG_JULIAN_TIME=n -# this eats ~1KiB of RAM ... work out why -CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=n -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=y -CONFIG_FDCLONE_STDIO=y -CONFIG_SDCLONE_DISABLE=y -CONFIG_SCHED_WORKQUEUE=n -CONFIG_SCHED_WORKPRIORITY=50 -CONFIG_SCHED_WORKPERIOD=50000 -CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 -CONFIG_SCHED_WAITPID=n -CONFIG_SCHED_ATEXIT=n - -# -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. -# -# There are certain dependency relationships in these -# features. -# -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. -# -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DISABLE_SIGNALS=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_POLL=y - -# -# Misc libc settings -# -# CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a -# little smaller if we do not support fieldwidthes -# -CONFIG_NOPRINTF_FIELDWIDTH=n - -# -# Allow for architecture optimized implementations -# -# The architecture can provide optimized versions of the -# following to improve system performance -# -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n - -# -# Sizes of configurable things (0 disables) -# -# CONFIG_MAX_TASKS - The maximum number of simultaneously -# active tasks. This value must be a power of two. -# CONFIG_MAX_TASK_ARGS - This controls the maximum number of -# of parameters that a task may receive (i.e., maxmum value -# of 'argc') -# CONFIG_NPTHREAD_KEYS - The number of items of thread- -# specific data that can be retained -# CONFIG_NFILE_DESCRIPTORS - The maximum number of file -# descriptors (one for each open) -# CONFIG_NFILE_STREAMS - The maximum number of streams that -# can be fopen'ed -# CONFIG_NAME_MAX - The maximum size of a file name. -# CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate -# on fopen. (Only if CONFIG_NFILE_STREAMS > 0) -# CONFIG_STDIO_LINEBUFFER - If standard C buffered I/O is enabled -# (CONFIG_STDIO_BUFFER_SIZE > 0), then this option may be added -# to force automatic, line-oriented flushing the output buffer -# for putc(), fputc(), putchar(), puts(), fputs(), printf(), -# fprintf(), and vfprintf(). When a newline is encountered in -# the output string, the output buffer will be flushed. This -# (slightly) increases the NuttX footprint but supports the kind -# of behavior that people expect for printf(). -# CONFIG_NUNGET_CHARS - Number of characters that can be -# buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0) -# CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message -# structures. The system manages a pool of preallocated -# message structures to minimize dynamic allocations -# CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with -# a fixed payload size given by this settin (does not include -# other message structure overhead. -# CONFIG_MAX_WDOGPARMS - Maximum number of parameters that -# can be passed to a watchdog handler -# CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog -# structures. The system manages a pool of preallocated -# watchdog structures to minimize dynamic allocations -# CONFIG_PREALLOC_TIMERS - The number of pre-allocated POSIX -# timer structures. The system manages a pool of preallocated -# timer structures to minimize dynamic allocations. Set to -# zero for all dynamic allocations. -# -CONFIG_MAX_TASKS=4 -CONFIG_MAX_TASK_ARGS=4 -CONFIG_NPTHREAD_KEYS=2 -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=0 -CONFIG_NAME_MAX=12 -CONFIG_STDIO_BUFFER_SIZE=32 -CONFIG_STDIO_LINEBUFFER=n -CONFIG_NUNGET_CHARS=2 -CONFIG_PREALLOC_MQ_MSGS=4 -CONFIG_MQ_MAXMSGSIZE=32 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_PREALLOC_TIMERS=0 - - -# -# Settings for apps/nshlib -# -# CONFIG_NSH_BUILTIN_APPS - Support external registered, -# "named" applications that can be executed from the NSH -# command line (see apps/README.txt for more information). -# CONFIG_NSH_FILEIOSIZE - Size of a static I/O buffer -# CONFIG_NSH_STRERROR - Use strerror(errno) -# CONFIG_NSH_LINELEN - Maximum length of one command line -# CONFIG_NSH_NESTDEPTH - Max number of nested if-then[-else]-fi -# CONFIG_NSH_DISABLESCRIPT - Disable scripting support -# CONFIG_NSH_DISABLEBG - Disable background commands -# CONFIG_NSH_ROMFSETC - Use startup script in /etc -# CONFIG_NSH_CONSOLE - Use serial console front end -# CONFIG_NSH_TELNET - Use telnetd console front end -# CONFIG_NSH_ARCHINIT - Platform provides architecture -# specific initialization (nsh_archinitialize()). -# - -# Disable NSH completely -CONFIG_NSH_CONSOLE=n - -# -# Stack and heap information -# -# CONFIG_BOOT_RUNFROMFLASH - Some configurations support XIP -# operation from FLASH but must copy initialized .data sections to RAM. -# (should also be =n for the STM3210E-EVAL which always runs from flash) -# CONFIG_BOOT_COPYTORAM - Some configurations boot in FLASH -# but copy themselves entirely into RAM for better performance. -# CONFIG_CUSTOM_STACK - The up_ implementation will handle -# all stack operations outside of the nuttx model. -# CONFIG_STACK_POINTER - The initial stack pointer (arm7tdmi only) -# CONFIG_IDLETHREAD_STACKSIZE - The size of the initial stack. -# This is the thread that (1) performs the inital boot of the system up -# to the point where user_start() is spawned, and (2) there after is the -# IDLE thread that executes only when there is no other thread ready to -# run. -# CONFIG_USERMAIN_STACKSIZE - The size of the stack to allocate -# for the main user thread that begins at the user_start() entry point. -# CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size -# CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size -# CONFIG_HEAP_BASE - The beginning of the heap -# CONFIG_HEAP_SIZE - The size of the heap -# -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_STACK_POINTER= -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=1200 -CONFIG_PTHREAD_STACK_MIN=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= diff --git a/nuttx/configs/px4io-v1/io/setenv.sh b/nuttx/configs/px4io-v1/io/setenv.sh deleted file mode 100755 index ff9a4bf8ae..0000000000 --- a/nuttx/configs/px4io-v1/io/setenv.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash -# configs/stm3210e-eval/dfu/setenv.sh -# -# Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi - -WD=`pwd` -export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin" -export BUILDROOT_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" -export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/nuttx/configs/px4io-v1/nsh/Make.defs b/nuttx/configs/px4io-v1/nsh/Make.defs index 87508e22ec..c7f6effd9a 100644 --- a/nuttx/configs/px4io-v1/nsh/Make.defs +++ b/nuttx/configs/px4io-v1/nsh/Make.defs @@ -1,3 +1,3 @@ include ${TOPDIR}/.config -include $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/Make.defs +include $(TOPDIR)/configs/px4io-v1/common/Make.defs diff --git a/nuttx/configs/px4io-v1/nsh/appconfig b/nuttx/configs/px4io-v1/nsh/appconfig index d5809a9391..48a41bcdb8 100644 --- a/nuttx/configs/px4io-v1/nsh/appconfig +++ b/nuttx/configs/px4io-v1/nsh/appconfig @@ -1,8 +1,6 @@ ############################################################################ -# configs/stm3210e-eval/nsh/appconfig # -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Copyright (C) 2012 PX4 Development Team. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions @@ -14,7 +12,7 @@ # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. -# 3. Neither the name NuttX nor the names of its contributors may be +# 3. Neither the name PX4 nor the names of its contributors may be # used to endorse or promote products derived from this software # without specific prior written permission. # @@ -32,12 +30,3 @@ # POSSIBILITY OF SUCH DAMAGE. # ############################################################################ - -# Path to example in apps/examples containing the user_start entry point - -CONFIGURED_APPS += examples/nsh - -CONFIGURED_APPS += system/readline -CONFIGURED_APPS += nshlib -CONFIGURED_APPS += reboot - diff --git a/nuttx/configs/px4io-v1/nsh/defconfig b/nuttx/configs/px4io-v1/nsh/defconfig index 6f4e208691..43dd1b0e85 100755 --- a/nuttx/configs/px4io-v1/nsh/defconfig +++ b/nuttx/configs/px4io-v1/nsh/defconfig @@ -1,7 +1,8 @@ ############################################################################ # configs/px4io/nsh/defconfig # -# Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2012 PX4 Development Team. All rights reserved. +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -41,7 +42,7 @@ # particular chip family that the architecture is implemented # in. # CONFIG_ARCH_architecture - for use in C code. This identifies the -# specific architecture within the chip familyl. +# specific architecture within the chip family. # CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory # CONFIG_ARCH_CHIP_name - For use in C code # CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence, @@ -51,7 +52,6 @@ # CONFIG_BOARD_LOOPSPERMSEC - for delay loops # CONFIG_DRAM_SIZE - Describes the installed DRAM. # CONFIG_DRAM_START - The start address of DRAM (physical) -# CONFIG_DRAM_END - Last address+1 of installed RAM # CONFIG_ARCH_IRQPRIO - The ST32F100CB supports interrupt prioritization # CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt # stack. If defined, this symbol is the size of the interrupt @@ -69,25 +69,30 @@ # the delay actually is 100 seconds. # CONFIG_ARCH_DMA - Support DMA initialization # -CONFIG_ARCH=arm +CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP=stm32 +CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32F100C8=y -CONFIG_ARCH_BOARD=px4io -CONFIG_ARCH_BOARD_PX4IO=y -CONFIG_BOARD_LOOPSPERMSEC=24000 +# +# Board Selection +# +CONFIG_ARCH_BOARD_PX4IO_V1=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="px4io-v1" +CONFIG_BOARD_LOOPSPERMSEC=2000 CONFIG_DRAM_SIZE=0x00002000 CONFIG_DRAM_START=0x20000000 -CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE) CONFIG_ARCH_IRQPRIO=y CONFIG_ARCH_INTERRUPTSTACK=n CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_BOOTLOADER=n -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_LEDS=n +CONFIG_ARCH_BUTTONS=n CONFIG_ARCH_CALIBRATION=n -CONFIG_ARCH_DMA=n +CONFIG_ARCH_DMA=y +CONFIG_ARCH_MATH_H=y + CONFIG_ARMV7M_CMNVECTOR=y # @@ -109,8 +114,9 @@ CONFIG_STM32_JTAG_SW_ENABLE=n # # Individual subsystems can be enabled: +# # AHB: -CONFIG_STM32_DMA1=n +CONFIG_STM32_DMA1=y CONFIG_STM32_DMA2=n CONFIG_STM32_CRC=n # APB1: @@ -131,6 +137,7 @@ CONFIG_STM32_BKP=n CONFIG_STM32_PWR=n CONFIG_STM32_DAC=n # APB2: +# We use our own ADC driver, but leave this on for clocking purposes. CONFIG_STM32_ADC1=y CONFIG_STM32_ADC2=n # TIM1 is owned by the HRT @@ -140,10 +147,6 @@ CONFIG_STM32_TIM8=n CONFIG_STM32_USART1=y CONFIG_STM32_ADC3=n -# -# Timer and I2C devices may need to the following to force power to be applied: -# -#CONFIG_STM32_FORCEPOWER=y # # STM32F100 specific serial device driver settings @@ -159,6 +162,9 @@ CONFIG_STM32_ADC3=n # CONFIG_USARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity # CONFIG_USARTn_2STOP - Two stop bits # +CONFIG_SERIAL_TERMIOS=y +CONFIG_STANDARD_SERIAL=y + CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART2_SERIAL_CONSOLE=n CONFIG_USART3_SERIAL_CONSOLE=n @@ -171,7 +177,7 @@ CONFIG_USART1_RXBUFSIZE=64 CONFIG_USART2_RXBUFSIZE=64 CONFIG_USART3_RXBUFSIZE=64 -CONFIG_USART1_BAUD=57600 +CONFIG_USART1_BAUD=115200 CONFIG_USART2_BAUD=115200 CONFIG_USART3_BAUD=115200 @@ -187,6 +193,12 @@ CONFIG_USART1_2STOP=0 CONFIG_USART2_2STOP=0 CONFIG_USART3_2STOP=0 +CONFIG_USART1_RXDMA=y +SERIAL_HAVE_CONSOLE_DMA=y +# Conflicts with I2C1 DMA +CONFIG_USART2_RXDMA=n +CONFIG_USART3_RXDMA=y + # # PX4IO specific driver settings # @@ -208,7 +220,6 @@ CONFIG_USART3_2STOP=0 # CONFIG_HRT_TIMER=y CONFIG_HRT_PPM=y -CONFIG_PWM_SERVO=y # # General build options @@ -306,9 +317,6 @@ CONFIG_HAVE_LIBM=n # CONFIG_SDCLONE_DISABLE. Disable cloning of all socket # desciptors by task_create() when a new task is started. If # set, all sockets will appear to be closed in the new task. -# CONFIG_NXFLAT. Enable support for the NXFLAT binary format. -# This format will support execution of NuttX binaries located -# in a ROMFS filesystem (see examples/nxflat). # CONFIG_SCHED_WORKQUEUE. Create a dedicated "worker" thread to # handle delayed processing from interrupt handlers. This feature # is required for some drivers but, if there are not complaints, @@ -327,39 +335,57 @@ CONFIG_HAVE_LIBM=n # thread. Default: CONFIG_IDLETHREAD_STACKSIZE. # CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up # the worker thread. Default: 4 +# CONFIG_SCHED_WAITPID - Enable the waitpid() API +# CONFIG_SCHED_ATEXIT - Enabled the atexit() API # +CONFIG_USER_ENTRYPOINT="user_start" #CONFIG_APPS_DIR= CONFIG_DEBUG=n CONFIG_DEBUG_VERBOSE=n CONFIG_DEBUG_SYMBOLS=y -CONFIG_HAVE_CXX=n -CONFIG_HAVE_CXXINITIALIZE=n +CONFIG_DEBUG_FS=n +CONFIG_DEBUG_GRAPHICS=n +CONFIG_DEBUG_LCD=n +CONFIG_DEBUG_USB=n +CONFIG_DEBUG_NET=n +CONFIG_DEBUG_RTC=n +CONFIG_DEBUG_ANALOG=n +CONFIG_DEBUG_PWM=n +CONFIG_DEBUG_CAN=n +CONFIG_DEBUG_I2C=n +CONFIG_DEBUG_INPUT=n + +CONFIG_MSEC_PER_TICK=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y CONFIG_MM_REGIONS=1 CONFIG_MM_SMALL=y CONFIG_ARCH_LOWPUTC=y -CONFIG_RR_INTERVAL=200 +CONFIG_RR_INTERVAL=0 CONFIG_SCHED_INSTRUMENTATION=n -CONFIG_TASK_NAME_SIZE=0 -CONFIG_START_YEAR=2009 -CONFIG_START_MONTH=9 -CONFIG_START_DAY=21 +CONFIG_TASK_NAME_SIZE=8 +CONFIG_START_YEAR=1970 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=1 CONFIG_GREGORIAN_TIME=n CONFIG_JULIAN_TIME=n +# this eats ~1KiB of RAM ... work out why CONFIG_DEV_CONSOLE=y CONFIG_DEV_LOWCONSOLE=n CONFIG_MUTEX_TYPES=n CONFIG_PRIORITY_INHERITANCE=n CONFIG_SEM_PREALLOCHOLDERS=0 CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n +CONFIG_FDCLONE_DISABLE=y CONFIG_FDCLONE_STDIO=y CONFIG_SDCLONE_DISABLE=y -CONFIG_NXFLAT=n CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=50 -CONFIG_SCHED_WORKPERIOD=(50*1000) -CONFIG_SCHED_WORKSTACKSIZE=512 +CONFIG_SCHED_WORKPERIOD=50000 +CONFIG_SCHED_WORKSTACKSIZE=1024 CONFIG_SIG_SIGWORK=4 +CONFIG_SCHED_WAITPID=n +CONFIG_SCHED_ATEXIT=n # # The following can be used to disable categories of @@ -378,8 +404,8 @@ CONFIG_SIG_SIGWORK=4 # CONFIG_DISABLE_CLOCK=n CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n +CONFIG_DISABLE_PTHREAD=y +CONFIG_DISABLE_SIGNALS=y CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_ENVIRON=y @@ -427,6 +453,14 @@ CONFIG_ARCH_BZERO=n # CONFIG_NAME_MAX - The maximum size of a file name. # CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate # on fopen. (Only if CONFIG_NFILE_STREAMS > 0) +# CONFIG_STDIO_LINEBUFFER - If standard C buffered I/O is enabled +# (CONFIG_STDIO_BUFFER_SIZE > 0), then this option may be added +# to force automatic, line-oriented flushing the output buffer +# for putc(), fputc(), putchar(), puts(), fputs(), printf(), +# fprintf(), and vfprintf(). When a newline is encountered in +# the output string, the output buffer will be flushed. This +# (slightly) increases the NuttX footprint but supports the kind +# of behavior that people expect for printf(). # CONFIG_NUNGET_CHARS - Number of characters that can be # buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0) # CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message @@ -448,16 +482,17 @@ CONFIG_ARCH_BZERO=n CONFIG_MAX_TASKS=4 CONFIG_MAX_TASK_ARGS=4 CONFIG_NPTHREAD_KEYS=2 -CONFIG_NFILE_DESCRIPTORS=6 -CONFIG_NFILE_STREAMS=4 -CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=0 +CONFIG_NAME_MAX=12 +CONFIG_STDIO_BUFFER_SIZE=32 +CONFIG_STDIO_LINEBUFFER=n CONFIG_NUNGET_CHARS=2 -CONFIG_PREALLOC_MQ_MSGS=1 +CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_MQ_MAXMSGSIZE=32 CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=3 -CONFIG_PREALLOC_TIMERS=1 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=0 # @@ -478,57 +513,9 @@ CONFIG_PREALLOC_TIMERS=1 # CONFIG_NSH_ARCHINIT - Platform provides architecture # specific initialization (nsh_archinitialize()). # -# If CONFIG_NSH_TELNET is selected: -# CONFIG_NSH_IOBUFFER_SIZE -- Telnetd I/O buffer size -# CONFIG_NSH_DHCPC - Obtain address using DHCP -# CONFIG_NSH_IPADDR - Provides static IP address -# CONFIG_NSH_DRIPADDR - Provides static router IP address -# CONFIG_NSH_NETMASK - Provides static network mask -# CONFIG_NSH_NOMAC - Use a bogus MAC address -# -# If CONFIG_NSH_ROMFSETC is selected: -# CONFIG_NSH_ROMFSMOUNTPT - ROMFS mountpoint -# CONFIG_NSH_INITSCRIPT - Relative path to init script -# CONFIG_NSH_ROMFSDEVNO - ROMFS RAM device minor -# CONFIG_NSH_ROMFSSECTSIZE - ROMF sector size -# CONFIG_NSH_FATDEVNO - FAT FS RAM device minor -# CONFIG_NSH_FATSECTSIZE - FAT FS sector size -# CONFIG_NSH_FATNSECTORS - FAT FS number of sectors -# CONFIG_NSH_FATMOUNTPT - FAT FS mountpoint -# -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_STRERROR=n -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_NESTDEPTH=1 -CONFIG_NSH_DISABLESCRIPT=y -CONFIG_NSH_DISABLEBG=n -CONFIG_NSH_ROMFSETC=n -CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=n -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_IOBUFFER_SIZE=256 -#CONFIG_NSH_STACKSIZE=1024 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=n -CONFIG_NSH_IPADDR=(10<<24|0<<16|0<<8|2) -CONFIG_NSH_DRIPADDR=(10<<24|0<<16|0<<8|1) -CONFIG_NSH_NETMASK=(255<<24|255<<16|255<<8|0) -CONFIG_NSH_ROMFSMOUNTPT="/etc" -CONFIG_NSH_INITSCRIPT="init.d/rcS" -CONFIG_NSH_ROMFSDEVNO=0 -CONFIG_NSH_ROMFSSECTSIZE=64 -CONFIG_NSH_FATDEVNO=1 -CONFIG_NSH_FATSECTSIZE=512 -CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT=/tmp -# -# Architecture-specific NSH options -# -CONFIG_NSH_MMCSDSPIPORTNO=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDMINOR=0 +# Disable NSH completely +CONFIG_NSH_CONSOLE=n # # Stack and heap information @@ -557,9 +544,9 @@ CONFIG_BOOT_RUNFROMFLASH=n CONFIG_BOOT_COPYTORAM=n CONFIG_CUSTOM_STACK=n CONFIG_STACK_POINTER= -CONFIG_IDLETHREAD_STACKSIZE=800 -CONFIG_USERMAIN_STACKSIZE=1024 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=512 +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=1200 +CONFIG_PTHREAD_STACK_MIN=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= diff --git a/nuttx/configs/px4io-v1/nsh/setenv.sh b/nuttx/configs/px4io-v1/nsh/setenv.sh index d836851921..ff9a4bf8ae 100755 --- a/nuttx/configs/px4io-v1/nsh/setenv.sh +++ b/nuttx/configs/px4io-v1/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/stm3210e-eval/dfu/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions @@ -41,7 +41,7 @@ if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi WD=`pwd` export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin" -export BUILDROOT_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" +export BUILDROOT_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" From a9fcb58d1adacffa644a61baafcdbe54e54389b9 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sat, 1 Jun 2013 12:39:52 +0200 Subject: [PATCH 06/41] Config improvements --- nuttx/arch/arm/src/armv7-m/up_stackcheck.c | 40 + nuttx/arch/arm/src/stm32/Make.defs | 2 +- nuttx/arch/arm/src/stm32/stm32_i2c.c | 2232 ++++++++++---------- nuttx/configs/px4fmu-v1/nsh/defconfig | 15 +- nuttx/configs/px4io-v1/nsh/defconfig | 8 +- 5 files changed, 1179 insertions(+), 1118 deletions(-) create mode 100644 nuttx/arch/arm/src/armv7-m/up_stackcheck.c diff --git a/nuttx/arch/arm/src/armv7-m/up_stackcheck.c b/nuttx/arch/arm/src/armv7-m/up_stackcheck.c new file mode 100644 index 0000000000..e8f02a863b --- /dev/null +++ b/nuttx/arch/arm/src/armv7-m/up_stackcheck.c @@ -0,0 +1,40 @@ + + +void __cyg_profile_func_enter(void *func, void *caller) __attribute__((naked, no_instrument_function)); +void __cyg_profile_func_exit(void *func, void *caller) __attribute__((naked, no_instrument_function)); +void __stack_overflow_trap(void) __attribute__((naked, no_instrument_function)); + +void +__stack_overflow_trap(void) +{ + /* if we get here, the stack has overflowed */ + asm ( "b ."); +} + +void +__cyg_profile_func_enter(void *func, void *caller) +{ + asm volatile ( + " mrs r2, ipsr \n" /* Check whether we are in interrupt mode */ + " cmp r2, #0 \n" /* since we don't switch r10 on interrupt entry, we */ + " bne 2f \n" /* can't detect overflow of the interrupt stack. */ + " \n" + " sub r2, sp, #68 \n" /* compute stack pointer as though we just stacked a full frame */ + " mrs r1, control \n" /* Test CONTROL.FPCA to see whether we also need room for the FP */ + " tst r1, #4 \n" /* context. */ + " beq 1f \n" + " sub r2, r2, #136 \n" /* subtract FP context frame size */ + "1: \n" + " cmp r2, r10 \n" /* compare stack with limit */ + " bgt 2f \n" /* stack is above limit and thus OK */ + " b __stack_overflow_trap\n" + "2: \n" + " bx lr \n" + ); +} + +void +__cyg_profile_func_exit(void *func, void *caller) +{ + asm volatile("bx lr"); +} diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs index 15b87ca9e8..cb979957d1 100644 --- a/nuttx/arch/arm/src/stm32/Make.defs +++ b/nuttx/arch/arm/src/stm32/Make.defs @@ -52,7 +52,7 @@ CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_systemreset.c CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c -CMN_CSRCS += up_svcall.c up_vfork.c +CMN_CSRCS += up_svcall.c up_stackcheck.c up_vfork.c ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) CMN_ASRCS += up_exception.S diff --git a/nuttx/arch/arm/src/stm32/stm32_i2c.c b/nuttx/arch/arm/src/stm32/stm32_i2c.c index c56870ee8a..c02bf4543f 100644 --- a/nuttx/arch/arm/src/stm32/stm32_i2c.c +++ b/nuttx/arch/arm/src/stm32/stm32_i2c.c @@ -123,14 +123,8 @@ /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32_I2CTIMEOTICKS -# define CONFIG_STM32_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) -#endif - -#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) -#endif +#define CONFIG_STM32_I2CTIMEOTICKS \ +(SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) /* On the STM32F103ZE, there is an internal conflict between I2C1 and FSMC. In that * case, it is necessary to disable FSMC before each I2C1 access and re-enable FSMC @@ -142,18 +136,6 @@ # define I2C1_FSMC_CONFLICT #endif -/* Macros to convert a I2C pin to a GPIO output */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ - GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ - GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) -#endif - -#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) - /* Debug ****************************************************************************/ /* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */ @@ -188,97 +170,115 @@ enum stm32_intstate_e { - INTSTATE_IDLE = 0, /* No I2C activity */ - INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ - INTSTATE_DONE, /* Interrupt activity complete */ + INTSTATE_IDLE = 0, /* No I2C activity */ + INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ + INTSTATE_DONE, /* Interrupt activity complete */ }; /* Trace events */ enum stm32_trace_e { - I2CEVENT_NONE = 0, /* No events have occurred with this status */ - I2CEVENT_SENDADDR, /* Start/Master bit set and address sent, param = msgc */ - I2CEVENT_SENDBYTE, /* Send byte, param = dcnt */ - I2CEVENT_ITBUFEN, /* Enable buffer interrupts, param = 0 */ - I2CEVENT_RCVBYTE, /* Read more dta, param = dcnt */ - I2CEVENT_REITBUFEN, /* Re-enable buffer interrupts, param = 0 */ - I2CEVENT_DISITBUFEN, /* Disable buffer interrupts, param = 0 */ - I2CEVENT_BTFNOSTART, /* BTF on last byte with no restart, param = msgc */ - I2CEVENT_BTFRESTART, /* Last byte sent, re-starting, param = msgc */ - I2CEVENT_BTFSTOP, /* Last byte sten, send stop, param = 0 */ - I2CEVENT_ERROR /* Error occurred, param = 0 */ + I2CEVENT_NONE = 0, /* No events have occurred with this status */ + I2CEVENT_SENDADDR, /* Start/Master bit set and address sent, param = msgc */ + I2CEVENT_SENDBYTE, /* Send byte, param = dcnt */ + I2CEVENT_ITBUFEN, /* Enable buffer interrupts, param = 0 */ + I2CEVENT_RCVBYTE, /* Read more dta, param = dcnt */ + I2CEVENT_REITBUFEN, /* Re-enable buffer interrupts, param = 0 */ + I2CEVENT_DISITBUFEN, /* Disable buffer interrupts, param = 0 */ + I2CEVENT_BTFNOSTART, /* BTF on last byte with no restart, param = msgc */ + I2CEVENT_BTFRESTART, /* Last byte sent, re-starting, param = msgc */ + I2CEVENT_BTFSTOP, /* Last byte sten, send stop, param = 0 */ + I2CEVENT_ERROR /* Error occurred, param = 0 */ +}; + +#ifdef CONFIG_I2C_TRACE +static const char *stm32_trace_names[] = { + "NONE ", + "SENDADDR ", + "SENDBYTE ", + "ITBUFEN ", + "RCVBYTE ", + "REITBUFEN ", + "DISITBUFEN", + "BTFNOSTART", + "BTFRESTART", + "BTFSTOP ", + "ERROR " }; +#endif /* Trace data */ struct stm32_trace_s { - uint32_t status; /* I2C 32-bit SR2|SR1 status */ - uint32_t count; /* Interrupt count when status change */ - enum stm32_intstate_e event; /* Last event that occurred with this status */ - uint32_t parm; /* Parameter associated with the event */ - uint32_t time; /* First of event or first status */ + uint32_t status; /* I2C 32-bit SR2|SR1 status */ + uint32_t count; /* Interrupt count when status change */ + enum stm32_intstate_e event; /* Last event that occurred with this status */ + uint32_t parm; /* Parameter associated with the event */ + uint32_t time; /* First of event or first status */ }; /* I2C Device hardware configuration */ struct stm32_i2c_config_s { - uint32_t base; /* I2C base address */ - uint32_t clk_bit; /* Clock enable bit */ - uint32_t reset_bit; /* Reset bit */ - uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ - uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ + uint32_t base; /* I2C base address */ #ifndef CONFIG_I2C_POLLED - int (*isr)(int, void *); /* Interrupt handler */ - uint32_t ev_irq; /* Event IRQ */ - uint32_t er_irq; /* Error IRQ */ + int ( *isr)(int, void *); /* Interrupt handler */ #endif + uint32_t clk_bit; /* Clock enable bit */ + uint32_t reset_bit; /* Reset bit */ + uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ + uint32_t scl_gpio; /* GPIO configuration for SCL as a GPIO */ + uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ + uint32_t sda_gpio; /* GPIO configuration for SDA as a GPIO */ + uint32_t ev_irq; /* Event IRQ */ + uint32_t er_irq; /* Error IRQ */ }; /* I2C Device Private Data */ struct stm32_i2c_priv_s { - const struct stm32_i2c_config_s *config; /* Port configuration */ - int refs; /* Referernce count */ - sem_t sem_excl; /* Mutual exclusion semaphore */ + const struct stm32_i2c_config_s *config; /* Port configuration */ + int refs; /* Referernce count */ + sem_t sem_excl; /* Mutual exclusion semaphore */ #ifndef CONFIG_I2C_POLLED - sem_t sem_isr; /* Interrupt wait semaphore */ + sem_t sem_isr; /* Interrupt wait semaphore */ #endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ + + uint8_t msgc; /* Message count */ + struct i2c_msg_s *msgv; /* Message list */ + uint8_t *ptr; /* Current message buffer */ + int dcnt; /* Current message length */ + uint16_t flags; /* Current message flags */ + + /* I2C trace support */ - uint8_t msgc; /* Message count */ - struct i2c_msg_s *msgv; /* Message list */ - uint8_t *ptr; /* Current message buffer */ - int dcnt; /* Current message length */ - uint16_t flags; /* Current message flags */ - - /* I2C trace support */ - #ifdef CONFIG_I2C_TRACE - int tndx; /* Trace array index */ - uint32_t start_time; /* Time when the trace was started */ - - /* The actual trace data */ - - struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; + int tndx; /* Trace array index */ + uint32_t start_time; /* Time when the trace was started */ + + /* The actual trace data */ + + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; #endif - - uint32_t status; /* End of transfer SR2|SR1 status */ + + uint32_t status; /* End of transfer SR2|SR1 status */ }; /* I2C Device, Instance */ struct stm32_i2c_inst_s { - struct i2c_ops_s *ops; /* Standard I2C operations */ - struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ + struct i2c_ops_s *ops; /* Standard I2C operations */ + struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ - uint32_t frequency; /* Frequency used in this instantiation */ - int address; /* Address used in this instantiation */ - uint16_t flags; /* Flags used in this instantiation */ + uint32_t frequency; /* Frequency used in this instantiation */ + int address; /* Address used in this instantiation */ + uint16_t flags; /* Flags used in this instantiation */ }; /************************************************************************************ @@ -293,11 +293,8 @@ static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t clearbits, uint16_t setbits); static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev); -#ifdef CONFIG_STM32_I2C_DYNTIMEO -static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32_I2C_DYNTIMEO */ -static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv); +static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int timeout_us); +static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv, int timeout_us); static inline void stm32_i2c_sem_post(FAR struct i2c_dev_s *dev); static inline void stm32_i2c_sem_init(FAR struct i2c_dev_s *dev); static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev); @@ -305,7 +302,7 @@ static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev); static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv); static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status); static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, - enum stm32_trace_e event, uint32_t parm); + enum stm32_trace_e event, uint32_t parm); static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv); #endif /* CONFIG_I2C_TRACE */ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, @@ -338,7 +335,7 @@ static int stm32_i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits); static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count); static int stm32_i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, - int buflen); + int buflen); static int stm32_i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen); #ifdef CONFIG_I2C_WRITEREAD static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev, @@ -355,89 +352,116 @@ static int stm32_i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *m ************************************************************************************/ #ifdef CONFIG_STM32_I2C1 -static const struct stm32_i2c_config_s stm32_i2c1_config = +# ifndef GPIO_I2C1_SCL_GPIO +# define GPIO_I2C1_SCL_GPIO 0 +# endif +# ifndef GPIO_I2C1_SDA_GPIO +# define GPIO_I2C1_SDA_GPIO 0 +# endif + +static const struct stm32_i2c_config_s stm32_i2c1_config = { - .base = STM32_I2C1_BASE, - .clk_bit = RCC_APB1ENR_I2C1EN, - .reset_bit = RCC_APB1RSTR_I2C1RST, - .scl_pin = GPIO_I2C1_SCL, - .sda_pin = GPIO_I2C1_SDA, + .base = STM32_I2C1_BASE, #ifndef CONFIG_I2C_POLLED - .isr = stm32_i2c1_isr, - .ev_irq = STM32_IRQ_I2C1EV, - .er_irq = STM32_IRQ_I2C1ER + .isr = stm32_i2c1_isr, #endif + .clk_bit = RCC_APB1ENR_I2C1EN, + .reset_bit = RCC_APB1RSTR_I2C1RST, + .scl_pin = GPIO_I2C1_SCL, + .scl_gpio = GPIO_I2C1_SCL_GPIO, + .sda_pin = GPIO_I2C1_SDA, + .sda_gpio = GPIO_I2C1_SDA_GPIO, + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER }; struct stm32_i2c_priv_s stm32_i2c1_priv = { - .config = &stm32_i2c1_config, - .refs = 0, - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0 + .config = &stm32_i2c1_config, + .refs = 0, + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 }; #endif #ifdef CONFIG_STM32_I2C2 -static const struct stm32_i2c_config_s stm32_i2c2_config = +# ifndef GPIO_I2C2_SCL_GPIO +# define GPIO_I2C2_SCL_GPIO 0 +# endif +# ifndef GPIO_I2C2_SDA_GPIO +# define GPIO_I2C2_SDA_GPIO 0 +# endif + +static const struct stm32_i2c_config_s stm32_i2c2_config = { - .base = STM32_I2C2_BASE, - .clk_bit = RCC_APB1ENR_I2C2EN, - .reset_bit = RCC_APB1RSTR_I2C2RST, - .scl_pin = GPIO_I2C2_SCL, - .sda_pin = GPIO_I2C2_SDA, -#ifndef CONFIG_I2C_POLLED - .isr = stm32_i2c2_isr, - .ev_irq = STM32_IRQ_I2C2EV, - .er_irq = STM32_IRQ_I2C2ER + .base = STM32_I2C2_BASE, +#ifndef CONFIG_I2C_POLLED + .isr = stm32_i2c2_isr, #endif + .clk_bit = RCC_APB1ENR_I2C2EN, + .reset_bit = RCC_APB1RSTR_I2C2RST, + .scl_pin = GPIO_I2C2_SCL, + .scl_gpio = GPIO_I2C2_SCL_GPIO, + .sda_pin = GPIO_I2C2_SDA, + .sda_gpio = GPIO_I2C2_SDA_GPIO, + .ev_irq = STM32_IRQ_I2C2EV, + .er_irq = STM32_IRQ_I2C2ER }; struct stm32_i2c_priv_s stm32_i2c2_priv = { - .config = &stm32_i2c2_config, - .refs = 0, - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0 + .config = &stm32_i2c2_config, + .refs = 0, + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 }; #endif #ifdef CONFIG_STM32_I2C3 -static const struct stm32_i2c_config_s stm32_i2c3_config = +# ifndef GPIO_I2C3_SCL_GPIO +# define GPIO_I2C3_SCL_GPIO 0 +# endif +# ifndef GPIO_I2C3_SDA_GPIO +# define GPIO_I2C3_SDA_GPIO 0 +# endif + +static const struct stm32_i2c_config_s stm32_i2c3_config = { - .base = STM32_I2C3_BASE, - .clk_bit = RCC_APB1ENR_I2C3EN, - .reset_bit = RCC_APB1RSTR_I2C3RST, - .scl_pin = GPIO_I2C3_SCL, - .sda_pin = GPIO_I2C3_SDA, + .base = STM32_I2C3_BASE, #ifndef CONFIG_I2C_POLLED - .isr = stm32_i2c3_isr, - .ev_irq = STM32_IRQ_I2C3EV, - .er_irq = STM32_IRQ_I2C3ER + .isr = stm32_i2c3_isr, #endif + .clk_bit = RCC_APB1ENR_I2C3EN, + .reset_bit = RCC_APB1RSTR_I2C3RST, + .scl_pin = GPIO_I2C3_SCL, + .scl_gpio = GPIO_I2C3_SCL_GPIO, + .sda_pin = GPIO_I2C3_SDA, + .sda_gpio = GPIO_I2C3_SDA_GPIO, + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER }; struct stm32_i2c_priv_s stm32_i2c3_priv = { - .config = &stm32_i2c3_config, - .refs = 0, - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0 + .config = &stm32_i2c3_config, + .refs = 0, + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 }; #endif @@ -445,18 +469,18 @@ struct stm32_i2c_priv_s stm32_i2c3_priv = struct i2c_ops_s stm32_i2c_ops = { - .setfrequency = stm32_i2c_setfrequency, - .setaddress = stm32_i2c_setaddress, - .write = stm32_i2c_write, - .read = stm32_i2c_read + .setfrequency = stm32_i2c_setfrequency, + .setaddress = stm32_i2c_setaddress, + .write = stm32_i2c_write, + .read = stm32_i2c_read #ifdef CONFIG_I2C_WRITEREAD - , .writeread = stm32_i2c_writeread + , .writeread = stm32_i2c_writeread #endif #ifdef CONFIG_I2C_TRANSFER - , .transfer = stm32_i2c_transfer + , .transfer = stm32_i2c_transfer #endif #ifdef CONFIG_I2C_SLAVE - , .setownaddress = stm32_i2c_setownaddress, + , .setownaddress = stm32_i2c_setownaddress, .registercallback = stm32_i2c_registercallback #endif }; @@ -476,7 +500,7 @@ struct i2c_ops_s stm32_i2c_ops = static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset) { - return getreg16(priv->config->base + offset); + return getreg16(priv->config->base + offset); } /************************************************************************************ @@ -490,7 +514,7 @@ static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value) { - putreg16(value, priv->config->base + offset); + putreg16(value, priv->config->base + offset); } /************************************************************************************ @@ -505,7 +529,7 @@ static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(priv->config->base + offset, clearbits, setbits); + modifyreg16(priv->config->base + offset, clearbits, setbits); } /************************************************************************************ @@ -518,40 +542,11 @@ static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev) { - while (sem_wait(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl) != 0) - { - ASSERT(errno == EINTR); - } -} - -/************************************************************************************ - * Name: stm32_i2c_tousecs - * - * Description: - * Return a micro-second delay based on the number of bytes left to be processed. - * - ************************************************************************************/ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) -{ - size_t bytecount = 0; - int i; - - /* Count the number of bytes left to process */ - - for (i = 0; i < msgc; i++) + while (sem_wait(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl) != 0) { - bytecount += msgs[i].length; + ASSERT(errno == EINTR); } - - /* Then return a number of microseconds based on a user provided scaling - * factor. - */ - - return (useconds_t)(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } -#endif /************************************************************************************ * Name: stm32_i2c_sem_waitdone @@ -562,137 +557,133 @@ static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) ************************************************************************************/ #ifndef CONFIG_I2C_POLLED -static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) +static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int timeout_us) { - struct timespec abstime; - irqstate_t flags; - uint32_t regval; - int ret; - - flags = irqsave(); - - /* Enable I2C interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); - - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * sem_timedwait() sleeps. - */ - - priv->intstate = INTSTATE_WAITING; - do + struct timespec abstime; + irqstate_t flags; + uint32_t regval; + int ret; + + flags = irqsave(); + + /* Enable I2C interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * sem_timedwait() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + do { - /* Get the current time */ - - (void)clock_gettime(CLOCK_REALTIME, &abstime); - - /* Calculate a time in the future */ - + /* Get the current time */ + + (void)clock_gettime(CLOCK_REALTIME, &abstime); + + /* Calculate a time in the future */ + #if CONFIG_STM32_I2CTIMEOSEC > 0 - abstime.tv_sec += CONFIG_STM32_I2CTIMEOSEC; + abstime.tv_sec += CONFIG_STM32_I2CTIMEOSEC; #endif - - /* Add a value proportional to the number of bytes in the transfer */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv); - if (abstime.tv_nsec > 1000 * 1000 * 1000) +#if CONFIG_STM32_I2CTIMEOUS_PER_BYTE > 0 + + /* Count the number of bytes left to process */ + int i; + int bytecount = 0; + for (i = 0; i < priv->msgc; i++) { - abstime.tv_sec++; - abstime.tv_nsec -= 1000 * 1000 * 1000; + bytecount += priv->msgv[i].length; } - + + abstime.tv_nsec += (CONFIG_STM32_I2CTIMEOUS_PER_BYTE * bytecount) * 1000; + if (abstime.tv_nsec > 1000 * 1000 * 1000) + { + abstime.tv_sec++; + abstime.tv_nsec -= 1000 * 1000 * 1000; + } + #elif CONFIG_STM32_I2CTIMEOMS > 0 - abstime.tv_nsec += CONFIG_STM32_I2CTIMEOMS * 1000 * 1000; - if (abstime.tv_nsec > 1000 * 1000 * 1000) + abstime.tv_nsec += CONFIG_STM32_I2CTIMEOMS * 1000 * 1000; + if (abstime.tv_nsec > 1000 * 1000 * 1000) { - abstime.tv_sec++; - abstime.tv_nsec -= 1000 * 1000 * 1000; + abstime.tv_sec++; + abstime.tv_nsec -= 1000 * 1000 * 1000; } #endif - /* Wait until either the transfer is complete or the timeout expires */ - - ret = sem_timedwait(&priv->sem_isr, &abstime); - if (ret != OK && errno != EINTR) + /* Wait until either the transfer is complete or the timeout expires */ + + ret = sem_timedwait(&priv->sem_isr, &abstime); + if (ret != OK && errno != EINTR) { - /* Break out of the loop on irrecoverable errors. This would - * include timeouts and mystery errors reported by sem_timedwait. - * NOTE that we try again if we are awakened by a signal (EINTR). - */ - - break; + /* Break out of the loop on irrecoverable errors. This would + * include timeouts and mystery errors reported by sem_timedwait. + * NOTE that we try again if we are awakened by a signal (EINTR). + */ + + break; } } - - /* Loop until the interrupt level transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE); - - /* Set the interrupt state back to IDLE */ - - priv->intstate = INTSTATE_IDLE; - - /* Disable I2C interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval &= ~I2C_CR2_ALLINTS; - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); - - irqrestore(flags); - return ret; + + /* Loop until the interrupt level transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE); + + /* Set the interrupt state back to IDLE */ + + priv->intstate = INTSTATE_IDLE; + + /* Disable I2C interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + irqrestore(flags); + return ret; } #else -static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) +static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int timeout_us) { - uint32_t timeout; - uint32_t start; - uint32_t elapsed; - int ret; - - /* Get the timeout value */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv)); -#else - timeout = CONFIG_STM32_I2CTIMEOTICKS; -#endif - - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * sem_timedwait() sleeps. - */ - - priv->intstate = INTSTATE_WAITING; - start = clock_systimer(); - - do + uint32_t start; + uint32_t elapsed; + int ret; + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * sem_timedwait() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + start = clock_systimer(); + + do { - /* Poll by simply calling the timer interrupt handler until it - * reports that it is done. - */ - - stm32_i2c_isr(priv); - - /* Calculate the elapsed time */ - - elapsed = clock_systimer() - start; + /* Poll by simply calling the timer interrupt handler until it + * reports that it is done. + */ + + stm32_i2c_isr(priv); + + /* Calculate the elapsed time */ + + elapsed = clock_systimer() - start; } - - /* Loop until the transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE && elapsed < timeout); - - i2cvdbg("intstate: %d elapsed: %d threshold: %d status: %08x\n", - priv->intstate, elapsed, timeout, priv->status); - - /* Set the interrupt state back to IDLE */ - - ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; - priv->intstate = INTSTATE_IDLE; - return ret; + + /* Loop until the transfer is complete. */ + while (priv->intstate != INTSTATE_DONE && elapsed < USEC2TICK(timeout_us)); + + i2cvdbg("intstate: %d elapsed: %d threshold: %d status: %08x\n", + priv->intstate, elapsed, USEC2TICK(timeout_us), priv->status); + + /* Set the interrupt state back to IDLE */ + + ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; + priv->intstate = INTSTATE_IDLE; + return ret; } #endif @@ -704,61 +695,52 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) * ************************************************************************************/ -static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) +static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv, int timeout_us) { - uint32_t start; - uint32_t elapsed; - uint32_t timeout; - uint32_t cr1; - uint32_t sr1; - - /* Select a timeout */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); -#else - timeout = CONFIG_STM32_I2CTIMEOTICKS; -#endif - - /* Wait as stop might still be in progress; but stop might also - * be set because of a timeout error: "The [STOP] bit is set and - * cleared by software, cleared by hardware when a Stop condition is - * detected, set by hardware when a timeout error is detected." - */ - - start = clock_systimer(); - do + uint32_t start; + uint32_t elapsed; + uint32_t cr1; + uint32_t sr1; + + /* Wait as stop might still be in progress; but stop might also + * be set because of a timeout error: "The [STOP] bit is set and + * cleared by software, cleared by hardware when a Stop condition is + * detected, set by hardware when a timeout error is detected." + */ + + start = clock_systimer(); + do { - /* Check for STOP condition */ - - cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); - if ((cr1 & I2C_CR1_STOP) == 0) + /* Check for STOP condition */ + + cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); + if ((cr1 & I2C_CR1_STOP) == 0) { - return; + return; } - - /* Check for timeout error */ - - sr1 = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); - if ((sr1 & I2C_SR1_TIMEOUT) != 0) + + /* Check for timeout error */ + + sr1 = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + if ((sr1 & I2C_SR1_TIMEOUT) != 0) { - return; - } - - /* Calculate the elapsed time */ - - elapsed = clock_systimer() - start; + return; + } + + /* Calculate the elapsed time */ + + elapsed = clock_systimer() - start; } - - /* Loop until the stop is complete or a timeout occurs. */ - - while (elapsed < timeout); - - /* If we get here then a timeout occurred with the STOP condition - * still pending. - */ - - i2cvdbg("Timeout with CR1: %04x SR1: %04x\n", cr1, sr1); + + /* Loop until the stop is complete or a timeout occurs. */ + + while (elapsed < USEC2TICK(timeout_us)); + + /* If we get here then a timeout occurred with the STOP condition + * still pending. + */ + + i2cvdbg("Timeout with CR1: %04x SR1: %04x\n", cr1, sr1); } /************************************************************************************ @@ -771,7 +753,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_sem_post(FAR struct i2c_dev_s *dev) { - sem_post( &((struct stm32_i2c_inst_s *)dev)->priv->sem_excl ); + sem_post( &((struct stm32_i2c_inst_s *)dev)->priv->sem_excl ); } /************************************************************************************ @@ -784,9 +766,9 @@ static inline void stm32_i2c_sem_post(FAR struct i2c_dev_s *dev) static inline void stm32_i2c_sem_init(FAR struct i2c_dev_s *dev) { - sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl, 0, 1); + sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl, 0, 1); #ifndef CONFIG_I2C_POLLED - sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0); + sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0); #endif } @@ -800,9 +782,9 @@ static inline void stm32_i2c_sem_init(FAR struct i2c_dev_s *dev) static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev) { - sem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl); + sem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl); #ifndef CONFIG_I2C_POLLED - sem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr); + sem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr); #endif } @@ -817,102 +799,103 @@ static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev) #ifdef CONFIG_I2C_TRACE static void stm32_i2c_traceclear(FAR struct stm32_i2c_priv_s *priv) { - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - trace->status = 0; /* I2C 32-bit SR2|SR1 status */ - trace->count = 0; /* Interrupt count when status change */ - trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ - trace->parm = 0; /* Parameter associated with the event */ - trace->time = 0; /* Time of first status or event */ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + trace->status = 0; /* I2C 32-bit SR2|SR1 status */ + trace->count = 0; /* Interrupt count when status change */ + trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ + trace->parm = 0; /* Parameter associated with the event */ + trace->time = 0; /* Time of first status or event */ } static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv) { - /* Reset the trace info for a new data collection */ - - priv->tndx = 0; - priv->start_time = clock_systimer(); - stm32_i2c_traceclear(priv); + /* Reset the trace info for a new data collection */ + + priv->tndx = 0; + priv->start_time = clock_systimer(); + stm32_i2c_traceclear(priv); } static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status) { - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - /* Is the current entry uninitialized? Has the status changed? */ - - if (trace->count == 0 || status != trace->status) + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + /* Is the current entry uninitialized? Has the status changed? */ + + if (trace->count == 0 || status != trace->status) { - /* Yes.. Was it the status changed? */ - - if (trace->count != 0) + /* Yes.. Was it the status changed? */ + + if (trace->count != 0) { - /* Yes.. bump up the trace index (unless we are out of trace entries) */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) + /* Yes.. bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cdbg("Trace table overflow\n"); - return; + i2cdbg("Trace table overflow\n"); + return; } - - priv->tndx++; - trace = &priv->trace[priv->tndx]; + + priv->tndx++; + trace = &priv->trace[priv->tndx]; } - - /* Initialize the new trace entry */ - - stm32_i2c_traceclear(priv); - trace->status = status; - trace->count = 1; - trace->time = clock_systimer(); + + /* Initialize the new trace entry */ + + stm32_i2c_traceclear(priv); + trace->status = status; + trace->count = 1; + trace->time = clock_systimer(); } - else + else { - /* Just increment the count of times that we have seen this status */ - - trace->count++; + /* Just increment the count of times that we have seen this status */ + + trace->count++; } } static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, - enum stm32_trace_e event, uint32_t parm) + enum stm32_trace_e event, uint32_t parm) { - struct stm32_trace_s *trace; - - if (event != I2CEVENT_NONE) + struct stm32_trace_s *trace; + + if (event != I2CEVENT_NONE) { - trace = &priv->trace[priv->tndx]; - - /* Initialize the new trace entry */ - - trace->event = event; - trace->parm = parm; - - /* Bump up the trace index (unless we are out of trace entries) */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) + trace = &priv->trace[priv->tndx]; + + /* Initialize the new trace entry */ + + trace->event = event; + trace->parm = parm; + trace->time = clock_systimer(); + + /* Bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cdbg("Trace table overflow\n"); - return; + i2cdbg("Trace table overflow\n"); + return; } - - priv->tndx++; - stm32_i2c_traceclear(priv); + + priv->tndx++; + stm32_i2c_traceclear(priv); } } static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv) { - struct stm32_trace_s *trace; - int i; - - syslog("Elapsed time: %d\n", clock_systimer() - priv->start_time); - for (i = 0; i <= priv->tndx; i++) + struct stm32_trace_s *trace; + int i; + + syslog("Elapsed time: %d\n", clock_systimer() - priv->start_time); + for (i = 0; i <= priv->tndx; i++) { - trace = &priv->trace[i]; - syslog("%2d. STATUS: %08x COUNT: %3d EVENT: %2d PARM: %08x TIME: %d\n", - i+1, trace->status, trace->count, trace->event, trace->parm, - trace->time - priv->start_time); + trace = &priv->trace[i]; + syslog("%2d. STATUS: %08x COUNT: %3d EVENT: %s PARM: %08x TIME: %d\n", + i+1, trace->status, trace->count, stm32_trace_names[trace->event], trace->parm, + trace->time - priv->start_time); } } #endif /* CONFIG_I2C_TRACE */ @@ -927,94 +910,94 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv) static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequency) { - uint16_t cr1; - uint16_t ccr; - uint16_t trise; - uint16_t freqmhz; - uint16_t speed; - - /* Disable the selected I2C peripheral to configure TRISE */ - - cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1 & ~I2C_CR1_PE); - - /* Update timing and control registers */ - - freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000); - ccr = 0; - - /* Configure speed in standard mode */ - - if (frequency <= 100000) + uint16_t cr1; + uint16_t ccr; + uint16_t trise; + uint16_t freqmhz; + uint16_t speed; + + /* Disable the selected I2C peripheral to configure TRISE */ + + cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1 & ~I2C_CR1_PE); + + /* Update timing and control registers */ + + freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000); + ccr = 0; + + /* Configure speed in standard mode */ + + if (frequency <= 100000) { - /* Standard mode speed calculation */ - - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1)); - - /* The CCR fault must be >= 4 */ - - if (speed < 4) + /* Standard mode speed calculation */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1)); + + /* The CCR fault must be >= 4 */ + + if (speed < 4) { - /* Set the minimum allowed value */ - - speed = 4; + /* Set the minimum allowed value */ + + speed = 4; } - ccr |= speed; - - /* Set Maximum Rise Time for standard mode */ - - trise = freqmhz + 1; + ccr |= speed; + + /* Set Maximum Rise Time for standard mode */ + + trise = freqmhz + 1; } - - /* Configure speed in fast mode */ - - else /* (frequency <= 400000) */ + + /* Configure speed in fast mode */ + + else /* (frequency <= 400000) */ { - /* Fast mode speed calculation with Tlow/Thigh = 16/9 */ - + /* Fast mode speed calculation with Tlow/Thigh = 16/9 */ + #ifdef CONFIG_STM32_I2C_DUTY16_9 - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25)); - - /* Set DUTY and fast speed bits */ - - ccr |= (I2C_CCR_DUTY|I2C_CCR_FS); + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25)); + + /* Set DUTY and fast speed bits */ + + ccr |= (I2C_CCR_DUTY|I2C_CCR_FS); #else - /* Fast mode speed calculation with Tlow/Thigh = 2 */ - - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3)); - - /* Set fast speed bit */ - - ccr |= I2C_CCR_FS; + /* Fast mode speed calculation with Tlow/Thigh = 2 */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3)); + + /* Set fast speed bit */ + + ccr |= I2C_CCR_FS; #endif - - /* Verify that the CCR speed value is nonzero */ - - if (speed < 1) + + /* Verify that the CCR speed value is nonzero */ + + if (speed < 1) { - /* Set the minimum allowed value */ - - speed = 1; + /* Set the minimum allowed value */ + + speed = 1; } - ccr |= speed; - - /* Set Maximum Rise Time for fast mode */ - - trise = (uint16_t)(((freqmhz * 300) / 1000) + 1); + ccr |= speed; + + /* Set Maximum Rise Time for fast mode */ + + trise = (uint16_t)(((freqmhz * 300) / 1000) + 1); } - - /* Write the new values of the CCR and TRISE registers */ - - stm32_i2c_putreg(priv, STM32_I2C_CCR_OFFSET, ccr); - stm32_i2c_putreg(priv, STM32_I2C_TRISE_OFFSET, trise); - - /* Bit 14 of OAR1 must be configured and kept at 1 */ - - stm32_i2c_putreg(priv, STM32_I2C_OAR1_OFFSET, I2C_OAR1_ONE); - - /* Re-enable the peripheral (or not) */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1); + + /* Write the new values of the CCR and TRISE registers */ + + stm32_i2c_putreg(priv, STM32_I2C_CCR_OFFSET, ccr); + stm32_i2c_putreg(priv, STM32_I2C_TRISE_OFFSET, trise); + + /* Bit 14 of OAR1 must be configured and kept at 1 */ + + stm32_i2c_putreg(priv, STM32_I2C_OAR1_OFFSET, I2C_OAR1_ONE); + + /* Re-enable the peripheral (or not) */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1); } /************************************************************************************ @@ -1027,9 +1010,9 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) { - /* Disable ACK on receive by default and generate START */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_START); + /* Disable ACK on receive by default and generate START */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_START); } /************************************************************************************ @@ -1042,25 +1025,25 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv) { - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." - * - * "The [STOP] bit is set and cleared by software, cleared by hardware - * when a Stop condition is detected, set by hardware when a timeout - * error is detected. - * - * "This [START] bit is set and cleared by software and cleared by hardware - * when start is sent or PE=0." The bit must be cleared by software if the - * START is never sent. - * - * "This [PEC] bit is set and cleared by software, and cleared by hardware - * when PEC is transferred or by a START or Stop condition or when PE=0." - */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, - I2C_CR1_START|I2C_CR1_STOP|I2C_CR1_PEC, 0); + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." + * + * "The [STOP] bit is set and cleared by software, cleared by hardware + * when a Stop condition is detected, set by hardware when a timeout + * error is detected. + * + * "This [START] bit is set and cleared by software and cleared by hardware + * when start is sent or PE=0." The bit must be cleared by software if the + * START is never sent. + * + * "This [PEC] bit is set and cleared by software, and cleared by hardware + * when PEC is transferred or by a START or Stop condition or when PE=0." + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, + I2C_CR1_START|I2C_CR1_STOP|I2C_CR1_PEC, 0); } /************************************************************************************ @@ -1073,7 +1056,7 @@ static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv) { - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_STOP); + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_STOP); } /************************************************************************************ @@ -1086,9 +1069,9 @@ static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv) static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv) { - uint32_t status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - return status; + uint32_t status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + return status; } /************************************************************************************ @@ -1106,22 +1089,22 @@ static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv) #ifdef I2C1_FSMC_CONFLICT static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv) { - uint32_t ret = 0; - uint32_t regval; - - /* Is this I2C1 */ - + uint32_t ret = 0; + uint32_t regval; + + /* Is this I2C1 */ + #if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) - if (priv->config->base == STM32_I2C1_BASE) + if (priv->config->base == STM32_I2C1_BASE) #endif { - /* Disable FSMC unconditionally */ - - ret = getreg32( STM32_RCC_AHBENR); - regval = ret & ~RCC_AHBENR_FSMCEN; - putreg32(regval, STM32_RCC_AHBENR); + /* Disable FSMC unconditionally */ + + ret = getreg32( STM32_RCC_AHBENR); + regval = ret & ~RCC_AHBENR_FSMCEN; + putreg32(regval, STM32_RCC_AHBENR); } - return ret; + return ret; } /************************************************************************************ @@ -1134,15 +1117,15 @@ static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_enablefsmc(uint32_t ahbenr) { - uint32_t regval; - - /* Enable AHB clocking to the FSMC only if it was previously enabled. */ - - if ((ahbenr & RCC_AHBENR_FSMCEN) != 0) + uint32_t regval; + + /* Enable AHB clocking to the FSMC only if it was previously enabled. */ + + if ((ahbenr & RCC_AHBENR_FSMCEN) != 0) { - regval = getreg32( STM32_RCC_AHBENR); - regval |= RCC_AHBENR_FSMCEN; - putreg32(regval, STM32_RCC_AHBENR); + regval = getreg32( STM32_RCC_AHBENR); + regval |= RCC_AHBENR_FSMCEN; + putreg32(regval, STM32_RCC_AHBENR); } } #else @@ -1160,227 +1143,227 @@ static inline void stm32_i2c_enablefsmc(uint32_t ahbenr) static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) { - uint32_t status = stm32_i2c_getstatus(priv); - - /* Check for new trace setup */ - - stm32_i2c_tracenew(priv, status); - - /* Was start bit sent */ + uint32_t status = stm32_i2c_getstatus(priv); + + /* Check for new trace setup */ + + stm32_i2c_tracenew(priv, status); + + /* Was start bit sent */ - if ((status & I2C_SR1_SB) != 0) + if ((status & I2C_SR1_SB) != 0) { - stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgc); - - /* Get run-time data */ - - priv->ptr = priv->msgv->buffer; - priv->dcnt = priv->msgv->length; - priv->flags = priv->msgv->flags; - - /* Send address byte and define addressing mode */ - - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, - (priv->flags & I2C_M_TEN) ? - 0 : ((priv->msgv->addr << 1) | (priv->flags & I2C_M_READ))); - - /* Set ACK for receive mode */ - - if (priv->dcnt > 1 && (priv->flags & I2C_M_READ) != 0) + stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgc); + + /* Get run-time data */ + + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + + /* Send address byte and define addressing mode */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, + (priv->flags & I2C_M_TEN) ? + 0 : ((priv->msgv->addr << 1) | (priv->flags & I2C_M_READ))); + + /* Set ACK for receive mode */ + + if (priv->dcnt > 1 && (priv->flags & I2C_M_READ) != 0) { - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_ACK); + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_ACK); } - - /* Increment to next pointer and decrement message count */ - - priv->msgv++; - priv->msgc--; + + /* Increment to next pointer and decrement message count */ + + priv->msgv++; + priv->msgc--; } - - /* In 10-bit addressing mode, was first byte sent */ - else if ((status & I2C_SR1_ADD10) != 0) + /* In 10-bit addressing mode, was first byte sent */ + + else if ((status & I2C_SR1_ADD10) != 0) { - /* TODO: Finish 10-bit mode addressing */ + /* TODO: Finish 10-bit mode addressing */ } - - /* Was address sent, continue with either sending or reading data */ - - else if ((priv->flags & I2C_M_READ) == 0 && (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0) + + /* Was address sent, continue with either sending or reading data */ + + else if ((priv->flags & I2C_M_READ) == 0 && (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0) { - if (priv->dcnt > 0) + if (priv->dcnt > 0) { - /* Send a byte */ - - stm32_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt); - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); - priv->dcnt--; + /* Send a byte */ + + stm32_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt); + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); + priv->dcnt--; } } - - else if ((priv->flags & I2C_M_READ) != 0 && (status & I2C_SR1_ADDR) != 0) + + else if ((priv->flags & I2C_M_READ) != 0 && (status & I2C_SR1_ADDR) != 0) { - /* Enable RxNE and TxE buffers in order to receive one or multiple bytes */ - + /* Enable RxNE and TxE buffers in order to receive one or multiple bytes */ + #ifndef CONFIG_I2C_POLLED - stm32_i2c_traceevent(priv, I2CEVENT_ITBUFEN, 0); - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); + stm32_i2c_traceevent(priv, I2CEVENT_ITBUFEN, 0); + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); #endif } - - /* More bytes to read */ - - else if ((status & I2C_SR1_RXNE) != 0) - { - /* Read a byte, if dcnt goes < 0, then read dummy bytes to ack ISRs */ - if (priv->dcnt > 0) + /* More bytes to read */ + + else if ((status & I2C_SR1_RXNE) != 0) + { + /* Read a byte, if dcnt goes < 0, then read dummy bytes to ack ISRs */ + + if (priv->dcnt > 0) { - stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); - - /* No interrupts or context switches may occur in the following - * sequence. Otherwise, additional bytes may be sent by the - * device. - */ - + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + + /* No interrupts or context switches may occur in the following + * sequence. Otherwise, additional bytes may be sent by the + * device. + */ + #ifdef CONFIG_I2C_POLLED - irqstate_t state = irqsave(); + irqstate_t state = irqsave(); #endif - /* Receive a byte */ - - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - - /* Disable acknowledge when last byte is to be received */ - - priv->dcnt--; - if (priv->dcnt == 1) + /* Receive a byte */ + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* Disable acknowledge when last byte is to be received */ + + priv->dcnt--; + if (priv->dcnt == 1) { - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); } - + #ifdef CONFIG_I2C_POLLED - irqrestore(state); + irqrestore(state); #endif } } - /* Do we have more bytes to send, enable/disable buffer interrupts - * (these ISRs could be replaced by DMAs) - */ - + /* Do we have more bytes to send, enable/disable buffer interrupts + * (these ISRs could be replaced by DMAs) + */ + #ifndef CONFIG_I2C_POLLED - if (priv->dcnt > 0) + if (priv->dcnt > 0) { - stm32_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0); - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); + stm32_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0); + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); } - else if (priv->dcnt == 0) + else if (priv->dcnt == 0) { - stm32_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0); - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); + stm32_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0); + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); } #endif - /* Was last byte received or sent? Hmmm... the F2 and F4 seems to differ from - * the F1 in that BTF is not set after data is received (only RXNE). - */ - + /* Was last byte received or sent? Hmmm... the F2 and F4 seems to differ from + * the F1 in that BTF is not set after data is received (only RXNE). + */ + #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) - if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF|I2C_SR1_RXNE)) != 0) + if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF|I2C_SR1_RXNE)) != 0) #else - if (priv->dcnt <= 0 && (status & I2C_SR1_BTF) != 0) + if (priv->dcnt <= 0 && (status & I2C_SR1_BTF) != 0) #endif - { - stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); /* ACK ISR */ - - /* Do we need to terminate or restart after this byte? - * If there are more messages to send, then we may: - * - * - continue with repeated start - * - or just continue sending writeable part - * - or we close down by sending the stop bit - */ - - if (priv->msgc > 0) { - if (priv->msgv->flags & I2C_M_NORESTART) + stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); /* ACK ISR */ + + /* Do we need to terminate or restart after this byte? + * If there are more messages to send, then we may: + * + * - continue with repeated start + * - or just continue sending writeable part + * - or we close down by sending the stop bit + */ + + if (priv->msgc > 0) { - stm32_i2c_traceevent(priv, I2CEVENT_BTFNOSTART, priv->msgc); - priv->ptr = priv->msgv->buffer; - priv->dcnt = priv->msgv->length; - priv->flags = priv->msgv->flags; - priv->msgv++; - priv->msgc--; - - /* Restart this ISR! */ - + if (priv->msgv->flags & I2C_M_NORESTART) + { + stm32_i2c_traceevent(priv, I2CEVENT_BTFNOSTART, priv->msgc); + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + priv->msgv++; + priv->msgc--; + + /* Restart this ISR! */ + #ifndef CONFIG_I2C_POLLED - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); #endif + } + else + { + stm32_i2c_traceevent(priv, I2CEVENT_BTFRESTART, priv->msgc); + stm32_i2c_sendstart(priv); + } } - else + else if (priv->msgv) { - stm32_i2c_traceevent(priv, I2CEVENT_BTFRESTART, priv->msgc); - stm32_i2c_sendstart(priv); - } - } - else if (priv->msgv) - { - stm32_i2c_traceevent(priv, I2CEVENT_BTFSTOP, 0); - stm32_i2c_sendstop(priv); - - /* Is there a thread waiting for this event (there should be) */ - + stm32_i2c_traceevent(priv, I2CEVENT_BTFSTOP, 0); + stm32_i2c_sendstop(priv); + + /* Is there a thread waiting for this event (there should be) */ + #ifndef CONFIG_I2C_POLLED - if (priv->intstate == INTSTATE_WAITING) - { - /* Yes.. inform the thread that the transfer is complete - * and wake it up. - */ - - sem_post( &priv->sem_isr ); - priv->intstate = INTSTATE_DONE; - } + if (priv->intstate == INTSTATE_WAITING) + { + /* Yes.. inform the thread that the transfer is complete + * and wake it up. + */ + + sem_post( &priv->sem_isr ); + priv->intstate = INTSTATE_DONE; + } #else - priv->intstate = INTSTATE_DONE; + priv->intstate = INTSTATE_DONE; #endif - - /* Mark that we have stopped with this transaction */ - - priv->msgv = NULL; + + /* Mark that we have stopped with this transaction */ + + priv->msgv = NULL; + } } - } - /* Check for errors, in which case, stop the transfer and return + /* Check for errors, in which case, stop the transfer and return * Note that in master reception mode AF becomes set on last byte * since ACK is not returned. We should ignore this error. */ if ((status & I2C_SR1_ERRORMASK) != 0) - { + { stm32_i2c_traceevent(priv, I2CEVENT_ERROR, 0); - + /* Clear interrupt flags */ - + stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); - + /* Is there a thread waiting for this event (there should be) */ - + #ifndef CONFIG_I2C_POLLED if (priv->intstate == INTSTATE_WAITING) - { - /* Yes.. inform the thread that the transfer is complete - * and wake it up. - */ - + { + /* Yes.. inform the thread that the transfer is complete + * and wake it up. + */ + sem_post( &priv->sem_isr ); priv->intstate = INTSTATE_DONE; - } + } #else priv->intstate = INTSTATE_DONE; #endif - } - + } + priv->status = status; return OK; } @@ -1397,7 +1380,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) #ifdef CONFIG_STM32_I2C1 static int stm32_i2c1_isr(int irq, void *context) { - return stm32_i2c_isr(&stm32_i2c1_priv); + return stm32_i2c_isr(&stm32_i2c1_priv); } #endif @@ -1412,7 +1395,7 @@ static int stm32_i2c1_isr(int irq, void *context) #ifdef CONFIG_STM32_I2C2 static int stm32_i2c2_isr(int irq, void *context) { - return stm32_i2c_isr(&stm32_i2c2_priv); + return stm32_i2c_isr(&stm32_i2c2_priv); } #endif @@ -1427,7 +1410,7 @@ static int stm32_i2c2_isr(int irq, void *context) #ifdef CONFIG_STM32_I2C3 static int stm32_i2c3_isr(int irq, void *context) { - return stm32_i2c_isr(&stm32_i2c3_priv); + return stm32_i2c_isr(&stm32_i2c3_priv); } #endif #endif @@ -1446,47 +1429,47 @@ static int stm32_i2c3_isr(int irq, void *context) static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) { - /* Power-up and configure GPIOs */ - - /* Enable power and reset the peripheral */ - - modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); - modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); - modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); - - /* Configure pins */ - - if (stm32_configgpio(priv->config->scl_pin) < 0) + /* Power-up and configure GPIOs */ + + /* Enable power and reset the peripheral */ + + modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); + + /* Configure pins */ + + if (stm32_configgpio(priv->config->scl_pin) < 0) { - return ERROR; + return ERROR; } - - if (stm32_configgpio(priv->config->sda_pin) < 0) + + if (stm32_configgpio(priv->config->sda_pin) < 0) { - stm32_unconfiggpio(priv->config->scl_pin); - return ERROR; + stm32_unconfiggpio(priv->config->scl_pin); + return ERROR; } - - /* Attach ISRs */ - + + /* Attach ISRs */ + #ifndef CONFIG_I2C_POLLED - irq_attach(priv->config->ev_irq, priv->config->isr); - irq_attach(priv->config->er_irq, priv->config->isr); - up_enable_irq(priv->config->ev_irq); - up_enable_irq(priv->config->er_irq); + irq_attach(priv->config->ev_irq, priv->config->isr); + irq_attach(priv->config->er_irq, priv->config->isr); + up_enable_irq(priv->config->ev_irq); + up_enable_irq(priv->config->er_irq); #endif - - /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz - * or 4 MHz for 400 kHz. This also disables all I2C interrupts. - */ - - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, (STM32_PCLK1_FREQUENCY / 1000000)); - stm32_i2c_setclock(priv, 100000); - - /* Enable I2C */ - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE); - return OK; + /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz + * or 4 MHz for 400 kHz. This also disables all I2C interrupts. + */ + + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, (STM32_PCLK1_FREQUENCY / 1000000)); + stm32_i2c_setclock(priv, 100000); + + /* Enable I2C */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE); + return OK; } /************************************************************************************ @@ -1499,28 +1482,28 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv) { - /* Disable I2C */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0); - - /* Unconfigure GPIO pins */ - - stm32_unconfiggpio(priv->config->scl_pin); - stm32_unconfiggpio(priv->config->sda_pin); - - /* Disable and detach interrupts */ - + /* Disable I2C */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0); + + /* Unconfigure GPIO pins */ + + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); + + /* Disable and detach interrupts */ + #ifndef CONFIG_I2C_POLLED - up_disable_irq(priv->config->ev_irq); - up_disable_irq(priv->config->er_irq); - irq_detach(priv->config->ev_irq); - irq_detach(priv->config->er_irq); + up_disable_irq(priv->config->ev_irq); + up_disable_irq(priv->config->er_irq); + irq_detach(priv->config->ev_irq); + irq_detach(priv->config->er_irq); #endif - - /* Disable clocking */ - - modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); - return OK; + + /* Disable clocking */ + + modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); + return OK; } /************************************************************************************ @@ -1537,16 +1520,16 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv) static uint32_t stm32_i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency) { - stm32_i2c_sem_wait(dev); - + stm32_i2c_sem_wait(dev); + #if STM32_PCLK1_FREQUENCY < 4000000 - ((struct stm32_i2c_inst_s *)dev)->frequency = 100000; + ((struct stm32_i2c_inst_s *)dev)->frequency = 100000; #else - ((struct stm32_i2c_inst_s *)dev)->frequency = frequency; + ((struct stm32_i2c_inst_s *)dev)->frequency = frequency; #endif - - stm32_i2c_sem_post(dev); - return ((struct stm32_i2c_inst_s *)dev)->frequency; + + stm32_i2c_sem_post(dev); + return ((struct stm32_i2c_inst_s *)dev)->frequency; } /************************************************************************************ @@ -1559,11 +1542,11 @@ static uint32_t stm32_i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequ static int stm32_i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) { - stm32_i2c_sem_wait(dev); - - ((struct stm32_i2c_inst_s *)dev)->address = addr; - ((struct stm32_i2c_inst_s *)dev)->flags = (nbits == 10) ? I2C_M_TEN : 0; - + stm32_i2c_sem_wait(dev); + + ((struct stm32_i2c_inst_s *)dev)->address = addr; + ((struct stm32_i2c_inst_s *)dev)->flags = (nbits == 10) ? I2C_M_TEN : 0; + stm32_i2c_sem_post(dev); return OK; } @@ -1578,178 +1561,198 @@ static int stm32_i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count) { - struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; - FAR struct stm32_i2c_priv_s *priv = inst->priv; - uint32_t status = 0; - uint32_t ahbenr; - int errval = 0; - - ASSERT(count); - - /* Disable FSMC that shares a pin with I2C1 (LBAR) */ - - ahbenr = stm32_i2c_disablefsmc(priv); - - /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC - * then we cannot do this at the top of the loop, unfortunately. The STOP - * will not complete normally if the FSMC is enabled. - */ - + struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; + FAR struct stm32_i2c_priv_s *priv = inst->priv; + uint32_t status = 0; + //uint32_t ahbenr; + int errval = 0; + + ASSERT(count); + + /* Disable FSMC that shares a pin with I2C1 (LBAR) */ + + (void)stm32_i2c_disablefsmc(priv); + + /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC + * then we cannot do this at the top of the loop, unfortunately. The STOP + * will not complete normally if the FSMC is enabled. + */ + #ifndef I2C1_FSMC_CONFLICT - stm32_i2c_sem_waitstop(priv); +#if CONFIG_STM32_I2CTIMEOUS_START_STOP > 0 + stm32_i2c_sem_waitstop(priv, CONFIG_STM32_I2CTIMEOUS_START_STOP); +#else + stm32_i2c_sem_waitstop(priv, CONFIG_STM32_I2CTIMEOMS + CONFIG_STM32_I2CTIMEOSEC * 1000000); +#endif #endif - - /* Clear any pending error interrupts */ - - stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); - - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." However, if the bits are - * not cleared by hardware, then we will have to do that from hardware. - */ - - stm32_i2c_clrstart(priv); - /* Old transfers are done */ - - priv->msgv = msgs; - priv->msgc = count; - - /* Reset I2C trace logic */ - - stm32_i2c_tracereset(priv); - - /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */ - - stm32_i2c_setclock(priv, inst->frequency); - - /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32_i2c_waitdone(). - */ - - priv->status = 0; - stm32_i2c_sendstart(priv); - - /* Wait for an ISR, if there was a timeout, fetch latest status to get - * the BUSY flag. - */ - - if (stm32_i2c_sem_waitdone(priv) < 0) + /* Clear any pending error interrupts */ + + stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); + + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." However, if the bits are + * not cleared by hardware, then we will have to do that from hardware. + */ + + stm32_i2c_clrstart(priv); + + /* Old transfers are done */ + + priv->msgv = msgs; + priv->msgc = count; + + /* Calculate timeout values */ + int timeout_us = 0; +#if CONFIG_STM32_I2CTIMEOUS_PER_BYTE > 0 + /* Count the number of bytes left to process */ + int i; + int bytecount = 10; + for (i = 0; i < count; i++) { - status = stm32_i2c_getstatus(priv); - errval = ETIMEDOUT; - - i2cdbg("Timed out: CR1: %04x status: %08x\n", - stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); - - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." - */ - - stm32_i2c_clrstart(priv); - - /* Clear busy flag in case of timeout */ - - status = priv->status & 0xffff; + bytecount += msgs[i].length; } - else + timeout_us = CONFIG_STM32_I2CTIMEOUS_PER_BYTE * bytecount; + //i2cvdbg("i2c wait: %d\n", timeout_us); +#else + timeout_us = CONFIG_STM32_I2CTIMEOMS + CONFIG_STM32_I2CTIMEOSEC * 1000000; +#endif + + /* Reset I2C trace logic */ + + stm32_i2c_tracereset(priv); + + /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */ + + stm32_i2c_setclock(priv, inst->frequency); + + /* Trigger start condition, then the process moves into the ISR. I2C + * interrupts will be enabled within stm32_i2c_waitdone(). + */ + + priv->status = 0; + stm32_i2c_sendstart(priv); + + /* Wait for an ISR, if there was a timeout, fetch latest status to get + * the BUSY flag. + */ + + if (stm32_i2c_sem_waitdone(priv, timeout_us) < 0) { - /* clear SR2 (BUSY flag) as we've done successfully */ - - status = priv->status & 0xffff; + status = stm32_i2c_getstatus(priv); + errval = ETIMEDOUT; + + i2cdbg("Timed out: CR1: %04x status: %08x after %d\n", + stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status, timeout_us); + + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." + */ + + stm32_i2c_clrstart(priv); + + /* Clear busy flag in case of timeout */ + + status = priv->status & 0xffff; } - - /* Check for error status conditions */ - - if ((status & I2C_SR1_ERRORMASK) != 0) + else { - /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */ - - if (status & I2C_SR1_BERR) + /* clear SR2 (BUSY flag) as we've done successfully */ + + status = priv->status & 0xffff; + } + + /* Check for error status conditions */ + + if ((status & I2C_SR1_ERRORMASK) != 0) + { + /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */ + + if (status & I2C_SR1_BERR) { - /* Bus Error */ - - errval = EIO; + /* Bus Error */ + + errval = EIO; } - else if (status & I2C_SR1_ARLO) + else if (status & I2C_SR1_ARLO) { - /* Arbitration Lost (master mode) */ - - errval = EAGAIN; + /* Arbitration Lost (master mode) */ + + errval = EAGAIN; } - else if (status & I2C_SR1_AF) + else if (status & I2C_SR1_AF) { - /* Acknowledge Failure */ - - errval = ENXIO; + /* Acknowledge Failure */ + + errval = ENXIO; } - else if (status & I2C_SR1_OVR) + else if (status & I2C_SR1_OVR) { - /* Overrun/Underrun */ - - errval = EIO; + /* Overrun/Underrun */ + + errval = EIO; } - else if (status & I2C_SR1_PECERR) + else if (status & I2C_SR1_PECERR) { - /* PEC Error in reception */ - - errval = EPROTO; + /* PEC Error in reception */ + + errval = EPROTO; } - else if (status & I2C_SR1_TIMEOUT) + else if (status & I2C_SR1_TIMEOUT) { - /* Timeout or Tlow Error */ - - errval = ETIME; + /* Timeout or Tlow Error */ + + errval = ETIME; } - - /* This is not an error and should never happen since SMBus is not enabled */ - - else /* if (status & I2C_SR1_SMBALERT) */ + + /* This is not an error and should never happen since SMBus is not enabled */ + + else /* if (status & I2C_SR1_SMBALERT) */ { - /* SMBus alert is an optional signal with an interrupt line for devices - * that want to trade their ability to master for a pin. - */ - - errval = EINTR; + /* SMBus alert is an optional signal with an interrupt line for devices + * that want to trade their ability to master for a pin. + */ + + errval = EINTR; } } - - /* This is not an error, but should not happen. The BUSY signal can hang, - * however, if there are unhealthy devices on the bus that need to be reset. - * NOTE: We will only see this buy indication if stm32_i2c_sem_waitdone() - * fails above; Otherwise it is cleared. - */ - - else if ((status & (I2C_SR2_BUSY << 16)) != 0) + + /* This is not an error, but should not happen. The BUSY signal can hang, + * however, if there are unhealthy devices on the bus that need to be reset. + * NOTE: We will only see this buy indication if stm32_i2c_sem_waitdone() + * fails above; Otherwise it is cleared. + */ + + else if ((status & (I2C_SR2_BUSY << 16)) != 0) { - /* I2C Bus is for some reason busy */ - - errval = EBUSY; - } - - /* Dump the trace result */ - - stm32_i2c_tracedump(priv); + /* I2C Bus is for some reason busy */ - /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC - * then we cannot do this at the top of the loop, unfortunately. The STOP - * will not complete normally if the FSMC is enabled. - */ - + errval = EBUSY; + } + + /* Dump the trace result */ + + stm32_i2c_tracedump(priv); + + /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC + * then we cannot do this at the top of the loop, unfortunately. The STOP + * will not complete normally if the FSMC is enabled. + */ + #ifdef I2C1_FSMC_CONFLICT - stm32_i2c_sem_waitstop(priv); + stm32_i2c_sem_waitstop(priv); #endif - - /* Re-enable the FSMC */ - - stm32_i2c_enablefsmc(ahbenr); - stm32_i2c_sem_post(dev); - - return -errval; + + /* Re-enable the FSMC */ + + stm32_i2c_enablefsmc(ahbenr); + stm32_i2c_sem_post(dev); + + return -errval; } /************************************************************************************ @@ -1762,17 +1765,17 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms static int stm32_i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen) { - stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */ - - struct i2c_msg_s msgv = - { - .addr = ((struct stm32_i2c_inst_s *)dev)->address, - .flags = ((struct stm32_i2c_inst_s *)dev)->flags, - .buffer = (uint8_t *)buffer, - .length = buflen - }; - - return stm32_i2c_process(dev, &msgv, 1); + stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */ + + struct i2c_msg_s msgv = + { + .addr = ((struct stm32_i2c_inst_s *)dev)->address, + .flags = ((struct stm32_i2c_inst_s *)dev)->flags, + .buffer = (uint8_t *)buffer, + .length = buflen + }; + + return stm32_i2c_process(dev, &msgv, 1); } /************************************************************************************ @@ -1785,17 +1788,17 @@ static int stm32_i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int int stm32_i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) { - stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */ - - struct i2c_msg_s msgv = - { - .addr = ((struct stm32_i2c_inst_s *)dev)->address, - .flags = ((struct stm32_i2c_inst_s *)dev)->flags | I2C_M_READ, - .buffer = buffer, - .length = buflen - }; + stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */ + + struct i2c_msg_s msgv = + { + .addr = ((struct stm32_i2c_inst_s *)dev)->address, + .flags = ((struct stm32_i2c_inst_s *)dev)->flags | I2C_M_READ, + .buffer = buffer, + .length = buflen + }; - return stm32_i2c_process(dev, &msgv, 1); + return stm32_i2c_process(dev, &msgv, 1); } /************************************************************************************ @@ -1811,25 +1814,25 @@ static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev, const uint8_t *wbuffer, int wbuflen, uint8_t *buffer, int buflen) { - stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */ - - struct i2c_msg_s msgv[2] = - { - { - .addr = ((struct stm32_i2c_inst_s *)dev)->address, - .flags = ((struct stm32_i2c_inst_s *)dev)->flags, - .buffer = (uint8_t *)wbuffer, /* this is really ugly, sorry const ... */ - .length = wbuflen - }, + stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */ + + struct i2c_msg_s msgv[2] = { - .addr = ((struct stm32_i2c_inst_s *)dev)->address, - .flags = ((struct stm32_i2c_inst_s *)dev)->flags | ((buflen>0) ? I2C_M_READ : I2C_M_NORESTART), - .buffer = buffer, - .length = (buflen>0) ? buflen : -buflen - } - }; - - return stm32_i2c_process(dev, msgv, 2); + { + .addr = ((struct stm32_i2c_inst_s *)dev)->address, + .flags = ((struct stm32_i2c_inst_s *)dev)->flags, + .buffer = (uint8_t *)wbuffer, /* this is really ugly, sorry const ... */ + .length = wbuflen + }, + { + .addr = ((struct stm32_i2c_inst_s *)dev)->address, + .flags = ((struct stm32_i2c_inst_s *)dev)->flags | ((buflen>0) ? I2C_M_READ : I2C_M_NORESTART), + .buffer = buffer, + .length = (buflen>0) ? buflen : -buflen + } + }; + + return stm32_i2c_process(dev, msgv, 2); } #endif @@ -1845,8 +1848,8 @@ static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev, static int stm32_i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count) { - stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */ - return stm32_i2c_process(dev, msgs, count); + stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */ + return stm32_i2c_process(dev, msgs, count); } #endif @@ -1864,71 +1867,71 @@ static int stm32_i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *m FAR struct i2c_dev_s *up_i2cinitialize(int port) { - struct stm32_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */ - struct stm32_i2c_inst_s * inst = NULL; /* device, single instance */ - int irqs; - + struct stm32_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */ + struct stm32_i2c_inst_s * inst = NULL; /* device, single instance */ + int irqs; + #if STM32_PCLK1_FREQUENCY < 4000000 # warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation. #endif - + #if STM32_PCLK1_FREQUENCY < 2000000 # warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation. return NULL; #endif - /* Get I2C private structure */ - - switch (port) + /* Get I2C private structure */ + + switch (port) { #ifdef CONFIG_STM32_I2C1 - case 1: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; - break; + case 1: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; + break; #endif #ifdef CONFIG_STM32_I2C2 - case 2: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; - break; + case 2: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; + break; #endif #ifdef CONFIG_STM32_I2C3 - case 3: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; - break; + case 3: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; + break; #endif - default: - return NULL; + default: + return NULL; } - - /* Allocate instance */ - if (!(inst = kmalloc( sizeof(struct stm32_i2c_inst_s)))) + /* Allocate instance */ + + if (!(inst = kmalloc( sizeof(struct stm32_i2c_inst_s)))) { - return NULL; + return NULL; } - - /* Initialize instance */ - - inst->ops = &stm32_i2c_ops; - inst->priv = priv; - inst->frequency = 100000; - inst->address = 0; - inst->flags = 0; - - /* Init private data for the first time, increment refs count, - * power-up hardware and configure GPIOs. - */ - irqs = irqsave(); + /* Initialize instance */ - if ((volatile int)priv->refs++ == 0) + inst->ops = &stm32_i2c_ops; + inst->priv = priv; + inst->frequency = 100000; + inst->address = 0; + inst->flags = 0; + + /* Init private data for the first time, increment refs count, + * power-up hardware and configure GPIOs. + */ + + irqs = irqsave(); + + if ((volatile int)priv->refs++ == 0) { - stm32_i2c_sem_init( (struct i2c_dev_s *)inst ); - stm32_i2c_init( priv ); + stm32_i2c_sem_init( (struct i2c_dev_s *)inst ); + stm32_i2c_init( priv ); } - irqrestore(irqs); - return (struct i2c_dev_s *)inst; + irqrestore(irqs); + return (struct i2c_dev_s *)inst; } /************************************************************************************ @@ -1941,38 +1944,38 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port) int up_i2cuninitialize(FAR struct i2c_dev_s * dev) { - int irqs; + int irqs; - ASSERT(dev); + ASSERT(dev); - /* Decrement refs and check for underflow */ + /* Decrement refs and check for underflow */ - if (((struct stm32_i2c_inst_s *)dev)->priv->refs == 0) + if (((struct stm32_i2c_inst_s *)dev)->priv->refs == 0) { - return ERROR; + return ERROR; } - - irqs = irqsave(); - - if (--((struct stm32_i2c_inst_s *)dev)->priv->refs) + + irqs = irqsave(); + + if (--((struct stm32_i2c_inst_s *)dev)->priv->refs) { - irqrestore(irqs); - kfree(dev); - return OK; + irqrestore(irqs); + kfree(dev); + return OK; } - - irqrestore(irqs); - - /* Disable power and other HW resource (GPIO's) */ - - stm32_i2c_deinit( ((struct stm32_i2c_inst_s *)dev)->priv ); - - /* Release unused resources */ - - stm32_i2c_sem_destroy( (struct i2c_dev_s *)dev ); - - kfree(dev); - return OK; + + irqrestore(irqs); + + /* Disable power and other HW resource (GPIO's) */ + + stm32_i2c_deinit( ((struct stm32_i2c_inst_s *)dev)->priv ); + + /* Release unused resources */ + + stm32_i2c_sem_destroy( (struct i2c_dev_s *)dev ); + + kfree(dev); + return OK; } /************************************************************************************ @@ -1983,115 +1986,122 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev) * ************************************************************************************/ -#ifdef CONFIG_I2C_RESET int up_i2creset(FAR struct i2c_dev_s * dev) { - struct stm32_i2c_priv_s * priv; - unsigned int clock_count; - unsigned int stretch_count; - uint32_t scl_gpio; - uint32_t sda_gpio; - int ret = ERROR; - - ASSERT(dev); - - /* Get I2C private structure */ - - priv = ((struct stm32_i2c_inst_s *)dev)->priv; - - /* Our caller must own a ref */ - - ASSERT(priv->refs > 0); - - /* Lock out other clients */ - - stm32_i2c_sem_wait(dev); - - /* De-init the port */ - - stm32_i2c_deinit(priv); - - /* Use GPIO configuration to un-wedge the bus */ - - scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); - sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); - - /* Let SDA go high */ - - stm32_gpiowrite(sda_gpio, 1); - - /* Clock the bus until any slaves currently driving it let it go. */ - - clock_count = 0; - while (!stm32_gpioread(sda_gpio)) + struct stm32_i2c_priv_s * priv; + unsigned clock_count; + unsigned stretch_count; + int ret = ERROR; + irqstate_t state; + + ASSERT(dev); + + /* Get I2C private structure */ + + priv = ((struct stm32_i2c_inst_s *)dev)->priv; + + /* Our caller must own a ref */ + + ASSERT(priv->refs > 0); + + /* Lock out other clients */ + + stm32_i2c_sem_wait(dev); + + /* De-init the port */ + + stm32_i2c_deinit(priv); + + /* If possible, use GPIO configuration to un-wedge the bus */ + + if ((priv->config->scl_gpio != 0) && (priv->config->sda_gpio != 0)) { - /* Give up if we have tried too hard */ - - if (clock_count++ > 10) - { - goto out; - } - - /* Sniff to make sure that clock stretching has finished. - * - * If the bus never relaxes, the reset has failed. - */ - - stretch_count = 0; - while (!stm32_gpioread(scl_gpio)) - { - /* Give up if we have tried too hard */ - - if (stretch_count++ > 10) + stm32_configgpio(priv->config->scl_gpio); + stm32_configgpio(priv->config->sda_gpio); + + /* + * Clock the bus until any slaves currently driving it let it go. + */ + + clock_count = 0; + while (!stm32_gpioread(priv->config->sda_gpio)) + { + + /* Give up if we have tried too hard */ + + if (clock_count++ > CONFIG_STM32_I2CTIMEOTICKS) { - goto out; + goto out; } - - up_udelay(10); + + /* + * Sniff to make sure that clock stretching has finished. + * + * If the bus never relaxes, the reset has failed. + */ + + stretch_count = 0; + while (!stm32_gpioread(priv->config->scl_gpio)) + { + + /* Give up if we have tried too hard */ + + if (stretch_count++ > 1000) + { + goto out; + } + + up_udelay(10); + + } + + /* Drive SCL low */ + + stm32_gpiowrite(priv->config->scl_gpio, 0); + up_udelay(10); + + /* Drive SCL high again */ + + stm32_gpiowrite(priv->config->scl_gpio, 1); + up_udelay(10); + } - - /* Drive SCL low */ - - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - - /* Drive SCL high again */ - - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); + + /* + * Generate a start followed by a stop to reset slave + * state machines. + */ + + stm32_gpiowrite(priv->config->sda_gpio, 0); + up_udelay(10); + stm32_gpiowrite(priv->config->scl_gpio, 0); + up_udelay(10); + stm32_gpiowrite(priv->config->scl_gpio, 1); + up_udelay(10); + stm32_gpiowrite(priv->config->sda_gpio, 1); + up_udelay(10); + + /* + * Revert the GPIO configuration. + */ + stm32_unconfiggpio(priv->config->sda_gpio); + stm32_unconfiggpio(priv->config->scl_gpio); + } - - /* Generate a start followed by a stop to reset slave - * state machines. - */ - - stm32_gpiowrite(sda_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - stm32_gpiowrite(sda_gpio, 1); - up_udelay(10); - - /* Revert the GPIO configuration. */ - - stm32_unconfiggpio(sda_gpio); - stm32_unconfiggpio(scl_gpio); - - /* Re-init the port */ - - stm32_i2c_init(priv); - ret = OK; - + + /* Re-init the port */ + + stm32_i2c_init(priv); + ret = OK; + out: - - /* Release the port for re-use by other clients */ - - stm32_i2c_sem_post(dev); - return ret; + + /* release the port for re-use by other clients */ + + stm32_i2c_sem_post(dev); + + return ret; } -#endif /* CONFIG_I2C_RESET */ #endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F40XX */ #endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/nuttx/configs/px4fmu-v1/nsh/defconfig b/nuttx/configs/px4fmu-v1/nsh/defconfig index 732bd41e08..f2a92f40da 100644 --- a/nuttx/configs/px4fmu-v1/nsh/defconfig +++ b/nuttx/configs/px4fmu-v1/nsh/defconfig @@ -4,6 +4,11 @@ # CONFIG_NUTTX_NEWCONFIG=y +# +# XXX Needs menu +CONFIG_HRT_TIMER=y +CONFIG_HRT_PPM=y + # # Build Setup # @@ -342,7 +347,7 @@ CONFIG_ARCH_BOARD="px4fmu-v1" # Common Board Options # CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y +# CONFIG_ARCH_LEDS is not set CONFIG_NSH_MMCSDMINOR=0 CONFIG_NSH_MMCSDSLOTNO=0 CONFIG_NSH_MMCSDSPIPORTNO=0 @@ -357,7 +362,7 @@ CONFIG_NSH_MMCSDSPIPORTNO=0 # CONFIG_BOARD_INITIALIZE is not set CONFIG_MSEC_PER_TICK=1 CONFIG_RR_INTERVAL=5 -# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_SCHED_INSTRUMENTATION=y CONFIG_TASK_NAME_SIZE=24 # CONFIG_SCHED_HAVE_PARENT is not set # CONFIG_JULIAN_TIME is not set @@ -435,7 +440,7 @@ CONFIG_I2C_TRANSFER=y # CONFIG_I2C_POLLED is not set # CONFIG_I2C_TRACE is not set CONFIG_ARCH_HAVE_I2CRESET=y -# CONFIG_I2C_RESET is not set +CONFIG_I2C_RESET=y CONFIG_SPI=y # CONFIG_SPI_OWNBUS is not set CONFIG_SPI_EXCHANGE=y @@ -697,7 +702,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CAN is not set -# CONFIG_EXAMPLES_CDCACM is not set +CONFIG_EXAMPLES_CDCACM=y # CONFIG_EXAMPLES_COMPOSITE is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -713,7 +718,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_LCDRW is not set # CONFIG_EXAMPLES_MM is not set # CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set +CONFIG_EXAMPLES_MOUNT=y CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set # CONFIG_EXAMPLES_NX is not set diff --git a/nuttx/configs/px4io-v1/nsh/defconfig b/nuttx/configs/px4io-v1/nsh/defconfig index 43dd1b0e85..3c06a27347 100755 --- a/nuttx/configs/px4io-v1/nsh/defconfig +++ b/nuttx/configs/px4io-v1/nsh/defconfig @@ -1,5 +1,5 @@ ############################################################################ -# configs/px4io/nsh/defconfig +# configs/px4io-v1/nsh/defconfig # # Copyright (C) 2012 PX4 Development Team. All rights reserved. # Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. @@ -550,3 +550,9 @@ CONFIG_PTHREAD_STACK_MIN=512 CONFIG_PTHREAD_STACK_DEFAULT=1024 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set +# CONFIG_NSH_BUILTIN_APPS is not set From b9011c1d2dc46e4e917ca7c17b4ef769f2429d92 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sat, 1 Jun 2013 14:50:45 +0200 Subject: [PATCH 07/41] Checkpoint: Board booting --- nuttx/configs/px4fmu-v1/Kconfig | 13 +++++ nuttx/configs/px4fmu-v1/include/board.h | 7 +++ .../configs/px4fmu-v1/include/nsh_romfsimg.h | 42 ++++++++++++++ nuttx/configs/px4fmu-v1/nsh/defconfig | 58 +++++++++++++------ nuttx/configs/px4io-v1/Kconfig | 13 +++++ 5 files changed, 115 insertions(+), 18 deletions(-) create mode 100644 nuttx/configs/px4fmu-v1/include/nsh_romfsimg.h diff --git a/nuttx/configs/px4fmu-v1/Kconfig b/nuttx/configs/px4fmu-v1/Kconfig index fd79f63f1c..b54c8980b9 100644 --- a/nuttx/configs/px4fmu-v1/Kconfig +++ b/nuttx/configs/px4fmu-v1/Kconfig @@ -5,4 +5,17 @@ if ARCH_BOARD_PX4FMU_V1 +config CONFIG_HRT_TIMER + bool "High resolution timer support" + default y + ---help--- + Enable high resolution timer for PPM capture and system clocks. + +config CONFIG_HRT_PPM + bool "PPM input capture" + default y + depends on CONFIG_HRT_TIMER + ---help--- + Enable PPM input capture via HRT (for CPPM / PPM sum RC inputs) + endif diff --git a/nuttx/configs/px4fmu-v1/include/board.h b/nuttx/configs/px4fmu-v1/include/board.h index bf825a899c..a0488917ca 100644 --- a/nuttx/configs/px4fmu-v1/include/board.h +++ b/nuttx/configs/px4fmu-v1/include/board.h @@ -310,6 +310,13 @@ #define GPIO_SPI3_SCK GPIO_SPI3_SCK_2 #define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 +/* XXX DMA setup not validated yet */ +//#define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1 +//#define DMAMAP_SPI3_RX DMAMAP_SPI3_TX_1 + +//#define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_1 +//#define DMAMAP_SPI1_RX DMAMAP_SPI1_TX_1 + /* * Use these in place of the spi_dev_e enumeration to * select a specific SPI device on SPI1 diff --git a/nuttx/configs/px4fmu-v1/include/nsh_romfsimg.h b/nuttx/configs/px4fmu-v1/include/nsh_romfsimg.h new file mode 100644 index 0000000000..15e4e7a8d5 --- /dev/null +++ b/nuttx/configs/px4fmu-v1/include/nsh_romfsimg.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * + * Copyright (C) 2013 PX4 Development Team. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name PX4 nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/** + * nsh_romfsetc.h + * + * This file is a stub for 'make export' purposes; the actual ROMFS + * must be supplied by the library client. + */ + +extern unsigned char romfs_img[]; +extern unsigned int romfs_img_len; diff --git a/nuttx/configs/px4fmu-v1/nsh/defconfig b/nuttx/configs/px4fmu-v1/nsh/defconfig index f2a92f40da..9dcd2b2e8e 100644 --- a/nuttx/configs/px4fmu-v1/nsh/defconfig +++ b/nuttx/configs/px4fmu-v1/nsh/defconfig @@ -6,6 +6,7 @@ CONFIG_NUTTX_NEWCONFIG=y # # XXX Needs menu +# CONFIG_HRT_TIMER=y CONFIG_HRT_PPM=y @@ -278,7 +279,7 @@ CONFIG_STM32_USART_SINGLEWIRE=y # SPI Configuration # # CONFIG_STM32_SPI_INTERRUPTS is not set -# CONFIG_STM32_SPI_DMA is not set +CONFIG_STM32_SPI_DMA=n # # I2C Configuration @@ -350,7 +351,7 @@ CONFIG_ARCH_HAVE_LEDS=y # CONFIG_ARCH_LEDS is not set CONFIG_NSH_MMCSDMINOR=0 CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=3 # # Board-Specific Options @@ -403,24 +404,24 @@ CONFIG_SIG_SIGWORK=17 # # Sizes of configurable things (0 disables) # -CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASKS=32 CONFIG_MAX_TASK_ARGS=10 CONFIG_NPTHREAD_KEYS=4 -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 +CONFIG_NFILE_DESCRIPTORS=32 +CONFIG_NFILE_STREAMS=25 CONFIG_NAME_MAX=32 CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_MQ_MAXMSGSIZE=32 CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=50 +CONFIG_PREALLOC_TIMERS=50 # # Stack and heap information # -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_IDLETHREAD_STACKSIZE=6000 +CONFIG_USERMAIN_STACKSIZE=4096 +CONFIG_PTHREAD_STACK_MIN=512 CONFIG_PTHREAD_STACK_DEFAULT=2048 # @@ -459,7 +460,7 @@ CONFIG_MMCSD_NSLOTS=1 # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_MMCSD_HAVECARDDETECT is not set CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SPICLOCK=20000000 +CONFIG_MMCSD_SPICLOCK=24000000 # CONFIG_MMCSD_SDIO is not set # CONFIG_MTD is not set CONFIG_PIPES=y @@ -476,6 +477,7 @@ CONFIG_ARCH_HAVE_USART2=y CONFIG_ARCH_HAVE_USART6=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 # CONFIG_USART1_SERIAL_CONSOLE is not set # CONFIG_USART2_SERIAL_CONSOLE is not set # CONFIG_UART5_SERIAL_CONSOLE is not set @@ -586,19 +588,28 @@ CONFIG_CDCACM_PRODUCTSTR="PX4FMU v1.x" # # CONFIG_DISABLE_MOUNTPOINT is not set # CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +CONFIG_FS_FATTIME=y +# CONFIG_FAT_DMAMEMORY is not set +CONFIG_FS_NXFFS=y +CONFIG_NXFFS_PREALLOCATED=y +CONFIG_NXFFS_ERASEDSTATE=0xff +CONFIG_NXFFS_PACKTHRESHOLD=32 +CONFIG_NXFFS_MAXNAMLEN=255 +CONFIG_NXFFS_TAILTHRESHOLD=2048 +CONFIG_FS_ROMFS=y # CONFIG_FS_SMARTFS is not set -# CONFIG_FS_BINFS is not set +CONFIG_FS_BINFS=y # # System Logging # # CONFIG_SYSLOG_ENABLE is not set -CONFIG_SYSLOG=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +# CONFIG_SYSLOG is not set +# CONFIG_SYSLOG_CHAR is not set # # Graphics Support @@ -850,6 +861,17 @@ CONFIG_NSH_LINELEN=64 CONFIG_NSH_NESTDEPTH=3 # CONFIG_NSH_DISABLESCRIPT is not set # CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_ROMFSETC=y +CONFIG_NSH_ARCHROMFS=y +# CONFIG_NSH_ROMFSRC is not set +CONFIG_NSH_ROMFSMOUNTPT="/etc" +CONFIG_NSH_INITSCRIPT="init.d/rcS" +CONFIG_NSH_ROMFSDEVNO=0 +CONFIG_NSH_ROMFSSECTSIZE=128 +CONFIG_NSH_FATDEVNO=1 +CONFIG_NSH_FATSECTSIZE=512 +CONFIG_NSH_FATNSECTORS=1024 +CONFIG_NSH_FATMOUNTPT=/tmp CONFIG_NSH_CONSOLE=y # CONFIG_NSH_USBCONSOLE is not set diff --git a/nuttx/configs/px4io-v1/Kconfig b/nuttx/configs/px4io-v1/Kconfig index 6bd2e8e21e..331bbb0dab 100644 --- a/nuttx/configs/px4io-v1/Kconfig +++ b/nuttx/configs/px4io-v1/Kconfig @@ -5,4 +5,17 @@ if ARCH_BOARD_PX4IO_V1 +config CONFIG_HRT_TIMER + bool "High resolution timer support" + default y + ---help--- + Enable high resolution timer for PPM capture and system clocks. + +config CONFIG_HRT_PPM + bool "PPM input capture" + default y + depends on CONFIG_HRT_TIMER + ---help--- + Enable PPM input capture via HRT (for CPPM / PPM sum RC inputs) + endif From e5a305a6fb33320e306eb910513745926ece8acd Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sat, 1 Jun 2013 18:47:26 +0200 Subject: [PATCH 08/41] Re-enable sys log to work around USB vs. ttyS0 issue - works, but needs further attention --- nuttx/configs/px4fmu-v1/nsh/defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nuttx/configs/px4fmu-v1/nsh/defconfig b/nuttx/configs/px4fmu-v1/nsh/defconfig index 9dcd2b2e8e..11fc24d419 100644 --- a/nuttx/configs/px4fmu-v1/nsh/defconfig +++ b/nuttx/configs/px4fmu-v1/nsh/defconfig @@ -608,8 +608,9 @@ CONFIG_FS_BINFS=y # System Logging # # CONFIG_SYSLOG_ENABLE is not set -# CONFIG_SYSLOG is not set -# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" # # Graphics Support From 1ecb373d35e2a6f2956e1f1f09112ed2dd0eda86 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sun, 2 Jun 2013 13:08:04 +0200 Subject: [PATCH 09/41] Added transitional tools to gitignore --- nuttx/.gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nuttx/.gitignore b/nuttx/.gitignore index 69b7bdb80e..05231462de 100644 --- a/nuttx/.gitignore +++ b/nuttx/.gitignore @@ -16,3 +16,6 @@ /*.ihx /*.hex /pcode +/cmpit.sh +/cmporig.sh +/tstit.sh \ No newline at end of file From c2688999fc33e82553a90d14fee079b5dc7efea0 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sun, 2 Jun 2013 13:08:39 +0200 Subject: [PATCH 10/41] Updated defconfig, now 100% vetted vs. old config AND KConfig clean --- nuttx/configs/px4fmu-v1/Kconfig | 6 +- nuttx/configs/px4fmu-v1/nsh/defconfig | 110 ++++++++++++++------------ 2 files changed, 64 insertions(+), 52 deletions(-) diff --git a/nuttx/configs/px4fmu-v1/Kconfig b/nuttx/configs/px4fmu-v1/Kconfig index b54c8980b9..edbafa06f8 100644 --- a/nuttx/configs/px4fmu-v1/Kconfig +++ b/nuttx/configs/px4fmu-v1/Kconfig @@ -5,16 +5,16 @@ if ARCH_BOARD_PX4FMU_V1 -config CONFIG_HRT_TIMER +config HRT_TIMER bool "High resolution timer support" default y ---help--- Enable high resolution timer for PPM capture and system clocks. -config CONFIG_HRT_PPM +config HRT_PPM bool "PPM input capture" default y - depends on CONFIG_HRT_TIMER + depends on HRT_TIMER ---help--- Enable PPM input capture via HRT (for CPPM / PPM sum RC inputs) diff --git a/nuttx/configs/px4fmu-v1/nsh/defconfig b/nuttx/configs/px4fmu-v1/nsh/defconfig index 11fc24d419..63628d47e1 100644 --- a/nuttx/configs/px4fmu-v1/nsh/defconfig +++ b/nuttx/configs/px4fmu-v1/nsh/defconfig @@ -4,12 +4,6 @@ # CONFIG_NUTTX_NEWCONFIG=y -# -# XXX Needs menu -# -CONFIG_HRT_TIMER=y -CONFIG_HRT_PPM=y - # # Build Setup # @@ -185,7 +179,7 @@ CONFIG_STM32_STM32F40XX=y CONFIG_STM32_ADC1=y # CONFIG_STM32_ADC2 is not set # CONFIG_STM32_ADC3 is not set -# CONFIG_STM32_BKPSRAM is not set +CONFIG_STM32_BKPSRAM=y # CONFIG_STM32_CAN1 is not set # CONFIG_STM32_CAN2 is not set CONFIG_STM32_CCMDATARAM=y @@ -219,9 +213,9 @@ CONFIG_STM32_TIM5=y CONFIG_STM32_TIM6=y CONFIG_STM32_TIM7=y # CONFIG_STM32_TIM8 is not set -# CONFIG_STM32_TIM9 is not set -# CONFIG_STM32_TIM10 is not set -# CONFIG_STM32_TIM11 is not set +CONFIG_STM32_TIM9=y +CONFIG_STM32_TIM10=y +CONFIG_STM32_TIM11=y CONFIG_STM32_TIM12=y CONFIG_STM32_TIM13=y CONFIG_STM32_TIM14=y @@ -232,7 +226,7 @@ CONFIG_STM32_USART2=y CONFIG_STM32_UART5=y CONFIG_STM32_USART6=y # CONFIG_STM32_IWDG is not set -# CONFIG_STM32_WWDG is not set +CONFIG_STM32_WWDG=y CONFIG_STM32_ADC=y CONFIG_STM32_SPI=y CONFIG_STM32_I2C=y @@ -242,15 +236,18 @@ CONFIG_STM32_I2C=y # CONFIG_STM32_FLASH_PREFETCH=y # CONFIG_STM32_JTAG_DISABLE is not set -# CONFIG_STM32_JTAG_FULL_ENABLE is not set +CONFIG_STM32_JTAG_FULL_ENABLE=y # CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set -CONFIG_STM32_JTAG_SW_ENABLE=y -# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set +# CONFIG_STM32_JTAG_SW_ENABLE is not set +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y # CONFIG_STM32_FORCEPOWER is not set # CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set # CONFIG_STM32_CCMEXCLUDE is not set # CONFIG_STM32_TIM4_PWM is not set # CONFIG_STM32_TIM5_PWM is not set +# CONFIG_STM32_TIM9_PWM is not set +# CONFIG_STM32_TIM10_PWM is not set +# CONFIG_STM32_TIM11_PWM is not set # CONFIG_STM32_TIM12_PWM is not set # CONFIG_STM32_TIM13_PWM is not set # CONFIG_STM32_TIM14_PWM is not set @@ -262,7 +259,7 @@ CONFIG_STM32_USART=y # U[S]ART Configuration # # CONFIG_USART1_RS485 is not set -# CONFIG_USART1_RXDMA is not set +CONFIG_USART1_RXDMA=y # CONFIG_USART2_RS485 is not set CONFIG_USART2_RXDMA=y # CONFIG_USART3_RXDMA is not set @@ -279,14 +276,14 @@ CONFIG_STM32_USART_SINGLEWIRE=y # SPI Configuration # # CONFIG_STM32_SPI_INTERRUPTS is not set -CONFIG_STM32_SPI_DMA=n +# CONFIG_STM32_SPI_DMA is not set # # I2C Configuration # # CONFIG_STM32_I2C_DYNTIMEO is not set CONFIG_STM32_I2CTIMEOSEC=0 -CONFIG_STM32_I2CTIMEOMS=500 +CONFIG_STM32_I2CTIMEOMS=10 CONFIG_STM32_I2CTIMEOTICKS=500 # CONFIG_STM32_I2C_DUTY16_9 is not set @@ -324,7 +321,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y CONFIG_BOARD_LOOPSPERMSEC=16717 # CONFIG_ARCH_CALIBRATION is not set CONFIG_DRAM_START=0x20000000 -CONFIG_DRAM_SIZE=114688 +CONFIG_DRAM_SIZE=196608 CONFIG_ARCH_HAVE_INTERRUPTSTACK=y CONFIG_ARCH_INTERRUPTSTACK=0 @@ -356,27 +353,29 @@ CONFIG_NSH_MMCSDSPIPORTNO=3 # # Board-Specific Options # +CONFIG_HRT_TIMER=y +CONFIG_HRT_PPM=y # # RTOS Features # # CONFIG_BOARD_INITIALIZE is not set CONFIG_MSEC_PER_TICK=1 -CONFIG_RR_INTERVAL=5 +CONFIG_RR_INTERVAL=0 CONFIG_SCHED_INSTRUMENTATION=y CONFIG_TASK_NAME_SIZE=24 # CONFIG_SCHED_HAVE_PARENT is not set # CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=12 -CONFIG_START_DAY=6 +CONFIG_START_YEAR=1970 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=1 # CONFIG_DEV_CONSOLE is not set # CONFIG_MUTEX_TYPES is not set CONFIG_PRIORITY_INHERITANCE=y -CONFIG_SEM_PREALLOCHOLDERS=16 -CONFIG_SEM_NNESTPRIO=16 +CONFIG_SEM_PREALLOCHOLDERS=0 +CONFIG_SEM_NNESTPRIO=8 # CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set +CONFIG_FDCLONE_STDIO=y CONFIG_SDCLONE_DISABLE=y CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_STARTHOOK is not set @@ -399,7 +398,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 -CONFIG_SIG_SIGWORK=17 +CONFIG_SIG_SIGWORK=4 # # Sizes of configurable things (0 disables) @@ -447,7 +446,7 @@ CONFIG_SPI=y CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set +CONFIG_WATCHDOG=y # CONFIG_ANALOG is not set # CONFIG_AUDIO_DEVICES is not set # CONFIG_BCH is not set @@ -487,8 +486,8 @@ CONFIG_NO_SERIAL_CONSOLE=y # # USART1 Configuration # -CONFIG_USART1_RXBUFSIZE=256 -CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_RXBUFSIZE=512 +CONFIG_USART1_TXBUFSIZE=512 CONFIG_USART1_BAUD=57600 CONFIG_USART1_BITS=8 CONFIG_USART1_PARITY=0 @@ -497,9 +496,9 @@ CONFIG_USART1_2STOP=0 # # USART2 Configuration # -CONFIG_USART2_RXBUFSIZE=256 -CONFIG_USART2_TXBUFSIZE=256 -CONFIG_USART2_BAUD=115200 +CONFIG_USART2_RXBUFSIZE=512 +CONFIG_USART2_TXBUFSIZE=512 +CONFIG_USART2_BAUD=57600 CONFIG_USART2_BITS=8 CONFIG_USART2_PARITY=0 CONFIG_USART2_2STOP=0 @@ -507,9 +506,9 @@ CONFIG_USART2_2STOP=0 # # UART5 Configuration # -CONFIG_UART5_RXBUFSIZE=256 -CONFIG_UART5_TXBUFSIZE=256 -CONFIG_UART5_BAUD=115200 +CONFIG_UART5_RXBUFSIZE=512 +CONFIG_UART5_TXBUFSIZE=512 +CONFIG_UART5_BAUD=57600 CONFIG_UART5_BITS=8 CONFIG_UART5_PARITY=0 CONFIG_UART5_2STOP=0 @@ -517,9 +516,9 @@ CONFIG_UART5_2STOP=0 # # USART6 Configuration # -CONFIG_USART6_RXBUFSIZE=256 -CONFIG_USART6_TXBUFSIZE=256 -CONFIG_USART6_BAUD=115200 +CONFIG_USART6_RXBUFSIZE=512 +CONFIG_USART6_TXBUFSIZE=512 +CONFIG_USART6_BAUD=57600 CONFIG_USART6_BITS=8 CONFIG_USART6_PARITY=0 CONFIG_USART6_2STOP=0 @@ -558,9 +557,9 @@ CONFIG_CDCACM_NRDREQS=4 CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_VENDORID=0x26ac -CONFIG_CDCACM_PRODUCTID=0x10 +CONFIG_CDCACM_PRODUCTID=0x0010 CONFIG_CDCACM_VENDORSTR="3D Robotics" -CONFIG_CDCACM_PRODUCTSTR="PX4FMU v1.x" +CONFIG_CDCACM_PRODUCTSTR="PX4 FMU v1.x" # CONFIG_USBMSC is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set @@ -598,7 +597,7 @@ CONFIG_FS_NXFFS=y CONFIG_NXFFS_PREALLOCATED=y CONFIG_NXFFS_ERASEDSTATE=0xff CONFIG_NXFFS_PACKTHRESHOLD=32 -CONFIG_NXFFS_MAXNAMLEN=255 +CONFIG_NXFFS_MAXNAMLEN=32 CONFIG_NXFFS_TAILTHRESHOLD=2048 CONFIG_FS_ROMFS=y # CONFIG_FS_SMARTFS is not set @@ -650,7 +649,7 @@ CONFIG_BUILTIN=y # # Standard C Library Options # -CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_BUFFER_SIZE=256 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 CONFIG_LIB_HOMEDIR="/" @@ -670,7 +669,19 @@ CONFIG_LIBC_STRERROR=y CONFIG_ARCH_LOWPUTC=y CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_OPTIMIZED_FUNCTIONS=y +CONFIG_ARCH_MEMCPY=y +# CONFIG_ARCH_MEMCMP is not set +# CONFIG_ARCH_MEMMOVE is not set +# CONFIG_ARCH_MEMSET is not set +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_ARCH_STRCHR is not set +# CONFIG_ARCH_STRCMP is not set +# CONFIG_ARCH_STRCPY is not set +# CONFIG_ARCH_STRNCPY is not set +# CONFIG_ARCH_STRLEN is not set +# CONFIG_ARCH_STRNLEN is not set +# CONFIG_ARCH_BZERO is not set # # Non-standard Library Support @@ -678,7 +689,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WORKPRIORITY=192 -CONFIG_SCHED_WORKPERIOD=50000 +CONFIG_SCHED_WORKPERIOD=5000 CONFIG_SCHED_WORKSTACKSIZE=2048 CONFIG_SCHED_LPWORK=y CONFIG_SCHED_LPWORKPRIORITY=50 @@ -857,22 +868,23 @@ CONFIG_NSH_BUILTIN_APPS=y # CONFIG_NSH_CMDOPT_DF_H is not set CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 -# CONFIG_NSH_STRERROR is not set -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_NESTDEPTH=3 +CONFIG_NSH_STRERROR=y +CONFIG_NSH_LINELEN=128 +CONFIG_NSH_MAXARGUMENTS=12 +CONFIG_NSH_NESTDEPTH=8 # CONFIG_NSH_DISABLESCRIPT is not set # CONFIG_NSH_DISABLEBG is not set CONFIG_NSH_ROMFSETC=y -CONFIG_NSH_ARCHROMFS=y # CONFIG_NSH_ROMFSRC is not set CONFIG_NSH_ROMFSMOUNTPT="/etc" CONFIG_NSH_INITSCRIPT="init.d/rcS" CONFIG_NSH_ROMFSDEVNO=0 CONFIG_NSH_ROMFSSECTSIZE=128 +CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_FATDEVNO=1 CONFIG_NSH_FATSECTSIZE=512 CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT=/tmp +CONFIG_NSH_FATMOUNTPT="/tmp" CONFIG_NSH_CONSOLE=y # CONFIG_NSH_USBCONSOLE is not set From c239e3577d53cb64869165b2e5b97f659df0d44b Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sun, 2 Jun 2013 13:15:32 +0200 Subject: [PATCH 11/41] KConfig fixes for STM32F4 (fixes flash prefetch never being enabled, added two NSH options to KConfig) --- apps/nshlib/Kconfig | 17 +++++++++++++++++ nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c | 2 +- nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c | 2 +- .../configs/mikroe-stm32f4/src/up_clockconfig.c | 2 +- 4 files changed, 20 insertions(+), 3 deletions(-) diff --git a/apps/nshlib/Kconfig b/apps/nshlib/Kconfig index 72041ec765..ded9f2e677 100644 --- a/apps/nshlib/Kconfig +++ b/apps/nshlib/Kconfig @@ -252,6 +252,13 @@ config NSH_LINELEN The maximum length of one command line and of one output line. Default: 80 +config NSH_MAXARGUMENTS + int "Maximum number of command arguments" + default 6 + ---help--- + The maximum number of NSH command arguments. + Default: 6 + config NSH_NESTDEPTH int "Maximum command nesting" default 3 @@ -354,6 +361,16 @@ config NSH_ROMFSSECTSIZE increased if the ROMFS volume were to be become large. Any value selected must be a power of 2. +config NSH_ARCHROMFS + bool "Architecture-specific ROMFS header" + default n + depends on NSH_ROMFSETC + ---help--- + Enable this option to provide an architecture-specific ROMFS + header at . Note that this header + will be copied from nuttx/configs//include and should + be stored at this location. + config NSH_FATDEVNO int "FAT block device minor number" default 0 diff --git a/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c index ac72fb60bc..dd796f86c2 100644 --- a/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c @@ -631,7 +631,7 @@ static void stm32_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ -#ifdef STM32_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c index fc7fe1697d..82757c43f6 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -669,7 +669,7 @@ static void stm32_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ -#ifdef STM32_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); diff --git a/nuttx/configs/mikroe-stm32f4/src/up_clockconfig.c b/nuttx/configs/mikroe-stm32f4/src/up_clockconfig.c index 9618cf8dd5..3c55bd9501 100644 --- a/nuttx/configs/mikroe-stm32f4/src/up_clockconfig.c +++ b/nuttx/configs/mikroe-stm32f4/src/up_clockconfig.c @@ -128,7 +128,7 @@ void stm32_board_clockconfig(void) /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ -#ifdef STM32_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); From ce52387ef60c946fed49444f433d35ade6dbf715 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sun, 2 Jun 2013 17:48:05 +0200 Subject: [PATCH 12/41] Enable stack checking for FMU --- nuttx/configs/px4fmu-v1/nsh/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/nuttx/configs/px4fmu-v1/nsh/defconfig b/nuttx/configs/px4fmu-v1/nsh/defconfig index 63628d47e1..f75fd0d19d 100644 --- a/nuttx/configs/px4fmu-v1/nsh/defconfig +++ b/nuttx/configs/px4fmu-v1/nsh/defconfig @@ -82,6 +82,7 @@ CONFIG_ARCH_CHIP="stm32" CONFIG_ARMV7M_USEBASEPRI=y CONFIG_ARCH_HAVE_CMNVECTOR=y CONFIG_ARMV7M_CMNVECTOR=y +CONFIG_ARMV7M_STACKCHECK=y CONFIG_ARCH_FPU=y CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set From 80a7f76152acab6d864047925069516eebea6543 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sun, 2 Jun 2013 17:52:52 +0200 Subject: [PATCH 13/41] Added stack checking for ARMv7M using R10, R10 NOT reserved yet --- nuttx/arch/arm/src/armv7-m/Kconfig | 6 ++++++ nuttx/arch/arm/src/armv7-m/up_initialstate.c | 10 ++++++++++ nuttx/arch/arm/src/stm32/Make.defs | 4 ++++ nuttx/arch/arm/src/stm32/stm32_start.c | 16 ++++++++++++++++ nuttx/include/nuttx/compiler.h | 2 +- 5 files changed, 37 insertions(+), 1 deletion(-) diff --git a/nuttx/arch/arm/src/armv7-m/Kconfig b/nuttx/arch/arm/src/armv7-m/Kconfig index a154a4c5c4..9c55068d5c 100644 --- a/nuttx/arch/arm/src/armv7-m/Kconfig +++ b/nuttx/arch/arm/src/armv7-m/Kconfig @@ -57,3 +57,9 @@ config ARMV7M_OABI_TOOLCHAIN ---help--- Most of the older buildroot toolchains are OABI and are named arm-nuttx-elf- vs. arm-nuttx-eabi- +config ARMV7M_STACKCHECK + bool "Steck for stack overflow on function calls" + default n + ---help--- + This check uses R10 to check for a stack overflow within function calls. This has a performance impact, + but will be able to catch hard to find stack overflows. diff --git a/nuttx/arch/arm/src/armv7-m/up_initialstate.c b/nuttx/arch/arm/src/armv7-m/up_initialstate.c index c19d32f116..04089f8ac1 100644 --- a/nuttx/arch/arm/src/armv7-m/up_initialstate.c +++ b/nuttx/arch/arm/src/armv7-m/up_initialstate.c @@ -93,6 +93,16 @@ void up_initial_state(struct tcb_s *tcb) xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; +#ifdef CONFIG_ARMV7M_STACKCHECK + /* Set the stack limit value */ + + xcp->regs[REG_R10] = (uint32_t)tcb->stack_alloc_ptr + 64; + + /* Fill the stack with a watermark value */ + + memset(tcb->stack_alloc_ptr, 0xff, tcb->adj_stack_size); +#endif + /* Save the task entry point (stripping off the thumb bit) */ xcp->regs[REG_PC] = (uint32_t)tcb->start & ~1; diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs index 15b87ca9e8..3b64958579 100644 --- a/nuttx/arch/arm/src/stm32/Make.defs +++ b/nuttx/arch/arm/src/stm32/Make.defs @@ -54,6 +54,10 @@ CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_systemreset.c CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c CMN_CSRCS += up_svcall.c up_vfork.c +ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) +CMN_CSRCS += up_stackcheck.c +endif + ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) CMN_ASRCS += up_exception.S CMN_CSRCS += up_vectors.c diff --git a/nuttx/arch/arm/src/stm32/stm32_start.c b/nuttx/arch/arm/src/stm32/stm32_start.c index a2f82f7b2b..add226b075 100644 --- a/nuttx/arch/arm/src/stm32/stm32_start.c +++ b/nuttx/arch/arm/src/stm32/stm32_start.c @@ -76,6 +76,16 @@ # define showprogress(c) #endif +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_STACKCHECK +/* we need to get r10 set before we can allow instrumentation calls */ + +void __start(void) __attribute__ ((no_instrument_function)); +#endif + /**************************************************************************** * Name: stm32_fpuconfig * @@ -183,6 +193,12 @@ void __start(void) const uint32_t *src; uint32_t *dest; +#ifdef CONFIG_ARMV7M_STACKCHECK + /* Set the stack limit before we attempt to call any functions */ + + __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : ); +#endif + /* Configure the uart so that we can get debug output as soon as possible */ stm32_clockconfig(); diff --git a/nuttx/include/nuttx/compiler.h b/nuttx/include/nuttx/compiler.h index 1e6acd6ff0..7aa7281b4f 100644 --- a/nuttx/include/nuttx/compiler.h +++ b/nuttx/include/nuttx/compiler.h @@ -108,7 +108,7 @@ * indicates that the function should never be inlined. */ -# define inline_function __attribute__ ((always_inline)) +# define inline_function __attribute__ ((always_inline,no_instrument_function)) # define noinline_function __attribute__ ((noinline)) /* GCC has does not use storage classes to qualify addressing */ From 6e4d238d61f30c508a5e8c282e9a409a659c0957 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sun, 2 Jun 2013 17:57:17 +0200 Subject: [PATCH 14/41] Commented out spurious assert --- nuttx/sched/sem_holder.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/nuttx/sched/sem_holder.c b/nuttx/sched/sem_holder.c index ab59ec8c80..de648e5669 100644 --- a/nuttx/sched/sem_holder.c +++ b/nuttx/sched/sem_holder.c @@ -452,7 +452,8 @@ static int sem_restoreholderprio(FAR struct semholder_s *pholder, FAR sem_t *sem * priorities back to the base priority. */ - DEBUGASSERT(htcb->sched_priority == stcb->sched_priority && htcb->npend_reprio == 0); + /* XXX Debug assertion needs inspection */ + //DEBUGASSERT(htcb->sched_priority == stcb->sched_priority && htcb->npend_reprio == 0); sched_reprioritize(htcb, htcb->base_priority); } From 3dfc0b6d951ffce1657167e56feb5609dd3ef167 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Sun, 2 Jun 2013 17:58:44 +0200 Subject: [PATCH 15/41] Hardware flow control bits --- nuttx/arch/arm/src/stm32/stm32_serial.c | 168 ++++++++++++++++++------ nuttx/include/nuttx/serial/serial.h | 12 ++ nuttx/include/termios.h | 3 + 3 files changed, 140 insertions(+), 43 deletions(-) diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c index af95244f00..b172a224f6 100644 --- a/nuttx/arch/arm/src/stm32/stm32_serial.c +++ b/nuttx/arch/arm/src/stm32/stm32_serial.c @@ -257,11 +257,15 @@ struct up_dev_s uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (7 or 8) */ bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ + bool iflow; /* input flow control (RTS) enabled */ + bool oflow; /* output flow control (CTS) enabled */ uint32_t baud; /* Configured baud */ #else const uint8_t parity; /* 0=none, 1=odd, 2=even */ const uint8_t bits; /* Number of bits (7 or 8) */ const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ + const bool iflow; /* input flow control (RTS) enabled */ + const bool oflow; /* output flow control (CTS) enabled */ const uint32_t baud; /* Configured baud */ #endif @@ -298,7 +302,7 @@ struct up_dev_s * Private Function Prototypes ****************************************************************************/ -static void up_setspeed(struct uart_dev_s *dev); +static void up_set_format(struct uart_dev_s *dev); static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); @@ -492,6 +496,8 @@ static struct up_dev_s g_usart1priv = .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, + .iflow = false, + .oflow = false, .baud = CONFIG_USART1_BAUD, .apbclock = STM32_PCLK2_FREQUENCY, .usartbase = STM32_USART1_BASE, @@ -552,6 +558,8 @@ static struct up_dev_s g_usart2priv = .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, + .iflow = false, + .oflow = false, .baud = CONFIG_USART2_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_USART2_BASE, @@ -612,6 +620,8 @@ static struct up_dev_s g_usart3priv = .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, + .iflow = false, + .oflow = false, .baud = CONFIG_USART3_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_USART3_BASE, @@ -672,17 +682,15 @@ static struct up_dev_s g_uart4priv = .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, + .iflow = false, + .oflow = false, .baud = CONFIG_UART4_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, -#ifdef GPIO_UART4_CTS - .cts_gpio = GPIO_UART4_CTS, -#endif -#ifdef GPIO_UART4_RTS - .rts_gpio = GPIO_UART4_RTS, -#endif + .cts_gpio = 0, /* flow control not supported on this port */ + .rts_gpio = 0, /* flow control not supported on this port */ #ifdef CONFIG_UART4_RXDMA .rxdma_channel = DMAMAP_UART4_RX, .rxfifo = g_uart4rxfifo, @@ -732,17 +740,15 @@ static struct up_dev_s g_uart5priv = .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, + .iflow = false, + .oflow = false, .baud = CONFIG_UART5_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, -#ifdef GPIO_UART5_CTS - .cts_gpio = GPIO_UART5_CTS, -#endif -#ifdef GPIO_UART5_RTS - .rts_gpio = GPIO_UART5_RTS, -#endif + .cts_gpio = 0, /* flow control not supported on this port */ + .rts_gpio = 0, /* flow control not supported on this port */ #ifdef CONFIG_UART5_RXDMA .rxdma_channel = DMAMAP_UART5_RX, .rxfifo = g_uart5rxfifo, @@ -792,6 +798,8 @@ static struct up_dev_s g_usart6priv = .parity = CONFIG_USART6_PARITY, .bits = CONFIG_USART6_BITS, .stopbits2 = CONFIG_USART6_2STOP, + .iflow = false, + .oflow = false, .baud = CONFIG_USART6_BAUD, .apbclock = STM32_PCLK2_FREQUENCY, .usartbase = STM32_USART6_BASE, @@ -1091,15 +1099,15 @@ static int up_dma_nextrx(struct up_dev_s *priv) #endif /**************************************************************************** - * Name: up_setspeed + * Name: up_set_format * * Description: - * Set the serial line speed. + * Set the serial line format and speed. * ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void up_setspeed(struct uart_dev_s *dev) +static void up_set_format(struct uart_dev_s *dev) { #ifdef CONFIG_STM32_STM32F30XX @@ -1168,6 +1176,7 @@ static void up_setspeed(struct uart_dev_s *dev) uint32_t mantissa; uint32_t fraction; uint32_t brr; + uint32_t regval; /* Configure the USART Baud Rate. The baud rate for the receiver and * transmitter (Rx and Tx) are both set to the same value as programmed @@ -1198,9 +1207,52 @@ static void up_setspeed(struct uart_dev_s *dev) brr |= fraction << USART_BRR_FRAC_SHIFT; up_serialout(priv, STM32_USART_BRR_OFFSET, brr); + /* Configure parity mode */ + + regval = up_serialin(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_PCE|USART_CR1_PS); + + if (priv->parity == 1) /* Odd parity */ + { + regval |= (USART_CR1_PCE|USART_CR1_PS); + } + else if (priv->parity == 2) /* Even parity */ + { + regval |= USART_CR1_PCE; + } + + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); + + /* Configure STOP bits */ + + regval = up_serialin(priv, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK); + + if (priv->stopbits2) + { + regval |= USART_CR2_STOP2; + } + up_serialout(priv, STM32_USART_CR2_OFFSET, regval); + + /* Configure hardware flow control */ + + regval = up_serialin(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSE|USART_CR3_RTSE); + + if (priv->iflow && (priv->rts_gpio != 0)) + { + regval |= USART_CR3_RTSE; + } + if (priv->oflow && (priv->cts_gpio != 0)) + { + regval |= USART_CR3_CTSE; + } + + up_serialout(priv, STM32_USART_CR3_OFFSET, regval); + #endif } -#endif +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ /**************************************************************************** * Name: up_setup @@ -1246,10 +1298,10 @@ static int up_setup(struct uart_dev_s *dev) #endif /* Configure CR2 */ - /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ + /* Clear CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ regval = up_serialin(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL| + regval &= ~(USART_CR2_CLKEN|USART_CR2_CPOL| USART_CR2_CPHA|USART_CR2_LBCL|USART_CR2_LBDIE); /* Configure STOP bits */ @@ -1262,28 +1314,19 @@ static int up_setup(struct uart_dev_s *dev) up_serialout(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ - /* Clear M, PCE, PS, TE, REm and all interrupt enable bits */ + /* Clear M, TE, REm and all interrupt enable bits */ regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_M|USART_CR1_PCE|USART_CR1_PS|USART_CR1_TE| + regval &= ~(USART_CR1_M|USART_CR1_TE| USART_CR1_RE|USART_CR1_ALLINTS); - /* Configure word length and parity mode */ + /* Configure word length */ if (priv->bits == 9) /* Default: 1 start, 8 data, n stop */ { regval |= USART_CR1_M; /* 1 start, 9 data, n stop */ } - if (priv->parity == 1) /* Odd parity */ - { - regval |= (USART_CR1_PCE|USART_CR1_PS); - } - else if (priv->parity == 2) /* Even parity */ - { - regval |= USART_CR1_PCE; - } - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ @@ -1292,13 +1335,11 @@ static int up_setup(struct uart_dev_s *dev) regval = up_serialin(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE); - /* Configure hardware flow control -- Not yet supported */ - up_serialout(priv, STM32_USART_CR3_OFFSET, regval); - /* Configure the USART Baud Rate. */ + /* Configure the USART line format and speed. */ - up_setspeed(dev); + up_set_format(dev); /* Enable Rx, Tx, and the USART */ @@ -1679,12 +1720,21 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; } - /* TODO: Other termios fields are not yet returned. - * Note that only cfsetospeed is not necessary because we have - * knowledge that only one speed is supported. + cfsetispeed(termiosp, priv->baud); + + /* Note that since we only support 8/9 bit modes and + * there is no way to report 9-bit mode, we always claim 8. */ - cfsetispeed(termiosp, priv->baud); + termiosp->c_cflag = + ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0) | + ((priv->stopbits2) ? CSTOPB : 0) | + ((priv->oflow) ? CCTS_OFLOW : 0) | + ((priv->iflow) ? CRTS_IFLOW : 0) | + CS8; + + /* TODO: CCTS_IFLOW, CCTS_OFLOW */ } break; @@ -1698,16 +1748,48 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; } - /* TODO: Handle other termios settings. - * Note that only cfgetispeed is used besued we have knowledge + /* Perform some sanity checks before accepting any changes */ + + if (((termiosp->c_cflag & CSIZE) != CS8) || + ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) || + ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0))) + { + ret = -EINVAL; + break; + } + + if (termiosp->c_cflag & PARENB) + { + priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + priv->parity = 0; + } + + priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; + + /* Note that since there is no way to request 9-bit mode + * and no way to support 5/6/7-bit modes, we ignore them + * all here. + */ + + /* Note that only cfgetispeed is used because we have knowledge * that only one speed is supported. */ priv->baud = cfgetispeed(termiosp); - up_setspeed(dev); + + /* effect the changes immediately - note that we do not implement + * TCSADRAIN / TCSAFLUSH + */ + + up_set_format(dev); } break; -#endif +#endif /* CONFIG_SERIAL_TERMIOS */ #ifdef CONFIG_USART_BREAKS case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ diff --git a/nuttx/include/nuttx/serial/serial.h b/nuttx/include/nuttx/serial/serial.h index 57bcf1f272..4ee2005ef2 100644 --- a/nuttx/include/nuttx/serial/serial.h +++ b/nuttx/include/nuttx/serial/serial.h @@ -46,6 +46,9 @@ #include #include #include +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif #include @@ -217,6 +220,15 @@ struct uart_dev_s #ifndef CONFIG_DISABLE_POLL struct pollfd *fds[CONFIG_SERIAL_NPOLLWAITERS]; #endif + + /* Terminal control flags */ + +#ifdef CONFIG_SERIAL_TERMIOS + tcflag_t tc_iflag; /* Input modes */ + tcflag_t tc_oflag; /* Output modes */ + tcflag_t tc_lflag; /* Local modes */ +#endif + }; typedef struct uart_dev_s uart_dev_t; diff --git a/nuttx/include/termios.h b/nuttx/include/termios.h index 2e1c38fc26..95b20a3d36 100644 --- a/nuttx/include/termios.h +++ b/nuttx/include/termios.h @@ -109,6 +109,9 @@ #define PARODD (1 << 5) /* Bit 5: Odd parity, else even */ #define HUPCL (1 << 6) /* Bit 6: Hang up on last close */ #define CLOCAL (1 << 7) /* Bit 7: Ignore modem status lines */ +#define CCTS_OFLOW (1 << 8) /* Bit 8: CTS flow control of output */ +#define CRTSCTS CCTS_OFLOW +#define CRTS_IFLOW (1 << 9) /* Bit 9: RTS flow control of input */ /* Local Modes (c_lflag in the termios structure) */ From 53c51e08ddc1b83bedb890338142ce9a6ba289be Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 2 Jun 2013 16:49:41 -0600 Subject: [PATCH 16/41] Fix an assertion --- nuttx/ChangeLog | 2 ++ nuttx/libc/stdio/Make.defs | 2 +- nuttx/libc/stdio/lib_vdprintf.c | 2 +- nuttx/sched/sem_holder.c | 17 ++++++++++++++--- 4 files changed, 18 insertions(+), 5 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 1906b3c125..2394f68d0d 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4868,3 +4868,5 @@ the SAM4L (2013-6-2). * libc/stdio/lib_dprintd.c and lib_vdprintf.c: Add dprintf() and vdprintf() (the latter from Andrew Tridgell, 2013-6-2). + * sched/sem_holder.c: Modify assertion that is reported to cause + false alarm assertions (2013-6-2). diff --git a/nuttx/libc/stdio/Make.defs b/nuttx/libc/stdio/Make.defs index b64d2bd5bc..f04dfb2157 100644 --- a/nuttx/libc/stdio/Make.defs +++ b/nuttx/libc/stdio/Make.defs @@ -37,7 +37,7 @@ # This first group of C files do not depend on having file descriptors or # C streams. -CSRCS += lib_fileno.c lib_printf.c lib_syslog.c lib_lowsyslog.c\ +CSRCS += lib_fileno.c lib_printf.c lib_syslog.c lib_lowsyslog.c \ lib_sprintf.c lib_asprintf.c lib_snprintf.c lib_libsprintf.c \ lib_vsprintf.c lib_avsprintf.c lib_vsnprintf.c lib_libvsprintf.c \ lib_dprintf.c lib_vdprintf.c \ diff --git a/nuttx/libc/stdio/lib_vdprintf.c b/nuttx/libc/stdio/lib_vdprintf.c index 8cdea96c6b..d96ca40f88 100644 --- a/nuttx/libc/stdio/lib_vdprintf.c +++ b/nuttx/libc/stdio/lib_vdprintf.c @@ -56,4 +56,4 @@ int vdprintf(int fd, FAR const char *fmt, va_list ap) lib_rawoutstream(&rawoutstream, fd); return lib_vsprintf(&rawoutstream.public, fmt, ap); -} +} diff --git a/nuttx/sched/sem_holder.c b/nuttx/sched/sem_holder.c index ab59ec8c80..b88bebf366 100644 --- a/nuttx/sched/sem_holder.c +++ b/nuttx/sched/sem_holder.c @@ -448,11 +448,22 @@ static int sem_restoreholderprio(FAR struct semholder_s *pholder, FAR sem_t *sem if (htcb->npend_reprio < 1) { - /* No... the holder thread has only been boosted once. Reset all - * priorities back to the base priority. + /* No... the holder thread has only been boosted once. + * npend_reprio should be 0 and the boosted priority should be the + * priority of the task that just got the semaphore + * (stcb->sched_priority) + * + * That latter assumption may not be true if the stcb's priority + * was also boosted so that it no longer matches the htcb's + * sched_priority. Or if CONFIG_SEM_NNESTPRIO is too small (so + * that we do not have a proper record of the reprioritizations). */ - DEBUGASSERT(htcb->sched_priority == stcb->sched_priority && htcb->npend_reprio == 0); + DEBUGASSERT(/* htcb->sched_priority == stcb->sched_priority && */ + htcb->npend_reprio == 0); + + /* Reset the holder's priority back to the base priority. */ + sched_reprioritize(htcb, htcb->base_priority); } From 68dcc997e8ae2390db87955dfc0d8c9bd7ec8f35 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 3 Jun 2013 09:32:04 -0600 Subject: [PATCH 17/41] Add interrupt and memory map definitions for the AT91SAM4L --- nuttx/ChangeLog | 3 + nuttx/arch/arm/include/sam34/irq.h | 221 ++---------- nuttx/arch/arm/include/sam34/sam3u_irq.h | 275 ++++++++++++++ nuttx/arch/arm/include/sam34/sam4l_irq.h | 336 ++++++++++++++++++ .../arch/arm/src/sam34/chip/sam3u_memorymap.h | 6 +- .../arch/arm/src/sam34/chip/sam4l_memorymap.h | 162 +++++++++ nuttx/arch/arm/src/sam34/chip/sam_memorymap.h | 6 +- 7 files changed, 803 insertions(+), 206 deletions(-) create mode 100644 nuttx/arch/arm/include/sam34/sam3u_irq.h create mode 100644 nuttx/arch/arm/include/sam34/sam4l_irq.h create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_memorymap.h diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 2394f68d0d..5de5652ae9 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4870,3 +4870,6 @@ vdprintf() (the latter from Andrew Tridgell, 2013-6-2). * sched/sem_holder.c: Modify assertion that is reported to cause false alarm assertions (2013-6-2). + * arch/arm/include/sam34/sam4l_irq.h and + arch/arm/src/sam34/chip/sam4l_memorymap.h: Add interrupt and memory + map definitions for the AT91SAM4L (2013-6-3). diff --git a/nuttx/arch/arm/include/sam34/irq.h b/nuttx/arch/arm/include/sam34/irq.h index 2c59f487a5..ea93b22b7d 100644 --- a/nuttx/arch/arm/include/sam34/irq.h +++ b/nuttx/arch/arm/include/sam34/irq.h @@ -33,10 +33,11 @@ * ****************************************************************************************/ -/* This file should never be included directed but, rather, - * only indirectly through nuttx/irq.h +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h */ + #ifndef __ARCH_ARM_INCLUDE_SAM34_IRQ_H #define __ARCH_ARM_INCLUDE_SAM34_IRQ_H @@ -44,50 +45,19 @@ * Included Files ****************************************************************************************/ +#include +#include + /**************************************************************************************** - * Definitions + * Pre-processor Definitions ****************************************************************************************/ -/* SAM3U Peripheral Identifiers */ - -#define SAM_PID_SUPC (0) /* Supply Controller */ -#define SAM_PID_RSTC (1) /* Reset Controller */ -#define SAM_PID_RTC (2) /* Real Time Clock */ -#define SAM_PID_RTT (3) /* Real Time Timer */ -#define SAM_PID_WDT (4) /* Watchdog Timer */ -#define SAM_PID_PMC (5) /* Power Management Controller */ -#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */ -#define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */ -#define SAM_PID_UART (8) /* Universal Asynchronous Receiver Transmitter */ -#define SAM_PID_SMC (9) /* Static Memory Controller */ -#define SAM_PID_PIOA (10) /* Parallel I/O Controller A */ -#define SAM_PID_PIOB (11) /* Parallel I/O Controller B */ -#define SAM_PID_PIOC (12) /* Parallel I/O Controller C */ -#define SAM_PID_USART0 (13) /* USART 0 */ -#define SAM_PID_USART1 (14) /* USART 1 */ -#define SAM_PID_USART2 (15) /* USART 2 */ -#define SAM_PID_USART3 (16) /* USART 3 */ -#define SAM_PID_HSMCI (17) /* High Speed Multimedia Card Interface */ -#define SAM_PID_TWI0 (18) /* Two-Wire Interface 0 */ -#define SAM_PID_TWI1 (19) /* Two-Wire Interface 1 */ -#define SAM_PID_SPI (20) /* Serial Peripheral Interface */ -#define SAM_PID_SSC (21) /* Synchronous Serial Controller */ -#define SAM_PID_TC0 (22) /* Timer Counter 0 */ -#define SAM_PID_TC1 (23) /* Timer Counter 1 */ -#define SAM_PID_TC2 (24) /* Timer Counter 2 */ -#define SAM_PID_PWM (25) /* Pulse Width Modulation Controller */ -#define SAM_PID_ADC12B (26) /* 12-bit ADC Controller */ -#define SAM_PID_ADC (27) /* 10-bit ADC Controller */ -#define SAM_PID_DMAC (28) /* DMA Controller */ -#define SAM_PID_UDPHS (29) /* USB Device High Speed */ -#define NR_PIDS (30) /* Number of peripheral identifiers */ - /* IRQ numbers. The IRQ number corresponds vector number and hence map directly to * bits in the NVIC. This does, however, waste several words of memory in the IRQ * to handle mapping tables. */ -/* Processor Exceptions (vectors 0-15) */ +/* Common Processor Exceptions (vectors 0-15) */ #define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ /* Vector 0: Reset stack pointer value */ @@ -103,183 +73,28 @@ #define SAM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ #define SAM_IRQ_SYSTICK (15) /* Vector 15: System tick */ -/* External interrupts (vectors >= 16) */ +/* Chip-Specific External interrupts */ #define SAM_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ -#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* Supply Controller */ -#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */ -#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */ -#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */ -#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */ -#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */ -#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* Enhanced Embedded Flash Controller 0 */ -#define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* Enhanced Embedded Flash Controller 1 */ -#define SAM_IRQ_UART (SAM_IRQ_EXTINT+SAM_PID_UART) /* Universal Asynchronous Receiver Transmitter */ -#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* Static Memory Controller */ -#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */ -#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */ -#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* Parallel I/O Controller C */ -#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* USART 0 */ -#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* USART 1 */ -#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+SAM_PID_USART2) /* USART 2 */ -#define SAM_IRQ_USART3 (SAM_IRQ_EXTINT+SAM_PID_USART3) /* USART 3 */ -#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* High Speed Multimedia Card Interface */ -#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* Two-Wire Interface 0 */ -#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* Two-Wire Interface 1 */ -#define SAM_IRQ_SPI (SAM_IRQ_EXTINT+SAM_PID_SPI) /* Serial Peripheral Interface */ -#define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* Synchronous Serial Controller */ -#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */ -#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */ -#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* Timer Counter 2 */ -#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* Pulse Width Modulation Controller */ -#define SAM_IRQ_ADC12B (SAM_IRQ_EXTINT+SAM_PID_ADC12B) /* 12-bit ADC Controller */ -#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* 10-bit ADC Controller */ -#define SAM_IRQ_DMAC (SAM_IRQ_EXTINT+SAM_PID_DMAC) /* DMA Controller */ -#define SAM_IRQ_UDPHS (SAM_IRQ_EXTINT+SAM_PID_UDPHS) /* USB Device High Speed */ -#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */ -#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */ -/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */ - -#ifdef CONFIG_GPIOA_IRQ -# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT) -# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */ -# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */ -# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */ -# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */ -# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */ -# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */ -# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */ -# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */ -# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */ -# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */ -# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */ -# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */ -# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */ -# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */ -# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */ -# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */ -# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */ -# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */ -# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */ -# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */ -# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */ -# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */ -# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */ -# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */ -# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */ -# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */ -# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */ -# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */ -# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */ -# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */ -# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */ -# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */ -# define SAM_NGPIOAIRQS 32 +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# include +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include #else -# define SAM_NGPIOAIRQS 0 +# error Unrecognized SAM architecture #endif -#ifdef CONFIG_GPIOB_IRQ -# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS) -# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */ -# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */ -# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */ -# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */ -# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */ -# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */ -# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */ -# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */ -# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */ -# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */ -# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */ -# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */ -# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */ -# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */ -# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */ -# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */ -# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */ -# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */ -# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */ -# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */ -# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */ -# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */ -# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */ -# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */ -# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */ -# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */ -# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */ -# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */ -# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */ -# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */ -# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */ -# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */ -# define SAM_NGPIOAIRQS 32 -#else -# define SAM_NGPIOBIRQS 0 -#endif - -#ifdef CONFIG_GPIOC_IRQ -# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS+SAM_IRQ_GPIOB_PINS) -# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */ -# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */ -# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */ -# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */ -# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */ -# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */ -# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */ -# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */ -# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */ -# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */ -# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */ -# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */ -# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */ -# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */ -# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */ -# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */ -# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */ -# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */ -# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */ -# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */ -# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */ -# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */ -# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */ -# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */ -# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */ -# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */ -# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */ -# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */ -# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */ -# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */ -# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */ -# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */ -# define SAM_NGPIOAIRQS 32 -#else -# define SAM_NGPIOCIRQS 0 -#endif - -/* Total number of IRQ numbers */ - -#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+\ - SAM_NGPIOAIRQS+SAM_NGPIOBIRQS+SAM_NGPIOCIRQS) - /**************************************************************************************** * Public Types ****************************************************************************************/ -/**************************************************************************************** - * Inline functions - ****************************************************************************************/ - -/**************************************************************************************** - * Public Variables - ****************************************************************************************/ +#ifndef __ASSEMBLY__ /**************************************************************************************** - * Public Function Prototypes + * Public Data ****************************************************************************************/ -#ifndef __ASSEMBLY__ #ifdef __cplusplus #define EXTERN extern "C" extern "C" { @@ -287,6 +102,10 @@ extern "C" { #define EXTERN extern #endif +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + #undef EXTERN #ifdef __cplusplus } diff --git a/nuttx/arch/arm/include/sam34/sam3u_irq.h b/nuttx/arch/arm/include/sam34/sam3u_irq.h new file mode 100644 index 0000000000..58f2afd946 --- /dev/null +++ b/nuttx/arch/arm/include/sam34/sam3u_irq.h @@ -0,0 +1,275 @@ +/**************************************************************************************** + * arch/arm/include/sam34/sam3u_irq.h + * + * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM3U_IRQ_H +#define __ARCH_ARM_INCLUDE_SAM34_SAM3U_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +/**************************************************************************************** + * Definitions + ****************************************************************************************/ + +/* SAM3U Peripheral Identifiers */ + +#define SAM_PID_SUPC (0) /* Supply Controller */ +#define SAM_PID_RSTC (1) /* Reset Controller */ +#define SAM_PID_RTC (2) /* Real Time Clock */ +#define SAM_PID_RTT (3) /* Real Time Timer */ +#define SAM_PID_WDT (4) /* Watchdog Timer */ +#define SAM_PID_PMC (5) /* Power Management Controller */ +#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */ +#define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */ +#define SAM_PID_UART (8) /* Universal Asynchronous Receiver Transmitter */ +#define SAM_PID_SMC (9) /* Static Memory Controller */ +#define SAM_PID_PIOA (10) /* Parallel I/O Controller A */ +#define SAM_PID_PIOB (11) /* Parallel I/O Controller B */ +#define SAM_PID_PIOC (12) /* Parallel I/O Controller C */ +#define SAM_PID_USART0 (13) /* USART 0 */ +#define SAM_PID_USART1 (14) /* USART 1 */ +#define SAM_PID_USART2 (15) /* USART 2 */ +#define SAM_PID_USART3 (16) /* USART 3 */ +#define SAM_PID_HSMCI (17) /* High Speed Multimedia Card Interface */ +#define SAM_PID_TWI0 (18) /* Two-Wire Interface 0 */ +#define SAM_PID_TWI1 (19) /* Two-Wire Interface 1 */ +#define SAM_PID_SPI (20) /* Serial Peripheral Interface */ +#define SAM_PID_SSC (21) /* Synchronous Serial Controller */ +#define SAM_PID_TC0 (22) /* Timer Counter 0 */ +#define SAM_PID_TC1 (23) /* Timer Counter 1 */ +#define SAM_PID_TC2 (24) /* Timer Counter 2 */ +#define SAM_PID_PWM (25) /* Pulse Width Modulation Controller */ +#define SAM_PID_ADC12B (26) /* 12-bit ADC Controller */ +#define SAM_PID_ADC (27) /* 10-bit ADC Controller */ +#define SAM_PID_DMAC (28) /* DMA Controller */ +#define SAM_PID_UDPHS (29) /* USB Device High Speed */ +#define NR_PIDS (30) /* Number of peripheral identifiers */ + +/* External interrupts (vectors >= 16) */ + +#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* Supply Controller */ +#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */ +#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */ +#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */ +#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */ +#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */ +#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* Enhanced Embedded Flash Controller 0 */ +#define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* Enhanced Embedded Flash Controller 1 */ +#define SAM_IRQ_UART (SAM_IRQ_EXTINT+SAM_PID_UART) /* Universal Asynchronous Receiver Transmitter */ +#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* Static Memory Controller */ +#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */ +#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */ +#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* Parallel I/O Controller C */ +#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* USART 0 */ +#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* USART 1 */ +#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+SAM_PID_USART2) /* USART 2 */ +#define SAM_IRQ_USART3 (SAM_IRQ_EXTINT+SAM_PID_USART3) /* USART 3 */ +#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* High Speed Multimedia Card Interface */ +#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* Two-Wire Interface 0 */ +#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* Two-Wire Interface 1 */ +#define SAM_IRQ_SPI (SAM_IRQ_EXTINT+SAM_PID_SPI) /* Serial Peripheral Interface */ +#define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* Synchronous Serial Controller */ +#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */ +#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */ +#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* Timer Counter 2 */ +#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* Pulse Width Modulation Controller */ +#define SAM_IRQ_ADC12B (SAM_IRQ_EXTINT+SAM_PID_ADC12B) /* 12-bit ADC Controller */ +#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* 10-bit ADC Controller */ +#define SAM_IRQ_DMAC (SAM_IRQ_EXTINT+SAM_PID_DMAC) /* DMA Controller */ +#define SAM_IRQ_UDPHS (SAM_IRQ_EXTINT+SAM_PID_UDPHS) /* USB Device High Speed */ +#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */ +#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */ + +/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */ + +#ifdef CONFIG_GPIOA_IRQ +# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT) +# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */ +# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */ +# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */ +# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */ +# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */ +# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */ +# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */ +# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */ +# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */ +# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */ +# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */ +# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */ +# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */ +# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */ +# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */ +# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */ +# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */ +# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */ +# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */ +# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */ +# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */ +# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */ +# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */ +# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */ +# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */ +# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */ +# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */ +# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */ +# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */ +# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */ +# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */ +# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOAIRQS 0 +#endif + +#ifdef CONFIG_GPIOB_IRQ +# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS) +# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */ +# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */ +# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */ +# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */ +# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */ +# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */ +# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */ +# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */ +# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */ +# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */ +# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */ +# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */ +# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */ +# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */ +# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */ +# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */ +# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */ +# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */ +# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */ +# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */ +# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */ +# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */ +# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */ +# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */ +# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */ +# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */ +# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */ +# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */ +# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */ +# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */ +# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */ +# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOBIRQS 0 +#endif + +#ifdef CONFIG_GPIOC_IRQ +# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS+SAM_IRQ_GPIOB_PINS) +# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */ +# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */ +# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */ +# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */ +# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */ +# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */ +# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */ +# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */ +# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */ +# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */ +# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */ +# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */ +# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */ +# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */ +# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */ +# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */ +# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */ +# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */ +# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */ +# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */ +# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */ +# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */ +# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */ +# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */ +# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */ +# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */ +# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */ +# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */ +# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */ +# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */ +# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */ +# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOCIRQS 0 +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+\ + SAM_NGPIOAIRQS+SAM_NGPIOBIRQS+SAM_NGPIOCIRQS) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Inline functions + ****************************************************************************************/ + +/**************************************************************************************** + * Public Variables + ****************************************************************************************/ + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM3U_IRQ_H */ + diff --git a/nuttx/arch/arm/include/sam34/sam4l_irq.h b/nuttx/arch/arm/include/sam34/sam4l_irq.h new file mode 100644 index 0000000000..061a5fe166 --- /dev/null +++ b/nuttx/arch/arm/include/sam34/sam4l_irq.h @@ -0,0 +1,336 @@ +/**************************************************************************************** + * arch/arm/include/sam34/sam4l_irq.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM4L_IRQ_H +#define __ARCH_ARM_INCLUDE_SAM34_SAM4L_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +/**************************************************************************************** + * Definitions + ****************************************************************************************/ + +/* SAM4L Peripheral Identifiers. NOTE: Interrupts are not tied to the DMA peripheral + * identifiers in the SAM4L as they were with the SAM3U. However, for consistency, those + * peripheral identifiers are defined in this file as well. + */ + +#define SAM_PID_USART0_RHR (0) /* DIR=RX REGISTER: USART0 RHR */ +#define SAM_PID_USART1_RHR (1) /* DIR=RX REGISTER: USART1 RHR */ +#define SAM_PID_USART2_RHR (2) /* DIR=RX REGISTER: USART2 RHR */ +#define SAM_PID_USART3_RHR (3) /* DIR=RX REGISTER: USART3 RHR */ +#define SAM_PID_SPI_RDR (4) /* DIR=RX REGISTER: SPI RDR */ +#define SAM_PID_TWIM0_RHR (5) /* DIR=RX REGISTER: TWIM0 RHR */ +#define SAM_PID_TWIM1_RHR (6) /* DIR=RX REGISTER: TWIM1 RHR */ +#define SAM_PID_TWIM2_RHR (7) /* DIR=RX REGISTER: TWIM2 RHR */ +#define SAM_PID_TWIM3_RHR (8) /* DIR=RX REGISTER: TWIM3 RHR */ +#define SAM_PID_TWIS0_RHR (9) /* DIR=RX REGISTER: TWIS0 RHR */ +#define SAM_PID_TWIS1_RHR (10) /* DIR=RX REGISTER: TWIS1 RHR */ +#define SAM_PID_ADCIFE_LCV (11) /* DIR=RX REGISTER: ADCIFE LCV */ +#define SAM_PID_CATB_RX (12) /* DIR=RX REGISTER: CATB Multiple */ + /* 13: Reserved */ +#define SAM_PID_IISC0_RHR (14) /* DIR=RX REGISTER: IISC RHR (CH0) */ +#define SAM_PID_IISC1_RHR (15) /* DIR=RX REGISTER: IISC RHR (CH1) */ +#define SAM_PID_PARC_RHR (16) /* DIR=RX REGISTER: PARC RHR */ +#define SAM_PID_AESA_ODATA (17) /* DIR=RX REGISTER: AESA ODATA */ +#define SAM_PID_USART0_THR (18) /* DIR=TX REGISTER: USART0 THR */ +#define SAM_PID_USART1_THR (19) /* DIR=TX REGISTER: USART1 THR */ +#define SAM_PID_USART2_THR (20) /* DIR=TX REGISTER: USART2 THR */ +#define SAM_PID_USART3_THR (21) /* DIR=TX REGISTER: USART3 THR */ +#define SAM_PID_SPI_TDR (22) /* DIR=TX REGISTER: SPI TDR */ +#define SAM_PID_TWIM0_THR (23) /* DIR=TX REGISTER: TWIM0 THR */ +#define SAM_PID_TWIM1_THR (24) /* DIR=TX REGISTER: TWIM1 THR */ +#define SAM_PID_TWIM2_THR (25) /* DIR=TX REGISTER: TWIM2 THR */ +#define SAM_PID_TWIM3_THR (26) /* DIR=TX REGISTER: TWIM3 THR */ +#define SAM_PID_TWIS0_THR (27) /* DIR=TX REGISTER: TWIS0 THR */ +#define SAM_PID_TWIS1_THR (28) /* DIR=TX REGISTER: TWIS1 THR */ +#define SAM_PID_ADCIFE_CDMA (29) /* DIR=TX REGISTER: ADCIFE CDMA */ +#define SAM_PID_CATB_TX (30) /* DIR=TX REGISTER: CATB Multiple */ +#define SAM_PID_ABDACB_SDR0 (31) /* DIR=TX REGISTER: ABDACB SDR0 */ +#define SAM_PID_ABDACB_SDR1 (32) /* DIR=TX REGISTER: ABDACB SDR1 */ +#define SAM_PID_IISC0_THR (33) /* DIR=TX REGISTER: IISC THR (CH0) */ +#define SAM_PID_IISC1_THR (34) /* DIR=TX REGISTER: IISC THR (CH1) */ +#define SAM_PID_DACC_CDR (35) /* DIR=TX REGISTER: DACC CDR */ +#define SAM_PID_AESA_IDATA (36) /* DIR=TX REGISTER: AESA IDATA */ +#define SAM_PID_LCDCA_ACMDR (37) /* DIR=TX REGISTER: LCDCA ACMDR */ +#define SAM_PID_LCDCA_ABMDR (38) /* DIR=TX REGISTER: LCDCA ABMDR */ + +/* External interrupts (vectors >= 16) */ + +#define SAM_IRQ_HFLASHC (SAM_IRQ_EXTINT+0) /* 0 Flash Controller */ +#define SAM_IRQ_PDCA0 (SAM_IRQ_EXTINT+1) /* 1 Peripheral DMA Controller 0 */ +#define SAM_IRQ_PDCA1 (SAM_IRQ_EXTINT+2) /* 2 Peripheral DMA Controller 1 */ +#define SAM_IRQ_PDCA2 (SAM_IRQ_EXTINT+3) /* 3 Peripheral DMA Controller 2 */ +#define SAM_IRQ_PDCA3 (SAM_IRQ_EXTINT+4) /* 4 Peripheral DMA Controller 3 */ +#define SAM_IRQ_PDCA4 (SAM_IRQ_EXTINT+5) /* 5 Peripheral DMA Controller 4 */ +#define SAM_IRQ_PDCA5 (SAM_IRQ_EXTINT+6) /* 6 Peripheral DMA Controller 5 */ +#define SAM_IRQ_PDCA6 (SAM_IRQ_EXTINT+7) /* 7 Peripheral DMA Controller 6 */ +#define SAM_IRQ_PDCA7 (SAM_IRQ_EXTINT+8) /* 8 Peripheral DMA Controller 7 */ +#define SAM_IRQ_PDCA8 (SAM_IRQ_EXTINT+9) /* 9 Peripheral DMA Controller 8 */ +#define SAM_IRQ_PDCA9 (SAM_IRQ_EXTINT+10) /* 10 Peripheral DMA Controller 9 */ +#define SAM_IRQ_PDCA10 (SAM_IRQ_EXTINT+11) /* 11 Peripheral DMA Controller 10 */ +#define SAM_IRQ_PDCA11 (SAM_IRQ_EXTINT+12) /* 12 Peripheral DMA Controller 11 */ +#define SAM_IRQ_PDCA12 (SAM_IRQ_EXTINT+13) /* 13 Peripheral DMA Controller 12 */ +#define SAM_IRQ_PDCA13 (SAM_IRQ_EXTINT+14) /* 14 Peripheral DMA Controller 13 */ +#define SAM_IRQ_PDCA14 (SAM_IRQ_EXTINT+15) /* 15 Peripheral DMA Controller 14 */ +#define SAM_IRQ_PDCA15 (SAM_IRQ_EXTINT+16) /* 16 Peripheral DMA Controller 15 */ +#define SAM_IRQ_CRCCU (SAM_IRQ_EXTINT+17) /* 17 CRC Calculation Unit */ +#define SAM_IRQ_USBC (SAM_IRQ_EXTINT+18) /* 18 USB 2.0 Interface */ +#define SAM_IRQ_PEVC_TR (SAM_IRQ_EXTINT+19) /* 19 Peripheral Event Controller TR */ +#define SAM_IRQ_PEVC_OV (SAM_IRQ_EXTINT+20) /* 20 Peripheral Event Controller OV */ +#define SAM_IRQ_AESA (SAM_IRQ_EXTINT+21) /* 21 Advanced Encryption Standard AESA */ +#define SAM_IRQ_PM (SAM_IRQ_EXTINT+22) /* 22 Power Manager */ +#define SAM_IRQ_SCIF (SAM_IRQ_EXTINT+23) /* 23 System Control Interface */ +#define SAM_IRQ_FREQM (SAM_IRQ_EXTINT+24) /* 24 Frequency Meter */ +#define SAM_IRQ_GPIO0 (SAM_IRQ_EXTINT+25) /* 25 General-Purpose Input/Output Controller 0 */ +#define SAM_IRQ_GPIO1 (SAM_IRQ_EXTINT+26) /* 26 General-Purpose Input/Output Controller 1 */ +#define SAM_IRQ_GPIO2 (SAM_IRQ_EXTINT+27) /* 27 General-Purpose Input/Output Controller 2 */ +#define SAM_IRQ_GPIO3 (SAM_IRQ_EXTINT+28) /* 28 General-Purpose Input/Output Controller 3 */ +#define SAM_IRQ_GPIO4 (SAM_IRQ_EXTINT+29) /* 29 General-Purpose Input/Output Controller 4 */ +#define SAM_IRQ_GPIO5 (SAM_IRQ_EXTINT+30) /* 30 General-Purpose Input/Output Controller 5 */ +#define SAM_IRQ_GPIO6 (SAM_IRQ_EXTINT+31) /* 31 General-Purpose Input/Output Controller 6 */ +#define SAM_IRQ_GPIO7 (SAM_IRQ_EXTINT+32) /* 32 General-Purpose Input/Output Controller 7 */ +#define SAM_IRQ_GPIO8 (SAM_IRQ_EXTINT+33) /* 33 General-Purpose Input/Output Controller 8 */ +#define SAM_IRQ_GPIO9 (SAM_IRQ_EXTINT+34) /* 34 General-Purpose Input/Output Controller 9 */ +#define SAM_IRQ_GPIO10 (SAM_IRQ_EXTINT+35) /* 35 General-Purpose Input/Output Controller 10 */ +#define SAM_IRQ_GPIO11 (SAM_IRQ_EXTINT+36) /* 36 General-Purpose Input/Output Controller 11 */ +#define SAM_IRQ_BPM (SAM_IRQ_EXTINT+37) /* 37 Backup Power Manager */ +#define SAM_IRQ_BSCIF (SAM_IRQ_EXTINT+38) /* 38 Backup System Control Interface */ +#define SAM_IRQ_AST_ALARM (SAM_IRQ_EXTINT+39) /* 39 Asynchronous Timer ALARM */ +#define SAM_IRQ_AST_PER (SAM_IRQ_EXTINT+40) /* 40 Asynchronous Timer PER */ +#define SAM_IRQ_AST_OVF (SAM_IRQ_EXTINT+41) /* 41 Asynchronous Timer OVF */ +#define SAM_IRQ_AST_READY (SAM_IRQ_EXTINT+42) /* 42 Asynchronous Timer READY */ +#define SAM_IRQ_AST_CLKREADY (SAM_IRQ_EXTINT+43) /* 43 Asynchronous Timer CLKREADY */ +#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+44) /* 44 Watchdog Timer */ +#define SAM_IRQ_EIC1 (SAM_IRQ_EXTINT+45) /* 45 External Interrupt Controller 1 */ +#define SAM_IRQ_EIC2 (SAM_IRQ_EXTINT+46) /* 46 External Interrupt Controller 2 */ +#define SAM_IRQ_EIC3 (SAM_IRQ_EXTINT+47) /* 47 External Interrupt Controller 3 */ +#define SAM_IRQ_EIC4 (SAM_IRQ_EXTINT+48) /* 48 External Interrupt Controller 4 */ +#define SAM_IRQ_EIC5 (SAM_IRQ_EXTINT+49) /* 49 External Interrupt Controller 5 */ +#define SAM_IRQ_EIC6 (SAM_IRQ_EXTINT+50) /* 50 External Interrupt Controller 6 */ +#define SAM_IRQ_EIC7 (SAM_IRQ_EXTINT+51) /* 51 External Interrupt Controller 7 */ +#define SAM_IRQ_EIC8 (SAM_IRQ_EXTINT+52) /* 52 External Interrupt Controller 8 */ +#define SAM_IRQ_IISC (SAM_IRQ_EXTINT+53) /* 53 Inter-IC Sound (I2S) Controller */ +#define SAM_IRQ_SPI (SAM_IRQ_EXTINT+54) /* 54 Serial Peripheral Interface */ +#define SAM_IRQ_TC00 (SAM_IRQ_EXTINT+55) /* 55 Timer/Counter 0 */ +#define SAM_IRQ_TC01 (SAM_IRQ_EXTINT+56) /* 56 Timer/Counter 1 */ +#define SAM_IRQ_TC02 (SAM_IRQ_EXTINT+57) /* 57 Timer/Counter 2 */ +#define SAM_IRQ_TC10 (SAM_IRQ_EXTINT+58) /* 58 Timer/Counter 10 */ +#define SAM_IRQ_TC11 (SAM_IRQ_EXTINT+59) /* 59 Timer/Counter 11 */ +#define SAM_IRQ_TC12 (SAM_IRQ_EXTINT+60) /* 60 Timer/Counter 12 */ +#define SAM_IRQ_TWIM0 (SAM_IRQ_EXTINT+61) /* 61 Two-wire Master Interface TWIM0 */ +#define SAM_IRQ_TWIS0 (SAM_IRQ_EXTINT+62) /* 62 Two-wire Slave Interface TWIS0 */ +#define SAM_IRQ_TWIM1 (SAM_IRQ_EXTINT+63) /* 63 Two-wire Master Interface TWIM1 */ +#define SAM_IRQ_TWIS1 (SAM_IRQ_EXTINT+64) /* 64 Two-wire Slave Interface TWIS1 */ +#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+65) /* 65 USART0 */ +#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+66) /* 66 USART1 */ +#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+67) /* 67 USART2 */ +#define SAM_IRQ_USART3 (SAM_IRQ_EXTINT+68) /* 68 USART3 */ +#define SAM_IRQ_ADCIFE (SAM_IRQ_EXTINT+69) /* 69 ADC controller interface */ +#define SAM_IRQ_DACC (SAM_IRQ_EXTINT+70) /* 70 DAC Controller */ +#define SAM_IRQ_ACIFC (SAM_IRQ_EXTINT+71) /* 71 Analog Comparator Interface */ +#define SAM_IRQ_ABDACB (SAM_IRQ_EXTINT+72) /* 72 Audio Bitstream DAC */ +#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+73) /* 73 True Random Number Generator */ +#define SAM_IRQ_PARC (SAM_IRQ_EXTINT+74) /* 74 Parallel Capture */ +#define SAM_IRQ_CATB (SAM_IRQ_EXTINT+75) /* 75 Capacitive Touch Module B */ +#define SAM_IRQ_TWIM2 (SAM_IRQ_EXTINT+77) /* 77 Two-wire Master Interface */ +#define SAM_IRQ_TWIM3 (SAM_IRQ_EXTINT+78) /* 78 Two-wire Master Interface */ +#define SAM_IRQ_LCDCA (SAM_IRQ_EXTINT+79) /* 79 LCD Controller A */ +#define SAM_IRQ_NEXTINT 80 /* Total number of external interrupt numbers */ + +#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT) /* The number of real IRQs */ + +/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */ + +#ifdef CONFIG_GPIOA_IRQ +# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT) +# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */ +# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */ +# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */ +# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */ +# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */ +# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */ +# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */ +# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */ +# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */ +# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */ +# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */ +# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */ +# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */ +# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */ +# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */ +# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */ +# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */ +# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */ +# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */ +# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */ +# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */ +# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */ +# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */ +# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */ +# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */ +# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */ +# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */ +# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */ +# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */ +# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */ +# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */ +# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOAIRQS 0 +#endif + +#ifdef CONFIG_GPIOB_IRQ +# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS) +# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */ +# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */ +# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */ +# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */ +# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */ +# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */ +# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */ +# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */ +# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */ +# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */ +# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */ +# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */ +# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */ +# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */ +# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */ +# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */ +# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */ +# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */ +# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */ +# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */ +# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */ +# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */ +# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */ +# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */ +# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */ +# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */ +# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */ +# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */ +# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */ +# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */ +# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */ +# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOBIRQS 0 +#endif + +#ifdef CONFIG_GPIOC_IRQ +# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS+SAM_IRQ_GPIOB_PINS) +# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */ +# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */ +# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */ +# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */ +# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */ +# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */ +# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */ +# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */ +# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */ +# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */ +# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */ +# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */ +# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */ +# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */ +# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */ +# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */ +# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */ +# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */ +# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */ +# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */ +# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */ +# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */ +# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */ +# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */ +# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */ +# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */ +# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */ +# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */ +# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */ +# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */ +# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */ +# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOCIRQS 0 +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+\ + SAM_NGPIOAIRQS+SAM_NGPIOBIRQS+SAM_NGPIOCIRQS) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Inline functions + ****************************************************************************************/ + +/**************************************************************************************** + * Public Variables + ****************************************************************************************/ + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM4L_IRQ_H */ + diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h index ea61f57d80..7e66c0b50f 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h @@ -33,8 +33,8 @@ * ************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_MEMORYMAP_H -#define __ARCH_ARM_SRC_SAM34_SAM3U_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MEMORYMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MEMORYMAP_H /************************************************************************************************ * Included Files @@ -142,4 +142,4 @@ * Public Functions ************************************************************************************************/ -#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam4l_memorymap.h new file mode 100644 index 0000000000..0a3acdcc2a --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_memorymap.h @@ -0,0 +1,162 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam4l_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_MEMORYMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_MEMORYMAP_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "chip.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Global Memory Space */ + +#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */ +#define SAM_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */ + /* 0x22000000-0x3fffffff: Undefined */ +#define SAM_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */ + /* 0x60000000-0xdfffffff: Reserved */ +#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */ + +/* Code Space */ + +#define SAM_INTFLASH_BASE 0x00000000 /* 0x00000000-0x003fffff: Internal FLASH */ + /* 0x00400000-0x1fffffff: Reserved */ +/* Internal SRAM Space */ + +#define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: HRAMC0 (see chip.h) */ + /* 0x20008000-0x20ffffff: Reserved */ +#define SAM_INTSRAM1_BASE 0x21000000 /* 0x21000000-0x210007ff: HRAMC1 (see chip.h) */ + /* 0x21000800-0x21ffffff: Reserved */ +/* Peripherals Space */ + +#define SAM_PERIPHA_BASE 0x40000000 /* 0x40000000-0x4009ffff: Peripheral Bridge A */ +#define SAM_PERIPHB_BASE 0x400a0000 /* 0x400a0000-0x400affff: Peripheral Bridge B */ +#define SAM_AESA_BASE 0x400b0000 /* 0x400b0000-0x400b00ff: AESA */ + /* 0x400b0100-0x400dffff: Reserved */ +#define SAM_PERIPHC_BASE 0x400e0000 /* 0x400e0000-0x400effff: Peripheral Bridge C */ +#define SAM_PERIPHD_BASE 0x400e0000 /* 0x400f0000-0x400fffff: Peripheral Bridge D */ + /* 0x40100000-0x5fffffff: Reserved */ +/* Peripheral Bridge A */ + /* 0x40000000-0x40003fff: Reserved */ +#define SAM_I2SC_BASE 0x40004000 /* 0x40004000-0x40007fff: I2S Controller */ +#define SAM_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ + /* 0x4000c000-0x4000ffff: Reserved */ +#define SAM_TC0_BASE 0x40100000 /* 0x40100000-0x4013ffff: Timer Counter 0 */ +#define SAM_TC1_BASE 0x40140000 /* 0x40180000-0x4017ffff: Timer Counter 1 */ +#define SAM_TWIMS0_BASE 0x40180000 /* 0x40180000-0x401bffff: Two-wire Master/Slave Interface 0 */ +#define SAM_TWIMS1_BASE 0x401c0000 /* 0x401c0000-0x401fffff: Two-wire Master/Slave Interface 1 */ + /* 0x40020000-0x40023fff: Reserved */ +#define SAM_USARTN_BASE(n) (0x40024000+((n)<<14)) +#define SAM_USART0_BASE 0x40024000 /* 0x40024000-0x40027fff: USART0 */ +#define SAM_USART1_BASE 0x40028000 /* 0x40028000-0x4002bfff: USART1 */ +#define SAM_USART2_BASE 0x4002c000 /* 0x4002c000-0x4002ffff: USART2 */ +#define SAM_USART3_BASE 0x40030000 /* 0x40030000-0x40033fff: USART3 */ + /* 0x40034000-0x40037fff: Reserved */ +#define SAM_ADCIFE_BASE 0x40038000 /* 0x40038000-0x4003bfff: ADC controller interface */ +#define SAM_DACC_BASE 0x4003c000 /* 0x4003c000-0x4003ffff: DAC Controller */ +#define SAM_ACIF_BASE 0x40040000 /* 0x40040000-0x40043fff: Analog Comparator Interface */ + /* 0x40044000-0x4005ffff: Reserved */ +#define SAM_GLOC_BASE 0x40040000 /* 0x40060000-0x40063fff: GLOC */ +#define SAM_ABDACB_BASE 0x40040000 /* 0x40064000-0x40067fff: Audio Bitstream DAC */ +#define SAM_TRNG_BASE 0x40068000 /* 0x40064000-0x4006bfff: True Random Number Generator */ +#define SAM_PARC_BASE 0x4006c000 /* 0x4006c000-0x4006ffff: Parallel Capture */ +#define SAM_CATB_BASE 0x40070000 /* 0x4006c000-0x40073fff: Capacitive Touch Module B */ + /* 0x40074000-0x40077fff: Reserved */ +#define SAM_TWIM2_BASE 0x40078000 /* 0x40078000-0x4007bfff: Two-wire Master Interface 2 */ +#define SAM_TWIM3_BASE 0x4007c000 /* 0x4007c000-0x4007ffff: Two-wire Master Interface 3 */ +#define SAM_LCDCA_BASE 0x40080000 /* 0x40080000-0x40083fff: LCD Controller A */ + /* 0x40084000-0x4009ffff: Reserved */ +/* Peripheral Bridge B */ + +#define SAM_FLASHCALW_BASE 0x400a0000 /* 0x400a0000-0x400a03ff: FLASHCALW */ +#define SAM_PICOCACHE_BASE 0x400a0400 /* 0x400a0400-0x400a0fff: PICOCACHE */ +#define SAM_HMATRIX_BASE 0x400a1000 /* 0x400a1000-0x400a1fff: PICOCACHE */ +#define SAM_PDCA_BASE 0x400a2000 /* 0x400a2000-0x400a2fff: Peripheral DMA Controller */ +#define SAM_SMAP_BASE 0x400a3000 /* 0x400a3000-0x400a3fff: SMAP */ +#define SAM_CRCCU_BASE 0x400a4000 /* 0x400a4000-0x400a4fff: CRC Calculation Unit */ +#define SAM_USBC_BASE 0x400a5000 /* 0x400a5000-0x400a5fff: USB 2.0 Interface */ +#define SAM_PEVC_BASE 0x400a6000 /* 0x400a6000-0x400a63ff: Peripheral Event Controller */ + /* 0x400a6400-0x400affff: Reserved */ +/* Peripheral Bridge C */ + +#define SAM_PM_BASE 0x400e0000 /* 0x400e0000-0x400e073f: Power Manager */ +#define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIPID */ +#define SAM_SCIF_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: System Control Interface */ +#define SAM_FREQM_BASE 0x400e0c00 /* 0x400e0c00-0x400e0fff: Frequency Meter */ +#define SAM_GPIO_BASE 0x400e1000 /* 0x400e1000-0x400e17ff: GPIO */ + /* 0x400e1800-0x400effff: Reserved */ +/* Peripheral Bridge D */ + +#define SAM_BPM_BASE 0x400f0000 /* 0x400f0000-0x400f03ff: Backup Power Manager */ +#define SAM_BSCIF_BASE 0x400f0400 /* 0x400f0400-0x400f07ff: Backup System Control Interface */ +#define SAM_AST_BASE 0x400f0800 /* 0x400f0800-0x400f0bff: Asynchronous Timer */ +#define SAM_WDT_BASE 0x400f0c00 /* 0x400f0c00-0x400f0fff: Watchdog Timer */ +#define SAM_EIC_BASE 0x400f1000 /* 0x400f1000-0x400f13ff: External Interrupt Controller */ +#define SAM_PICOUART_BASE 0x400f1400 /* 0x400f1400-0x400f17ff: PICOUART */ + /* 0x400f1800-0x400fffff: Reserved */ +/* System Space */ + +#define SAM_ITM_BASE 0xe0000000 /* 0xe0000000-0xe0000fff: ITM */ +#define SAM_DWT_BASE 0xe0001000 /* 0xe0001000-0xe0001fff: DWT */ +#define SAM_FPB_BASE 0xe0002000 /* 0xe0002000-0xe0002fff: FPB */ + /* 0xe0003000-0xe000dfff: Reserved */ +#define SAM_SCS_BASE 0xe000e000 /* 0xe000e000-0xe000efff: SCS */ + /* 0xe000f000-0xe003ffff: Reserved */ +#define SAM_TPIU_BASE 0xe0040000 /* 0xe0040000-0xe0040fff: TPIU */ + /* 0xe0041000-0xe0041fff: Reserved */ +#define SAM_EXTPPB_BASE 0xe0042000 /* 0xe0042000-0xe00fefff: External PPB */ +#define SAM_ROMTAB_BASE 0xe00ff000 /* 0xe00ff000-0xe00fffff: ROM Table */ + /* 0xe0100000-0xffffffff: Reserved */ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h index ad4a6018c6..a1fe603823 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h @@ -41,12 +41,14 @@ ************************************************************************************/ #include -#include "chip.h" +#include #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_memorymap.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_memorymap.h" #else -# Unrecognized SAM architecture +# error Unrecognized SAM architecture #endif #endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_MEMORYMAP_H */ From ccadba524f6e5ff381a5b24397af7124e814866a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 3 Jun 2013 11:23:41 -0600 Subject: [PATCH 18/41] Add vector and chip cability definitions for the SAM4L family --- nuttx/ChangeLog | 4 + nuttx/arch/arm/include/sam34/chip.h | 148 +++++++++++++++++- nuttx/arch/arm/src/sam34/chip.h | 15 ++ nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h | 3 - nuttx/arch/arm/src/sam34/chip/sam4l_vectors.h | 136 ++++++++++++++++ nuttx/arch/arm/src/sam34/chip/sam_pinmap.h | 2 +- nuttx/arch/arm/src/sam34/sam_dmac.c | 20 +-- nuttx/arch/arm/src/sam34/sam_vectors.S | 4 + 8 files changed, 310 insertions(+), 22 deletions(-) create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_vectors.h diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 5de5652ae9..0ee3d7495c 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4873,3 +4873,7 @@ * arch/arm/include/sam34/sam4l_irq.h and arch/arm/src/sam34/chip/sam4l_memorymap.h: Add interrupt and memory map definitions for the AT91SAM4L (2013-6-3). + * arch/arm/src/sam34/chip/sam4l_vectors.h and arm/src/sam34/sam_vectors.S: + Add interrupt vector support for the SAM4L family (2013-6-3). + * arch/include/sam34/chip.h: Add chip definitions for the SAM4L + family (2013-6-3). diff --git a/nuttx/arch/arm/include/sam34/chip.h b/nuttx/arch/arm/include/sam34/chip.h index 9cc7d1b7c5..ce56fd41ed 100644 --- a/nuttx/arch/arm/include/sam34/chip.h +++ b/nuttx/arch/arm/include/sam34/chip.h @@ -48,20 +48,152 @@ /* Get customizations for each supported chip */ -#ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E +/* AT91SAM3U Family *****************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_AT91SAM3U4E) + +/* Internal memory */ + +# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */ +# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ +# define CONFIG_SAM34_SRAM1_SIZE (16*1024) /* 16Kb */ +# define CONFIG_SAM34_NFCSRAM_SIZE (4*1024) /* 4Kb */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 4 /* 4 DMA Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 1 /* One USB high speed device */ +# define SAM32_NUDPFS 0 /* No USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + +/* AT91SAM4L Family *****************************************************************/ +/* Sub-family differences: + * + * FEATURE ATSAM4LCxx ATSAM4LSxx + * ----------------------- ------------- ------------- + * SEGMENT LCD Yes No + * AESA Yes No + * USB Device + Host Device Only + * + * Note: The SEGMENT LCD capability varies with packaging. + * + * FEATURE ATSAM4Lx2x ATSAM4Lx4x + * ----------------------- ------------- ------------- + * FLASH 256KB 128KB + * SRAM 32KB 32KB + * + * Packaging differences: + * + * FEATURE ATSAM4LxxC ATSAM4LxxB ATSAM4LxxA + * ----------------------- ---------- ---------- ---------- + * Number of Pins 100 64 48 + * Max Frequency 48MHz 48MHz 48MHz + * SEGMENT LCD 4x40 4x23 4x13 + * GPIO 75 43 27 + * High-drive pins 6 3 1 + * External Interrupts 8+NMI 8+NMI 8+NMI + * TWI Masters 2 2 1 + * TWI Master/Slave 2 2 1 + * USART 4 4 3 + * PICOUART 1 1 1 + * Peripheral DMA Channels 16 16 16 + * Peripheral Even System 1 1 1 + * SPI 1 1 1 + * Asynchronous Timers 1 1 1 + * Timer/Counter Channels 6 3 3 + * Parallel Capture Inputs 8 8 8 + * Frequency Meter 1 1 1 + * Watchdog Timer 1 1 1 + * Power Manager 1 1 1 + * Glue Logic LUT 2 2 1 + * ADC 15-channel 7-channel 3-channel + * DAC 1-channel 1-channel 1-channel + * Analog Comparators 4 2 1 + * CATB Sensors 32 32 26 + * Audio Bitstream DAC 1 1 1 + * IIS Controller 1 1 1 + * Packages TQFP/VFBGA TQFP/QFN TQFP/QFN + */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LC2) + +/* Internal memory */ + +# define CONFIG_SAM34_FLASH_SIZE (128*1024) /* 128Kb */ +# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ +# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ +# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 1 /* 1 segment LCD interface */ +# define SAM32_NAESA 1 /* 1 advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LC4) + +/* Internal memory */ + +# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */ +# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ +# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ +# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 1 /* 1 segment LCD interface */ +# define SAM32_NAESA 1 /* 1 advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LS2) + /* Internal memory */ -# define CONFIG_SAM34_SRAM0_SIZE 0x00008000 /* 32Kb */ -# define CONFIG_SAM34_SRAM1_SIZE 0x00004000 /* 16Kb */ -# define CONFIG_SAM34_NFCSRAM_SIZE 0x00001000 /* 4Kb */ +# define CONFIG_SAM34_FLASH_SIZE (128*1024) /* 128Kb */ +# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ +# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ +# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LS4) + +/* Internal memory */ -/* DMA */ +# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */ +# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ +# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ +# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ -# define CONFIG_SAM34_NDMACHAN 4 /* 4 DMA Channels */ +/* Peripherals */ -/* Memory card interface */ +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ -# define CONFIG_SAM34_MCI2 1 #else # error "Unknown SAM3/4 chip type" #endif diff --git a/nuttx/arch/arm/src/sam34/chip.h b/nuttx/arch/arm/src/sam34/chip.h index cd5f76d89b..3c92f53ef6 100644 --- a/nuttx/arch/arm/src/sam34/chip.h +++ b/nuttx/arch/arm/src/sam34/chip.h @@ -49,6 +49,21 @@ #include #include "chip/sam_memorymap.h" +/* If the common ARMv7-M vector handling logic is used, then include the required + * vector definitions as well. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR +# if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "chip/sam3u_vectors.h" +# elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_vectors.h" +# include "chip/sam4l_memorymap.h" +# else +# error Unrecognized SAM architecture +# endif +#endif + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h b/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h index d1828ddd81..fd4c1a39e6 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h @@ -41,9 +41,6 @@ * (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h. * sam_vectors.S will defined the VECTOR in different ways in order to generate * the interrupt vectors and handlers in their final form. - * - * - * Vectors for low and medium density devices */ /* If the common ARMv7-M vector handling is used, then all it needs is the following diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_vectors.h b/nuttx/arch/arm/src/sam34/chip/sam4l_vectors.h new file mode 100644 index 0000000000..b4158965ff --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_vectors.h @@ -0,0 +1,136 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam4l_vectors.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ +/* This file is included by sam_vectors.S. It provides the macro VECTOR that + * supplies ach SAM3U vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/sam/sam4l_irq.h. + * sam_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 80 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 80 + +#else + VECTOR(sam_hflashc, SAM_IRQ_HFLASHC) /* Vector 16+0: Flash Controller */ + VECTOR(sam_pdca0, SAM_IRQ_PDCA0) /* Vector 16+1: Peripheral DMA Controller 0 */ + VECTOR(sam_pdca1, SAM_IRQ_PDCA1) /* Vector 16+2: Peripheral DMA Controller 1 */ + VECTOR(sam_pdca2, SAM_IRQ_PDCA2) /* Vector 16+3: Peripheral DMA Controller 2 */ + VECTOR(sam_pdca3, SAM_IRQ_PDCA3) /* Vector 16+4: Peripheral DMA Controller 3 */ + VECTOR(sam_pdca4, SAM_IRQ_PDCA4) /* Vector 16+5: Peripheral DMA Controller 4 */ + VECTOR(sam_pdca5, SAM_IRQ_PDCA5) /* Vector 16+6: Peripheral DMA Controller 5 */ + VECTOR(sam_pdca6, SAM_IRQ_PDCA6) /* Vector 16+7: Peripheral DMA Controller 6 */ + VECTOR(sam_pdca7, SAM_IRQ_PDCA7) /* Vector 16+8: Peripheral DMA Controller 7 */ + VECTOR(sam_pdca8, SAM_IRQ_PDCA8) /* Vector 16+9: Peripheral DMA Controller 8 */ + VECTOR(sam_pdca9, SAM_IRQ_PDCA9) /* Vector 16+10: Peripheral DMA Controller 9 */ + VECTOR(sam_pdca10, SAM_IRQ_PDCA10) /* Vector 16+11: Peripheral DMA Controller 10 */ + VECTOR(sam_pdca11, SAM_IRQ_PDCA11) /* Vector 16+12: Peripheral DMA Controller 11 */ + VECTOR(sam_pdca12, SAM_IRQ_PDCA12) /* Vector 16+13: Peripheral DMA Controller 12 */ + VECTOR(sam_pdca13, SAM_IRQ_PDCA13) /* Vector 16+14: Peripheral DMA Controller 13 */ + VECTOR(sam_pdca14, SAM_IRQ_PDCA14) /* Vector 16+15: Peripheral DMA Controller 14 */ + VECTOR(sam_pdca15, SAM_IRQ_PDCA15) /* Vector 16+16: Peripheral DMA Controller 15 */ + VECTOR(sam_crccu, SAM_IRQ_CRCCU) /* Vector 16+17: CRC Calculation Unit */ + VECTOR(sam_usbc, SAM_IRQ_USBC) /* Vector 16+18: USB 2.0 Interface */ + VECTOR(sam_pevc_tr, SAM_IRQ_PEVC_TR) /* Vector 16+19: Peripheral Event Controller TR */ + VECTOR(sam_pevc_ov, SAM_IRQ_PEVC_OV) /* Vector 16+20: Peripheral Event Controller OV */ + VECTOR(sam_aesa, SAM_IRQ_AESA) /* Vector 16+21: Advanced Encryption Standard */ + VECTOR(sam_pm, SAM_IRQ_PM) /* Vector 16+22: Power Manager */ + VECTOR(sam_scif, SAM_IRQ_SCIF) /* Vector 16+23: System Control Interface */ + VECTOR(sam_freqm, SAM_IRQ_FREQM) /* Vector 16+24: Frequency Meter */ + VECTOR(sam_gpio0, SAM_IRQ_GPIO0) /* Vector 16+25: General-Purpose Input/Output Controller 0 */ + VECTOR(sam_gpio1, SAM_IRQ_GPIO1) /* Vector 16+26: General-Purpose Input/Output Controller 1 */ + VECTOR(sam_gpio2, SAM_IRQ_GPIO2) /* Vector 16+27: General-Purpose Input/Output Controller 2 */ + VECTOR(sam_gpio3, SAM_IRQ_GPIO3) /* Vector 16+28: General-Purpose Input/Output Controller 3 */ + VECTOR(sam_gpio4, SAM_IRQ_GPIO4) /* Vector 16+29: General-Purpose Input/Output Controller 4 */ + VECTOR(sam_gpio5, SAM_IRQ_GPIO5) /* Vector 16+30: General-Purpose Input/Output Controller 5 */ + VECTOR(sam_gpio6, SAM_IRQ_GPIO6) /* Vector 16+31: General-Purpose Input/Output Controller 6 */ + VECTOR(sam_gpio7, SAM_IRQ_GPIO7) /* Vector 16+32: General-Purpose Input/Output Controller 7 */ + VECTOR(sam_gpio8, SAM_IRQ_GPIO8) /* Vector 16+33: General-Purpose Input/Output Controller 8 */ + VECTOR(sam_gpio9, SAM_IRQ_GPIO9) /* Vector 16+34: General-Purpose Input/Output Controller 9 */ + VECTOR(sam_gpio10, SAM_IRQ_GPIO10) /* Vector 16+35: General-Purpose Input/Output Controller 10 */ + VECTOR(sam_gpio11, SAM_IRQ_GPIO11) /* Vector 16+36: General-Purpose Input/Output Controller 11 */ + VECTOR(sam_bpm, SAM_IRQ_BPM) /* Vector 16+37: Backup Power Manager */ + VECTOR(sam_bscif, SAM_IRQ_BSCIF) /* Vector 16+38: Backup System Control Interface */ + VECTOR(sam_ast_alarm, SAM_IRQ_AST_ALARM) /* Vector 16+39: Asynchronous Timer ALARM */ + VECTOR(sam_ast_per, SAM_IRQ_AST_PER) /* Vector 16+40: Asynchronous Timer PER */ + VECTOR(sam_ast_ovf, SAM_IRQ_AST_OVF) /* Vector 16+41: Asynchronous Timer OVF */ + VECTOR(sam_ast_ready, SAM_IRQ_AST_READY) /* Vector 16+42: Asynchronous Timer READY */ + VECTOR(sam_ast_clkready, SAM_IRQ_AST_CLKREADY) /* Vector 16+43: Asynchronous Timer CLKREADY */ + VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+44: Watchdog Timer */ + VECTOR(sam_eic1, SAM_IRQ_EIC1) /* Vector 16+45: External Interrupt Controller 1 */ + VECTOR(sam_eic2, SAM_IRQ_EIC2) /* Vector 16+46: External Interrupt Controller 2 */ + VECTOR(sam_eic3, SAM_IRQ_EIC3) /* Vector 16+47: External Interrupt Controller 3 */ + VECTOR(sam_eic4, SAM_IRQ_EIC4) /* Vector 16+48: External Interrupt Controller 4 */ + VECTOR(sam_eic5, SAM_IRQ_EIC5) /* Vector 16+49: External Interrupt Controller 5 */ + VECTOR(sam_eic6, SAM_IRQ_EIC6) /* Vector 16+50: External Interrupt Controller 6 */ + VECTOR(sam_eic7, SAM_IRQ_EIC7) /* Vector 16+51: External Interrupt Controller 7 */ + VECTOR(sam_eic8, SAM_IRQ_EIC8) /* Vector 16+52: External Interrupt Controller 8 */ + VECTOR(sam_iisc, SAM_IRQ_IISC) /* Vector 16+53: Inter-IC Sound (I2S) Controller */ + VECTOR(sam_spi, SAM_IRQ_SPI) /* Vector 16+54: Serial Peripheral Interface */ + VECTOR(sam_tc00, SAM_IRQ_TC00) /* Vector 16+55: Timer/Counter 0 */ + VECTOR(sam_tc01, SAM_IRQ_TC01) /* Vector 16+56: Timer/Counter 1 */ + VECTOR(sam_tc02, SAM_IRQ_TC02) /* Vector 16+57: Timer/Counter 2 */ + VECTOR(sam_tc10, SAM_IRQ_TC10) /* Vector 16+58: Timer/Counter 10 */ + VECTOR(sam_tc11, SAM_IRQ_TC11) /* Vector 16+59: Timer/Counter 11 */ + VECTOR(sam_tc12, SAM_IRQ_TC12) /* Vector 16+60: Timer/Counter 12 */ + VECTOR(sam_twim0, SAM_IRQ_TWIM0) /* Vector 16+61: Two-wire Master Interface TWIM0 */ + VECTOR(sam_twis0, SAM_IRQ_TWIS0) /* Vector 16+62: Two-wire Slave Interface TWIS0 */ + VECTOR(sam_twim1, SAM_IRQ_TWIM1) /* Vector 16+63: Two-wire Master Interface TWIM1 */ + VECTOR(sam_twis1, SAM_IRQ_TWIS1) /* Vector 16+64: Two-wire Slave Interface TWIS1 */ + VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+65: USART0 */ + VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+66: USART1 */ + VECTOR(sam_usart2, SAM_IRQ_USART2) /* Vector 16+67: USART2 */ + VECTOR(sam_usart3, SAM_IRQ_USART3) /* Vector 16+68: USART3 */ + VECTOR(sam_adcife, SAM_IRQ_ADCIFE) /* Vector 16+69: ADC controller interface */ + VECTOR(sam_dacc, SAM_IRQ_DACC) /* Vector 16+70: DAC Controller */ + VECTOR(sam_acifc, SAM_IRQ_ACIFC) /* Vector 16+71: Analog Comparator Interface */ + VECTOR(sam_abdacb, SAM_IRQ_ABDACB) /* Vector 16+72: Audio Bitstream DAC */ + VECTOR(sam_trng, SAM_IRQ_TRNG) /* Vector 16+73: True Random Number Generator */ + VECTOR(sam_parc, SAM_IRQ_PARC) /* Vector 16+74: Parallel Capture */ + VECTOR(sam_catb, SAM_IRQ_CATB) /* Vector 16+75: Capacitive Touch Module B */ + VECTOR(sam_twim2, SAM_IRQ_TWIM2) /* Vector 16+77: Two-wire Master Interface */ + VECTOR(sam_twim3, SAM_IRQ_TWIM3) /* Vector 16+78: Two-wire Master Interface */ + VECTOR(sam_lcdca, SAM_IRQ_LCDCA) /* Vector 16+79: LCD Controller A */ +#endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h index 2adfac974f..6adb547bf7 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h @@ -46,7 +46,7 @@ #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_pinmap.h" #else -# Unrecognized SAM architecture +# error Unrecognized SAM architecture #endif #endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PINMAP_H */ diff --git a/nuttx/arch/arm/src/sam34/sam_dmac.c b/nuttx/arch/arm/src/sam34/sam_dmac.c index 75d6927542..b11199fb17 100644 --- a/nuttx/arch/arm/src/sam34/sam_dmac.c +++ b/nuttx/arch/arm/src/sam34/sam_dmac.c @@ -78,14 +78,14 @@ /* Check the number of link list descriptors to allocate */ #ifndef CONFIG_SAM34_NLLDESC -# define CONFIG_SAM34_NLLDESC CONFIG_SAM34_NDMACHAN +# define CONFIG_SAM34_NLLDESC SAM34_NDMACHAN #endif -#if CONFIG_SAM34_NLLDESC < CONFIG_SAM34_NDMACHAN -# warning "At least CONFIG_SAM34_NDMACHAN descriptors must be allocated" +#if CONFIG_SAM34_NLLDESC < SAM34_NDMACHAN +# warning "At least SAM34_NDMACHAN descriptors must be allocated" # undef CONFIG_SAM34_NLLDESC -# define CONFIG_SAM34_NLLDESC CONFIG_SAM34_NDMACHAN +# define CONFIG_SAM34_NLLDESC SAM34_NDMACHAN #endif /* Register values **********************************************************/ @@ -150,15 +150,15 @@ static struct dma_linklist_s g_linklist[CONFIG_SAM34_NLLDESC]; /* This array describes the state of each DMA */ -static struct sam_dma_s g_dma[CONFIG_SAM34_NDMACHAN] = +static struct sam_dma_s g_dma[SAM34_NDMACHAN] = { #ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E /* the AT91SAM3U4E has four DMA channels. The FIFOs for channels 0-2 are * 8 bytes in size; channel 3 is 32 bytes. */ -#if CONFIG_SAM34_NDMACHAN != 4 -# error "Logic here assumes CONFIG_SAM34_NDMACHAN is 4" +#if SAM34_NDMACHAN != 4 +# error "Logic here assumes SAM34_NDMACHAN is 4" #endif { @@ -1099,7 +1099,7 @@ static int sam_dmainterrupt(int irq, void *context) { /* Yes.. Check each bit to see which channel has interrupted */ - for (chndx = 0; chndx < CONFIG_SAM34_NDMACHAN; chndx++) + for (chndx = 0; chndx < SAM34_NDMACHAN; chndx++) { /* Are any interrupts pending for this channel? */ @@ -1185,7 +1185,7 @@ void weak_function up_dmainitialize(void) /* Initialize semaphores */ sem_init(&g_chsem, 0, 1); - sem_init(&g_dsem, 0, CONFIG_SAM34_NDMACHAN); + sem_init(&g_dsem, 0, SAM34_NDMACHAN); } /**************************************************************************** @@ -1224,7 +1224,7 @@ DMA_HANDLE sam_dmachannel(uint32_t dmach_flags) dmach = NULL; sam_takechsem(); - for (chndx = 0; chndx < CONFIG_SAM34_NDMACHAN; chndx++) + for (chndx = 0; chndx < SAM34_NDMACHAN; chndx++) { struct sam_dma_s *candidate = &g_dma[chndx]; if (!candidate->inuse && diff --git a/nuttx/arch/arm/src/sam34/sam_vectors.S b/nuttx/arch/arm/src/sam34/sam_vectors.S index a80df32632..007367857c 100644 --- a/nuttx/arch/arm/src/sam34/sam_vectors.S +++ b/nuttx/arch/arm/src/sam34/sam_vectors.S @@ -132,6 +132,8 @@ sam_vectors: #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_vectors.h" #else # Unrecognized SAM architecture #endif @@ -165,6 +167,8 @@ handlers: #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_vectors.h" #else # Unrecognized SAM architecture #endif From 5cc921b5ae92b3b354b3e727743e5393607f624c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 3 Jun 2013 15:11:56 -0600 Subject: [PATCH 19/41] Add a skeleton configuration that will eventually support the SAM4L Xplained Pro board --- nuttx/ChangeLog | 2 + nuttx/Documentation/README.html | 2 + nuttx/README.txt | 2 + nuttx/arch/arm/Kconfig | 8 +- nuttx/arch/arm/include/sam34/chip.h | 51 +- nuttx/arch/arm/src/lm/Kconfig | 1 + nuttx/arch/arm/src/sam34/Kconfig | 119 ++++ nuttx/arch/arm/src/sam34/chip/sam_chipid.h | 35 +- nuttx/arch/arm/src/stm32/Kconfig | 24 + nuttx/configs/Kconfig | 13 + nuttx/configs/README.txt | 3 + nuttx/configs/sam4l-xplained/Kconfig | 7 + nuttx/configs/sam4l-xplained/README.txt | 386 ++++++++++++ nuttx/configs/sam4l-xplained/include/board.h | 236 +++++++ nuttx/configs/sam4l-xplained/ostest/Make.defs | 109 ++++ nuttx/configs/sam4l-xplained/ostest/defconfig | 581 ++++++++++++++++++ nuttx/configs/sam4l-xplained/ostest/setenv.sh | 63 ++ .../configs/sam4l-xplained/scripts/ld.script | 107 ++++ nuttx/configs/sam4l-xplained/src/.gitignore | 2 + nuttx/configs/sam4l-xplained/src/Makefile | 86 +++ .../sam4l-xplained/src/sam4l-xplained.h | 140 +++++ .../configs/sam4l-xplained/src/sam_autoleds.c | 182 ++++++ nuttx/configs/sam4l-xplained/src/sam_boot.c | 86 +++ .../configs/sam4l-xplained/src/sam_buttons.c | 155 +++++ nuttx/configs/sam4l-xplained/src/sam_spi.c | 239 +++++++ .../configs/stm32f4discovery/include/board.h | 16 +- 26 files changed, 2638 insertions(+), 17 deletions(-) create mode 100644 nuttx/configs/sam4l-xplained/Kconfig create mode 100644 nuttx/configs/sam4l-xplained/README.txt create mode 100644 nuttx/configs/sam4l-xplained/include/board.h create mode 100644 nuttx/configs/sam4l-xplained/ostest/Make.defs create mode 100644 nuttx/configs/sam4l-xplained/ostest/defconfig create mode 100755 nuttx/configs/sam4l-xplained/ostest/setenv.sh create mode 100755 nuttx/configs/sam4l-xplained/scripts/ld.script create mode 100644 nuttx/configs/sam4l-xplained/src/.gitignore create mode 100644 nuttx/configs/sam4l-xplained/src/Makefile create mode 100644 nuttx/configs/sam4l-xplained/src/sam4l-xplained.h create mode 100644 nuttx/configs/sam4l-xplained/src/sam_autoleds.c create mode 100644 nuttx/configs/sam4l-xplained/src/sam_boot.c create mode 100644 nuttx/configs/sam4l-xplained/src/sam_buttons.c create mode 100644 nuttx/configs/sam4l-xplained/src/sam_spi.c diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 0ee3d7495c..5057d41df4 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4877,3 +4877,5 @@ Add interrupt vector support for the SAM4L family (2013-6-3). * arch/include/sam34/chip.h: Add chip definitions for the SAM4L family (2013-6-3). + * configs/sam4l-xplained: A partial configuration that will (eventually) + support the SAM4L Xplained Pro developement board (2013-6-3). diff --git a/nuttx/Documentation/README.html b/nuttx/Documentation/README.html index e82dd2210a..7161abf070 100644 --- a/nuttx/Documentation/README.html +++ b/nuttx/Documentation/README.html @@ -184,6 +184,8 @@

NuttX README Files

| | | `- README.txt> | | |- sam3u-ek/ | | | `- README.txt + | | |- sam4l-xplained/ + | | | `- README.txt | | |- shenzhou/ | | | `- README.txt | | |- sim/ diff --git a/nuttx/README.txt b/nuttx/README.txt index 4b0c742c6f..142ca872ac 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -1112,6 +1112,8 @@ nuttx | | `- README.txt | |- sam3u-ek/ | | `- README.txt + | |- sam4l-xplained/ + | | `- README.txt | |- sim/ | | |- include/README.txt | | |- src/README.txt diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig index fdd120779b..92a4275ce0 100644 --- a/nuttx/arch/arm/Kconfig +++ b/nuttx/arch/arm/Kconfig @@ -46,6 +46,7 @@ config ARCH_CHIP_KINETIS bool "Freescale Kinetis" select ARCH_CORTEXM4 select ARCH_HAVE_MPU + select ARCH_HAVE_FPU select ARCH_HAVE_RAMFUNCS select ARCH_RAMFUNCS ---help--- @@ -100,6 +101,7 @@ config ARCH_CHIP_LPC43XX select ARCH_HAVE_CMNVECTOR select ARMV7M_CMNVECTOR select ARCH_HAVE_MPU + select ARCH_HAVE_FPU ---help--- NPX LPC43XX architectures (ARM Cortex-M4). @@ -205,10 +207,14 @@ config ARMV7M_CMNVECTOR logic or the common vector logic. This applies only to ARMv7-M architectures. +config ARCH_HAVE_FPU + bool + default n + config ARCH_FPU bool "FPU support" default y - depends on ARCH_CORTEXM4 + depends on ARCH_HAVE_FPU ---help--- Build in support for the ARM Cortex-M4 Floating Point Unit (FPU). Check your chip specifications first; not all Cortex-M4 chips support the FPU. diff --git a/nuttx/arch/arm/include/sam34/chip.h b/nuttx/arch/arm/include/sam34/chip.h index ce56fd41ed..e5c5fa6748 100644 --- a/nuttx/arch/arm/include/sam34/chip.h +++ b/nuttx/arch/arm/include/sam34/chip.h @@ -118,7 +118,8 @@ * Packages TQFP/VFBGA TQFP/QFN TQFP/QFN */ -#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LC2) +#elif defined(CONFIG_ARCH_CHIP_ATSAM4LC2C) || defined (CONFIG_ARCH_CHIP_ATSAM4LC2B) || \ + defined(CONFIG_ARCH_CHIP_ATSAM4LC2A) /* Internal memory */ @@ -137,7 +138,8 @@ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ -#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LC4) +#elif defined(CONFIG_ARCH_CHIP_ATSAM4LC4C) || defined (CONFIG_ARCH_CHIP_ATSAM4LC4B) || \ + defined(CONFIG_ARCH_CHIP_ATSAM4LC4A) /* Internal memory */ @@ -156,7 +158,8 @@ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ -#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LS2) +#elif defined(CONFIG_ARCH_CHIP_ATSAM4LS2C) || defined (CONFIG_ARCH_CHIP_ATSAM4LS2B) || \ + defined(CONFIG_ARCH_CHIP_ATSAM4LS2A) /* Internal memory */ @@ -175,7 +178,8 @@ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ -#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LS4) +#elif defined(CONFIG_ARCH_CHIP_ATSAM4LS4C) || defined (CONFIG_ARCH_CHIP_ATSAM4LS4B) || \ + defined(CONFIG_ARCH_CHIP_ATSAM4LS4A) /* Internal memory */ @@ -194,6 +198,45 @@ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ +/* AT91SAM4S Family *****************************************************************/ +/* + * FEATURE SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B + * Flash 2x1MB 2x1MB 2x512KB 1x1MB 1x1MB 1x1MB 1x1MB 1x1MB 1x512KB 1x512KB + * SRAM 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB + * HCACHE 2KB 2KB 2KB 2KB 2KB 2KB - - - - + * Pins 100 64 100 64 100 64 100 64 100 64 + * No. PIOs 79 47 79 47 79 47 79 47 79 47 + * Ext. BUS Yes No Yes No Yes No Yes No Yes No + * 12-bit ADC 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch + * 12-bit DAC 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch + * Timer Counter 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch + * PDC 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch + * USART 2 2 2 2 2 2 2 2 2 2 + * UART 2 2 2 2 2 2 2 2 2 2 + * HSMCI Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes + */ + +#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32C) +# error To be provided +#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32B) +# error To be provided +#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD16C) +# error To be provided +#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD16B) +# error To be provided +#elif defined(CONFIG_ARCH_CHIP_ATSAM4SA16C) +# error To be provided +#elif defined(CONFIG_ARCH_CHIP_ATSAM4SA16B) +# error To be provided +#elif defined(CONFIG_ARCH_CHIP_ATSAM4S16C) +# error To be provided +#elif defined(CONFIG_ARCH_CHIP_ATSAM4S16B) +# error To be provided +#elif defined(CONFIG_ARCH_CHIP_ATSAM4S8C) +# error To be provided +#elif defined(CONFIG_ARCH_CHIP_ATSAM4S8B) +# error To be provided + #else # error "Unknown SAM3/4 chip type" #endif diff --git a/nuttx/arch/arm/src/lm/Kconfig b/nuttx/arch/arm/src/lm/Kconfig index 061fab52a7..c1266c4739 100644 --- a/nuttx/arch/arm/src/lm/Kconfig +++ b/nuttx/arch/arm/src/lm/Kconfig @@ -40,6 +40,7 @@ config ARCH_CHIP_LM4F120 bool "LM4F120" select ARCH_CORTEXM4 select ARCH_CHIP_LM4F + select ARCH_HAVE_FPU endchoice diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig index 9cd9a019ac..3991798a70 100644 --- a/nuttx/arch/arm/src/sam34/Kconfig +++ b/nuttx/arch/arm/src/sam34/Kconfig @@ -15,10 +15,129 @@ config ARCH_CHIP_AT91SAM3U4E select ARCH_CORTEXM3 select ARCH_CHIP_SAM3U +config ARCH_CHIP_SAM34_NDMACHANC2C + bool "ATSAM4LC2C" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LC2B + bool "ATSAM4LC2B" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LC2A + bool "ATSAM4LC2A" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LC4C + bool "ATSAM4LC4C" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LC4B + bool "ATSAM4LC4B" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LC4A + bool "ATSAM4LC4A" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LS2C + bool "ATSAM4LS2C" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LS2B + bool "ATSAM4LS2B" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LS2A + bool "ATSAM4LS2A" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LS4C + bool "ATSAM4LS4C" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LS4B + bool "ATSAM4LS4B" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config ARCH_CHIP_ATSAM4LS4A + bool "ATSAM4LS4A" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4L + +config CONFIG_ARCH_CHIP_ATSAM4SD32C + bool "ATSAM4SD32C" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4S + +config CONFIG_ARCH_CHIP_ATSAM4SD32B + bool "ATSAM4SD32B" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4S + +config CONFIG_ARCH_CHIP_ATSAM4SD16C + bool "ATSAM4SD16C" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4S + +config CONFIG_ARCH_CHIP_ATSAM4SD16B + bool "ATSAM4SD16B" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4S + +config CONFIG_ARCH_CHIP_ATSAM4SA16C + bool "ATSAM4SA16C" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4S + +config CONFIG_ARCH_CHIP_ATSAM4SA16B + bool "ATSAM4SA16B" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4S + +config CONFIG_ARCH_CHIP_ATSAM4S16C + bool "ATSAM4S16C" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4S + +config CONFIG_ARCH_CHIP_ATSAM4S16B + bool "ATSAM4S16B" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4S + +config CONFIG_ARCH_CHIP_ATSAM4S8C + bool "ATSAM4S8C" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4S + +config CONFIG_ARCH_CHIP_ATSAM4S8B + bool "ATSAM4S8B" + select ARCH_CORTEXM4 + select ARCH_CHIP_SAM4S + endchoice config ARCH_CHIP_SAM3U bool + default n + +config ARCH_CHIP_SAM4L + bool + default n + +config ARCH_CHIP_SAM4S + bool + default n menu "AT91SAM3 Peripheral Support" diff --git a/nuttx/arch/arm/src/sam34/chip/sam_chipid.h b/nuttx/arch/arm/src/sam34/chip/sam_chipid.h index 1c1e972b71..c98130efec 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_chipid.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_chipid.h @@ -51,13 +51,13 @@ /* CHIPID register offsets **************************************************************/ -#define SAM_CHIPID_CIDR 0x00 /* Chip ID Register */ -#define SAM_CHIPID_EXID 0x04 /* Chip ID Extension Register */ +#define SAM_CHIPID_CIDR 0x00 /* Chip ID Register */ +#define SAM_CHIPID_EXID 0x04 /* Chip ID Extension Register */ /* CHIPID register adresses *************************************************************/ -#define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR) -#define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID) +#define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR) +#define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID) /* CHIPID register bit definitions ******************************************************/ @@ -70,6 +70,8 @@ # define CHIPID_CIDR_EPROC_CORTEXM3 (3 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M3 */ # define CHIPID_CIDR_EPROC_ARM920T (4 << CHIPID_CIDR_EPROC_SHIFT) /* ARM920T */ # define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */ +# define CHIPID_CIDR_EPROC_CORTEXA5 (6 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-A5 */ +# define CHIPID_CIDR_EPROC_CORTEXM4 (7 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M4 */ #define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */ #define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) # define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ @@ -101,6 +103,7 @@ # define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */ # define CHIPID_CIDR_SRAMSIZ_6KB (3 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 6K bytes */ # define CHIPID_CIDR_SRAMSIZ_112KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 112K bytes */ +# define CHIPID_CIDR_SRAMSIZ_24KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 24K bytes */ # define CHIPID_CIDR_SRAMSIZ_4KB (5 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 4K bytes */ # define CHIPID_CIDR_SRAMSIZ_80KB (6 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 80K bytes */ # define CHIPID_CIDR_SRAMSIZ_160KB (7 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 160K bytes */ @@ -142,6 +145,13 @@ # define CHIPID_CIDR_ARCH_SAM3SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxB Series (64-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxC Series (100-pin version) */ # define CHIPID_CIDR_ARCH_AT91X92 (0x92 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x92 Series */ +# define CHIPID_CIDR_ARCH_SAM3NXA (0x93 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxA Series (48-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3NXB (0x94 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3NxC (0x95 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3NXC (0x99 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxB SAM3SDxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3SDXC (0x9a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM5A (0xa5 << CHIPID_CIDR_ARCH_SHIFT) /* SAM5A */ +# define CHIPID_CIDR_ARCH_SAM4L (0xb0 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4Lxx Series */ # define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ #define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ #define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT) @@ -152,6 +162,23 @@ # define CHIPID_CIDR_NVPTYP REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ #define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ +/* Chip ID Extension Register */ + +#ifdef CONFIG_ARCH_CHIP_SAM4L +# define CHIPID_EXID_AES (1 << 0) /* Bit 0: AES Option */ +# define CHIPID_EXID_USB (1 << 1) /* Bit 1: USB Configuration */ +# define CHIPID_EXID_USBFULL (1 << 2) /* Bit 2: USB Option */ +# define CHIPID_EXID_LCD (1 << 3) /* Bit 3: LCD Option */ +# define CHIPID_EXID_PACKAGE_SHIFT (24) /* Bits 24-26: Package Type */ +# define CHIPID_EXID_PACKAGE_MASK (7 << CHIPID_EXID_PACKAGE_SHIFT) +# define CHIPID_EXID_PACKAGE_24PIN (0 << CHIPID_EXID_PACKAGE_SHIFT) /* 24-pin package */ +# define CHIPID_EXID_PACKAGE_32PIN (1 << CHIPID_EXID_PACKAGE_SHIFT) /* 32-pin package */ +# define CHIPID_EXID_PACKAGE_48PIN (2 << CHIPID_EXID_PACKAGE_SHIFT) /* 48-pin package */ +# define CHIPID_EXID_PACKAGE_64PIN (3 << CHIPID_EXID_PACKAGE_SHIFT) /* 64-pin package */ +# define CHIPID_EXID_PACKAGE_100PIN (4 << CHIPID_EXID_PACKAGE_SHIFT) /* 100-pin package */ +# define CHIPID_EXID_PACKAGE_144PIN (5 << CHIPID_EXID_PACKAGE_SHIFT) /* 144-pin package */ +#endif + /**************************************************************************************** * Public Types ****************************************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig index 5eee354b97..458190745b 100644 --- a/nuttx/arch/arm/src/stm32/Kconfig +++ b/nuttx/arch/arm/src/stm32/Kconfig @@ -304,124 +304,148 @@ config ARCH_CHIP_STM32F302CB bool "STM32F302CB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F302CC bool "STM32F302CC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F302RB bool "STM32F302RB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F302RC bool "STM32F302RC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F302VB bool "STM32F302VB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F302VC bool "STM32F302VC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F303CB bool "STM32F303CB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F303CC bool "STM32F303CC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F303RB bool "STM32F303RB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F303RC bool "STM32F303RC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F303VB bool "STM32F303VB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F303VC bool "STM32F303VC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F405RG bool "STM32F405RG" select ARCH_CORTEXM4 select STM32_STM32F40XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F405VG bool "STM32F405VG" select ARCH_CORTEXM4 select STM32_STM32F40XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F405ZG bool "STM32F405ZG" select ARCH_CORTEXM4 select STM32_STM32F40XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F407VE bool "STM32F407VE" select ARCH_CORTEXM4 select STM32_STM32F40XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F407VG bool "STM32F407VG" select ARCH_CORTEXM4 select STM32_STM32F40XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F407ZE bool "STM32F407ZE" select ARCH_CORTEXM4 select STM32_STM32F40XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F407ZG bool "STM32F407ZG" select ARCH_CORTEXM4 select STM32_STM32F40XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F407IE bool "STM32F407IE" select ARCH_CORTEXM4 select STM32_STM32F40XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F407IG bool "STM32F407IG" select ARCH_CORTEXM4 select STM32_STM32F40XX + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F427V bool "STM32F427V" select ARCH_CORTEXM4 select STM32_STM32F40XX select STM32_STM32F427 + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F427Z bool "STM32F427Z" select ARCH_CORTEXM4 select STM32_STM32F40XX select STM32_STM32F427 + select ARCH_HAVE_FPU config ARCH_CHIP_STM32F427I bool "STM32F427I" select ARCH_CORTEXM4 select STM32_STM32F40XX select STM32_STM32F427 + select ARCH_HAVE_FPU endchoice diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig index f7ee6d9c0f..e500819bcc 100644 --- a/nuttx/configs/Kconfig +++ b/nuttx/configs/Kconfig @@ -473,6 +473,15 @@ config ARCH_BOARD_SAM3UEK ---help--- The port of NuttX to the Atmel SAM3U-EK development board. +config ARCH_BOARD_SAM4L_XPLAINED + bool "Atmel SAM4L-Xplained Pro development board" + depends on ARCH_CHIP_ATSAM4LC4C + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + The port of NuttX to the Atmel SAM4L-Xplained Pro development board. + config ARCH_BOARD_SHENZHOU bool "Shenzhou STM32F107 board" depends on ARCH_CHIP_STM32F107VC @@ -772,6 +781,7 @@ config ARCH_BOARD default "qemu-i486" if ARCH_BOARD_QEMU_I486 default "rgmp" if ARCH_BOARD_RGMP default "sam3u-ek" if ARCH_BOARD_SAM3UEK + default "sam4l-xplained" if ARCH_BOARD_SAM4L_XPLAINED default "shenzhou" if ARCH_BOARD_SHENZHOU default "skp16c26" if ARCH_BOARD_SKP16C26 default "stm32_tiny" if ARCH_BOARD_STM32_TINY @@ -992,6 +1002,9 @@ endif if ARCH_BOARD_SAM3UEK source "configs/sam3u-ek/Kconfig" endif +if ARCH_BOARD_SAM4L_XPLAINED +source "configs/sam4l-xplained/Kconfig" +endif if ARCH_BOARD_SHENZHOU source "configs/shenzhou/Kconfig" endif diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index af50535b88..33b6c217b4 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -1962,6 +1962,9 @@ configs/rgmp configs/sam3u-ek The port of NuttX to the Atmel SAM3U-EK development board. +configs/sam4l-xplained + The port of NuttX to the Atmel SAM4L-Xplained development board. + configs/sim A user-mode port of NuttX to the x86 Linux platform is available. The purpose of this port is primarily to support OS feature development. diff --git a/nuttx/configs/sam4l-xplained/Kconfig b/nuttx/configs/sam4l-xplained/Kconfig new file mode 100644 index 0000000000..daae10472d --- /dev/null +++ b/nuttx/configs/sam4l-xplained/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_SAM4L_XPLAINED +endif diff --git a/nuttx/configs/sam4l-xplained/README.txt b/nuttx/configs/sam4l-xplained/README.txt new file mode 100644 index 0000000000..ca5ecf2f9e --- /dev/null +++ b/nuttx/configs/sam4l-xplained/README.txt @@ -0,0 +1,386 @@ +README +^^^^^^ + +This README discusses issues unique to NuttX configurations for the +Atmel SAM4L Xplained Pro development board. This board features the +ATSAM4LC4C MCU + +Contents +^^^^^^^^ + + - Development Environment + - GNU Toolchain Options + - IDEs + - NuttX EABI "buildroot" Toolchain + - NuttX OABI "buildroot" Toolchain + - NXFLAT Toolchain + - LEDs + - SAM4L Xplained Pro-specific Configuration Options + - Configurations + +Development Environment +^^^^^^^^^^^^^^^^^^^^^^^ + + Either Linux or Cygwin on Windows can be used for the development environment. + The source has been built only using the GNU toolchain (see below). Other + toolchains will likely cause problems. Testing was performed using the Cygwin + environment. + +GNU Toolchain Options +^^^^^^^^^^^^^^^^^^^^^ + + The NuttX make system has been modified to support the following different + toolchain options. + + 1. The CodeSourcery GNU toolchain, + 2. The devkitARM GNU toolchain, ok + 4. The NuttX buildroot Toolchain (see below). + + All testing has been conducted using the NuttX buildroot toolchain. However, + the make system is setup to default to use the devkitARM toolchain. To use + the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to + add one of the following configuration options to your .config (or defconfig) + file: + + CONFIG_SAM34_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_SAM34_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_SAM34_DEVKITARM=y : devkitARM under Windows + CONFIG_SAM34_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + + If you are not using CONFIG_SAM34_BUILDROOT, then you may also have to modify + the PATH in the setenv.h file if your make cannot find the tools. + + NOTE: the CodeSourcery (for Windows), devkitARM, and Raisonance toolchains are + Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot + toolchains are Cygwin and/or Linux native toolchains. There are several limitations + to using a Windows based toolchain in a Cygwin environment. The three biggest are: + + 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are + performed automatically in the Cygwin makefiles using the 'cygpath' utility + but you might easily find some new path problems. If so, check out 'cygpath -w' + + 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links + are used in Nuttx (e.g., include/arch). The make system works around these + problems for the Windows tools by copying directories instead of linking them. + But this can also cause some confusion for you: For example, you may edit + a file in a "linked" directory and find that your changes had no effect. + That is because you are building the copy of the file in the "fake" symbolic + directory. If you use a Windows toolchain, you should get in the habit of + making like this: + + make clean_context all + + An alias in your .bashrc file might make that less painful. + + 3. Dependencies are not made when using Windows versions of the GCC. This is + because the dependencies are generated using Windows pathes which do not + work with the Cygwin make. + + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + + NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization + level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with + -Os. + + NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that + the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM + path or will get the wrong version of make. + +IDEs +^^^^ + + NuttX is built using command-line make. It can be used with an IDE, but some + effort will be required to create the project (There is a simple RIDE project + in the RIDE subdirectory). + + Makefile Build + -------------- + Under Eclipse, it is pretty easy to set up an "empty makefile project" and + simply use the NuttX makefile to build the system. That is almost for free + under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty + makefile project in order to work with Windows (Google for "Eclipse Cygwin" - + there is a lot of help on the internet). + + Native Build + ------------ + Here are a few tips before you start that effort: + + 1) Select the toolchain that you will be using in your .config file + 2) Start the NuttX build at least one time from the Cygwin command line + before trying to create your project. This is necessary to create + certain auto-generated files and directories that will be needed. + 3) Set up include pathes: You will need include/, arch/arm/src/sam34, + arch/arm/src/common, arch/arm/src/armv7-m, and sched/. + 4) All assembly files need to have the definition option -D __ASSEMBLY__ + on the command line. + + Startup files will probably cause you some headaches. The NuttX startup file + is arch/arm/src/sam34/sam_vectors.S. You may need to build NuttX + one time from the Cygwin command line in order to obtain the pre-built + startup object needed by RIDE. + +NuttX EABI "buildroot" Toolchain +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + A GNU GCC-based toolchain is assumed. The files */setenv.sh should + be modified to point to the correct path to the Cortex-M3 GCC toolchain (if + different from the default in your PATH variable). + + If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX + SourceForge download site (https://sourceforge.net/projects/nuttx/files/buildroot/). + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in /nuttx. + + cd tools + ./configure.shsam4l-xplained/ + + 2. Download the latest buildroot package into + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename /buildroot-x.y.z to /buildroot. + + 4. cd /buildroot + + 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly built binaries. + + See the file configs/README.txt in the buildroot source tree. That has more + details PLUS some special instructions that you will need to follow if you are + building a Cortex-M3 toolchain for Cygwin under Windows. + + NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the + the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for + more information about this problem. If you plan to use NXFLAT, please do not + use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. + See instructions below. + +NuttX OABI "buildroot" Toolchain +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + The older, OABI buildroot toolchain is also available. To use the OABI + toolchain: + + 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 + configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI + configuration such as cortexm3-defconfig-4.3.3 + + 2. Modify the Make.defs file to use the OABI conventions: + + +CROSSDEV = arm-nuttx-elf- + +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft + +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections + -CROSSDEV = arm-nuttx-eabi- + -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft + -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections + +NXFLAT Toolchain +^^^^^^^^^^^^^^^^ + + If you are *not* using the NuttX buildroot toolchain and you want to use + the NXFLAT tools, then you will still have to build a portion of the buildroot + tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can + be downloaded from the NuttX SourceForge download site + (https://sourceforge.net/projects/nuttx/files/). + + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in /nuttx. + + cd tools + ./configure.sh lpcxpresso-lpc1768/ + + 2. Download the latest buildroot package into + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename /buildroot-x.y.z to /buildroot. + + 4. cd /buildroot + + 5. cp configs/cortexm3-defconfig-nxflat .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly builtNXFLAT binaries. + +LEDs +^^^^ + There are three LEDs on board the SAM4L Xplained Pro board: The EDBG + controls two of the LEDs, a power LED and a status LED. There is only + one user controllable LED, a yellow LED labeled LED0 near the SAM4L USB + connector. + + This LED is controlled by PC07 and LED0 can be activated by driving the + PC07 to GND. + + When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + control LED0 as follows: + + SYMBOL Meaning LED0 + ------------------- ----------------------- ------ + LED_STARTED NuttX has been started OFF + LED_HEAPALLOCATE Heap has been allocated OFF + LED_IRQSENABLED Interrupts enabled OFF + LED_STACKCREATED Idle stack created ON + LED_INIRQ In an interrupt N/C + LED_SIGNAL In a signal handler N/C + LED_ASSERTION An assertion failed N/C + LED_PANIC The system has crashed FLASH + + Thus is LED0 is statically on, NuttX has successfully booted and is, + apparently, running normmally. If LED0 is flashing at approximately + 2Hz, then a fatal error has been detected and the system has halted. + +SAM4L Xplained Pro-specific Configuration Options +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + CONFIG_ARCH - Identifies the arch/ subdirectory. This should + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM3=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP="sam34" + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_SAM34 + CONFIG_ARCH_CHIP_SAM3U + CONFIG_ARCH_CHIP_AT91SAM3U4 + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD=sam4l-xplained (for the SAM4L Xplained Pro development board) + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_SAM4L_XPLAINED=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case): + + CONFIG_DRAM_SIZE=0x0000c000 (48Kb) + + CONFIG_DRAM_START - The start address of installed DRAM + + CONFIG_DRAM_START=0x20000000 + + CONFIG_ARCH_IRQPRIO - The SAM3UF103Z supports interrupt prioritization + + CONFIG_ARCH_IRQPRIO=y + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibratre + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + + CONFIG_SAM34_DMA + CONFIG_SAM34_HSMCI + CONFIG_SAM34_NAND + CONFIG_SAM34_SPI + CONFIG_SAM34_UART + CONFIG_SAM34_USART0 + CONFIG_SAM34_USART1 + CONFIG_SAM34_USART2 + CONFIG_SAM34_USART3 + + Some subsystems can be configured to operate in different ways. The drivers + need to know how to configure the subsystem. + + CONFIG_GPIOA_IRQ + CONFIG_GPIOB_IRQ + CONFIG_GPIOC_IRQ + CONFIG_USART0_ISUART + CONFIG_USART1_ISUART + CONFIG_USART2_ISUART + CONFIG_USART3_ISUART + + AT91SAM3U specific device driver settings + + CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=0,1,2,3) or UART + m (m=4,5) for the console and ttys0 (default is the USART1). + CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be + CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8. + CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + CONFIG_U[S]ARTn_2STOP - Two stop bits + + LCD Options. Other than the standard LCD configuration options + (see configs/README.txt), the SAM4L Xplained Pro driver also supports: + + CONFIG_LCD_PORTRAIT - Present the display in the standard 240x320 + "Portrait" orientation. Default: The display is rotated to + support a 320x240 "Landscape" orientation. + +Configurations +^^^^^^^^^^^^^^ + +Each SAM4L Xplained Pro configuration is maintained in a sub-directory and +can be selected as follow: + + cd tools + ./configure.shsam4l-xplained/ + cd - + . ./setenv.sh + +Before sourcing the setenv.sh file above, you should examine it and perform +edits as necessary so that BUILDROOT_BIN is the correct path to the directory +than holds your toolchain binaries. + +And then build NuttX by simply typing the following. At the conclusion of +the make, the nuttx binary will reside in an ELF file called, simply, nuttx. + + make + +The that is provided above as an argument to the tools/configure.sh +must be is one of the following: + + ostest: + This configuration directory, performs a simple OS test using + examples/ostest. diff --git a/nuttx/configs/sam4l-xplained/include/board.h b/nuttx/configs/sam4l-xplained/include/board.h new file mode 100644 index 0000000000..3c8cb82e3c --- /dev/null +++ b/nuttx/configs/sam4l-xplained/include/board.h @@ -0,0 +1,236 @@ +/************************************************************************************ + * configs/sam4l-xplained/include/board.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAM4L_XPLAINED_INCLUDE_BOARD_H +#define __CONFIGS_SAM4L_XPLAINED_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# ifdef CONFIG_GPIO_IRQ +# include +# endif +#endif + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* After power-on reset, the sam3u device is running on a 4MHz internal RC. These + * definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=48MHz. + */ + +/* Main oscillator register settings */ + +#define BOARD_CKGR_MOR_MOSCXTST (63 << CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ + +/* PLLA configuration */ + +#define BOARD_CKGR_PLLAR_MULA (7 << CKGR_PLLAR_MULA_SHIFT) +#define BOARD_CKGR_PLLAR_STMODE CKGR_PLLAR_STMODE_FAST +#define BOARD_CKGR_PLLAR_PLLACOUNT (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) +#define BOARD_CKGR_PLLAR_DIVA CKGR_PLLAR_DIVA_BYPASS + +/* PMC master clock register settings */ + +#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA +#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2 + +/* USB UTMI PLL start-up time */ + +#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << CKGR_UCKR_UPLLCOUNT_SHIFT) + +/* Resulting frequencies */ + +#define SAM_MAINOSC_FREQUENCY (12000000) +#define SAM_MCK_FREQUENCY (48000000) +#define SAM_PLLA_FREQUENCY (96000000) +#define SAM_CPU_FREQUENCY (48000000) + +/* HSMCI clocking + * + * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + * divided by (2*(CLKDIV+1)). + * + * MCI_SPEED = MCK / (2*(CLKDIV+1)) + * CLKDIV = MCI / MCI_SPEED / 2 - 1 + */ + +/* MCK = 48MHz, CLKDIV = 59, MCI_SPEED = 48MHz / 2 * (59+1) = 400 KHz */ + +#define HSMCI_INIT_CLKDIV (59 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 48MHz, CLKDIV = 1, MCI_SPEED = 48MHz / 2 * (1+1) = 12 MHz */ + +#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 48MHz, CLKDIV = 0, MCI_SPEED = 48MHz / 2 * (0+1) = 24 MHz */ + +#define HSMCI_SDXFR_CLKDIV (0 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV + +/* LED definitions ******************************************************************/ +/* There are three LEDs on board the SAM4L Xplained Pro board: The EDBG + * controls two of the LEDs, a power LED and a status LED. There is only + * one user controllable LED, a yellow LED labeled LED0 near the SAM4L USB + * connector. + * + * This LED is controlled by PC07 and LED0 can be activated by driving the + * PC07 to GND. + * + * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + * control LED0 as defined below. Thus is LED0 is statically on, NuttX has + * successfully booted and is, apparently, running normmally. If LED0 is + * flashing at approximately 2Hz, then a fatal error has been detected and the + * system has halted. + */ + +#define LED_STARTED 0 /* LED0=OFF */ +#define LED_HEAPALLOCATE 0 /* LED0=OFF */ +#define LED_IRQSENABLED 0 /* LED0=OFF */ +#define LED_STACKCREATED 1 /* LED0=ON */ +#define LED_INIRQ 2 /* LED0=no change */ +#define LED_SIGNAL 2 /* LED0=no change */ +#define LED_ASSERTION 2 /* LED0=no change */ +#define LED_PANIC 3 /* LED0=flashing */ + +/* Button definitions ***************************************************************/ +/* QTouch button: The SAM4L Xplained Pro kit has one QTouch button. The connection + * to the SAM4L is: + * + * PC13 CATB_SENSE15 + * PC14 CATB_DIS + */ + +/* Mechanical buttons: + * + * The SAM4L Xplained Pro contains two mechanical buttons. One button is the + * RESET button connected to the SAM4L reset line and the other is a generic user + * configurable button. When a button is pressed it will drive the I/O line to GND. + * + * PC24 SW0 + */ + +/* The STM32F4 Discovery supports one button: */ + +#define BUTTON_SW0 0 +#define NUM_BUTTONS 1 + +#define BUTTON_SW0_BIT (1 << BUTTON_SW0) + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAM3U architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void sam_boardinitialize(void); + +/************************************************************************************ + * Name: up_buttoninit + * + * Description: + * up_buttoninit() must be called to initialize button resources. After that, + * up_buttons() may be called to collect the current state of all buttons or + * up_irqbutton() may be called to register button interrupt handlers. + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_BUTTONS +void up_buttoninit(void); + +/************************************************************************************ + * Name: up_buttons + * + * Description: + * After up_buttoninit() has been called, up_buttons() may be called to collect + * the state of all buttons. up_buttons() returns an 8-bit bit set with each bit + * associated with a button. See the BUTTON* definitions above for the meaning of + * each bit in the returned value. + * + ************************************************************************************/ + +uint8_t up_buttons(void); + +/************************************************************************************ + * Name: up_irqbutton + * + * Description: + * This function may be called to register an interrupt handler that will be + * called when a button is depressed or released. The ID value is one of the + * BUTTON* definitions provided above. The previous interrupt handler address is + * returned (so that it may restored, if so desired). + * + ************************************************************************************/ + +#ifdef CONFIG_GPIOA_IRQ +xcpt_t up_irqbutton(int id, xcpt_t irqhandler); +#endif +#endif /* CONFIG_ARCH_BUTTONS */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_SAM4L_XPLAINED_INCLUDE_BOARD_H */ diff --git a/nuttx/configs/sam4l-xplained/ostest/Make.defs b/nuttx/configs/sam4l-xplained/ostest/Make.defs new file mode 100644 index 0000000000..ac828cabbe --- /dev/null +++ b/nuttx/configs/sam4l-xplained/ostest/Make.defs @@ -0,0 +1,109 @@ +############################################################################ +# configs/sam4l-xplained/ostest/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" + MAXOPTIMIZATION = -O2 +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + diff --git a/nuttx/configs/sam4l-xplained/ostest/defconfig b/nuttx/configs/sam4l-xplained/ostest/defconfig new file mode 100644 index 0000000000..e10037477e --- /dev/null +++ b/nuttx/configs/sam4l-xplained/ostest/defconfig @@ -0,0 +1,581 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +CONFIG_ARCH_CHIP_SAM34=y +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_CORTEXM4=y +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="sam34" +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set + +# +# ARMV7M Configuration Options +# +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +CONFIG_ARMV7M_OABI_TOOLCHAIN=y + +# +# AT91SAM3/SAM4 Configuration Options +# +# CONFIG_ARCH_CHIP_AT91SAM3U4E is not set +# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2A is not set +CONFIG_ARCH_CHIP_ATSAM4LC4C=y +# CONFIG_ARCH_CHIP_ATSAM4LC4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4A is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD32C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD32B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD16C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD16B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SA16C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SA16B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S16C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S16B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S8C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S8B is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +CONFIG_ARCH_CHIP_SAM4L=y +# CONFIG_ARCH_CHIP_SAM4S is not set + +# +# AT91SAM3 Peripheral Support +# +# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_NAND is not set +# CONFIG_SAM34_HSMCI is not set +CONFIG_SAM34_UART=y +# CONFIG_SAM34_USART0 is not set +# CONFIG_SAM34_USART1 is not set +# CONFIG_SAM34_USART2 is not set +# CONFIG_SAM34_USART3 is not set +# CONFIG_SAM34_SPI is not set + +# +# AT91SAM3 UART Configuration +# + +# +# AT91SAM3 GPIO Interrupt Configuration +# +# CONFIG_GPIOA_IRQ is not set +# CONFIG_GPIOB_IRQ is not set +# CONFIG_GPIOC_IRQ is not set + +# +# External Memory Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=4768 +# CONFIG_ARCH_CALIBRATION is not set +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=32768 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_SAM4L_XPLAINED=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="sam4l-xplained" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set + +# +# Board-Specific Options +# + +# +# RTOS Features +# +# CONFIG_BOARD_INITIALIZE is not set +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=6 +CONFIG_START_DAY=3 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="ostest_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +CONFIG_DISABLE_ENVIRON=y + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_SERIAL=y +CONFIG_DEV_LOWCONSOLE=y +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART=y +CONFIG_MCU_SERIAL=y +CONFIG_UART_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART Configuration +# +CONFIG_UART_RXBUFSIZE=256 +CONFIG_UART_TXBUFSIZE=256 +CONFIG_UART_BAUD=115200 +CONFIG_UART_BITS=8 +CONFIG_UART_PARITY=0 +CONFIG_UART_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +CONFIG_DISABLE_MOUNTPOINT=y +# CONFIG_FS_RAMMAP is not set + +# +# System Logging +# +# CONFIG_SYSLOG_ENABLE is not set +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_MULTIHEAP is not set +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=3 +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Library Support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +CONFIG_EXAMPLES_OSTEST=y +# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set +CONFIG_EXAMPLES_OSTEST_LOOPS=1 +CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 +CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 +CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# FLASH Erase-all Command +# + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set + +# +# USB Monitor +# diff --git a/nuttx/configs/sam4l-xplained/ostest/setenv.sh b/nuttx/configs/sam4l-xplained/ostest/setenv.sh new file mode 100755 index 0000000000..bf503b833e --- /dev/null +++ b/nuttx/configs/sam4l-xplained/ostest/setenv.sh @@ -0,0 +1,63 @@ +#!/bin/bash +# configs/sam4l-xplained/ostest/setenv.sh +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/sam4l-xplained/scripts/ld.script b/nuttx/configs/sam4l-xplained/scripts/ld.script new file mode 100755 index 0000000000..751ab0299f --- /dev/null +++ b/nuttx/configs/sam4l-xplained/scripts/ld.script @@ -0,0 +1,107 @@ +/**************************************************************************** + * configs/sam3u-ek/scripts/ld.script + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The ATSAM4LC4C has 256Kb of FLASH beginning at address 0x0000:0000 and + * 32Kb of SRAM beginning at address 0x2000:0000 + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .ARM.extab : { + *(.ARM.extab*) + } >sram + + .ARM.exidx : { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } >sram + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/sam4l-xplained/src/.gitignore b/nuttx/configs/sam4l-xplained/src/.gitignore new file mode 100644 index 0000000000..726d936e1e --- /dev/null +++ b/nuttx/configs/sam4l-xplained/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/nuttx/configs/sam4l-xplained/src/Makefile b/nuttx/configs/sam4l-xplained/src/Makefile new file mode 100644 index 0000000000..4b1efd0cef --- /dev/null +++ b/nuttx/configs/sam4l-xplained/src/Makefile @@ -0,0 +1,86 @@ +############################################################################ +# configs/sam4l-xplained/src/Makefile +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +CFLAGS += -I$(TOPDIR)/sched + +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = sam_boot.c sam_autoleds.c sam_buttons.c sam_spi.c + +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(WINTOOL),y) + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}" +else + CFLAGS += -I$(ARCH_SRCDIR)/chip + CFLAGS += -I$(ARCH_SRCDIR)/common + CFLAGS += -I$(ARCH_SRCDIR)/armv7-m +endif + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h b/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h new file mode 100644 index 0000000000..edeb24fe10 --- /dev/null +++ b/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h @@ -0,0 +1,140 @@ +/************************************************************************************ + * configs/sam3uek_eval/src/sam4l-xplained.h + * + * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAM4L_XPLAINED_SRC_SAM4L_XPLAINED_H +#define __CONFIGS_SAM4L_XPLAINED_SRC_SAM4L_XPLAINED_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include + +#include +#include + +#include "chip/sam_pinmap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* LEDs: There are three LEDs on board the SAM4L Xplained Pro board: The EDBG + * controls two of the LEDs, a power LED and a status LED. There is only + * one user controllable LED, a yellow LED labeled LED0 near the SAM4L USB + * connector. + * + * This LED is controlled by PC07 and LED0 can be activated by driving the + * PC07 to GND. + * + * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + * control LED0 as follows: + * + * SYMBOL Meaning LED0 + * ------------------- ----------------------- ------ + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt N/C + * LED_SIGNAL In a signal handler N/C + * LED_ASSERTION An assertion failed N/C + * LED_PANIC The system has crashed FLASH + * + * Thus is LED0 is statically on, NuttX has successfully booted and is, + * apparently, running normmally. If LED0 is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +#define GPIO_LED0 (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | \ + GPIO_OUTPUT_SET | GPIO_PIN7) + +/* QTouch button: The SAM4L Xplained Pro kit has one QTouch button. The connection + * to the SAM4L is: + * + * PC13 CATB_SENSE15 + * PC14 CATB_DIS + */ + +/* Mechanical buttons: + * + * The SAM4L Xplained Pro contains two mechanical buttons. One button is the + * RESET button connected to the SAM4L reset line and the other is a generic user + * configurable button. When a button is pressed it will drive the I/O line to GND. + * + * PC24 SW0 + */ + +#define GPIO_SW0 (GPIO_INPUT | GPIO_CFG_PULLUP | GPIO_CFG_DEGLITCH | \ + GPIO_PORT_PIOC | GPIO_PIN24) +#define IRQ_SW0 SAM_IRQ_PC24 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the SAM3U-EK board. + * + ************************************************************************************/ + +void weak_function sam_spiinitialize(void); + +/**************************************************************************** + * Name: up_ledinit + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void up_ledinit(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_SAM4L_XPLAINED_SRC_SAM4L_XPLAINED_H */ + diff --git a/nuttx/configs/sam4l-xplained/src/sam_autoleds.c b/nuttx/configs/sam4l-xplained/src/sam_autoleds.c new file mode 100644 index 0000000000..1ea1afbe49 --- /dev/null +++ b/nuttx/configs/sam4l-xplained/src/sam_autoleds.c @@ -0,0 +1,182 @@ +/**************************************************************************** + * configs/sam4l-xplained/src/sam_autoleds.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* There are three LEDs on board the SAM4L Xplained Pro board: The EDBG + * controls two of the LEDs, a power LED and a status LED. There is only + * one user controllable LED, a yellow LED labeled LED0 near the SAM4L USB + * connector. + * + * This LED is controlled by PC07 and LED0 can be activated by driving the + * PC07 to GND. + * + * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + * control LED0 as follows: + * + * SYMBOL Meaning LED0 + * ------------------- ----------------------- ------ + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt** N/C + * LED_SIGNAL In a signal handler*** N/C + * LED_ASSERTION An assertion failed N/C + * LED_PANIC The system has crashed FLASH + * + * Thus is LED0 is statically on, NuttX has successfully booted and is, + * apparently, running normmally. If LED0 is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "sam_gpio.h" +#include "sam4l-xplained.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG + * with CONFIG_DEBUG_VERBOSE too) + */ + +#ifdef CONFIG_DEBUG_LEDS +# define leddbg lldbg +# define ledvdbg llvdbg +#else +# define leddbg(x...) +# define ledvdbg(x...) +#endif + +#define LED_OFF 0 +#define LED_ON 1 +#define LED_NOCHANGE 2 +#define LED_MASK 3 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_ledinit + ****************************************************************************/ + +void up_ledinit(void) +{ + (void)sam_configgpio(GPIO_LED0); +} + +/**************************************************************************** + * Name: up_ledon + ****************************************************************************/ + +void up_ledon(int led) +{ + bool ledstate = true; + + switch (led) + { + case LED_STARTED : /* NuttX has been started LED0=OFF */ + case LED_HEAPALLOCATE: /* Heap has been allocated LED0=OFF */ + case LED_IRQSENABLED: /* Interrupts enabled LED0=OFF */ + break; /* Leave ledstate == true to turn OFF */ + + default: + case LED_INIRQ: /* In an interrupt LED0=N/C */ + case LED_SIGNAL: /* In a signal handler LED0=N/C */ + case LED_ASSERTION: /* An assertion failed LED0=N/C */ + return; + + case LED_PANIC: /* The system has crashed LED0=FLASH */ + case LED_STACKCREATED: /* Idle stack created LED0=ON */ + ledstate = false; /* Set ledstate == false to turn ON */ + break; + } + + sam_gpiowrite(GPIO_LED0, ledstate); +} + +/**************************************************************************** + * Name: up_ledoff + ****************************************************************************/ + +void up_ledoff(int led) +{ + switch (led) + { + /* These should not happen and are ignored */ + + default: + case LED_STARTED : /* NuttX has been started LED0=OFF */ + case LED_HEAPALLOCATE: /* Heap has been allocated LED0=OFF */ + case LED_IRQSENABLED: /* Interrupts enabled LED0=OFF */ + case LED_STACKCREATED: /* Idle stack created LED0=ON */ + + /* These result in no-change */ + + case LED_INIRQ: /* In an interrupt LED0=N/C */ + case LED_SIGNAL: /* In a signal handler LED0=N/C */ + case LED_ASSERTION: /* An assertion failed LED0=N/C */ + return; + + /* Turn LED0 off set driving the output high */ + + case LED_PANIC: /* The system has crashed LED0=FLASH */ + sam_gpiowrite(GPIO_LED0, true); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/nuttx/configs/sam4l-xplained/src/sam_boot.c b/nuttx/configs/sam4l-xplained/src/sam_boot.c new file mode 100644 index 0000000000..09123c5065 --- /dev/null +++ b/nuttx/configs/sam4l-xplained/src/sam_boot.c @@ -0,0 +1,86 @@ +/************************************************************************************ + * configs/sam4l-xplained/src/sam_boot.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "sam4l-xplained.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAM3U architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void sam_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function + * sam_spiinitialize() has been brought into the link. + */ + +#ifdef CONFIG_SAM34_SPI + if (sam_spiinitialize) + { + sam_spiinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinit(); +#endif +} diff --git a/nuttx/configs/sam4l-xplained/src/sam_buttons.c b/nuttx/configs/sam4l-xplained/src/sam_buttons.c new file mode 100644 index 0000000000..2a5081a44b --- /dev/null +++ b/nuttx/configs/sam4l-xplained/src/sam_buttons.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * configs/sam4l-xplained/src/sam_buttons.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include +#include + +#include "sam_gpio.h" +#include "sam4l-xplained.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static xcpt_t g_irqsw0; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_buttoninit + * + * Description: + * up_buttoninit() must be called to initialize button resources. After + * that, up_buttons() may be called to collect the current state of all + * buttons or up_irqbutton() may be called to register button interrupt + * handlers. + * + ****************************************************************************/ + +void up_buttoninit(void) +{ + (void)sam_configgpio(GPIO_SW0); +} + +/************************************************************************************ + * Name: up_buttons + * + * Description: + * After up_buttoninit() has been called, up_buttons() may be called to collect + * the state of all buttons. up_buttons() returns an 8-bit bit set with each bit + * associated with a button. See the BUTTON* definitions above for the meaning of + * each bit in the returned value. + * + ************************************************************************************/ + +uint8_t up_buttons(void) +{ + return sam_gpioread(GPIO_SW0) ? 0 : BUTTON_SW0_BIT; +} + +/**************************************************************************** + * Name: up_irqbutton + * + * Description: + * This function may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is one + * of the BUTTON* definitions provided above. The previous interrupt + * handler address isreturned (so that it may restored, if so desired). + * + * Configuration Notes: + * Configuration CONFIG_AVR32_GPIOIRQ must be selected to enable the + * overall GPIO IRQ feature and CONFIG_AVR32_GPIOIRQSETA and/or + * CONFIG_AVR32_GPIOIRQSETB must be enabled to select GPIOs to support + * interrupts on. For button support, bits 2 and 3 must be set in + * CONFIG_AVR32_GPIOIRQSETB (PB2 and PB3). + * + ****************************************************************************/ + +#if defined(CONFIG_GPIOA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) +xcpt_t up_irqbutton(int id, xcpt_t irqhandler) +{ + xcpt_t oldhandler = NULL; + + if (id == BUTTON_SW0) + { + irqstate_t flags; + + /* Disable interrupts until we are done. This guarantees that the + * following operations are atomic. + */ + + flags = irqsave(); + + /* Get the old button interrupt handler and save the new one */ + + oldhandler = *g_irqsw0; + *g_irqsw0 = irqhandler; + + /* Configure the interrupt */ + + sam_gpioirq(IRQ_SW0); + (void)irq_attach(IRQ_SW0, irqhandler); + sam_gpioirqenable(IRQ_SW0); + } + + /* Return the old button handler (so that it can be restored) */ + + return oldhandler; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/nuttx/configs/sam4l-xplained/src/sam_spi.c b/nuttx/configs/sam4l-xplained/src/sam_spi.c new file mode 100644 index 0000000000..0bd7df9bb7 --- /dev/null +++ b/nuttx/configs/sam4l-xplained/src/sam_spi.c @@ -0,0 +1,239 @@ +/************************************************************************************ + * configs/sam4l-xplained/src/sam_spi.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "sam_gpio.h" +#include "sam_spi.h" +#include "sam4l-xplained.h" + +#ifdef CONFIG_SAM34_SPI + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG too) */ + +#undef SPI_DEBUG /* Define to enable debug */ +#undef SPI_VERBOSE /* Define to enable verbose debug */ + +#ifdef SPI_DEBUG +# define spidbg lldbg +# ifdef SPI_VERBOSE +# define spivdbg lldbg +# else +# define spivdbg(x...) +# endif +#else +# undef SPI_VERBOSE +# define spidbg(x...) +# define spivdbg(x...) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the SAM3U10E-EVAL board. + * + ************************************************************************************/ + +void weak_function sam_spiinitialize(void) +{ + /* The ZigBee module connects used NPCS0. However, there is not yet any + * ZigBee support. + */ + + /* The touchscreen connects using NPCS2 (PC14). */ + +#if defined(CONFIG_INPUT) && defined(CONFIG_INPUT_ADS7843E) + sam_configgpio(GPIO_TSC_NPCS2); +#endif +} + +/**************************************************************************** + * Name: sam_spicsnumber, sam_spiselect, sam_spistatus, and sam_spicmddata + * + * Description: + * These external functions must be provided by board-specific logic. They + * include: + * + * o sam_spicsnumber and sam_spiselect which are helper functions to + * manage the board-specific aspects of the unique SAM3U chip select + * architecture. + * o sam_spistatus and sam_spicmddata: Implementations of the status + * and cmddata methods of the SPI interface defined by struct spi_ops_ + * (see include/nuttx/spi.h). All other methods including + * up_spiinitialize()) are provided by common SAM3U logic. + * + * To use this common SPI logic on your board: + * + * 1. Provide logic in sam_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide sam_spicsnumber(), sam_spiselect() and sam_spistatus() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your board + * is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * sam_spicmddata() functions in your board-specific logic. This + * function will perform cmd/data selection operations using GPIOs in + * the way your board is configured. + * 3. Add a call to up_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_spicsnumber + * + * Description: + * The SAM3U has 4 CS registers for controlling device features. This + * function must be provided by board-specific code. Given a logical device + * ID, this function returns a number from 0 to 3 that identifies one of + * these SAM3U CS resources. + * + * Input Parameters: + * devid - Identifies the (logical) device + * + * Returned Values: + * On success, a CS number from 0 to 3 is returned; A negated errno may + * be returned on a failure. + * + ****************************************************************************/ + +int sam_spicsnumber(enum spi_dev_e devid) +{ + int cs = -EINVAL; + +#if defined(CONFIG_INPUT) && defined(CONFIG_INPUT_ADS7843E) + if (devid == SPIDEV_TOUCHSCREEN) + { + /* Assert the CS pin to the OLED display */ + + cs = 2; + } +#endif + + spidbg("devid: %d CS: %d\n", (int)devid, cs); + return cs; +} + +/**************************************************************************** + * Name: sam_spiselect + * + * Description: + * PIO chip select pins may be programmed by the board specific logic in + * one of two different ways. First, the pins may be programmed as SPI + * peripherals. In that case, the pins are completely controlled by the + * SPI driver. This method still needs to be provided, but it may be only + * a stub. + * + * An alternative way to program the PIO chip select pins is as a normal + * GPIO output. In that case, the automatic control of the CS pins is + * bypassed and this function must provide control of the chip select. + * NOTE: In this case, the GPIO output pin does *not* have to be the + * same as the NPCS pin normal associated with the chip select number. + * + * Input Parameters: + * devid - Identifies the (logical) device + * selected - TRUE:Select the device, FALSE:De-select the device + * + * Returned Values: + * None + * + ****************************************************************************/ + +void sam_spiselect(enum spi_dev_e devid, bool selected) +{ + /* The touchscreen chip select is implemented as a GPIO OUTPUT that must + * be controlled by this function. This is because the ADS7843E driver + * must be able to sample the device BUSY GPIO input between SPI transfers. + * However, the AD7843E will tri-state the BUSY input whenever the chip + * select is de-asserted. So the only option is to control the chip select + * manually and hold it low throughout the SPI transfer. + */ + +#if defined(CONFIG_INPUT) && defined(CONFIG_INPUT_ADS7843E) + if (devid == SPIDEV_TOUCHSCREEN) + { + sam_gpiowrite(GPIO_TSC_NPCS2, !selected); + } +#endif +} + +/**************************************************************************** + * Name: sam_spistatus + * + * Description: + * Return status information associated with the SPI device. + * + * Input Parameters: + * devid - Identifies the (logical) device + * + * Returned Values: + * Bit-encoded SPI status (see include/nuttx/spi.h. + * + ****************************************************************************/ + +uint8_t sam_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + return 0; +} + +#endif /* CONFIG_SAM34_SPI */ diff --git a/nuttx/configs/stm32f4discovery/include/board.h b/nuttx/configs/stm32f4discovery/include/board.h index 793592b0b0..de829f19e2 100644 --- a/nuttx/configs/stm32f4discovery/include/board.h +++ b/nuttx/configs/stm32f4discovery/include/board.h @@ -265,22 +265,22 @@ extern "C" { * ************************************************************************************/ -EXTERN void stm32_boardinitialize(void); +void stm32_boardinitialize(void); /************************************************************************************ * Name: stm32_ledinit, stm32_setled, and stm32_setleds * * Description: * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If - * CONFIG_ARCH_LEDS is not defined, then the following interfacesare available to + * CONFIG_ARCH_LEDS is not defined, then the following interfaces are available to * control the LEDs from user applications. * ************************************************************************************/ #ifndef CONFIG_ARCH_LEDS -EXTERN void stm32_ledinit(void); -EXTERN void stm32_setled(int led, bool ledon); -EXTERN void stm32_setleds(uint8_t ledset); +void stm32_ledinit(void); +void stm32_setled(int led, bool ledon); +void stm32_setleds(uint8_t ledset); #endif /************************************************************************************ @@ -307,10 +307,10 @@ EXTERN void stm32_setleds(uint8_t ledset); ************************************************************************************/ #ifdef CONFIG_ARCH_BUTTONS -EXTERN void up_buttoninit(void); -EXTERN uint8_t up_buttons(void); +void up_buttoninit(void); +uint8_t up_buttons(void); #ifdef CONFIG_ARCH_IRQBUTTONS -EXTERN xcpt_t up_irqbutton(int id, xcpt_t irqhandler); +xcpt_t up_irqbutton(int id, xcpt_t irqhandler); #endif #endif From 5d0aaebaa4a9bc03a1813425d4721c5550f46ba1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 3 Jun 2013 17:53:05 -0600 Subject: [PATCH 20/41] SAM4L alternate pin mapping header file; Use USART1 for virtual COM port console --- nuttx/ChangeLog | 3 + nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h | 579 ++++++++++++++++++ nuttx/configs/sam4l-xplained/README.txt | 12 + nuttx/configs/sam4l-xplained/include/board.h | 13 + nuttx/configs/sam4l-xplained/ostest/defconfig | 24 +- 5 files changed, 620 insertions(+), 11 deletions(-) create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 5057d41df4..fd94f27bae 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4879,3 +4879,6 @@ family (2013-6-3). * configs/sam4l-xplained: A partial configuration that will (eventually) support the SAM4L Xplained Pro developement board (2013-6-3). + * arch/arm/src/sam34/chip/sam4l_pinmap.h: Initial cut as SAM4L + pin mapping (2013-6-3). + diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h new file mode 100644 index 0000000000..1c6f4a481f --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h @@ -0,0 +1,579 @@ +/************************************************************************************ + * arch/arm/src/sam34/chip/sam3u_pinmap.h + * + * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "sam_gpio.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Alternate Pin Functions. + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * SPI MSIO connects vis PA21 on some board, then the following definition should + * appear in the board.h header file for that board: + * + * #define GPIO_SPI_MISO GPIO_SPI_MISO_1 + * + * The driver will then automatically configre PA21 as the SPI MISO pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +/* Audio Bitstream DAC */ + +#define GPIO_ABDACB_CLK_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_ABDACB_CLK_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_ABDACB_DAC0_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_ABDACB_DAC0_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_ABDACB_DAC0_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_ABDACB_DAC0_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_ABDACB_DAC1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_ABDACB_DAC1_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_ABDACB_DAC1_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) +#define GPIO_ABDACB_DAC1_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_ABDACB_DACN0_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_ABDACB_DACN0_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_ABDACB_DACN0_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) +#define GPIO_ABDACB_DACN0_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_ABDACB_DACN1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_ABDACB_DACN1_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_ABDACB_DACN1_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) +#define GPIO_ABDACB_DACN1_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) + +/* Analog Comparator Interface */ + +#define GPIO_ACIFC_ACAN0 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_ACIFC_ACAN1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_ACIFC_ACAP0 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_ACIFC_ACAP1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_ACIFC_ACBN0 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_ACIFC_ACBN1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_ACIFC_ACBP0 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) +#define GPIO_ACIFC_ACBP1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) + +/* ADC controller interface */ + +#define GPIO_ADCIFE_AD0 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_ADCIFE_AD1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_ADCIFE_AD2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_ADCIFE_AD3 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_ADCIFE_AD4 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) +#define GPIO_ADCIFE_AD5 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) +#define GPIO_ADCIFE_AD6 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) +#define GPIO_ADCIFE_AD7 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_ADCIFE_AD8 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) +#define GPIO_ADCIFE_AD9 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_ADCIFE_AD10 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_ADCIFE_AD11 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) +#define GPIO_ADCIFE_AD12 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_ADCIFE_AD13 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_ADCIFE_AD14 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_ADCIFE_TRIGGER (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) + +/* Capacitive Touch Module B */ + +#define GPIO_CATB_DIS_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_CATB_DIS_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) +#define GPIO_CATB_DIS_3 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_CATB_DIS_4 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_CATB_DIS_5 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) +#define GPIO_CATB_DIS_6 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) +#define GPIO_CATB_DIS_7 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_CATB_DIS_8 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_CATB_DIS_9 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) +#define GPIO_CATB_SENSE0_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_CATB_SENSE0_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_CATB_SENSE0_3 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_CATB_SENSE1_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_CATB_SENSE1_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_CATB_SENSE1_3 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_CATB_SENSE2_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_CATB_SENSE2_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_CATB_SENSE2_3 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) +#define GPIO_CATB_SENSE3_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_CATB_SENSE3_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_CATB_SENSE3_3 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_CATB_SENSE4_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) +#define GPIO_CATB_SENSE4_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_CATB_SENSE5_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_CATB_SENSE5_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_CATB_SENSE6_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_CATB_SENSE6_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_CATB_SENSE7_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_CATB_SENSE7_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_CATB_SENSE8_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_CATB_SENSE8_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) +#define GPIO_CATB_SENSE9_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) +#define GPIO_CATB_SENSE9_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_CATB_SENSE10_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_CATB_SENSE10_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) +#define GPIO_CATB_SENSE11_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_CATB_SENSE11_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_CATB_SENSE12_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_CATB_SENSE12_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_CATB_SENSE13_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_CATB_SENSE13_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) +#define GPIO_CATB_SENSE14_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_CATB_SENSE14_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_CATB_SENSE15_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_CATB_SENSE15_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_CATB_SENSE16_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_CATB_SENSE16_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_CATB_SENSE17_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_CATB_SENSE17_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_CATB_SENSE18_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_CATB_SENSE18_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_CATB_SENSE19_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_CATB_SENSE19_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_CATB_SENSE20_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_CATB_SENSE20_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_CATB_SENSE21_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0) +#define GPIO_CATB_SENSE21_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_CATB_SENSE22_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) +#define GPIO_CATB_SENSE22_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_CATB_SENSE23_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_CATB_SENSE23_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_CATB_SENSE24_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) +#define GPIO_CATB_SENSE24_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_CATB_SENSE25_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) +#define GPIO_CATB_SENSE25_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_CATB_SENSE26_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN6) +#define GPIO_CATB_SENSE26_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_CATB_SENSE27_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) +#define GPIO_CATB_SENSE27_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_CATB_SENSE28_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) +#define GPIO_CATB_SENSE28_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_CATB_SENSE29_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) +#define GPIO_CATB_SENSE29_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_CATB_SENSE30_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) +#define GPIO_CATB_SENSE30_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_CATB_SENSE31_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) +#define GPIO_CATB_SENSE31_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) + +/* DAC Controller */ + +#define GPIO_DACC_EXT_TRIG0 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) +#define GPIO_DACC_VOUT (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_EIC_EXTINT0 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) +#define GPIO_EIC_EXTINT1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_EIC_EXTINT1_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_EIC_EXTINT1_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_EIC_EXTINT2_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_EIC_EXTINT2_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_EIC_EXTINT2_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_EIC_EXTINT3_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_EIC_EXTINT3_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_EIC_EXTINT3_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_EIC_EXTINT4_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_EIC_EXTINT4_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_EIC_EXTINT4_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_EIC_EXTINT5_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_EIC_EXTINT5_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_EIC_EXTINT6_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_EIC_EXTINT6_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_EIC_EXTINT7_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) +#define GPIO_EIC_EXTINT7_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_EIC_EXTINT8_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) +#define GPIO_EIC_EXTINT8_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) + +/* Glue Logic Controller */ + +#define GPIO_GLOC_IN0_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_GLOC_IN0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_GLOC_IN1_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_GLOC_IN1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_GLOC_IN2_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_GLOC_IN2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_GLOC_IN3_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_GLOC_IN3_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_GLOC_IN4_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN6) +#define GPIO_GLOC_IN4_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_GLOC_IN4_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_GLOC_IN4_4 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_GLOC_IN5_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) +#define GPIO_GLOC_IN5_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_GLOC_IN5_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_GLOC_IN5_4 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_GLOC_IN6_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) +#define GPIO_GLOC_IN6_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_GLOC_IN6_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_GLOC_IN6_4 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_GLOC_IN7_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) +#define GPIO_GLOC_IN7_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_GLOC_IN7_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_GLOC_OUT0_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_GLOC_OUT0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) +#define GPIO_GLOC_OUT1_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) +#define GPIO_GLOC_OUT1_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_GLOC_OUT1_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_GLOC_OUT1_4 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) + +/* Inter-IC Sound (I2S) Controller */ + +#define GPIO_IISC_IMCK_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_IISC_IMCK_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) +#define GPIO_IISC_IMCK_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_IISC_ISCK_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_IISC_ISCK_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_IISC_ISCK_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_IISC_ISDI_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_IISC_ISDI_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) +#define GPIO_IISC_ISDI_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_IISC_ISDO_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_IISC_ISDO_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) +#define GPIO_IISC_ISDO_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_IISC_IWS_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_IISC_IWS_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN6) +#define GPIO_IISC_IWS_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) + +/* LCD Controller A */ + +#define GPIO_LCDCA_COM0 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_LCDCA_COM1 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_LCDCA_COM2 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_LCDCA_COM3 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_LCDCA_SEG0 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_LCDCA_SEG1 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_LCDCA_SEG2 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_LCDCA_SEG3 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_LCDCA_SEG4 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_LCDCA_SEG5 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_LCDCA_SEG6 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) +#define GPIO_LCDCA_SEG7 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_LCDCA_SEG8 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_LCDCA_SEG9 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_LCDCA_SEG10 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_LCDCA_SEG11 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_LCDCA_SEG12 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_LCDCA_SEG13 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_LCDCA_SEG14 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) +#define GPIO_LCDCA_SEG15 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) +#define GPIO_LCDCA_SEG16 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) +#define GPIO_LCDCA_SEG17 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) +#define GPIO_LCDCA_SEG18 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_LCDCA_SEG19 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_LCDCA_SEG20 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_LCDCA_SEG21 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) +#define GPIO_LCDCA_SEG22 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN6) +#define GPIO_LCDCA_SEG23 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) +#define GPIO_LCDCA_SEG24 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_LCDCA_SEG25 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_LCDCA_SEG26 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_LCDCA_SEG27 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_LCDCA_SEG28 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_LCDCA_SEG29 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_LCDCA_SEG30 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_LCDCA_SEG31 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_LCDCA_SEG32 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) +#define GPIO_LCDCA_SEG33 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_LCDCA_SEG34 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_LCDCA_SEG35 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_LCDCA_SEG36 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_LCDCA_SEG37 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) +#define GPIO_LCDCA_SEG38 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_LCDCA_SEG39 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) + +/* Parallel Capture */ + +#define GPIO_PARC_PCCK_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_PARC_PCCK_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_PARC_PCDATA0_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_PARC_PCDATA0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_PARC_PCDATA1_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_PARC_PCDATA1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_PARC_PCDATA2_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_PARC_PCDATA2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_PARC_PCDATA3_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_PARC_PCDATA3_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_PARC_PCDATA4_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_PARC_PCDATA4_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_PARC_PCDATA5_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) +#define GPIO_PARC_PCDATA5_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_PARC_PCDATA6_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_PARC_PCDATA6_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_PARC_PCDATA7_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_PARC_PCDATA7_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_PARC_PCEN1_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_PARC_PCEN1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_PARC_PCEN2_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_PARC_PCEN2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) + +/* Peripheral Event Controller */ + +#define GPIO_PEVC_PAD_EVT0_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) +#define GPIO_PEVC_PAD_EVT0_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) +#define GPIO_PEVC_PAD_EVT0_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_PEVC_PAD_EVT0_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_PEVC_PAD_EVT1_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_PEVC_PAD_EVT1_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_PEVC_PAD_EVT1_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_PEVC_PAD_EVT1_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) +#define GPIO_PEVC_PAD_EVT2_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) +#define GPIO_PEVC_PAD_EVT2_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_PEVC_PAD_EVT2_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) +#define GPIO_PEVC_PAD_EVT2_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_PEVC_PAD_EVT3_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) +#define GPIO_PEVC_PAD_EVT3_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_PEVC_PAD_EVT3_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) + +/* System Control Interface */ + +#define GPIO_SCIF_GCLK0_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) +#define GPIO_SCIF_GCLK0_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_SCIF_GCLK0_3 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) +#define GPIO_SCIF_GCLK0_4 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_SCIF_GCLK1_1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_SCIF_GCLK1_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) +#define GPIO_SCIF_GCLK1_3 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_SCIF_GCLK2_1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) +#define GPIO_SCIF_GCLK2_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_SCIF_GCLK3_1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_SCIF_GCLK3_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_SCIF_GCLK_IN0_1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_SCIF_GCLK_IN0_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_SCIF_GCLK_IN0_3 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_SCIF_GCLK_IN1_1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_SCIF_GCLK_IN1_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) +#define GPIO_SCIF_GCLK_IN1_3 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) + +/* Serial Peripheral Interface */ + +#define GPIO_SPI_MISO_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_SPI_MISO_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_SPI_MISO_3 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_SPI_MISO_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN3) +#define GPIO_SPI_MISO_5 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_SPI_MISO_6 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_SPI_MOSI_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_SPI_MOSI_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_SPI_MOSI_3 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) +#define GPIO_SPI_MOSI_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) +#define GPIO_SPI_MOSI_5 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_SPI_NPCS0_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_SPI_NPCS0_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_SPI_NPCS0_3 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_SPI_NPCS0_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) +#define GPIO_SPI_NPCS0_5 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_SPI_NPCS1_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_SPI_NPCS1_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_SPI_NPCS1_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_SPI_NPCS1_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_SPI_NPCS2_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_SPI_NPCS2_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) +#define GPIO_SPI_NPCS2_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) +#define GPIO_SPI_NPCS3_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_SPI_NPCS3_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) +#define GPIO_SPI_NPCS3_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_SPI_SCK_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_SPI_SCK_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_SPI_SCK_3 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) +#define GPIO_SPI_SCK_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) + +/* Timer/Counters */ + +#define GPIO_TC0_A0_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) +#define GPIO_TC0_A0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) +#define GPIO_TC0_A1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_TC0_A1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) +#define GPIO_TC0_A2_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_TC0_A2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) +#define GPIO_TC0_B0_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_TC0_B0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) +#define GPIO_TC0_B1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_TC0_B1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) +#define GPIO_TC0_B2_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_TC0_B2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) +#define GPIO_TC0_CLK0_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) +#define GPIO_TC0_CLK0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_TC0_CLK1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_TC0_CLK1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_TC0_CLK2_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_TC0_CLK2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) + +#define GPIO_TC1_A0_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_TC1_A0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_TC1_A1_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_TC1_A1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_TC1_A2_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_TC1_A2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_TC1_B0_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_TC1_B0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_TC1_B1_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_TC1_B1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_TC1_B2_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_TC1_B2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) +#define GPIO_TC1_CLK0_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_TC1_CLK0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) +#define GPIO_TC1_CLK1_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_TC1_CLK1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_TC1_CLK2_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_TC1_CLK2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) + +/* Two-wire Master Interface */ + +#define GPIO_TWIM2_TWCK (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_TWIM2_TWD (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_TWIM3_TWCK (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) +#define GPIO_TWIM3_TWD (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_TWIMS0_TWCK (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_TWIMS0_TWD (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_TWIMS1_TWCK (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) +#define GPIO_TWIMS1_TWD (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0) + +/* USARTs */ + +#define GPIO_USART0_CLK_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_USART0_CLK_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_USART0_CLK_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_USART0_CLK_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_USART0_CTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_USART0_CTS_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) +#define GPIO_USART0_CTS_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_USART0_RTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) +#define GPIO_USART0_RTS_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) +#define GPIO_USART0_RTS_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_USART0_RTS_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_USART0_RXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_USART0_RXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_USART0_RXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_USART0_RXD_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0) +#define GPIO_USART0_RXD_5 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_USART0_TXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_USART0_TXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) +#define GPIO_USART0_TXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_USART0_TXD_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) +#define GPIO_USART0_TXD_5 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) + +#define GPIO_USART1_CLK_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) +#define GPIO_USART1_CLK_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_USART1_CLK_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) +#define GPIO_USART1_CTS (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_USART1_RTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_USART1_RTS_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_USART1_RTS_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_USART1_RXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_USART1_RXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_USART1_RXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) +#define GPIO_USART1_TXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_USART1_TXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_USART1_TXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) + +#define GPIO_USART2_CLK_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_USART2_CLK_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) +#define GPIO_USART2_CTS_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_USART2_CTS_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) +#define GPIO_USART2_RTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_USART2_RTS_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_USART2_RXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_USART2_RXD_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_USART2_RXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) +#define GPIO_USART2_TXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_USART2_TXD_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_USART2_TXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) + +#define GPIO_USART3_CLK_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) +#define GPIO_USART3_CLK_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_USART3_CLK_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_USART3_CLK_4 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_USART3_CTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) +#define GPIO_USART3_CTS_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_USART3_RTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN6) +#define GPIO_USART3_RTS_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_USART3_RTS_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_USART3_RTS_4 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_USART3_RXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) +#define GPIO_USART3_RXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_USART3_RXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_USART3_RXD_4 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_USART3_TXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) +#define GPIO_USART3_TXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_USART3_TXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_USART3_TXD_4 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) + +/* USB 2.0 Interface */ + +#define GPIO_USBC_DM (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_USBC_DP (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H */ diff --git a/nuttx/configs/sam4l-xplained/README.txt b/nuttx/configs/sam4l-xplained/README.txt index ca5ecf2f9e..ea97942f7a 100644 --- a/nuttx/configs/sam4l-xplained/README.txt +++ b/nuttx/configs/sam4l-xplained/README.txt @@ -15,6 +15,7 @@ Contents - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain - LEDs + - Virtual COM Port - SAM4L Xplained Pro-specific Configuration Options - Configurations @@ -242,6 +243,17 @@ LEDs apparently, running normmally. If LED0 is flashing at approximately 2Hz, then a fatal error has been detected and the system has halted. +Virtual COM Port +^^^^^^^^^^^^^^^^ + + The SAM4L Xplained Pro contains an Embedded Debugger (EDBG) that can be + used to program and debug the ATSAM4LC4C using Serial Wire Debug (SWD). + The Embedded debugger also include a Virtual Com port interface over + USART1. Virtual COM port connections: + + PC26 USART1 RXD + PC27 USART1 TXD + SAM4L Xplained Pro-specific Configuration Options ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/configs/sam4l-xplained/include/board.h b/nuttx/configs/sam4l-xplained/include/board.h index 3c8cb82e3c..cb70aff041 100644 --- a/nuttx/configs/sam4l-xplained/include/board.h +++ b/nuttx/configs/sam4l-xplained/include/board.h @@ -156,6 +156,19 @@ #define BUTTON_SW0_BIT (1 << BUTTON_SW0) +/* Alternate Function Disambiguation ************************************************/ +/* The SAM4L Xplained Pro contains an Embedded Debugger (EDBG) that can be + * used to program and debug the ATSAM4LC4C using Serial Wire Debug (SWD). + * The Embedded debugger also include a Virtual Com port interface over + * USART1. Virtual COM port connections: + * + * PC26 USART1 RXD + * PC27 USART1 TXD + */ + +#define GPIO_USART1_RXD GPIO_USART1_RXD_2 +#define GPIO_USART1_TXD GPIO_USART1_TXD_2 + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/nuttx/configs/sam4l-xplained/ostest/defconfig b/nuttx/configs/sam4l-xplained/ostest/defconfig index e10037477e..3cab5109b3 100644 --- a/nuttx/configs/sam4l-xplained/ostest/defconfig +++ b/nuttx/configs/sam4l-xplained/ostest/defconfig @@ -80,6 +80,7 @@ CONFIG_ARCH_CORTEXM4=y CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="sam34" # CONFIG_ARMV7M_USEBASEPRI is not set +# CONFIG_ARCH_HAVE_FPU is not set CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set @@ -128,9 +129,9 @@ CONFIG_ARCH_CHIP_SAM4L=y # CONFIG_SAM34_DMA is not set # CONFIG_SAM34_NAND is not set # CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y +# CONFIG_SAM34_UART is not set # CONFIG_SAM34_USART0 is not set -# CONFIG_SAM34_USART1 is not set +CONFIG_SAM34_USART1=y # CONFIG_SAM34_USART2 is not set # CONFIG_SAM34_USART3 is not set # CONFIG_SAM34_SPI is not set @@ -138,6 +139,7 @@ CONFIG_SAM34_UART=y # # AT91SAM3 UART Configuration # +CONFIG_USART1_ISUART=y # # AT91SAM3 GPIO Interrupt Configuration @@ -297,20 +299,20 @@ CONFIG_DEV_NULL=y CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_USART1=y CONFIG_MCU_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_USART1_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# USART1 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set From 87b4c6a3048f34bfb828285fbd48237aa60464cf Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 4 Jun 2013 07:54:26 -0600 Subject: [PATCH 21/41] NxWidgets::CImage: Allow NULL bitmaps. From Petteri Aimonen --- NxWidgets/ChangeLog.txt | 45 ++++++++++++++------------- NxWidgets/libnxwidgets/src/cimage.cxx | 34 +++++++++++++------- 2 files changed, 46 insertions(+), 33 deletions(-) diff --git a/NxWidgets/ChangeLog.txt b/NxWidgets/ChangeLog.txt index 0737e5ca3f..f83364b9ac 100644 --- a/NxWidgets/ChangeLog.txt +++ b/NxWidgets/ChangeLog.txt @@ -347,25 +347,28 @@ 1.8 2013-xx-xx Gregory Nutt -* NxWM::CMediaPlayer: shell application for an MP3 Media Player with - Kconfig settings to enable it. I plan to write this app to help - develop and test the MP3 codec chip driver. It really doesn't do - anything yet except display a text box saying "Coming soon", and I - need to minimize the icon size a bit. From Ken Pettit (2013-5-11). -* NxWidgets/nxwm/src/glyph_mediaplayer.cxx: Smaller version of the - media player glyph. From Ken Pettit (2013-5-12). -* NxWidgets/nxwm/include/ccalibration.hxx and src/ccalibration.cxx: - Fix a race condition that would cause the calibration screen - to fail to come up when its icon was touched (From Ken Pettit, - 2013-5-12). -* Kconfig: Default priorities for NxWidget and NxWM threads - should be 100, not 50, to be consistent with other default priorities. -* NxWidgets::CGlyphSliderHorizontal and NxWidgets::CGlyphSliderHorizontalGrip: - New widgets added by Ken Pettit (2013-5-15). -* NxWidgets/UnitTests/CGlyphSliderHorizontal: Addes a unit test for the - NxWidgets::CGlyphSliderHorizontal class. From Ken Pettit (2013-5-17) . -* NxWidgets::CGlyphSliderHorizontal: Fix a drawing error. From Ken - Pettit (2013-5-17). -* UnitTests/*/Makefile and .gitignore: Update the way that NSH - the Unit Tests are registered as built-in NSH applications (2013-5-30). +* NxWM::CMediaPlayer: shell application for an MP3 Media Player with + Kconfig settings to enable it. I plan to write this app to help + develop and test the MP3 codec chip driver. It really doesn't do + anything yet except display a text box saying "Coming soon", and I + need to minimize the icon size a bit. From Ken Pettit (2013-5-11). +* NxWidgets/nxwm/src/glyph_mediaplayer.cxx: Smaller version of the + media player glyph. From Ken Pettit (2013-5-12). +* NxWidgets/nxwm/include/ccalibration.hxx and src/ccalibration.cxx: + Fix a race condition that would cause the calibration screen + to fail to come up when its icon was touched (From Ken Pettit, + 2013-5-12). +* Kconfig: Default priorities for NxWidget and NxWM threads + should be 100, not 50, to be consistent with other default priorities. +* NxWidgets::CGlyphSliderHorizontal and NxWidgets::CGlyphSliderHorizontalGrip: + New widgets added by Ken Pettit (2013-5-15). +* NxWidgets/UnitTests/CGlyphSliderHorizontal: Addes a unit test for the + NxWidgets::CGlyphSliderHorizontal class. From Ken Pettit (2013-5-17) . +* NxWidgets::CGlyphSliderHorizontal: Fix a drawing error. From Ken + Pettit (2013-5-17). +* UnitTests/*/Makefile and .gitignore: Update the way that NSH + the Unit Tests are registered as built-in NSH applications (2013-5-30). +* NxWidgets::CImage: Allow a NULL pointer for a bitmap. Add protection + to prevent dereferencing the NULL pointer. From Petteri Aimonen + (2013-6-3). diff --git a/NxWidgets/libnxwidgets/src/cimage.cxx b/NxWidgets/libnxwidgets/src/cimage.cxx index 9b3137129b..b9b93ebb60 100644 --- a/NxWidgets/libnxwidgets/src/cimage.cxx +++ b/NxWidgets/libnxwidgets/src/cimage.cxx @@ -138,19 +138,29 @@ CImage::CImage(CWidgetControl *pWidgetControl, nxgl_coord_t x, nxgl_coord_t y, void CImage::getPreferredDimensions(CRect &rect) const { - nxgl_coord_t width = m_bitmap->getWidth(); - nxgl_coord_t height = m_bitmap->getHeight(); - - if (!m_flags.borderless) + if (!m_bitmap) { - width += (m_borderSize.left + m_borderSize.right); - height += (m_borderSize.top + m_borderSize.bottom); + rect.setX(m_rect.getX()); + rect.setY(m_rect.getY()); + rect.setWidth(0); + rect.setHeight(0); } + else + { + nxgl_coord_t width = m_bitmap->getWidth(); + nxgl_coord_t height = m_bitmap->getHeight(); - rect.setX(m_rect.getX()); - rect.setY(m_rect.getY()); - rect.setWidth(width); - rect.setHeight(height); + if (!m_flags.borderless) + { + width += (m_borderSize.left + m_borderSize.right); + height += (m_borderSize.top + m_borderSize.bottom); + } + + rect.setX(m_rect.getX()); + rect.setY(m_rect.getY()); + rect.setWidth(width); + rect.setHeight(height); + } } /** @@ -440,7 +450,7 @@ void CImage::onReleaseOutside(nxgl_coord_t x, nxgl_coord_t y) void CImage::setImageLeft(nxgl_coord_t column) { - if (column > 0 && column <= m_bitmap->getWidth()) + if (m_bitmap && column > 0 && column <= m_bitmap->getWidth()) { m_origin.x = column; } @@ -455,7 +465,7 @@ void CImage::setImageLeft(nxgl_coord_t column) void CImage::setImageTop(nxgl_coord_t row) { - if (row > 0 && row <= m_bitmap->getHeight()) + if (m_bitmap && row > 0 && row <= m_bitmap->getHeight()) { m_origin.x = row; } From eb9a60d5780d431a6fb579de8021d9e05c0453ee Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 4 Jun 2013 08:02:06 -0600 Subject: [PATCH 22/41] Change auto-increment timing in NxWidgets::CNumericEdit. From Petteri Aimonen --- NxWidgets/ChangeLog.txt | 5 ++++- NxWidgets/libnxwidgets/src/cnumericedit.cxx | 12 ++++++++++-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/NxWidgets/ChangeLog.txt b/NxWidgets/ChangeLog.txt index f83364b9ac..93112b7a01 100644 --- a/NxWidgets/ChangeLog.txt +++ b/NxWidgets/ChangeLog.txt @@ -370,5 +370,8 @@ the Unit Tests are registered as built-in NSH applications (2013-5-30). * NxWidgets::CImage: Allow a NULL pointer for a bitmap. Add protection to prevent dereferencing the NULL pointer. From Petteri Aimonen - (2013-6-3). + (2013-6-4). +* NxWidgets::CNumericEdit: Delay before auto-incrementing now varies: + A longer delay is required to start auto-incrementing and speed increases + while pressed. From Petteri Aimonen (2013-6-4). diff --git a/NxWidgets/libnxwidgets/src/cnumericedit.cxx b/NxWidgets/libnxwidgets/src/cnumericedit.cxx index 993e86fb80..4a1f6a0e24 100644 --- a/NxWidgets/libnxwidgets/src/cnumericedit.cxx +++ b/NxWidgets/libnxwidgets/src/cnumericedit.cxx @@ -216,15 +216,23 @@ void CNumericEdit::handleActionEvent(const CWidgetEventArgs &e) { m_timercount++; - int increment = m_increment; + // Increment the value at increasing speed. + // Ignore the first 3 timer ticks so that single clicks + // only increment by one. + + int increment = 0; if (m_timercount > 50) { increment = m_increment * 100; } - else if (m_timercount > 10) + else if (m_timercount > 20) { increment = m_increment * 10; } + else if (m_timercount > 3) + { + increment = m_increment; + } if (m_button_minus->isClicked()) { From 7525149138b8aa7b122683a55ef7b75f010995c6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 4 Jun 2013 08:11:45 -0600 Subject: [PATCH 23/41] NxWM::CTaskbar: Add a method to redraw the task bar and the top application. From Petteri Aimonen --- NxWidgets/ChangeLog.txt | 4 ++++ NxWidgets/libnxwidgets/src/cnumericedit.cxx | 2 +- NxWidgets/nxwm/include/ctaskbar.hxx | 24 ++++++++++++++------- 3 files changed, 21 insertions(+), 9 deletions(-) diff --git a/NxWidgets/ChangeLog.txt b/NxWidgets/ChangeLog.txt index 93112b7a01..95a8990118 100644 --- a/NxWidgets/ChangeLog.txt +++ b/NxWidgets/ChangeLog.txt @@ -374,4 +374,8 @@ * NxWidgets::CNumericEdit: Delay before auto-incrementing now varies: A longer delay is required to start auto-incrementing and speed increases while pressed. From Petteri Aimonen (2013-6-4). +* NxWM::CTaskbar: Add a method to redraw the taskbar and the current + application. This should only be necessary if the display loses + state due to e.g. powerdown or other manual intervention. From + Petteri Aimonen (2013-6-4). diff --git a/NxWidgets/libnxwidgets/src/cnumericedit.cxx b/NxWidgets/libnxwidgets/src/cnumericedit.cxx index 4a1f6a0e24..5030e782b3 100644 --- a/NxWidgets/libnxwidgets/src/cnumericedit.cxx +++ b/NxWidgets/libnxwidgets/src/cnumericedit.cxx @@ -1,7 +1,7 @@ /**************************************************************************** * NxWidgets/libnxwidgets/include/cnumericedit.cxx * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * Petteri Aimonen * diff --git a/NxWidgets/nxwm/include/ctaskbar.hxx b/NxWidgets/nxwm/include/ctaskbar.hxx index 229e78b229..84c7b28f44 100644 --- a/NxWidgets/nxwm/include/ctaskbar.hxx +++ b/NxWidgets/nxwm/include/ctaskbar.hxx @@ -1,7 +1,7 @@ /**************************************************************************** * NxWidgets/nxwm/include/cnxtaskbar.hxx * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -89,7 +89,7 @@ namespace NxWM /** * This structure represents an application and its associated icon image */ - + struct STaskbarSlot { IApplication *app; /**< A reference to the icon */ @@ -108,7 +108,7 @@ namespace NxWM bool m_started; /**< True if window manager has been started */ /** - * Create a raw window. + * Create a raw window. * * 1) Create a dumb NXWidgets::CWidgetControl instance (See not). * 2) Pass the dumb NXWidgets::CWindowMessenger instance to the window constructor @@ -134,7 +134,7 @@ namespace NxWM * * @return A partially initialized application window instance. */ - + NXWidgets::CNxTkWindow *openFramedWindow(void); /** @@ -155,7 +155,7 @@ namespace NxWM virtual bool createTaskbarWindow(void); /** - * Create the background window. + * Create the background window. * * @return true on success */ @@ -163,7 +163,7 @@ namespace NxWM virtual bool createBackgroundWindow(void); /** - * Create the background image. + * Create the background image. * * @return true on success */ @@ -247,7 +247,7 @@ namespace NxWM /** * Connect to the server */ - + bool connect(void); /** @@ -409,7 +409,15 @@ namespace NxWM */ void getDisplaySize(FAR struct nxgl_size_s &size); - + + /** + * Force a redraw of the taskbar and current application. + * This should only be necessary if the display loses state due to e.g. powerdown + * or other manual intervention. + */ + + inline void redraw() { redrawTopApplication(); } + /** * Simulate a mouse click or release on the icon at index. This method * is only available during automated testing of NxWM. From 6275eae430d05c992c9584c133df318af6137641 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 4 Jun 2013 08:44:49 -0600 Subject: [PATCH 24/41] Add stm32_dmacapable interface to determine is it is possible to perform DMA from a given address. --- nuttx/ChangeLog | 4 ++ nuttx/arch/arm/src/stm32/Kconfig | 11 ++++ .../src/stm32/chip/stm32f10xxx_memorymap.h | 1 + nuttx/arch/arm/src/stm32/stm32_dma.h | 41 +++++++++---- nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c | 43 +++++++++++-- nuttx/arch/arm/src/stm32/stm32f20xxx_dma.c | 39 +++++++++++- nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c | 61 ++++++++++++++++--- 7 files changed, 174 insertions(+), 26 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index fd94f27bae..39a3aa27f0 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4881,4 +4881,8 @@ support the SAM4L Xplained Pro developement board (2013-6-3). * arch/arm/src/sam34/chip/sam4l_pinmap.h: Initial cut as SAM4L pin mapping (2013-6-3). + * arch/arm/src/stm32/stm32*_dma.*: Add a new interface function, + stm32_dmacapable() that can be used to determine if DMA is + possible from the specified memory address. From Petteri Aimonen + (2013-6-4). diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig index 458190745b..7249b382ff 100644 --- a/nuttx/arch/arm/src/stm32/Kconfig +++ b/nuttx/arch/arm/src/stm32/Kconfig @@ -1128,6 +1128,17 @@ config STM32_CCMEXCLUDE and (2) it appears to be impossible to execute ELF modules from CCM RAM. +config STM32_DMACAPABLE + bool "Workaround non-DMA capable memory" + depends on ARCH_DMA + default y if STM32_STM32F40XX && !STM32_CCMEXCLUDE + default n if !STM32_STM32F40XX || STM32_CCMEXCLUDE + ---help--- + This option enables the DMA interface stm32_dmacapable that can be + used to check if it is possible to do DMA from the selected address. + Drivers then may use this information to determine if they should + attempt the DMA or fall back to a different transfer method. + config STM32_FSMC_SRAM bool "External SRAM on FSMC" default n diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h index c405a6dead..217836999b 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h @@ -42,6 +42,7 @@ /* FLASH and SRAM *******************************************************************/ +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ #define STM32_FLASH_BASE 0x08000000 /* 0x08000000 - Up to 512Kb */ #define STM32_SRAM_BASE 0x20000000 /* 0x20000000 - 64Kb SRAM */ #define STM32_SRAMBB_BASE 0x22000000 diff --git a/nuttx/arch/arm/src/stm32/stm32_dma.h b/nuttx/arch/arm/src/stm32/stm32_dma.h index f40a757b56..771754bf92 100644 --- a/nuttx/arch/arm/src/stm32/stm32_dma.h +++ b/nuttx/arch/arm/src/stm32/stm32_dma.h @@ -146,7 +146,6 @@ extern "C" { #define EXTERN extern #endif - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -211,7 +210,7 @@ EXTERN DMA_HANDLE stm32_dmachannel(unsigned int chan); * ****************************************************************************/ -EXTERN void stm32_dmafree(DMA_HANDLE handle); +void stm32_dmafree(DMA_HANDLE handle); /**************************************************************************** * Name: stm32_dmasetup @@ -221,8 +220,8 @@ EXTERN void stm32_dmafree(DMA_HANDLE handle); * ****************************************************************************/ -EXTERN void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr); +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t ccr); /**************************************************************************** * Name: stm32_dmastart @@ -236,8 +235,8 @@ EXTERN void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * ****************************************************************************/ -EXTERN void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, - void *arg, bool half); +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, + bool half); /**************************************************************************** * Name: stm32_dmastop @@ -252,7 +251,7 @@ EXTERN void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, * ****************************************************************************/ -EXTERN void stm32_dmastop(DMA_HANDLE handle); +void stm32_dmastop(DMA_HANDLE handle); /**************************************************************************** * Name: stm32_dmaresidual @@ -265,7 +264,27 @@ EXTERN void stm32_dmastop(DMA_HANDLE handle); * ****************************************************************************/ -EXTERN size_t stm32_dmaresidual(DMA_HANDLE handle); +size_t stm32_dmaresidual(DMA_HANDLE handle); + +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address. This depends on the internal connections in the ARM bus matrix + * of the processor. Note that this only applies to memory addresses, it + * will return false for any peripheral address. + * + * Returned value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uintptr_t maddr); +#else +# define stm32_dmacapable(maddr) (true) +#endif /**************************************************************************** * Name: stm32_dmasample @@ -279,7 +298,7 @@ EXTERN size_t stm32_dmaresidual(DMA_HANDLE handle); ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA -EXTERN void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else # define stm32_dmasample(handle,regs) #endif @@ -296,8 +315,8 @@ EXTERN void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA -EXTERN void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg); +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, + const char *msg); #else # define stm32_dmadump(handle,regs,msg) #endif diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c index 29b09150d6..9ab64ce7e6 100644 --- a/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32f10xxx_dma.c * - * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -77,7 +77,7 @@ #endif /* Convert the DMA channel base address to the DMA register block address */ - + #define DMA_BASE(ch) (ch & 0xfffffc00) /**************************************************************************** @@ -358,7 +358,7 @@ void weak_function up_dmainitialize(void) /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ up_enable_irq(dmach->irq); - + /* Set the interrrupt priority */ up_prioritize_irq(dmach->irq, CONFIG_DMA_PRI); @@ -548,7 +548,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool { /* In nonstop mode, when the transfer completes it immediately resets * and starts again. The transfer-complete interrupt is thus always - * enabled, and the half-complete interrupt can be used in circular + * enabled, and the half-complete interrupt can be used in circular * mode to determine when the buffer is half-full, or in double-buffered * mode to determine when one of the two buffers is full. */ @@ -596,6 +596,41 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); } +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address. This depends on the internal connections in the ARM bus matrix + * of the processor. Note that this only applies to memory addresses, it + * will return false for any peripheral address. + * + * Returned value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uint32_t maddr) +{ + switch (maddr & STM32_REGION_MASK) + { + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_FSMC_BANK4: + case STM32_SRAM_BASE: + case STM32_CODE_BASE: + /* All RAM and flash is supported */ + return true; + + default: + /* Everything else is unsupported by DMA */ + return false; + } +} +#endif + /**************************************************************************** * Name: stm32_dmasample * diff --git a/nuttx/arch/arm/src/stm32/stm32f20xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f20xxx_dma.c index 844fa6a670..71ac263fbb 100644 --- a/nuttx/arch/arm/src/stm32/stm32f20xxx_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32f20xxx_dma.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32f20xxx_dma.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -773,7 +773,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool * Interrupt Enable bit (TCIE) is set. */ - scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE)); + scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE)); } else { @@ -841,6 +841,41 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) return (size_t)residual; } +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address. This depends on the internal connections in the ARM bus matrix + * of the processor. Note that this only applies to memory addresses, it + * will return false for any peripheral address. + * + * Returned value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uint32_t maddr) +{ + switch (maddr & STM32_REGION_MASK) + { + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_FSMC_BANK4: + case STM32_SRAM_BASE: + case STM32_CODE_BASE: + /* All RAM and flash is supported */ + return true; + + default: + /* Everything else is unsupported by DMA */ + return false; + } +} +#endif + /**************************************************************************** * Name: stm32_dmasample * diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c index fd8164a321..5bff603b9f 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32f40xxx_dma.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -79,7 +79,7 @@ #endif /* Convert the DMA stream base address to the DMA register block address */ - + #define DMA_BASE(ch) (ch & 0xfffffc00) /**************************************************************************** @@ -358,7 +358,7 @@ static void stm32_dmastreamdisable(struct stm32_dma_s *dmast) { regoffset = STM32_DMA_HIFCR_OFFSET; } - + dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift)); } @@ -491,7 +491,7 @@ void weak_function up_dmainitialize(void) /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ up_enable_irq(dmast->irq); - + /* Set the interrrupt priority */ up_prioritize_irq(dmast->irq, CONFIG_DMA_PRI); @@ -634,7 +634,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, { regoffset = STM32_DMA_HIFCR_OFFSET; } - + dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift)); /* "Set the peripheral register address in the DMA_SPARx register. The data @@ -692,7 +692,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * generated when the stream is enabled, then the stream will be automatically * disabled." * - * The FIFO is disabled in circular mode when transferring data from a + * The FIFO is disabled in circular mode when transferring data from a * peripheral to memory, as in this case it is usually desirable to know that * every byte from the peripheral is transferred immediately to memory. It is * not practical to flush the DMA FIFO, as this requires disabling the channel @@ -776,13 +776,13 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool * Interrupt Enable bit (TCIE) is set. */ - scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE)); + scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE)); } else { /* In non-stop modes, when the transfer completes it immediately resets * and starts again. The transfer-complete interrupt is thus always - * enabled, and the half-complete interrupt can be used in circular + * enabled, and the half-complete interrupt can be used in circular * mode to determine when the buffer is half-full, or in double-buffered * mode to determine when one of the two buffers is full. */ @@ -828,7 +828,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; uint32_t residual; - /* Fetch the count of bytes remaining to be transferred. + /* Fetch the count of bytes remaining to be transferred. * * If the FIFO is enabled, this count may be inaccurate. ST don't * appear to document whether this counts the peripheral or the memory @@ -844,6 +844,49 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) return (size_t)residual; } +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address. This depends on the internal connections in the ARM bus matrix + * of the processor. Note that this only applies to memory addresses, it + * will return false for any peripheral address. + * + * Returned value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uint32_t maddr) +{ + switch (maddr & STM32_REGION_MASK) + { + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_FSMC_BANK4: + case STM32_SRAM_BASE: + /* All RAM is supported */ + return true; + + case STM32_CODE_BASE: + /* Everything except the CCM ram is supported */ + if (maddr >= STM32_CCMRAM_BASE && + (maddr - STM32_CCMRAM_BASE) < 65536) + { + return false; + } + return true; + + default: + /* Everything else is unsupported by DMA */ + return false; + } +} +#endif + /**************************************************************************** * Name: stm32_dmasample * From e7e1e834a6b45cbbd2b1bb2881802511676bfed3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 4 Jun 2013 09:05:39 -0600 Subject: [PATCH 25/41] If CONFIG_STM32_DMACAPABLE is defined, use stm32_dmacapable to workaround attempt SPI DMAs from the CCM stack --- nuttx/ChangeLog | 6 +++ nuttx/arch/arm/src/stm32/stm32_spi.c | 55 ++++++++++++++++++---------- 2 files changed, 42 insertions(+), 19 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 39a3aa27f0..66f5286b87 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4885,4 +4885,10 @@ stm32_dmacapable() that can be used to determine if DMA is possible from the specified memory address. From Petteri Aimonen (2013-6-4). + * arch/arm/src/stm32/stm32_spi.c: If CONFIG_STM32_DMACAPABLE is + defined, use stm32_dmacapable() to determine if it is possible + to perform DMA from the specified address. This change is + important for the STM32 F4 which may have SPI data buffers + allocated on the stack in CCM memory which cannot support the + DMA. From Petteri Aimonen (2013-6-4). diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.c b/nuttx/arch/arm/src/stm32/stm32_spi.c index 620b8315b0..929dcef36d 100644 --- a/nuttx/arch/arm/src/stm32/stm32_spi.c +++ b/nuttx/arch/arm/src/stm32/stm32_spi.c @@ -1,7 +1,7 @@ /************************************************************************************ * arm/arm/src/stm32/stm32_spi.c * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -1215,7 +1215,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) } /************************************************************************************ - * Name: spi_exchange (no DMA) + * Name: spi_exchange (no DMA). aka spi_exchange_nodma * * Description: * Exchange a block of data on SPI without using DMA @@ -1234,9 +1234,14 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) * ************************************************************************************/ -#ifndef CONFIG_STM32_SPI_DMA +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, FAR void *rxbuffer, size_t nwords) +#else +static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) +#endif { FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); @@ -1312,7 +1317,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, } } } -#endif +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /************************************************************************* * Name: spi_exchange (with DMA capability) @@ -1338,29 +1343,41 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, FAR void *rxbuffer, size_t nwords) { - FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; - static uint16_t rxdummy = 0xffff; - static const uint16_t txdummy = 0xffff; +#ifdef CONFIG_STM32_DMACAPABLE + if ((txbuffer && !stm32_dmacapable((uint32_t)txbuffer)) || + (rxbuffer && !stm32_dmacapable((uint32_t)rxbuffer))) + { + /* Unsupported memory region, fall back to non-DMA method. */ - spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); - DEBUGASSERT(priv && priv->spibase); + spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + } + else +#endif + { + FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev; + static uint16_t rxdummy = 0xffff; + static const uint16_t txdummy = 0xffff; - /* Setup DMAs */ + spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); + DEBUGASSERT(priv && priv->spibase); - spi_dmarxsetup(priv, rxbuffer, &rxdummy, nwords); - spi_dmatxsetup(priv, txbuffer, &txdummy, nwords); + /* Setup DMAs */ - /* Start the DMAs */ + spi_dmarxsetup(priv, rxbuffer, &rxdummy, nwords); + spi_dmatxsetup(priv, txbuffer, &txdummy, nwords); - spi_dmarxstart(priv); - spi_dmatxstart(priv); + /* Start the DMAs */ - /* Then wait for each to complete */ + spi_dmarxstart(priv); + spi_dmatxstart(priv); - spi_dmarxwait(priv); - spi_dmatxwait(priv); + /* Then wait for each to complete */ + + spi_dmarxwait(priv); + spi_dmatxwait(priv); + } } -#endif +#endif /* CONFIG_STM32_SPI_DMA */ /************************************************************************* * Name: spi_sndblock From a9561ad73b90cdddef887bfb603d0e1333360b2d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 4 Jun 2013 11:38:23 -0600 Subject: [PATCH 26/41] Add SAM4L (and 4S) GPIO register definitions --- nuttx/arch/arm/src/sam34/chip.h | 3 +- nuttx/arch/arm/src/sam34/chip/sam3u_pio.h | 324 ++++++++++++++++ nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h | 327 ++++++++++++++++ nuttx/arch/arm/src/sam34/chip/sam4s_pio.h | 399 ++++++++++++++++++++ nuttx/arch/arm/src/sam34/chip/sam_pio.h | 271 +------------ nuttx/arch/arm/src/sam34/sam_allocateheap.c | 9 +- 6 files changed, 1067 insertions(+), 266 deletions(-) create mode 100644 nuttx/arch/arm/src/sam34/chip/sam3u_pio.h create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4s_pio.h diff --git a/nuttx/arch/arm/src/sam34/chip.h b/nuttx/arch/arm/src/sam34/chip.h index 3c92f53ef6..eefb969bc1 100644 --- a/nuttx/arch/arm/src/sam34/chip.h +++ b/nuttx/arch/arm/src/sam34/chip.h @@ -58,7 +58,8 @@ # include "chip/sam3u_vectors.h" # elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_vectors.h" -# include "chip/sam4l_memorymap.h" +# elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_vectors.h" # else # error Unrecognized SAM architecture # endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h new file mode 100644 index 0000000000..14ceb0724f --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h @@ -0,0 +1,324 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam3u_pio.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PIO_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PIO_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PIO register offsets *****************************************************************/ + +#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ +#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ +#define SAM_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */ + /* 0x000c: Reserved */ +#define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */ +#define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */ +#define SAM_PIO_OSR_OFFSET 0x0018 /* utput Status Register */ + /* 0x001c: Reserved */ +#define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */ +#define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */ +#define SAM_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */ + /* 0x002c: Reserved */ +#define SAM_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */ +#define SAM_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */ +#define SAM_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */ +#define SAM_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */ +#define SAM_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */ +#define SAM_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */ +#define SAM_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */ +#define SAM_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */ +#define SAM_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */ +#define SAM_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */ +#define SAM_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */ + /* 0x005c: Reserved */ +#define SAM_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */ +#define SAM_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */ +#define SAM_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */ + /* 0x006c: Reserved */ +#define SAM_PIO_ABSR_OFFSET 0x0070 /* Peripheral AB Select Register */ + /* 0x0074-0x007c: Reserved */ +#define SAM_PIO_SCIFSR_OFFSET 0x0080 /* System Clock Glitch Input Filter Select Register */ +#define SAM_PIO_DIFSR_OFFSET 0x0084 /* Debouncing Input Filter Select Register */ +#define SAM_PIO_IFDGSR_OFFSET 0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define SAM_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */ + /* 0x0090-0x009c: Reserved */ +#define SAM_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */ +#define SAM_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */ +#define SAM_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */ + /* 0x00ac: Reserved */ +#define SAM_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */ +#define SAM_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */ +#define SAM_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */ + /* 0x00bc: Reserved */ +#define SAM_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */ +#define SAM_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */ +#define SAM_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */ + /* 0x00cc: Reserved */ +#define SAM_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */ +#define SAM_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */ +#define SAM_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */ + /* 0x00dc: Reserved */ +#define SAM_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */ +#define SAM_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + /* 0x00ec-0x00f8: Reserved */ + /* 0x0100-0x0144: Reserved */ + +/* PIO register adresses ****************************************************************/ + +#define PIOA (0) +#define PIOB (1) +#define PIOC (2) +#define NPIO (3) + +#define SAM_PIO_PER(n) (SAM_PIO_BASE(n)+SAM_PIO_PER_OFFSET) +#define SAM_PIO_PDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDR_OFFSET) +#define SAM_PIO_PSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PSR_OFFSET) +#define SAM_PIO_OER(n) (SAM_PIO_BASE(n)+SAM_PIO_OER_OFFSET) +#define SAM_PIO_ODR(n) (SAM_PIO_BASE(n)+SAM_PIO_ODR_OFFSET) +#define SAM_PIO_OSR(n) (SAM_PIO_BASE(n)+SAM_PIO_OSR_OFFSET) +#define SAM_PIO_IFER(n) (SAM_PIO_BASE(n)+SAM_PIO_IFER_OFFSET) +#define SAM_PIO_IFDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFDR_OFFSET) +#define SAM_PIO_IFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFSR_OFFSET) +#define SAM_PIO_SODR(n) (SAM_PIO_BASE(n)+SAM_PIO_SODR_OFFSET) +#define SAM_PIO_CODR(n) (SAM_PIO_BASE(n)+SAM_PIO_CODR_OFFSET) +#define SAM_PIO_ODSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ODSR_OFFSET) +#define SAM_PIO_PDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDSR_OFFSET) +#define SAM_PIO_IER(n) (SAM_PIO_BASE(n)+SAM_PIO_IER_OFFSET) +#define SAM_PIO_IDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IDR_OFFSET) +#define SAM_PIO_IMR(n) (SAM_PIO_BASE(n)+SAM_PIO_IMR_OFFSET) +#define SAM_PIO_ISR(n) (SAM_PIO_BASE(n)+SAM_PIO_ISR_OFFSET) +#define SAM_PIO_MDER(n) (SAM_PIO_BASE(n)+SAM_PIO_MDER_OFFSET) +#define SAM_PIO_MDDR(n) (SAM_PIO_BASE(n)+SAM_PIO_MDDR_OFFSET) +#define SAM_PIO_MDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_MDSR_OFFSET) +#define SAM_PIO_PUDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PUDR_OFFSET) +#define SAM_PIO_PUER(n) (SAM_PIO_BASE(n)+SAM_PIO_PUER_OFFSET) +#define SAM_PIO_PUSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PUSR_OFFSET) +#define SAM_PIO_ABSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ABSR_OFFSET) +#define SAM_PIO_SCIFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_SCIFSR_OFFSET) +#define SAM_PIO_DIFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_DIFSR_OFFSET) +#define SAM_PIO_IFDGSR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFDGSR_OFFSET) +#define SAM_PIO_SCDR(n) (SAM_PIO_BASE(n)+SAM_PIO_SCDR_OFFSET) +#define SAM_PIO_OWER(n) (SAM_PIO_BASE(n)+SAM_PIO_OWER_OFFSET) +#define SAM_PIO_OWDR(n) (SAM_PIO_BASE(n)+SAM_PIO_OWDR_OFFSET) +#define SAM_PIO_OWSR(n) (SAM_PIO_BASE(n)+SAM_PIO_OWSR_OFFSET) +#define SAM_PIO_AIMER(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMER_OFFSET) +#define SAM_PIO_AIMDR(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIO_AIMMR(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIO_ESR(n) (SAM_PIO_BASE(n)+SAM_PIO_ESR_OFFSET) +#define SAM_PIO_LSR(n) (SAM_PIO_BASE(n)+SAM_PIO_LSR_OFFSET) +#define SAM_PIO_ELSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ELSR_OFFSET) +#define SAM_PIO_FELLSR(n) (SAM_PIO_BASE(n)+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIO_REHLSR(n) (SAM_PIO_BASE(n)+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIO_FRLHSR(n) (SAM_PIO_BASE(n)+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIO_LOCKSR(n) (SAM_PIO_BASE(n)+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIO_WPMR(n) (SAM_PIO_BASE(n)+SAM_PIO_WPMR_OFFSET) +#define SAM_PIO_WPSR(n) (SAM_PIO_BASE(n)+SAM_PIO_WPSR_OFFSET) + +#define SAM_PIOA_PER (SAM_PIOA_BASE+SAM_PIO_PER_OFFSET) +#define SAM_PIOA_PDR (SAM_PIOA_BASE+SAM_PIO_PDR_OFFSET) +#define SAM_PIOA_PSR (SAM_PIOA_BASE+SAM_PIO_PSR_OFFSET) +#define SAM_PIOA_OER (SAM_PIOA_BASE+SAM_PIO_OER_OFFSET) +#define SAM_PIOA_ODR (SAM_PIOA_BASE+SAM_PIO_ODR_OFFSET) +#define SAM_PIOA_OSR (SAM_PIOA_BASE+SAM_PIO_OSR_OFFSET) +#define SAM_PIOA_IFER (SAM_PIOA_BASE+SAM_PIO_IFER_OFFSET) +#define SAM_PIOA_IFDR (SAM_PIOA_BASE+SAM_PIO_IFDR_OFFSET) +#define SAM_PIOA_IFSR (SAM_PIOA_BASE+SAM_PIO_IFSR_OFFSET) +#define SAM_PIOA_SODR (SAM_PIOA_BASE+SAM_PIO_SODR_OFFSET) +#define SAM_PIOA_CODR (SAM_PIOA_BASE+SAM_PIO_CODR_OFFSET) +#define SAM_PIOA_ODSR (SAM_PIOA_BASE+SAM_PIO_ODSR_OFFSET) +#define SAM_PIOA_PDSR (SAM_PIOA_BASE+SAM_PIO_PDSR_OFFSET) +#define SAM_PIOA_IER (SAM_PIOA_BASE+SAM_PIO_IER_OFFSET) +#define SAM_PIOA_IDR (SAM_PIOA_BASE+SAM_PIO_IDR_OFFSET) +#define SAM_PIOA_IMR (SAM_PIOA_BASE+SAM_PIO_IMR_OFFSET) +#define SAM_PIOA_ISR (SAM_PIOA_BASE+SAM_PIO_ISR_OFFSET) +#define SAM_PIOA_MDER (SAM_PIOA_BASE+SAM_PIO_MDER_OFFSET) +#define SAM_PIOA_MDDR (SAM_PIOA_BASE+SAM_PIO_MDDR_OFFSET) +#define SAM_PIOA_MDSR (SAM_PIOA_BASE+SAM_PIO_MDSR_OFFSET) +#define SAM_PIOA_PUDR (SAM_PIOA_BASE+SAM_PIO_PUDR_OFFSET) +#define SAM_PIOA_PUER (SAM_PIOA_BASE+SAM_PIO_PUER_OFFSET) +#define SAM_PIOA_PUSR (SAM_PIOA_BASE+SAM_PIO_PUSR_OFFSET) +#define SAM_PIOA_ABSR (SAM_PIOA_BASE+SAM_PIO_ABSR_OFFSET) +#define SAM_PIOA_SCIFSR (SAM_PIOA_BASE+SAM_PIO_SCIFSR_OFFSET) +#define SAM_PIOA_DIFSR (SAM_PIOA_BASE+SAM_PIO_DIFSR_OFFSET) +#define SAM_PIOA_IFDGSR (SAM_PIOA_BASE+SAM_PIO_IFDGSR_OFFSET) +#define SAM_PIOA_SCDR (SAM_PIOA_BASE+SAM_PIO_SCDR_OFFSET) +#define SAM_PIOA_OWER (SAM_PIOA_BASE+SAM_PIO_OWER_OFFSET) +#define SAM_PIOA_OWDR (SAM_PIOA_BASE+SAM_PIO_OWDR_OFFSET) +#define SAM_PIOA_OWSR (SAM_PIOA_BASE+SAM_PIO_OWSR_OFFSET) +#define SAM_PIOA_AIMER (SAM_PIOA_BASE+SAM_PIO_AIMER_OFFSET) +#define SAM_PIOA_AIMDR (SAM_PIOA_BASE+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIOA_AIMMR (SAM_PIOA_BASE+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIOA_ESR (SAM_PIOA_BASE+SAM_PIO_ESR_OFFSET) +#define SAM_PIOA_LSR (SAM_PIOA_BASE+SAM_PIO_LSR_OFFSET) +#define SAM_PIOA_ELSR (SAM_PIOA_BASE+SAM_PIO_ELSR_OFFSET) +#define SAM_PIOA_FELLSR (SAM_PIOA_BASE+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIOA_REHLSR (SAM_PIOA_BASE+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIOA_FRLHSR (SAM_PIOA_BASE+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIOA_LOCKSR (SAM_PIOA_BASE+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIOA_WPMR (SAM_PIOA_BASE+SAM_PIO_WPMR_OFFSET) +#define SAM_PIOA_WPSR (SAM_PIOA_BASE+SAM_PIO_WPSR_OFFSET) + +#define SAM_PIOB_PER (SAM_PIOB_BASE+SAM_PIO_PER_OFFSET) +#define SAM_PIOB_PDR_ (SAM_PIOB_BASE+SAM_PIO_PDR_OFFSET) +#define SAM_PIOB_PSR (SAM_PIOB_BASE+SAM_PIO_PSR_OFFSET) +#define SAM_PIOB_OER (SAM_PIOB_BASE+SAM_PIO_OER_OFFSET) +#define SAM_PIOB_ODR (SAM_PIOB_BASE+SAM_PIO_ODR_OFFSET) +#define SAM_PIOB_OSR (SAM_PIOB_BASE+SAM_PIO_OSR_OFFSET) +#define SAM_PIOB_IFER (SAM_PIOB_BASE+SAM_PIO_IFER_OFFSET) +#define SAM_PIOB_IFDR (SAM_PIOB_BASE+SAM_PIO_IFDR_OFFSET) +#define SAM_PIOB_IFSR (SAM_PIOB_BASE+SAM_PIO_IFSR_OFFSET) +#define SAM_PIOB_SODR (SAM_PIOB_BASE+SAM_PIO_SODR_OFFSET) +#define SAM_PIOB_CODR (SAM_PIOB_BASE+SAM_PIO_CODR_OFFSET) +#define SAM_PIOB_ODSR (SAM_PIOB_BASE+SAM_PIO_ODSR_OFFSET) +#define SAM_PIOB_PDSR (SAM_PIOB_BASE+SAM_PIO_PDSR_OFFSET) +#define SAM_PIOB_IER (SAM_PIOB_BASE+SAM_PIO_IER_OFFSET) +#define SAM_PIOB_IDR (SAM_PIOB_BASE+SAM_PIO_IDR_OFFSET) +#define SAM_PIOB_IMR (SAM_PIOB_BASE+SAM_PIO_IMR_OFFSET) +#define SAM_PIOB_ISR (SAM_PIOB_BASE+SAM_PIO_ISR_OFFSET) +#define SAM_PIOB_MDER (SAM_PIOB_BASE+SAM_PIO_MDER_OFFSET) +#define SAM_PIOB_MDDR (SAM_PIOB_BASE+SAM_PIO_MDDR_OFFSET) +#define SAM_PIOB_MDSR (SAM_PIOB_BASE+SAM_PIO_MDSR_OFFSET) +#define SAM_PIOB_PUDR (SAM_PIOB_BASE+SAM_PIO_PUDR_OFFSET) +#define SAM_PIOB_PUER (SAM_PIOB_BASE+SAM_PIO_PUER_OFFSET) +#define SAM_PIOB_PUSR (SAM_PIOB_BASE+SAM_PIO_PUSR_OFFSET) +#define SAM_PIOB_ABSR (SAM_PIOB_BASE+SAM_PIO_ABSR_OFFSET) +#define SAM_PIOB_SCIFSR (SAM_PIOB_BASE+SAM_PIO_SCIFSR_OFFSET) +#define SAM_PIOB_DIFSR (SAM_PIOB_BASE+SAM_PIO_DIFSR_OFFSET) +#define SAM_PIOB_IFDGSR (SAM_PIOB_BASE+SAM_PIO_IFDGSR_OFFSET) +#define SAM_PIOB_SCDR (SAM_PIOB_BASE+SAM_PIO_SCDR_OFFSET) +#define SAM_PIOB_OWER (SAM_PIOB_BASE+SAM_PIO_OWER_OFFSET) +#define SAM_PIOB_OWDR (SAM_PIOB_BASE+SAM_PIO_OWDR_OFFSET) +#define SAM_PIOB_OWSR (SAM_PIOB_BASE+SAM_PIO_OWSR_OFFSET) +#define SAM_PIOB_AIMER (SAM_PIOB_BASE+SAM_PIO_AIMER_OFFSET) +#define SAM_PIOB_AIMDR (SAM_PIOB_BASE+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIOB_AIMMR (SAM_PIOB_BASE+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIOB_ESR (SAM_PIOB_BASE+SAM_PIO_ESR_OFFSET) +#define SAM_PIOB_LSR (SAM_PIOB_BASE+SAM_PIO_LSR_OFFSET) +#define SAM_PIOB_ELSR (SAM_PIOB_BASE+SAM_PIO_ELSR_OFFSET) +#define SAM_PIOB_FELLSR (SAM_PIOB_BASE+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIOB_REHLSR (SAM_PIOB_BASE+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIOB_FRLHSR (SAM_PIOB_BASE+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIOB_LOCKSR (SAM_PIOB_BASE+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIOB_WPMR (SAM_PIOB_BASE+SAM_PIO_WPMR_OFFSET) +#define SAM_PIOB_WPSR (SAM_PIOB_BASE+SAM_PIO_WPSR_OFFSET) + +#define SAM_PIOC_PER (SAM_PIOC_BASE+SAM_PIO_PER_OFFSET) +#define SAM_PIOC_PDR_ (SAM_PIOC_BASE+SAM_PIO_PDR_OFFSET) +#define SAM_PIOC_PSR (SAM_PIOC_BASE+SAM_PIO_PSR_OFFSET) +#define SAM_PIOC_OER (SAM_PIOC_BASE+SAM_PIO_OER_OFFSET) +#define SAM_PIOC_ODR (SAM_PIOC_BASE+SAM_PIO_ODR_OFFSET) +#define SAM_PIOC_OSR (SAM_PIOC_BASE+SAM_PIO_OSR_OFFSET) +#define SAM_PIOC_IFER (SAM_PIOC_BASE+SAM_PIO_IFER_OFFSET) +#define SAM_PIOC_IFDR (SAM_PIOC_BASE+SAM_PIO_IFDR_OFFSET) +#define SAM_PIOC_IFSR (SAM_PIOC_BASE+SAM_PIO_IFSR_OFFSET) +#define SAM_PIOC_SODR (SAM_PIOC_BASE+SAM_PIO_SODR_OFFSET) +#define SAM_PIOC_CODR (SAM_PIOC_BASE+SAM_PIO_CODR_OFFSET) +#define SAM_PIOC_ODSR (SAM_PIOC_BASE+SAM_PIO_ODSR_OFFSET) +#define SAM_PIOC_PDSR (SAM_PIOC_BASE+SAM_PIO_PDSR_OFFSET) +#define SAM_PIOC_IER (SAM_PIOC_BASE+SAM_PIO_IER_OFFSET) +#define SAM_PIOC_IDR (SAM_PIOC_BASE+SAM_PIO_IDR_OFFSET) +#define SAM_PIOC_IMR (SAM_PIOC_BASE+SAM_PIO_IMR_OFFSET) +#define SAM_PIOC_ISR (SAM_PIOC_BASE+SAM_PIO_ISR_OFFSET) +#define SAM_PIOC_MDER (SAM_PIOC_BASE+SAM_PIO_MDER_OFFSET) +#define SAM_PIOC_MDDR (SAM_PIOC_BASE+SAM_PIO_MDDR_OFFSET) +#define SAM_PIOC_MDSR (SAM_PIOC_BASE+SAM_PIO_MDSR_OFFSET) +#define SAM_PIOC_PUDR (SAM_PIOC_BASE+SAM_PIO_PUDR_OFFSET) +#define SAM_PIOC_PUER (SAM_PIOC_BASE+SAM_PIO_PUER_OFFSET) +#define SAM_PIOC_PUSR (SAM_PIOC_BASE+SAM_PIO_PUSR_OFFSET) +#define SAM_PIOC_ABSR (SAM_PIOC_BASE+SAM_PIO_ABSR_OFFSET) +#define SAM_PIOC_SCIFSR (SAM_PIOC_BASE+SAM_PIO_SCIFSR_OFFSET) +#define SAM_PIOC_DIFSR (SAM_PIOC_BASE+SAM_PIO_DIFSR_OFFSET) +#define SAM_PIOC_IFDGSR (SAM_PIOC_BASE+SAM_PIO_IFDGSR_OFFSET) +#define SAM_PIOC_SCDR (SAM_PIOC_BASE+SAM_PIO_SCDR_OFFSET) +#define SAM_PIOC_OWER (SAM_PIOC_BASE+SAM_PIO_OWER_OFFSET) +#define SAM_PIOC_OWDR (SAM_PIOC_BASE+SAM_PIO_OWDR_OFFSET) +#define SAM_PIOC_OWSR (SAM_PIOC_BASE+SAM_PIO_OWSR_OFFSET) +#define SAM_PIOC_AIMER (SAM_PIOC_BASE+SAM_PIO_AIMER_OFFSET) +#define SAM_PIOC_AIMDR (SAM_PIOC_BASE+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIOC_AIMMR (SAM_PIOC_BASE+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIOC_ESR (SAM_PIOC_BASE+SAM_PIO_ESR_OFFSET) +#define SAM_PIOC_LSR (SAM_PIOC_BASE+SAM_PIO_LSR_OFFSET) +#define SAM_PIOC_ELSR (SAM_PIOC_BASE+SAM_PIO_ELSR_OFFSET) +#define SAM_PIOC_FELLSR (SAM_PIOC_BASE+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIOC_REHLSR (SAM_PIOC_BASE+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIOC_FRLHSR (SAM_PIOC_BASE+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIOC_LOCKSR (SAM_PIOC_BASE+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIOC_WPMR (SAM_PIOC_BASE+SAM_PIO_WPMR_OFFSET) +#define SAM_PIOC_WPSR (SAM_PIOC_BASE+SAM_PIO_WPSR_OFFSET) + +/* PIO register bit definitions *********************************************************/ + +/* Common bit definitions for ALMOST all IO registers (exceptions follow) */ + +#define PIO(n) (1<<(n)) /* Bit n: PIO n */ + +/* PIO Write Protect Mode Register */ + +#define PIO_WPMR_WPEN 1 << 0) /* Bit 0: Write Protect Enable */ +#define PIO_WPMR_WPKEY_SHIFT 8) /* Bits 8-31: Write Protect KEY */ +#define PIO_WPMR_WPKEY_MASK 0xffffff << PIO_WPMR_WPKEY_SHIFT) + +/* PIO Write Protect Status Register */ + +#define PIO_WPSR_WPVS 1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_SHIFT 8) /* Bits 8-23: Write Protect Violation Source */ +#define PIO_WPSR_WPVSRC_MASK 0xffff << PIO_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PIO_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h new file mode 100644 index 0000000000..d180b2b929 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h @@ -0,0 +1,327 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_gpio.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_GPIO_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_GPIO_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PIO register offsets *****************************************************************/ + +#define SAM_GPIO_GPER_OFFSET 0x0000 /* GPIO Enable Register Read/Write */ +#define SAM_GPIO_GPERS_OFFSET 0x0004 /* GPIO Enable Register Set */ +#define SAM_GPIO_GPERC_OFFSET 0x0008 /* GPIO Enable Register Clear */ +#define SAM_GPIO_GPERT_OFFSET 0x000c /* GPIO Enable Register Toggle */ + +/* {PMR2, PMR1, PMR0} Selected Peripheral Function + * + * 000 GPIO 100 D + * 001 A 101 E + * 010 B 110 F + * 011 C 111 G + * + * NOTE: Labeling in the data sheet is inconsistent. In the pin multiplexing table, + * It shows GPIO functions A-G with 000 apparently corresponding to the GPIO. In the + * register description, it should A-H with presumably A corresponding to 000. Here + * we adopt the above convention. + */ + +#define SAM_GPIO_PMR0_OFFSET 0x0010 /* Peripheral Mux Register 0 Read/Write */ +#define SAM_GPIO_PMR0S_OFFSET 0x0014 /* Peripheral Mux Register 0 Set */ +#define SAM_GPIO_PMR0C_OFFSET 0x0018 /* Peripheral Mux Register 0 Clear */ +#define SAM_GPIO_PMR0T_OFFSET 0x001c /* Peripheral Mux Register 0 Toggle */ + +#define SAM_GPIO_PMR1_OFFSET 0x0020 /* Peripheral Mux Register 1 Read/Write */ +#define SAM_GPIO_PMR1S_OFFSET 0x0024 /* Peripheral Mux Register 1 Set */ +#define SAM_GPIO_PMR1C_OFFSET 0x0028 /* Peripheral Mux Register 1 Clear */ +#define SAM_GPIO_PMR1T_OFFSET 0x002c /* Peripheral Mux Register 1 Toggle */ + +#define SAM_GPIO_PMR2_OFFSET 0x0030 /* Peripheral Mux Register 2 Read/Write */ +#define SAM_GPIO_PMR2S_OFFSET 0x0034 /* Peripheral Mux Register 2 Set */ +#define SAM_GPIO_PMR2C_OFFSET 0x0038 /* Peripheral Mux Register 2 Clear */ +#define SAM_GPIO_PMR2T_OFFSET 0x003c /* Peripheral Mux Register 2 Toggle */ + +#define SAM_GPIO_ODER_OFFSET 0x0040 /* Output Driver Enable Register Read/Write */ +#define SAM_GPIO_ODERS_OFFSET 0x0044 /* Output Driver Enable Register Set */ +#define SAM_GPIO_ODERC_OFFSET 0x0048 /* Output Driver Enable Register Clear */ +#define SAM_GPIO_ODERT_OFFSET 0x004c /* Output Driver Enable Register Toggle */ + +#define SAM_GPIO_OVR_OFFSET 0x0050 /* Output Value Register Read/Write */ +#define SAM_GPIO_OVRS_OFFSET 0x0054 /* Output Value Register Set */ +#define SAM_GPIO_OVRC_OFFSET 0x0058 /* Output Value Register Clear */ +#define SAM_GPIO_OVRT_OFFSET 0x005c /* Output Value Register Toggle */ + +/* Pin Value Register Read (4 registers)*/ + +#define SAM_GPIO_PVR_OFFSET(n) (0x0060 + (((n) & ~31) >> 3)) +#define SAM_GPIO_PVR0_OFFSET 0x0060 /* Pin Value Register 0 Read*/ +#define SAM_GPIO_PVR1_OFFSET 0x0064 /* Pin Value Register 1 Read*/ +#define SAM_GPIO_PVR2_OFFSET 0x0068 /* Pin Value Register 2 Read*/ +#define SAM_GPIO_PVR3_OFFSET 0x006c /* Pin Value Register 3 Read*/ + +/* {PUER, PDER} Selected Function + * + * 00 Disabled + * 01 Pull-down enabled + * 10 Pull-up enabled + * 11 Buskeeper enabled + */ + +#define SAM_GPIO_PUER_OFFSET 0x0070 /* Pull-up Enable Register Read/Write */ +#define SAM_GPIO_PUERS_OFFSET 0x0074 /* Pull-up Enable Register Set */ +#define SAM_GPIO_PUERC_OFFSET 0x0078 /* Pull-up Enable Register Clear*/ +#define SAM_GPIO_PUERT_OFFSET 0x007c /* Pull-up Enable Register Toggle */ + +#define SAM_GPIO_PDER_OFFSET 0x0080 /* Pull-down Enable Register Read/Write */ +#define SAM_GPIO_PDERS_OFFSET 0x0084 /* Pull-down Enable Register Set */ +#define SAM_GPIO_PDERC_OFFSET 0x0088 /* Pull-down Enable Register Clear */ +#define SAM_GPIO_PDERT_OFFSET 0x008c /* Pull-down Enable Register Toggle */ + +#define SAM_GPIO_IER_OFFSET 0x0090 /* Interrupt Enable Register Read/Write */ +#define SAM_GPIO_IERS_OFFSET 0x0094 /* Interrupt Enable Register Set */ +#define SAM_GPIO_IERC_OFFSET 0x0098 /* Interrupt Enable Register Clear */ +#define SAM_GPIO_IERT_OFFSET 0x009c /* Interrupt Enable Register Toggle */ + +/* {IMR1, IMR0} Interrupt Mode + * + * 00 Pin Change + * 01 Rising Edge + * 10 Falling Edge + * 11 Reserved + */ + +#define SAM_GPIO_IMR0_OFFSET 0x00a0 /* Interrupt Mode Register 0 Read/Write */ +#define SAM_GPIO_IMR0S_OFFSET 0x00a4 /* Interrupt Mode Register 0 Set */ +#define SAM_GPIO_IMR0C_OFFSET 0x00a8 /* Interrupt Mode Register 0 Clear */ +#define SAM_GPIO_IMR0T_OFFSET 0x00ac /* Interrupt Mode Register 0 Toggle */ + +#define SAM_GPIO_IMR1_OFFSET 0x00b0 /* Interrupt Mode Register 1 Read/Write */ +#define SAM_GPIO_IMR1S_OFFSET 0x00b4 /* Interrupt Mode Register 1 Set */ +#define SAM_GPIO_IMR1C_OFFSET 0x00b8 /* Interrupt Mode Register 1 Clear */ +#define SAM_GPIO_IMR1T_OFFSET 0x00bc /* Interrupt Mode Register 1 Toggle */ + +#define SAM_GPIO_GFER_OFFSET 0x00c0 /* Glitch Filter Enable Register Read/Write */ +#define SAM_GPIO_GFERS_OFFSET 0x00c4 /* Glitch Filter Enable Register Set */ +#define SAM_GPIO_GFERC_OFFSET 0x00c8 /* Glitch Filter Enable Register Clear */ +#define SAM_GPIO_GFERT_OFFSET 0x00cc /* Glitch Filter Enable Register Toggle */ + +/* Interrupt Flag Register Read (2 registers)*/ + +#define SAM_GPIO_IFR_OFFSET(n) (0x00d0 + (((n) & ~31) >> 3)) +#define SAM_GPIO_IFR0_OFFSET 0x00d0 /* Interrupt Flag Register 0 Read */ +#define SAM_GPIO_IFR1_OFFSET 0x00d4 /* Interrupt Flag Register 0 Read */ + +/* Interrupt Flag Register Clear (2 registers)*/ + +#define SAM_GPIO_IFRC_OFFSET(n) (0x00d8 + (((n) & ~31) >> 3)) +#define SAM_GPIO_IFRC0_OFFSET 0x00d8 /* Interrupt Flag Register 0 Clear */ +#define SAM_GPIO_IFRC1_OFFSET 0x00dc /* Interrupt Flag Register 1 Clear */ + +/* {ODCR1, ODCR0} Interrupt Mode + * + * 00 Lowest drive strength + * 01 ... + * 10 ... + * 11 Highest drive strength + */ + +#define SAM_GPIO_ODCR0_OFFSET 0x0100 /* Output Driving Capability Register 0 Read/Write */ +#define SAM_GPIO_ODCR0S_OFFSET 0x0104 /* Output Driving Capability Register 0 Set */ +#define SAM_GPIO_ODCR0C_OFFSET 0x0108 /* Output Driving Capability Register 0 Clear */ +#define SAM_GPIO_ODCR0T_OFFSET 0x010c /* Output Driving Capability Register 0 Toggle */ + +#define SAM_GPIO_ODCR1_OFFSET 0x0110 /* Output Driving Capability Register 1 Read */ +#define SAM_GPIO_ODCR1S_OFFSET 0x0114 /* Output Driving Capability Register 1 Set */ +#define SAM_GPIO_ODCR1C_OFFSET 0x0118 /* Output Driving Capability Register 1 Clear */ +#define SAM_GPIO_ODCR1T_OFFSET 0x011c /* Output Driving Capability Register 1 Toggle */ + +#define SAM_GPIO_OSRR0_OFFSET 0x0130 /* Output Slew Rate Register 0 Read */ +#define SAM_GPIO_OSRR0S_OFFSET 0x0134 /* Output Slew Rate Register 0 Set */ +#define SAM_GPIO_OSRR0C_OFFSET 0x0138 /* Output Slew Rate Register 0 Clear */ +#define SAM_GPIO_OSRR0T_OFFSET 0x013c /* Output Slew Rate Register 0 Toggle */ + +#define SAM_GPIO_STER_OFFSET 0x0160 /* Schmitt Trigger Enable Register Read */ +#define SAM_GPIO_STERS_OFFSET 0x0164 /* Schmitt Trigger Enable Register Set */ +#define SAM_GPIO_STERC_OFFSET 0x0168 /* Schmitt Trigger Enable Register Clear */ +#define SAM_GPIO_STERT_OFFSET 0x016c /* Schmitt Trigger Enable Register Toggle */ + +#define SAM_GPIO_EVER_OFFSET 0x0180 /* Event Enable Register Read */ +#define SAM_GPIO_EVERS_OFFSET 0x0184 /* Event Enable Register Set */ +#define SAM_GPIO_EVERC_OFFSET 0x0188 /* Event Enable Register Clear */ +#define SAM_GPIO_EVERT_OFFSET 0x018c /* Event Enable Register Toggle */ + +#define SAM_GPIO_PARAMETER_OFFSET 0x01f8 /* Parameter Register Read */ +#define SAM_GPIO_VERSION_OFFSET 0x01fc /* Version Register Read */ + +/* GPIO register adresses ***************************************************************/ + +#define SAM_GPIO_GPER (SAM_GPIO_BASE+SAM_GPIO_GPER_OFFSET) +#define SAM_GPIO_GPERS (SAM_GPIO_BASE+SAM_GPIO_GPERS_OFFSET) +#define SAM_GPIO_GPERC (SAM_GPIO_BASE+SAM_GPIO_GPERC_OFFSET) +#define SAM_GPIO_GPERT (SAM_GPIO_BASE+SAM_GPIO_GPERT_OFFSET) + +#define SAM_GPIO_PMR0 (SAM_GPIO_BASE+SAM_GPIO_PMR0_OFFSET) +#define SAM_GPIO_PMR0S (SAM_GPIO_BASE+SAM_GPIO_PMR0S_OFFSET) +#define SAM_GPIO_PMR0C (SAM_GPIO_BASE+SAM_GPIO_PMR0C_OFFSET) +#define SAM_GPIO_PMR0T (SAM_GPIO_BASE+SAM_GPIO_PMR0T_OFFSET_ + +#define SAM_GPIO_PMR1 (SAM_GPIO_BASE+SAM_GPIO_PMR1_OFFSET) +#define SAM_GPIO_PMR1S (SAM_GPIO_BASE+SAM_GPIO_PMR1S_OFFSET) +#define SAM_GPIO_PMR1C (SAM_GPIO_BASE+SAM_GPIO_PMR1C_OFFSET) +#define SAM_GPIO_PMR1T (SAM_GPIO_BASE+SAM_GPIO_PMR1T_OFFSET) + +#define SAM_GPIO_PMR2 (SAM_GPIO_BASE+SAM_GPIO_PMR2_OFFSET) +#define SAM_GPIO_PMR2S (SAM_GPIO_BASE+SAM_GPIO_PMR2S_OFFSET) +#define SAM_GPIO_PMR2C (SAM_GPIO_BASE+SAM_GPIO_PMR2C_OFFSET) +#define SAM_GPIO_PMR2T (SAM_GPIO_BASE+SAM_GPIO_PMR2T_OFFSET) + +#define SAM_GPIO_ODER (SAM_GPIO_BASE+SAM_GPIO_ODER_OFFSET) +#define SAM_GPIO_ODERS (SAM_GPIO_BASE+SAM_GPIO_ODERS_OFFSET) +#define SAM_GPIO_ODERC (SAM_GPIO_BASE+SAM_GPIO_ODERC_OFFSET) +#define SAM_GPIO_ODERT (SAM_GPIO_BASE+SAM_GPIO_ODERT_OFFSET) + +#define SAM_GPIO_OVR (SAM_GPIO_BASE+SAM_GPIO_OVR_OFFSET) +#define SAM_GPIO_OVRS (SAM_GPIO_BASE+SAM_GPIO_OVRS_OFFSET) +#define SAM_GPIO_OVRC (SAM_GPIO_BASE+SAM_GPIO_OVRC_OFFSET) +#define SAM_GPIO_OVRT (SAM_GPIO_BASE+SAM_GPIO_OVRT_OFFSET) + +/* Pin Value Register Read (4 registers)*/ + +#define SAM_GPIO_PVR(n) (SAM_GPIO_BASE+SAM_GPIO_PVR_OFFSET(n)) +#define SAM_GPIO_PVR0 (SAM_GPIO_BASE+SAM_GPIO_PVR0_OFFSET) +#define SAM_GPIO_PVR1 (SAM_GPIO_BASE+SAM_GPIO_PVR1_OFFSET) +#define SAM_GPIO_PVR2 (SAM_GPIO_BASE+SAM_GPIO_PVR2_OFFSET) +#define SAM_GPIO_PVR3 (SAM_GPIO_BASE+SAM_GPIO_PVR3_OFFSET) + +#define SAM_GPIO_PUER (SAM_GPIO_BASE+SAM_GPIO_PUER_OFFSET) +#define SAM_GPIO_PUERS (SAM_GPIO_BASE+SAM_GPIO_PUERS_OFFSET) +#define SAM_GPIO_PUERC (SAM_GPIO_BASE+SAM_GPIO_PUERC_OFFSET) +#define SAM_GPIO_PUERT (SAM_GPIO_BASE+SAM_GPIO_PUERT_OFFSET) + +#define SAM_GPIO_PDER (SAM_GPIO_BASE+SAM_GPIO_PDER_OFFSET) +#define SAM_GPIO_PDERS (SAM_GPIO_BASE+SAM_GPIO_PDERS_OFFSET) +#define SAM_GPIO_PDERC (SAM_GPIO_BASE+SAM_GPIO_PDERC_OFFSET) +#define SAM_GPIO_PDERT (SAM_GPIO_BASE+SAM_GPIO_PDERT_OFFSET) + +#define SAM_GPIO_IER (SAM_GPIO_BASE+SAM_GPIO_IER_OFFSET) +#define SAM_GPIO_IERS (SAM_GPIO_BASE+SAM_GPIO_IERS_OFFSET) +#define SAM_GPIO_IERC (SAM_GPIO_BASE+SAM_GPIO_IERC_OFFSET) +#define SAM_GPIO_IERT (SAM_GPIO_BASE+SAM_GPIO_IERT_OFFSET) + +#define SAM_GPIO_IMR0 (SAM_GPIO_BASE+SAM_GPIO_IMR0_OFFSET) +#define SAM_GPIO_IMR0S (SAM_GPIO_BASE+SAM_GPIO_IMR0S_OFFSET) +#define SAM_GPIO_IMR0C (SAM_GPIO_BASE+SAM_GPIO_IMR0C_OFFSET) +#define SAM_GPIO_IMR0T (SAM_GPIO_BASE+SAM_GPIO_IMR0T_OFFSET) + +#define SAM_GPIO_IMR1 (SAM_GPIO_BASE+SAM_GPIO_IMR1_OFFSET) +#define SAM_GPIO_IMR1S (SAM_GPIO_BASE+SAM_GPIO_IMR1S_OFFSET) +#define SAM_GPIO_IMR1C (SAM_GPIO_BASE+SAM_GPIO_IMR1C_OFFSET) +#define SAM_GPIO_IMR1T (SAM_GPIO_BASE+SAM_GPIO_IMR1T_OFFSET) + +#define SAM_GPIO_GFER (SAM_GPIO_BASE+SAM_GPIO_GFER_OFFSET) +#define SAM_GPIO_GFERS (SAM_GPIO_BASE+SAM_GPIO_GFERS_OFFSET) +#define SAM_GPIO_GFERC (SAM_GPIO_BASE+SAM_GPIO_GFERC_OFFSET) +#define SAM_GPIO_GFERT (SAM_GPIO_BASE+SAM_GPIO_GFERT_OFFSET) + +/* Interrupt Flag Register Read (2 registers)*/ + +#define SAM_GPIO_IFR(n) (SAM_GPIO_BASE+SAM_GPIO_IFR_OFFSET(n)) +#define SAM_GPIO_IFR0 (SAM_GPIO_BASE+SAM_GPIO_IFR0_OFFSET) +#define SAM_GPIO_IFR1 (SAM_GPIO_BASE+SAM_GPIO_IFR1_OFFSET) + +/* Interrupt Flag Register Clear (2 registers)*/ + +#define SAM_GPIO_IFRC(n) (SAM_GPIO_BASE+SAM_GPIO_IFRC_OFFSET(n)) +#define SAM_GPIO_IFRC0 (SAM_GPIO_BASE+SAM_GPIO_IFRC0_OFFSET) +#define SAM_GPIO_IFRC1 (SAM_GPIO_BASE+SAM_GPIO_IFRC1_OFFSET) + +#define SAM_GPIO_ODCR0 (SAM_GPIO_BASE+SAM_GPIO_ODCR0_OFFSET) +#define SAM_GPIO_ODCR0S (SAM_GPIO_BASE+SAM_GPIO_ODCR0S_OFFSET) +#define SAM_GPIO_ODCR0C (SAM_GPIO_BASE+SAM_GPIO_ODCR0C_OFFSET) +#define SAM_GPIO_ODCR0T (SAM_GPIO_BASE+SAM_GPIO_ODCR0T_OFFSET) + +#define SAM_GPIO_ODCR1 (SAM_GPIO_BASE+SAM_GPIO_ODCR1_OFFSET) +#define SAM_GPIO_ODCR1S (SAM_GPIO_BASE+SAM_GPIO_ODCR1S_OFFSET) +#define SAM_GPIO_ODCR1C (SAM_GPIO_BASE+SAM_GPIO_ODCR1C_OFFSET) +#define SAM_GPIO_ODCR1T (SAM_GPIO_BASE+SAM_GPIO_ODCR1T_OFFSET) + +#define SAM_GPIO_OSRR0 (SAM_GPIO_BASE+SAM_GPIO_OSRR0_OFFSET) +#define SAM_GPIO_OSRR0S (SAM_GPIO_BASE+SAM_GPIO_OSRR0S_OFFSET) +#define SAM_GPIO_OSRR0C (SAM_GPIO_BASE+SAM_GPIO_OSRR0C_OFFSET) +#define SAM_GPIO_OSRR0T (SAM_GPIO_BASE+SAM_GPIO_OSRR0T_OFFSET) + +#define SAM_GPIO_STER (SAM_GPIO_BASE+SAM_GPIO_STER_OFFSET) +#define SAM_GPIO_STERS (SAM_GPIO_BASE+SAM_GPIO_STERS_OFFSET) +#define SAM_GPIO_STERC (SAM_GPIO_BASE+SAM_GPIO_STERC_OFFSET) +#define SAM_GPIO_STERT (SAM_GPIO_BASE+SAM_GPIO_STERT_OFFSET) + +#define SAM_GPIO_EVER (SAM_GPIO_BASE+SAM_GPIO_EVER_OFFSET) +#define SAM_GPIO_EVERS (SAM_GPIO_BASE+SAM_GPIO_EVERS_OFFSET) +#define SAM_GPIO_EVERC (SAM_GPIO_BASE+SAM_GPIO_EVERC_OFFSET) +#define SAM_GPIO_EVERT (SAM_GPIO_BASE+SAM_GPIO_EVERT_OFFSET) + +#define SAM_GPIO_PARAMETER (SAM_GPIO_BASE+SAM_GPIO_PARAMETER_OFFSET) +#define SAM_GPIO_VERSION (SAM_GPIO_BASE+SAM_GPIO_VERSION_OFFSET) + +/* GPIO register bit definitions ********************************************************/ + +/* Common bit definitions for all GPIO registers */ + +#define PIN(n) (1 << (n)) /* Bit n: PIO n */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_GPIO_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h b/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h new file mode 100644 index 0000000000..c65d5dcbef --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h @@ -0,0 +1,399 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4s_pio.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PIO_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PIO_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PIO register offsets *****************************************************************/ + +#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ +#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ +#define SAM_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */ + /* 0x000c: Reserved */ +#define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */ +#define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */ +#define SAM_PIO_OSR_OFFSET 0x0018 /* utput Status Register */ + /* 0x001c: Reserved */ +#define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */ +#define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */ +#define SAM_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */ + /* 0x002c: Reserved */ +#define SAM_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */ +#define SAM_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */ +#define SAM_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */ +#define SAM_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */ +#define SAM_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */ +#define SAM_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */ +#define SAM_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */ +#define SAM_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */ +#define SAM_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */ +#define SAM_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */ +#define SAM_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */ + /* 0x005c: Reserved */ +#define SAM_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */ +#define SAM_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */ +#define SAM_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */ + /* 0x006c: Reserved */ +#define SAM_PIO_ABCDSR1_OFFSET 0x0070 /* Peripheral Select Register 1 */ +#define SAM_PIO_ABCDSR2_OFFSET 0x0074 /* Peripheral Select Register 2 */ + /* 0x0078-0x007c: Reserved */ +#define SAM_PIO_IFSCDR_OFFSET 0x0080 /* SInput Filter Slow Clock Disable Register */ +#define SAM_PIO_IFSCER_OFFSET 0x0084 /* Input Filter Slow Clock Enable Register */ +#define SAM_PIO_IFSCSR_OFFSET 0x0088 /* Input Filter Slow Clock Status Register */ +#define SAM_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */ +#define SAM_PIO_PPDDR_OFFSET 0x0090 /* Pad Pull-down Enable Register */ +#define SAM_PIO_PPDER_OFFSET 0x0094 /* Pad Pull-down Status Register */ +#define SAM_PIO_PPDSR_OFFSET 0x0098 /* Input Filter Slow Clock Disable Register */ + /* 0x009c: Reserved */ +#define SAM_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */ +#define SAM_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */ +#define SAM_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */ + /* 0x00ac: Reserved */ +#define SAM_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */ +#define SAM_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */ +#define SAM_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */ + /* 0x00bc: Reserved */ +#define SAM_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */ +#define SAM_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */ +#define SAM_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */ + /* 0x00cc: Reserved */ +#define SAM_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */ +#define SAM_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */ +#define SAM_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */ + /* 0x00dc: Reserved */ +#define SAM_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */ +#define SAM_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + /* 0x00ec-0x00f8: Reserved */ +#define SAM_PIO_SCHMITT_OFFSET 0x0100 /* Schmitt Trigger Register */ + /* 0x0104-0x14c: Reserved */ +#define SAM_PIO_PCMR_OFFSET 0x0150 /* Parallel Capture Mode Register */ +#define SAM_PIO_PCIER_OFFSET 0x0154 /* Parallel Capture Interrupt Enable Register */ +#define SAM_PIO_PCIDR_OFFSET 0x0158 /* Parallel Capture Interrupt Disable Register */ +#define SAM_PIO_PCIMR_OFFSET 0x015c /* Parallel Capture Interrupt Mask Register */ +#define SAM_PIO_PCISR_OFFSET 0x0160 /* Parallel Capture Interrupt Status Register */ +#define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */ + /* 0x0168-0x018c: Reserved for PDC registers */ + +/* PIO register adresses ****************************************************************/ + +#define PIOA (0) +#define PIOB (1) +#define PIOC (2) +#define NPIO (3) + +#define SAM_PIO_PER(n) (SAM_PIO_BASE(n)+SAM_PIO_PER_OFFSET) +#define SAM_PIO_PDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDR_OFFSET) +#define SAM_PIO_PSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PSR_OFFSET) +#define SAM_PIO_OER(n) (SAM_PIO_BASE(n)+SAM_PIO_OER_OFFSET) +#define SAM_PIO_ODR(n) (SAM_PIO_BASE(n)+SAM_PIO_ODR_OFFSET) +#define SAM_PIO_OSR(n) (SAM_PIO_BASE(n)+SAM_PIO_OSR_OFFSET) +#define SAM_PIO_IFER(n) (SAM_PIO_BASE(n)+SAM_PIO_IFER_OFFSET) +#define SAM_PIO_IFDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFDR_OFFSET) +#define SAM_PIO_IFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFSR_OFFSET) +#define SAM_PIO_SODR(n) (SAM_PIO_BASE(n)+SAM_PIO_SODR_OFFSET) +#define SAM_PIO_CODR(n) (SAM_PIO_BASE(n)+SAM_PIO_CODR_OFFSET) +#define SAM_PIO_ODSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ODSR_OFFSET) +#define SAM_PIO_PDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDSR_OFFSET) +#define SAM_PIO_IER(n) (SAM_PIO_BASE(n)+SAM_PIO_IER_OFFSET) +#define SAM_PIO_IDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IDR_OFFSET) +#define SAM_PIO_IMR(n) (SAM_PIO_BASE(n)+SAM_PIO_IMR_OFFSET) +#define SAM_PIO_ISR(n) (SAM_PIO_BASE(n)+SAM_PIO_ISR_OFFSET) +#define SAM_PIO_MDER(n) (SAM_PIO_BASE(n)+SAM_PIO_MDER_OFFSET) +#define SAM_PIO_MDDR(n) (SAM_PIO_BASE(n)+SAM_PIO_MDDR_OFFSET) +#define SAM_PIO_MDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_MDSR_OFFSET) +#define SAM_PIO_PUDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PUDR_OFFSET) +#define SAM_PIO_PUER(n) (SAM_PIO_BASE(n)+SAM_PIO_PUER_OFFSET) +#define SAM_PIO_PUSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PUSR_OFFSET) +#define SAM_PIO_ABCDSR1(n) (SAM_PIO_BASE(n)+SAM_PIO_ABCDSR1_OFFSET) +#define SAM_PIO_ABCDSR2(n) (SAM_PIO_BASE(n)+SAM_PIO_ABCDSR2_OFFSET) +#define SAM_PIO_IFSCDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFSCDR_OFFSET) +#define SAM_PIO_IFSCER(n) (SAM_PIO_BASE(n)+SAM_PIO_IFSCER_OFFSET) +#define SAM_PIO_IFSCSR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFSCSR_OFFSET) +#define SAM_PIO_SCDR(n) (SAM_PIO_BASE(n)+SAM_PIO_SCDR_OFFSET) +#define SAM_PIO_PPDDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PPDDR_OFFSET) +#define SAM_PIO_PPDER(n) (SAM_PIO_BASE(n)+SAM_PIO_PPDER_OFFSET) +#define SAM_PIO_PPDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PPDSR_OFFSET) +#define SAM_PIO_OWER(n) (SAM_PIO_BASE(n)+SAM_PIO_OWER_OFFSET) +#define SAM_PIO_OWDR(n) (SAM_PIO_BASE(n)+SAM_PIO_OWDR_OFFSET) +#define SAM_PIO_OWSR(n) (SAM_PIO_BASE(n)+SAM_PIO_OWSR_OFFSET) +#define SAM_PIO_AIMER(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMER_OFFSET) +#define SAM_PIO_AIMDR(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIO_AIMMR(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIO_ESR(n) (SAM_PIO_BASE(n)+SAM_PIO_ESR_OFFSET) +#define SAM_PIO_LSR(n) (SAM_PIO_BASE(n)+SAM_PIO_LSR_OFFSET) +#define SAM_PIO_ELSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ELSR_OFFSET) +#define SAM_PIO_FELLSR(n) (SAM_PIO_BASE(n)+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIO_REHLSR(n) (SAM_PIO_BASE(n)+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIO_FRLHSR(n) (SAM_PIO_BASE(n)+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIO_LOCKSR(n) (SAM_PIO_BASE(n)+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIO_WPMR(n) (SAM_PIO_BASE(n)+SAM_PIO_WPMR_OFFSET) +#define SAM_PIO_WPSR(n) (SAM_PIO_BASE(n)+SAM_PIO_WPSR_OFFSET) +#define SAM_PIO_SCHMITT(n) (SAM_PIO_BASE(n)+SAM_PIO_SCHMITT_OFFSET) +#define SAM_PIO_PCMR(n) (SAM_PIO_BASE(n)+SAM_PIO_PCMR_OFFSET) +#define SAM_PIO_PCIER(n) (SAM_PIO_BASE(n)+SAM_PIO_PCIER_OFFSET) +#define SAM_PIO_PCIDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PCIDR_OFFSET) +#define SAM_PIO_PCIMR(n) (SAM_PIO_BASE(n)+SAM_PIO_PCIMR_OFFSET) +#define SAM_PIO_PCISR(n) (SAM_PIO_BASE(n)+SAM_PIO_PCISR_OFFSET) +#define SAM_PIO_PCRHR(n) (SAM_PIO_BASE(n)+SAM_PIO_PCRHR_OFFSET + +#define SAM_PIOA_PER (SAM_PIOA_BASE+SAM_PIO_PER_OFFSET) +#define SAM_PIOA_PDR (SAM_PIOA_BASE+SAM_PIO_PDR_OFFSET) +#define SAM_PIOA_PSR (SAM_PIOA_BASE+SAM_PIO_PSR_OFFSET) +#define SAM_PIOA_OER (SAM_PIOA_BASE+SAM_PIO_OER_OFFSET) +#define SAM_PIOA_ODR (SAM_PIOA_BASE+SAM_PIO_ODR_OFFSET) +#define SAM_PIOA_OSR (SAM_PIOA_BASE+SAM_PIO_OSR_OFFSET) +#define SAM_PIOA_IFER (SAM_PIOA_BASE+SAM_PIO_IFER_OFFSET) +#define SAM_PIOA_IFDR (SAM_PIOA_BASE+SAM_PIO_IFDR_OFFSET) +#define SAM_PIOA_IFSR (SAM_PIOA_BASE+SAM_PIO_IFSR_OFFSET) +#define SAM_PIOA_SODR (SAM_PIOA_BASE+SAM_PIO_SODR_OFFSET) +#define SAM_PIOA_CODR (SAM_PIOA_BASE+SAM_PIO_CODR_OFFSET) +#define SAM_PIOA_ODSR (SAM_PIOA_BASE+SAM_PIO_ODSR_OFFSET) +#define SAM_PIOA_PDSR (SAM_PIOA_BASE+SAM_PIO_PDSR_OFFSET) +#define SAM_PIOA_IER (SAM_PIOA_BASE+SAM_PIO_IER_OFFSET) +#define SAM_PIOA_IDR (SAM_PIOA_BASE+SAM_PIO_IDR_OFFSET) +#define SAM_PIOA_IMR (SAM_PIOA_BASE+SAM_PIO_IMR_OFFSET) +#define SAM_PIOA_ISR (SAM_PIOA_BASE+SAM_PIO_ISR_OFFSET) +#define SAM_PIOA_MDER (SAM_PIOA_BASE+SAM_PIO_MDER_OFFSET) +#define SAM_PIOA_MDDR (SAM_PIOA_BASE+SAM_PIO_MDDR_OFFSET) +#define SAM_PIOA_MDSR (SAM_PIOA_BASE+SAM_PIO_MDSR_OFFSET) +#define SAM_PIOA_PUDR (SAM_PIOA_BASE+SAM_PIO_PUDR_OFFSET) +#define SAM_PIOA_PUER (SAM_PIOA_BASE+SAM_PIO_PUER_OFFSET) +#define SAM_PIOA_PUSR (SAM_PIOA_BASE+SAM_PIO_PUSR_OFFSET) +#define SAM_PIOA_ABCDSR1 (SAM_PIOA_BASE+SAM_PIO_ABCDSR1_OFFSET) +#define SAM_PIOA_ABCDSR2 (SAM_PIOA_BASE+SAM_PIO_ABCDSR2_OFFSET) +#define SAM_PIOA_IFSCDR (SAM_PIOA_BASE+SAM_PIO_IFSCDR_OFFSET) +#define SAM_PIOA_IFSCER (SAM_PIOA_BASE+SAM_PIO_IFSCER_OFFSET) +#define SAM_PIOA_IFSCSR (SAM_PIOA_BASE+SAM_PIO_IFSCSR_OFFSET) +#define SAM_PIOA_SCDR (SAM_PIOA_BASE+SAM_PIO_SCDR_OFFSET) +#define SAM_PIOA_PPDDR (SAM_PIOA_BASE+SAM_PIO_PPDDR_OFFSET) +#define SAM_PIOA_PPDER (SAM_PIOA_BASE+SAM_PIO_PPDER_OFFSET) +#define SAM_PIOA_PPDSR (SAM_PIOA_BASE+SAM_PIO_PPDSR_OFFSET) +#define SAM_PIOA_OWER (SAM_PIOA_BASE+SAM_PIO_OWER_OFFSET) +#define SAM_PIOA_OWDR (SAM_PIOA_BASE+SAM_PIO_OWDR_OFFSET) +#define SAM_PIOA_OWSR (SAM_PIOA_BASE+SAM_PIO_OWSR_OFFSET) +#define SAM_PIOA_AIMER (SAM_PIOA_BASE+SAM_PIO_AIMER_OFFSET) +#define SAM_PIOA_AIMDR (SAM_PIOA_BASE+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIOA_AIMMR (SAM_PIOA_BASE+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIOA_ESR (SAM_PIOA_BASE+SAM_PIO_ESR_OFFSET) +#define SAM_PIOA_LSR (SAM_PIOA_BASE+SAM_PIO_LSR_OFFSET) +#define SAM_PIOA_ELSR (SAM_PIOA_BASE+SAM_PIO_ELSR_OFFSET) +#define SAM_PIOA_FELLSR (SAM_PIOA_BASE+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIOA_REHLSR (SAM_PIOA_BASE+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIOA_FRLHSR (SAM_PIOA_BASE+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIOA_LOCKSR (SAM_PIOA_BASE+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIOA_WPMR (SAM_PIOA_BASE+SAM_PIO_WPMR_OFFSET) +#define SAM_PIOA_WPSR (SAM_PIOA_BASE+SAM_PIO_WPSR_OFFSET) +#define SAM_PIOA_SCHMITT (SAM_PIOA_BASE+SAM_PIO_SCHMITT_OFFSET) +#define SAM_PIOA_PCMR (SAM_PIOA_BASE+SAM_PIO_PCMR_OFFSET) +#define SAM_PIOA_PCIER (SAM_PIOA_BASE+SAM_PIO_PCIER_OFFSET) +#define SAM_PIOA_PCIDR (SAM_PIOA_BASE+SAM_PIO_PCIDR_OFFSET) +#define SAM_PIOA_PCIMR (SAM_PIOA_BASE+SAM_PIO_PCIMR_OFFSET) +#define SAM_PIOA_PCISR (SAM_PIOA_BASE+SAM_PIO_PCISR_OFFSET) +#define SAM_PIOA_PCRHR (SAM_PIOA_BASE+SAM_PIO_PCRHR_OFFSET + +#define SAM_PIOB_PER (SAM_PIOB_BASE+SAM_PIO_PER_OFFSET) +#define SAM_PIOB_PDR (SAM_PIOB_BASE+SAM_PIO_PDR_OFFSET) +#define SAM_PIOB_PSR (SAM_PIOB_BASE+SAM_PIO_PSR_OFFSET) +#define SAM_PIOB_OER (SAM_PIOB_BASE+SAM_PIO_OER_OFFSET) +#define SAM_PIOB_ODR (SAM_PIOB_BASE+SAM_PIO_ODR_OFFSET) +#define SAM_PIOB_OSR (SAM_PIOB_BASE+SAM_PIO_OSR_OFFSET) +#define SAM_PIOB_IFER (SAM_PIOB_BASE+SAM_PIO_IFER_OFFSET) +#define SAM_PIOB_IFDR (SAM_PIOB_BASE+SAM_PIO_IFDR_OFFSET) +#define SAM_PIOB_IFSR (SAM_PIOB_BASE+SAM_PIO_IFSR_OFFSET) +#define SAM_PIOB_SODR (SAM_PIOB_BASE+SAM_PIO_SODR_OFFSET) +#define SAM_PIOB_CODR (SAM_PIOB_BASE+SAM_PIO_CODR_OFFSET) +#define SAM_PIOB_ODSR (SAM_PIOB_BASE+SAM_PIO_ODSR_OFFSET) +#define SAM_PIOB_PDSR (SAM_PIOB_BASE+SAM_PIO_PDSR_OFFSET) +#define SAM_PIOB_IER (SAM_PIOB_BASE+SAM_PIO_IER_OFFSET) +#define SAM_PIOB_IDR (SAM_PIOB_BASE+SAM_PIO_IDR_OFFSET) +#define SAM_PIOB_IMR (SAM_PIOB_BASE+SAM_PIO_IMR_OFFSET) +#define SAM_PIOB_ISR (SAM_PIOB_BASE+SAM_PIO_ISR_OFFSET) +#define SAM_PIOB_MDER (SAM_PIOB_BASE+SAM_PIO_MDER_OFFSET) +#define SAM_PIOB_MDDR (SAM_PIOB_BASE+SAM_PIO_MDDR_OFFSET) +#define SAM_PIOB_MDSR (SAM_PIOB_BASE+SAM_PIO_MDSR_OFFSET) +#define SAM_PIOB_PUDR (SAM_PIOB_BASE+SAM_PIO_PUDR_OFFSET) +#define SAM_PIOB_PUER (SAM_PIOB_BASE+SAM_PIO_PUER_OFFSET) +#define SAM_PIOB_PUSR (SAM_PIOB_BASE+SAM_PIO_PUSR_OFFSET) +#define SAM_PIOB_ABCDSR1 (SAM_PIOB_BASE+SAM_PIO_ABCDSR1_OFFSET) +#define SAM_PIOB_ABCDSR2 (SAM_PIOB_BASE+SAM_PIO_ABCDSR2_OFFSET) +#define SAM_PIOB_IFSCDR (SAM_PIOB_BASE+SAM_PIO_IFSCDR_OFFSET) +#define SAM_PIOB_IFSCER (SAM_PIOB_BASE+SAM_PIO_IFSCER_OFFSET) +#define SAM_PIOB_IFSCSR (SAM_PIOB_BASE+SAM_PIO_IFSCSR_OFFSET) +#define SAM_PIOB_SCDR (SAM_PIOB_BASE+SAM_PIO_SCDR_OFFSET) +#define SAM_PIOB_PPDDR (SAM_PIOB_BASE+SAM_PIO_PPDDR_OFFSET) +#define SAM_PIOB_PPDER (SAM_PIOB_BASE+SAM_PIO_PPDER_OFFSET) +#define SAM_PIOB_PPDSR (SAM_PIOB_BASE+SAM_PIO_PPDSR_OFFSET) +#define SAM_PIOB_OWER (SAM_PIOB_BASE+SAM_PIO_OWER_OFFSET) +#define SAM_PIOB_OWDR (SAM_PIOB_BASE+SAM_PIO_OWDR_OFFSET) +#define SAM_PIOB_OWSR (SAM_PIOB_BASE+SAM_PIO_OWSR_OFFSET) +#define SAM_PIOB_AIMER (SAM_PIOB_BASE+SAM_PIO_AIMER_OFFSET) +#define SAM_PIOB_AIMDR (SAM_PIOB_BASE+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIOB_AIMMR (SAM_PIOB_BASE+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIOB_ESR (SAM_PIOB_BASE+SAM_PIO_ESR_OFFSET) +#define SAM_PIOB_LSR (SAM_PIOB_BASE+SAM_PIO_LSR_OFFSET) +#define SAM_PIOB_ELSR (SAM_PIOB_BASE+SAM_PIO_ELSR_OFFSET) +#define SAM_PIOB_FELLSR (SAM_PIOB_BASE+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIOB_REHLSR (SAM_PIOB_BASE+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIOB_FRLHSR (SAM_PIOB_BASE+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIOB_LOCKSR (SAM_PIOB_BASE+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIOB_WPMR (SAM_PIOB_BASE+SAM_PIO_WPMR_OFFSET) +#define SAM_PIOB_WPSR (SAM_PIOB_BASE+SAM_PIO_WPSR_OFFSET) +#define SAM_PIOB_SCHMITT (SAM_PIOB_BASE+SAM_PIO_SCHMITT_OFFSET) +#define SAM_PIOB_PCMR (SAM_PIOB_BASE+SAM_PIO_PCMR_OFFSET) +#define SAM_PIOB_PCIER (SAM_PIOB_BASE+SAM_PIO_PCIER_OFFSET) +#define SAM_PIOB_PCIDR (SAM_PIOB_BASE+SAM_PIO_PCIDR_OFFSET) +#define SAM_PIOB_PCIMR (SAM_PIOB_BASE+SAM_PIO_PCIMR_OFFSET) +#define SAM_PIOB_PCISR (SAM_PIOB_BASE+SAM_PIO_PCISR_OFFSET) +#define SAM_PIOB_PCRHR (SAM_PIOB_BASE+SAM_PIO_PCRHR_OFFSET + +#define SAM_PIOC_PER (SAM_PIOC_BASE+SAM_PIO_PER_OFFSET) +#define SAM_PIOC_PDR (SAM_PIOC_BASE+SAM_PIO_PDR_OFFSET) +#define SAM_PIOC_PSR (SAM_PIOC_BASE+SAM_PIO_PSR_OFFSET) +#define SAM_PIOC_OER (SAM_PIOC_BASE+SAM_PIO_OER_OFFSET) +#define SAM_PIOC_ODR (SAM_PIOC_BASE+SAM_PIO_ODR_OFFSET) +#define SAM_PIOC_OSR (SAM_PIOC_BASE+SAM_PIO_OSR_OFFSET) +#define SAM_PIOC_IFER (SAM_PIOC_BASE+SAM_PIO_IFER_OFFSET) +#define SAM_PIOC_IFDR (SAM_PIOC_BASE+SAM_PIO_IFDR_OFFSET) +#define SAM_PIOC_IFSR (SAM_PIOC_BASE+SAM_PIO_IFSR_OFFSET) +#define SAM_PIOC_SODR (SAM_PIOC_BASE+SAM_PIO_SODR_OFFSET) +#define SAM_PIOC_CODR (SAM_PIOC_BASE+SAM_PIO_CODR_OFFSET) +#define SAM_PIOC_ODSR (SAM_PIOC_BASE+SAM_PIO_ODSR_OFFSET) +#define SAM_PIOC_PDSR (SAM_PIOC_BASE+SAM_PIO_PDSR_OFFSET) +#define SAM_PIOC_IER (SAM_PIOC_BASE+SAM_PIO_IER_OFFSET) +#define SAM_PIOC_IDR (SAM_PIOC_BASE+SAM_PIO_IDR_OFFSET) +#define SAM_PIOC_IMR (SAM_PIOC_BASE+SAM_PIO_IMR_OFFSET) +#define SAM_PIOC_ISR (SAM_PIOC_BASE+SAM_PIO_ISR_OFFSET) +#define SAM_PIOC_MDER (SAM_PIOC_BASE+SAM_PIO_MDER_OFFSET) +#define SAM_PIOC_MDDR (SAM_PIOC_BASE+SAM_PIO_MDDR_OFFSET) +#define SAM_PIOC_MDSR (SAM_PIOC_BASE+SAM_PIO_MDSR_OFFSET) +#define SAM_PIOC_PUDR (SAM_PIOC_BASE+SAM_PIO_PUDR_OFFSET) +#define SAM_PIOC_PUER (SAM_PIOC_BASE+SAM_PIO_PUER_OFFSET) +#define SAM_PIOC_PUSR (SAM_PIOC_BASE+SAM_PIO_PUSR_OFFSET) +#define SAM_PIOC_ABCDSR1 (SAM_PIOC_BASE+SAM_PIO_ABCDSR1_OFFSET) +#define SAM_PIOC_ABCDSR2 (SAM_PIOC_BASE+SAM_PIO_ABCDSR2_OFFSET) +#define SAM_PIOC_IFSCDR (SAM_PIOC_BASE+SAM_PIO_IFSCDR_OFFSET) +#define SAM_PIOC_IFSCER (SAM_PIOC_BASE+SAM_PIO_IFSCER_OFFSET) +#define SAM_PIOC_IFSCSR (SAM_PIOC_BASE+SAM_PIO_IFSCSR_OFFSET) +#define SAM_PIOC_SCDR (SAM_PIOC_BASE+SAM_PIO_SCDR_OFFSET) +#define SAM_PIOC_PPDDR (SAM_PIOC_BASE+SAM_PIO_PPDDR_OFFSET) +#define SAM_PIOC_PPDER (SAM_PIOC_BASE+SAM_PIO_PPDER_OFFSET) +#define SAM_PIOC_PPDSR (SAM_PIOC_BASE+SAM_PIO_PPDSR_OFFSET) +#define SAM_PIOC_OWER (SAM_PIOC_BASE+SAM_PIO_OWER_OFFSET) +#define SAM_PIOC_OWDR (SAM_PIOC_BASE+SAM_PIO_OWDR_OFFSET) +#define SAM_PIOC_OWSR (SAM_PIOC_BASE+SAM_PIO_OWSR_OFFSET) +#define SAM_PIOC_AIMER (SAM_PIOC_BASE+SAM_PIO_AIMER_OFFSET) +#define SAM_PIOC_AIMDR (SAM_PIOC_BASE+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIOC_AIMMR (SAM_PIOC_BASE+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIOC_ESR (SAM_PIOC_BASE+SAM_PIO_ESR_OFFSET) +#define SAM_PIOC_LSR (SAM_PIOC_BASE+SAM_PIO_LSR_OFFSET) +#define SAM_PIOC_ELSR (SAM_PIOC_BASE+SAM_PIO_ELSR_OFFSET) +#define SAM_PIOC_FELLSR (SAM_PIOC_BASE+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIOC_REHLSR (SAM_PIOC_BASE+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIOC_FRLHSR (SAM_PIOC_BASE+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIOC_LOCKSR (SAM_PIOC_BASE+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIOC_WPMR (SAM_PIOC_BASE+SAM_PIO_WPMR_OFFSET) +#define SAM_PIOC_WPSR (SAM_PIOC_BASE+SAM_PIO_WPSR_OFFSET) +#define SAM_PIOC_SCHMITT (SAM_PIOC_BASE+SAM_PIO_SCHMITT_OFFSET) +#define SAM_PIOC_PCMR (SAM_PIOC_BASE+SAM_PIO_PCMR_OFFSET) +#define SAM_PIOC_PCIER (SAM_PIOC_BASE+SAM_PIO_PCIER_OFFSET) +#define SAM_PIOC_PCIDR (SAM_PIOC_BASE+SAM_PIO_PCIDR_OFFSET) +#define SAM_PIOC_PCIMR (SAM_PIOC_BASE+SAM_PIO_PCIMR_OFFSET) +#define SAM_PIOC_PCISR (SAM_PIOC_BASE+SAM_PIO_PCISR_OFFSET) +#define SAM_PIOC_PCRHR (SAM_PIOC_BASE+SAM_PIO_PCRHR_OFFSET + +/* PIO register bit definitions *********************************************************/ + +/* Common bit definitions for ALMOST all IO registers (exceptions follow) */ + +#define PIO(n) (1 << (n)) /* Bit n: PIO n */ + +/* PIO Write Protect Mode Register */ + +#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT) + +/* PIO Write Protect Status Register */ + +#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT) + +/* PIO Parallel Capture Mode Register */ + +#define PIO_PCMR_PCEN (1 << 0) /* Bit 0: Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_SHIFT (4) /* Bits 4-5: Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE_MASK (3 << PIO_PCMR_DSIZE_SHIFT) +# define PIO_PCMR_DSIZE_BYTE (0 << PIO_PCMR_DSIZE_SHIFT) /* 8-bit data in PIO_PCRHR */ +# define PIO_PCMR_DSIZE_HWORD (1 << PIO_PCMR_DSIZE_SHIFT) /* 16-bit data in PIO_PCRHR */ +# define PIO_PCMR_DSIZE_WORD (2 << PIO_PCMR_DSIZE_SHIFT) /* 32-bit data in PIO_PCRHR */ +#define PIO_PCMR_ALWYS (1 << 9) /* Bit 9: Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (1 << 10) /* Bit 10: Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (1 << 11) /* Bit 11: Parallel Capture Mode First Sample */ + +/* PIO Parallel Capture Interrupt Enable, Disable, Mask, and Status Registers */ + +#define PIOC_PCINT_DRDY (1 << 0) /* Bit 0: Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIOC_PCINT_OVRE (1 << 1) /* Bit 1: Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIOC_PCINT_ENDRX (1 << 2) /* Bit 2: End of Reception Transfer Interrupt Enable */ +#define PIOC_PCINT_RXBUFF (1 << 3) /* Bit 3: Reception Buffer Full Interrupt Enable */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PIO_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pio.h b/nuttx/arch/arm/src/sam34/chip/sam_pio.h index f6cef564bc..e2596475d5 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_pio.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_pio.h @@ -1,7 +1,7 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_pio.h * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -43,272 +43,19 @@ #include #include "chip.h" -#include "chip/sam_memorymap.h" + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "chip/sam3u_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_vectors.h" +#else +# error Unrecognized SAM architecture +#endif /**************************************************************************************** * Pre-processor Definitions ****************************************************************************************/ -/* PIO register offsets *****************************************************************/ - -#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ -#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ -#define SAM_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */ - /* 0x000c: Reserved */ -#define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */ -#define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */ -#define SAM_PIO_OSR_OFFSET 0x0018 /* utput Status Register */ - /* 0x001c: Reserved */ -#define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */ -#define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */ -#define SAM_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */ - /* 0x002c: Reserved */ -#define SAM_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */ -#define SAM_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */ -#define SAM_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */ -#define SAM_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */ -#define SAM_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */ -#define SAM_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */ -#define SAM_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */ -#define SAM_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */ -#define SAM_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */ -#define SAM_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */ -#define SAM_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */ - /* 0x005c: Reserved */ -#define SAM_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */ -#define SAM_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */ -#define SAM_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */ - /* 0x006c: Reserved */ -#define SAM_PIO_ABSR_OFFSET 0x0070 /* Peripheral AB Select Register */ - /* 0x0074-0x007c: Reserved */ -#define SAM_PIO_SCIFSR_OFFSET 0x0080 /* System Clock Glitch Input Filter Select Register */ -#define SAM_PIO_DIFSR_OFFSET 0x0084 /* Debouncing Input Filter Select Register */ -#define SAM_PIO_IFDGSR_OFFSET 0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define SAM_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */ - /* 0x0090-0x009c: Reserved */ -#define SAM_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */ -#define SAM_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */ -#define SAM_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */ - /* 0x00ac: Reserved */ -#define SAM_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */ -#define SAM_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */ -#define SAM_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */ - /* 0x00bc: Reserved */ -#define SAM_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */ -#define SAM_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */ -#define SAM_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */ - /* 0x00cc: Reserved */ -#define SAM_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */ -#define SAM_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */ -#define SAM_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */ - /* 0x00dc: Reserved */ -#define SAM_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */ -#define SAM_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ -#define SAM_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ - /* 0x00ec-0x00f8: Reserved */ - /* 0x0100-0x0144: Reserved */ - -/* PIO register adresses ****************************************************************/ - -#define PIOA (0) -#define PIOB (1) -#define PIOC (2) -#define NPIO (3) - -#define SAM_PIO_PER(n) (SAM_PIO_BASE(n)+SAM_PIO_PER_OFFSET) -#define SAM_PIO_PDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDR_OFFSET) -#define SAM_PIO_PSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PSR_OFFSET) -#define SAM_PIO_OER(n) (SAM_PIO_BASE(n)+SAM_PIO_OER_OFFSET) -#define SAM_PIO_ODR(n) (SAM_PIO_BASE(n)+SAM_PIO_ODR_OFFSET) -#define SAM_PIO_OSR(n) (SAM_PIO_BASE(n)+SAM_PIO_OSR_OFFSET) -#define SAM_PIO_IFER(n) (SAM_PIO_BASE(n)+SAM_PIO_IFER_OFFSET) -#define SAM_PIO_IFDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFDR_OFFSET) -#define SAM_PIO_IFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFSR_OFFSET) -#define SAM_PIO_SODR(n) (SAM_PIO_BASE(n)+SAM_PIO_SODR_OFFSET) -#define SAM_PIO_CODR(n) (SAM_PIO_BASE(n)+SAM_PIO_CODR_OFFSET) -#define SAM_PIO_ODSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ODSR_OFFSET) -#define SAM_PIO_PDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDSR_OFFSET) -#define SAM_PIO_IER(n) (SAM_PIO_BASE(n)+SAM_PIO_IER_OFFSET) -#define SAM_PIO_IDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IDR_OFFSET) -#define SAM_PIO_IMR(n) (SAM_PIO_BASE(n)+SAM_PIO_IMR_OFFSET) -#define SAM_PIO_ISR(n) (SAM_PIO_BASE(n)+SAM_PIO_ISR_OFFSET) -#define SAM_PIO_MDER(n) (SAM_PIO_BASE(n)+SAM_PIO_MDER_OFFSET) -#define SAM_PIO_MDDR(n) (SAM_PIO_BASE(n)+SAM_PIO_MDDR_OFFSET) -#define SAM_PIO_MDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_MDSR_OFFSET) -#define SAM_PIO_PUDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PUDR_OFFSET) -#define SAM_PIO_PUER(n) (SAM_PIO_BASE(n)+SAM_PIO_PUER_OFFSET) -#define SAM_PIO_PUSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PUSR_OFFSET) -#define SAM_PIO_ABSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ABSR_OFFSET) -#define SAM_PIO_SCIFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_SCIFSR_OFFSET) -#define SAM_PIO_DIFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_DIFSR_OFFSET) -#define SAM_PIO_IFDGSR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFDGSR_OFFSET) -#define SAM_PIO_SCDR(n) (SAM_PIO_BASE(n)+SAM_PIO_SCDR_OFFSET) -#define SAM_PIO_OWER(n) (SAM_PIO_BASE(n)+SAM_PIO_OWER_OFFSET) -#define SAM_PIO_OWDR(n) (SAM_PIO_BASE(n)+SAM_PIO_OWDR_OFFSET) -#define SAM_PIO_OWSR(n) (SAM_PIO_BASE(n)+SAM_PIO_OWSR_OFFSET) -#define SAM_PIO_AIMER(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMER_OFFSET) -#define SAM_PIO_AIMDR(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMDR_OFFSET) -#define SAM_PIO_AIMMR(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMMR_OFFSET) -#define SAM_PIO_ESR(n) (SAM_PIO_BASE(n)+SAM_PIO_ESR_OFFSET) -#define SAM_PIO_LSR(n) (SAM_PIO_BASE(n)+SAM_PIO_LSR_OFFSET) -#define SAM_PIO_ELSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ELSR_OFFSET) -#define SAM_PIO_FELLSR(n) (SAM_PIO_BASE(n)+SAM_PIO_FELLSR_OFFSET) -#define SAM_PIO_REHLSR(n) (SAM_PIO_BASE(n)+SAM_PIO_REHLSR_OFFSET) -#define SAM_PIO_FRLHSR(n) (SAM_PIO_BASE(n)+SAM_PIO_FRLHSR_OFFSET) -#define SAM_PIO_LOCKSR(n) (SAM_PIO_BASE(n)+SAM_PIO_LOCKSR_OFFSET) -#define SAM_PIO_WPMR(n) (SAM_PIO_BASE(n)+SAM_PIO_WPMR_OFFSET) -#define SAM_PIO_WPSR(n) (SAM_PIO_BASE(n)+SAM_PIO_WPSR_OFFSET) - -#define SAM_PIOA_PER (SAM_PIOA_BASE+SAM_PIO_PER_OFFSET) -#define SAM_PIOA_PDR (SAM_PIOA_BASE+SAM_PIO_PDR_OFFSET) -#define SAM_PIOA_PSR (SAM_PIOA_BASE+SAM_PIO_PSR_OFFSET) -#define SAM_PIOA_OER (SAM_PIOA_BASE+SAM_PIO_OER_OFFSET) -#define SAM_PIOA_ODR (SAM_PIOA_BASE+SAM_PIO_ODR_OFFSET) -#define SAM_PIOA_OSR (SAM_PIOA_BASE+SAM_PIO_OSR_OFFSET) -#define SAM_PIOA_IFER (SAM_PIOA_BASE+SAM_PIO_IFER_OFFSET) -#define SAM_PIOA_IFDR (SAM_PIOA_BASE+SAM_PIO_IFDR_OFFSET) -#define SAM_PIOA_IFSR (SAM_PIOA_BASE+SAM_PIO_IFSR_OFFSET) -#define SAM_PIOA_SODR (SAM_PIOA_BASE+SAM_PIO_SODR_OFFSET) -#define SAM_PIOA_CODR (SAM_PIOA_BASE+SAM_PIO_CODR_OFFSET) -#define SAM_PIOA_ODSR (SAM_PIOA_BASE+SAM_PIO_ODSR_OFFSET) -#define SAM_PIOA_PDSR (SAM_PIOA_BASE+SAM_PIO_PDSR_OFFSET) -#define SAM_PIOA_IER (SAM_PIOA_BASE+SAM_PIO_IER_OFFSET) -#define SAM_PIOA_IDR (SAM_PIOA_BASE+SAM_PIO_IDR_OFFSET) -#define SAM_PIOA_IMR (SAM_PIOA_BASE+SAM_PIO_IMR_OFFSET) -#define SAM_PIOA_ISR (SAM_PIOA_BASE+SAM_PIO_ISR_OFFSET) -#define SAM_PIOA_MDER (SAM_PIOA_BASE+SAM_PIO_MDER_OFFSET) -#define SAM_PIOA_MDDR (SAM_PIOA_BASE+SAM_PIO_MDDR_OFFSET) -#define SAM_PIOA_MDSR (SAM_PIOA_BASE+SAM_PIO_MDSR_OFFSET) -#define SAM_PIOA_PUDR (SAM_PIOA_BASE+SAM_PIO_PUDR_OFFSET) -#define SAM_PIOA_PUER (SAM_PIOA_BASE+SAM_PIO_PUER_OFFSET) -#define SAM_PIOA_PUSR (SAM_PIOA_BASE+SAM_PIO_PUSR_OFFSET) -#define SAM_PIOA_ABSR (SAM_PIOA_BASE+SAM_PIO_ABSR_OFFSET) -#define SAM_PIOA_SCIFSR (SAM_PIOA_BASE+SAM_PIO_SCIFSR_OFFSET) -#define SAM_PIOA_DIFSR (SAM_PIOA_BASE+SAM_PIO_DIFSR_OFFSET) -#define SAM_PIOA_IFDGSR (SAM_PIOA_BASE+SAM_PIO_IFDGSR_OFFSET) -#define SAM_PIOA_SCDR (SAM_PIOA_BASE+SAM_PIO_SCDR_OFFSET) -#define SAM_PIOA_OWER (SAM_PIOA_BASE+SAM_PIO_OWER_OFFSET) -#define SAM_PIOA_OWDR (SAM_PIOA_BASE+SAM_PIO_OWDR_OFFSET) -#define SAM_PIOA_OWSR (SAM_PIOA_BASE+SAM_PIO_OWSR_OFFSET) -#define SAM_PIOA_AIMER (SAM_PIOA_BASE+SAM_PIO_AIMER_OFFSET) -#define SAM_PIOA_AIMDR (SAM_PIOA_BASE+SAM_PIO_AIMDR_OFFSET) -#define SAM_PIOA_AIMMR (SAM_PIOA_BASE+SAM_PIO_AIMMR_OFFSET) -#define SAM_PIOA_ESR (SAM_PIOA_BASE+SAM_PIO_ESR_OFFSET) -#define SAM_PIOA_LSR (SAM_PIOA_BASE+SAM_PIO_LSR_OFFSET) -#define SAM_PIOA_ELSR (SAM_PIOA_BASE+SAM_PIO_ELSR_OFFSET) -#define SAM_PIOA_FELLSR (SAM_PIOA_BASE+SAM_PIO_FELLSR_OFFSET) -#define SAM_PIOA_REHLSR (SAM_PIOA_BASE+SAM_PIO_REHLSR_OFFSET) -#define SAM_PIOA_FRLHSR (SAM_PIOA_BASE+SAM_PIO_FRLHSR_OFFSET) -#define SAM_PIOA_LOCKSR (SAM_PIOA_BASE+SAM_PIO_LOCKSR_OFFSET) -#define SAM_PIOA_WPMR (SAM_PIOA_BASE+SAM_PIO_WPMR_OFFSET) -#define SAM_PIOA_WPSR (SAM_PIOA_BASE+SAM_PIO_WPSR_OFFSET) - -#define SAM_PIOB_PER (SAM_PIOB_BASE+SAM_PIO_PER_OFFSET) -#define SAM_PIOB_PDR_ (SAM_PIOB_BASE+SAM_PIO_PDR_OFFSET) -#define SAM_PIOB_PSR (SAM_PIOB_BASE+SAM_PIO_PSR_OFFSET) -#define SAM_PIOB_OER (SAM_PIOB_BASE+SAM_PIO_OER_OFFSET) -#define SAM_PIOB_ODR (SAM_PIOB_BASE+SAM_PIO_ODR_OFFSET) -#define SAM_PIOB_OSR (SAM_PIOB_BASE+SAM_PIO_OSR_OFFSET) -#define SAM_PIOB_IFER (SAM_PIOB_BASE+SAM_PIO_IFER_OFFSET) -#define SAM_PIOB_IFDR (SAM_PIOB_BASE+SAM_PIO_IFDR_OFFSET) -#define SAM_PIOB_IFSR (SAM_PIOB_BASE+SAM_PIO_IFSR_OFFSET) -#define SAM_PIOB_SODR (SAM_PIOB_BASE+SAM_PIO_SODR_OFFSET) -#define SAM_PIOB_CODR (SAM_PIOB_BASE+SAM_PIO_CODR_OFFSET) -#define SAM_PIOB_ODSR (SAM_PIOB_BASE+SAM_PIO_ODSR_OFFSET) -#define SAM_PIOB_PDSR (SAM_PIOB_BASE+SAM_PIO_PDSR_OFFSET) -#define SAM_PIOB_IER (SAM_PIOB_BASE+SAM_PIO_IER_OFFSET) -#define SAM_PIOB_IDR (SAM_PIOB_BASE+SAM_PIO_IDR_OFFSET) -#define SAM_PIOB_IMR (SAM_PIOB_BASE+SAM_PIO_IMR_OFFSET) -#define SAM_PIOB_ISR (SAM_PIOB_BASE+SAM_PIO_ISR_OFFSET) -#define SAM_PIOB_MDER (SAM_PIOB_BASE+SAM_PIO_MDER_OFFSET) -#define SAM_PIOB_MDDR (SAM_PIOB_BASE+SAM_PIO_MDDR_OFFSET) -#define SAM_PIOB_MDSR (SAM_PIOB_BASE+SAM_PIO_MDSR_OFFSET) -#define SAM_PIOB_PUDR (SAM_PIOB_BASE+SAM_PIO_PUDR_OFFSET) -#define SAM_PIOB_PUER (SAM_PIOB_BASE+SAM_PIO_PUER_OFFSET) -#define SAM_PIOB_PUSR (SAM_PIOB_BASE+SAM_PIO_PUSR_OFFSET) -#define SAM_PIOB_ABSR (SAM_PIOB_BASE+SAM_PIO_ABSR_OFFSET) -#define SAM_PIOB_SCIFSR (SAM_PIOB_BASE+SAM_PIO_SCIFSR_OFFSET) -#define SAM_PIOB_DIFSR (SAM_PIOB_BASE+SAM_PIO_DIFSR_OFFSET) -#define SAM_PIOB_IFDGSR (SAM_PIOB_BASE+SAM_PIO_IFDGSR_OFFSET) -#define SAM_PIOB_SCDR (SAM_PIOB_BASE+SAM_PIO_SCDR_OFFSET) -#define SAM_PIOB_OWER (SAM_PIOB_BASE+SAM_PIO_OWER_OFFSET) -#define SAM_PIOB_OWDR (SAM_PIOB_BASE+SAM_PIO_OWDR_OFFSET) -#define SAM_PIOB_OWSR (SAM_PIOB_BASE+SAM_PIO_OWSR_OFFSET) -#define SAM_PIOB_AIMER (SAM_PIOB_BASE+SAM_PIO_AIMER_OFFSET) -#define SAM_PIOB_AIMDR (SAM_PIOB_BASE+SAM_PIO_AIMDR_OFFSET) -#define SAM_PIOB_AIMMR (SAM_PIOB_BASE+SAM_PIO_AIMMR_OFFSET) -#define SAM_PIOB_ESR (SAM_PIOB_BASE+SAM_PIO_ESR_OFFSET) -#define SAM_PIOB_LSR (SAM_PIOB_BASE+SAM_PIO_LSR_OFFSET) -#define SAM_PIOB_ELSR (SAM_PIOB_BASE+SAM_PIO_ELSR_OFFSET) -#define SAM_PIOB_FELLSR (SAM_PIOB_BASE+SAM_PIO_FELLSR_OFFSET) -#define SAM_PIOB_REHLSR (SAM_PIOB_BASE+SAM_PIO_REHLSR_OFFSET) -#define SAM_PIOB_FRLHSR (SAM_PIOB_BASE+SAM_PIO_FRLHSR_OFFSET) -#define SAM_PIOB_LOCKSR (SAM_PIOB_BASE+SAM_PIO_LOCKSR_OFFSET) -#define SAM_PIOB_WPMR (SAM_PIOB_BASE+SAM_PIO_WPMR_OFFSET) -#define SAM_PIOB_WPSR (SAM_PIOB_BASE+SAM_PIO_WPSR_OFFSET) - -#define SAM_PIOC_PER (SAM_PIOC_BASE+SAM_PIO_PER_OFFSET) -#define SAM_PIOC_PDR_ (SAM_PIOC_BASE+SAM_PIO_PDR_OFFSET) -#define SAM_PIOC_PSR (SAM_PIOC_BASE+SAM_PIO_PSR_OFFSET) -#define SAM_PIOC_OER (SAM_PIOC_BASE+SAM_PIO_OER_OFFSET) -#define SAM_PIOC_ODR (SAM_PIOC_BASE+SAM_PIO_ODR_OFFSET) -#define SAM_PIOC_OSR (SAM_PIOC_BASE+SAM_PIO_OSR_OFFSET) -#define SAM_PIOC_IFER (SAM_PIOC_BASE+SAM_PIO_IFER_OFFSET) -#define SAM_PIOC_IFDR (SAM_PIOC_BASE+SAM_PIO_IFDR_OFFSET) -#define SAM_PIOC_IFSR (SAM_PIOC_BASE+SAM_PIO_IFSR_OFFSET) -#define SAM_PIOC_SODR (SAM_PIOC_BASE+SAM_PIO_SODR_OFFSET) -#define SAM_PIOC_CODR (SAM_PIOC_BASE+SAM_PIO_CODR_OFFSET) -#define SAM_PIOC_ODSR (SAM_PIOC_BASE+SAM_PIO_ODSR_OFFSET) -#define SAM_PIOC_PDSR (SAM_PIOC_BASE+SAM_PIO_PDSR_OFFSET) -#define SAM_PIOC_IER (SAM_PIOC_BASE+SAM_PIO_IER_OFFSET) -#define SAM_PIOC_IDR (SAM_PIOC_BASE+SAM_PIO_IDR_OFFSET) -#define SAM_PIOC_IMR (SAM_PIOC_BASE+SAM_PIO_IMR_OFFSET) -#define SAM_PIOC_ISR (SAM_PIOC_BASE+SAM_PIO_ISR_OFFSET) -#define SAM_PIOC_MDER (SAM_PIOC_BASE+SAM_PIO_MDER_OFFSET) -#define SAM_PIOC_MDDR (SAM_PIOC_BASE+SAM_PIO_MDDR_OFFSET) -#define SAM_PIOC_MDSR (SAM_PIOC_BASE+SAM_PIO_MDSR_OFFSET) -#define SAM_PIOC_PUDR (SAM_PIOC_BASE+SAM_PIO_PUDR_OFFSET) -#define SAM_PIOC_PUER (SAM_PIOC_BASE+SAM_PIO_PUER_OFFSET) -#define SAM_PIOC_PUSR (SAM_PIOC_BASE+SAM_PIO_PUSR_OFFSET) -#define SAM_PIOC_ABSR (SAM_PIOC_BASE+SAM_PIO_ABSR_OFFSET) -#define SAM_PIOC_SCIFSR (SAM_PIOC_BASE+SAM_PIO_SCIFSR_OFFSET) -#define SAM_PIOC_DIFSR (SAM_PIOC_BASE+SAM_PIO_DIFSR_OFFSET) -#define SAM_PIOC_IFDGSR (SAM_PIOC_BASE+SAM_PIO_IFDGSR_OFFSET) -#define SAM_PIOC_SCDR (SAM_PIOC_BASE+SAM_PIO_SCDR_OFFSET) -#define SAM_PIOC_OWER (SAM_PIOC_BASE+SAM_PIO_OWER_OFFSET) -#define SAM_PIOC_OWDR (SAM_PIOC_BASE+SAM_PIO_OWDR_OFFSET) -#define SAM_PIOC_OWSR (SAM_PIOC_BASE+SAM_PIO_OWSR_OFFSET) -#define SAM_PIOC_AIMER (SAM_PIOC_BASE+SAM_PIO_AIMER_OFFSET) -#define SAM_PIOC_AIMDR (SAM_PIOC_BASE+SAM_PIO_AIMDR_OFFSET) -#define SAM_PIOC_AIMMR (SAM_PIOC_BASE+SAM_PIO_AIMMR_OFFSET) -#define SAM_PIOC_ESR (SAM_PIOC_BASE+SAM_PIO_ESR_OFFSET) -#define SAM_PIOC_LSR (SAM_PIOC_BASE+SAM_PIO_LSR_OFFSET) -#define SAM_PIOC_ELSR (SAM_PIOC_BASE+SAM_PIO_ELSR_OFFSET) -#define SAM_PIOC_FELLSR (SAM_PIOC_BASE+SAM_PIO_FELLSR_OFFSET) -#define SAM_PIOC_REHLSR (SAM_PIOC_BASE+SAM_PIO_REHLSR_OFFSET) -#define SAM_PIOC_FRLHSR (SAM_PIOC_BASE+SAM_PIO_FRLHSR_OFFSET) -#define SAM_PIOC_LOCKSR (SAM_PIOC_BASE+SAM_PIO_LOCKSR_OFFSET) -#define SAM_PIOC_WPMR (SAM_PIOC_BASE+SAM_PIO_WPMR_OFFSET) -#define SAM_PIOC_WPSR (SAM_PIOC_BASE+SAM_PIO_WPSR_OFFSET) - -/* PIO register bit definitions *********************************************************/ - -/* Common bit definitions for ALMOST all IO registers (exceptions follow) */ - -#define PIO(n) (1<<(n)) /* Bit n: PIO n */ - -/* PIO Write Protect Mode Register */ - -#define PIO_WPMR_WPEN 1 << 0) /* Bit 0: Write Protect Enable */ -#define PIO_WPMR_WPKEY_SHIFT 8) /* Bits 8-31: Write Protect KEY */ -#define PIO_WPMR_WPKEY_MASK 0xffffff << PIO_WPMR_WPKEY_SHIFT) - -/* PIO Write Protect Status Register */ - -#define PIO_WPSR_WPVS 1 << 0) /* Bit 0: Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC_SHIFT 8) /* Bits 8-23: Write Protect Violation Source */ -#define PIO_WPSR_WPVSRC_MASK 0xffff << PIO_WPSR_WPVSRC_SHIFT) - /**************************************************************************************** * Public Types ****************************************************************************************/ diff --git a/nuttx/arch/arm/src/sam34/sam_allocateheap.c b/nuttx/arch/arm/src/sam34/sam_allocateheap.c index bf765462e5..390234b710 100644 --- a/nuttx/arch/arm/src/sam34/sam_allocateheap.c +++ b/nuttx/arch/arm/src/sam34/sam_allocateheap.c @@ -224,6 +224,7 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void up_addregion(void) { +#if CONFIG_SAM34_SRAM1_SIZE > 0 /* Allow user access to the heap memory */ sam_mpu_uheap(SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE); @@ -232,7 +233,7 @@ void up_addregion(void) kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE); -#if CONFIG_MM_REGIONS > 2 +#if CONFIG_MM_REGIONS > 2 && CONFIG_SAM34_NFCSRAM_SIZE > 0 /* Allow user access to the heap memory */ sam_mpu_uheap(SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE); @@ -240,6 +241,8 @@ void up_addregion(void) /* Add the region */ kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE); -#endif + +#endif /* CONFIG_MM_REGIONS > 2 && CONFIG_SAM34_NFCSRAM_SIZE > 0 */ +#endif /* CONFIG_SAM34_SRAM1_SIZE > 0 */ } -#endif +#endif /* CONFIG_MM_REGIONS > 1 */ From 1344f8cc1c7e76dd50752b3e34ccf19dea9619cb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 4 Jun 2013 13:33:30 -0600 Subject: [PATCH 27/41] Create SAM4L GPIO driver header file --- nuttx/ChangeLog | 4 +- nuttx/arch/arm/src/sam34/sam3u_gpio.h | 184 +++++++++++++ nuttx/arch/arm/src/sam34/sam4l_gpio.h | 359 ++++++++++++++++++++++++++ nuttx/arch/arm/src/sam34/sam_gpio.c | 16 +- nuttx/arch/arm/src/sam34/sam_gpio.h | 114 +------- 5 files changed, 566 insertions(+), 111 deletions(-) create mode 100644 nuttx/arch/arm/src/sam34/sam3u_gpio.h create mode 100644 nuttx/arch/arm/src/sam34/sam4l_gpio.h diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 66f5286b87..08ef5784f7 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4891,4 +4891,6 @@ important for the STM32 F4 which may have SPI data buffers allocated on the stack in CCM memory which cannot support the DMA. From Petteri Aimonen (2013-6-4). - + * nuttx/arch/arm/src/sam34/sam4l_gpio.h: Created GPIO driver + header file for the SAM4L. Also renamed the SAM3U header + file to sam3u_gpio.h (2013-6-4). diff --git a/nuttx/arch/arm/src/sam34/sam3u_gpio.h b/nuttx/arch/arm/src/sam34/sam3u_gpio.h new file mode 100644 index 0000000000..7a9fea1ca1 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam3u_gpio.h @@ -0,0 +1,184 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam3u_gpio.h + * + * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H +#define __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Bit-encoded input to sam_configgpio() ********************************************/ + +/* 16-bit Encoding: + * MMCC CII. VPPB BBBB + */ + +/* Input/Output mode: + * + * MM.. .... .... .... + */ + +#define GPIO_MODE_SHIFT (14) /* Bits 14-15: GPIO mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */ +# define GPIO_PERIPHA (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */ +# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */ + +/* These bits set the configuration of the pin: + * ..CC C... .... .... + */ + +#define GPIO_CFG_SHIFT (11) /* Bits 11-13: GPIO configuration bits */ +#define GPIO_CFG_MASK (7 << GPIO_CFG_SHIFT) +# define GPIO_CFG_DEFAULT (0 << GPIO_CFG_SHIFT) /* Default, no attribute */ +# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */ +# define GPIO_CFG_DEGLITCH (2 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */ +# define GPIO_CFG_OPENDRAIN (4 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */ + +/* Additional interrupt modes: + * .... .II. .... .... + */ + +#define GPIO_INT_SHIFT (9) /* Bits 9-10: GPIO configuration bits */ +#define GPIO_INT_MASK (3 << GPIO_INT_SHIFT) +# define GPIO_INT_LEVEL (1 << 10) /* Bit 10: Level detection interrupt */ +# define GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */ +# define GPIO_INT_HIGHLEVEL (1 << 9) /* Bit 9: High level detection interrupt */ +# define GPIO_INT_LOWLEVEL (0) /* (vs. Low level detection interrupt) */ +# define GPIO_INT_RISING (1 << 9) /* Bit 9: Rising edge detection interrupt */ +# define GPIO_INT_FALLING (0) /* (vs. Falling edge detection interrupt) */ + +/* If the pin is an GPIO output, then this identifies the initial output value: + * .... .... V... .... + */ + +#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */ +#define GPIO_OUTPUT_CLEAR (0) + +/* This identifies the GPIO port: + * .... .... .PP. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */ +#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT_PIOA (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT_PIOB (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT) + +/* This identifies the bit in the port: + * .... .... ...B BBBB + */ + +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/* Must be big enough to hold the 16-bit encoding */ + +typedef uint16_t gpio_pinset_t; + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H */ diff --git a/nuttx/arch/arm/src/sam34/sam4l_gpio.h b/nuttx/arch/arm/src/sam34/sam4l_gpio.h new file mode 100644 index 0000000000..2a65ac134e --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam4l_gpio.h @@ -0,0 +1,359 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam4l_gpio.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM4L_GPIO_H +#define __ARCH_ARM_SRC_SAM34_SAM4L_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Bit-encoded input to sam_configgpio() ********************************************/ + +/* 24-bit Encoding. This could be compacted into 16-bits by making the bit usage + * mode specific. However, by giving each bit field a unique position, we handle + * bad combinations of properties safely. + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: MMRR .... .... IIGT .PPB BBBB + * GPIO Output: MM.. .... DDSV .... .PPB BBBB + * Peripheral: MM.. FFFE .... IIG. .PPB BBBB + * ------------ ----------------------------- + * MMRR FFFE DDSV IIGT .PPB BBBB + */ + +/* Input/output/peripheral mode: + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: MM.. .... .... .... .... .... + * GPIO Output: MM.. .... .... .... .... .... + * Peripheral: MM.. .... .... .... .... .... + */ + +#define GPIO_MODE_SHIFT (22) /* Bits 22-23: GPIO mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO Input */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO Output */ +# define GPIO_PERIPHERAL (2 << GPIO_MODE_SHIFT) /* Controlled by peripheral */ +# define GPIO_INTERRUPT (3 << GPIO_MODE_SHIFT) /* Interrupting input */ + +/* Pull-up/down resistor control for inputs + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: ..RR .... .... .... .... .... + * GPIO Output: .... .... .... .... .... .... + * Peripheral: .... .... .... .... .... .... + */ + +#define GPIO_PULL_SHIFT (20) /* Bits 20-21: Pull-up/down resistor control */ +#define GPIO_PULL_MASK (3 << GPIO_FUNC_SHIFT) +# define GPIO_PULL_NONE (0 << GPIO_FUNC_SHIFT) +# define GPIO_PULL_UP (1 << GPIO_FUNC_SHIFT) +# define GPIO_PULL_DOWN (2 << GPIO_FUNC_SHIFT) +# define GPIO_PULL_BUSKEEPER (3 << GPIO_FUNC_SHIFT) + +/* Peripheral Function + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... .... .... .... + * GPIO Output: .... .... .... .... .... .... + * Peripheral: .... FFF. .... .... .... .... + */ + +#define GPIO_FUNC_SHIFT (17) /* Bits 17-19: Peripheral function */ +#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) +# define _GPIO_FUNCA (0 << GPIO_FUNC_SHIFT) /* Function A */ +# define _GPIO_FUNCB (1 << GPIO_FUNC_SHIFT) /* Function B */ +# define _GPIO_FUNCC (2 << GPIO_FUNC_SHIFT) /* Function C */ +# define _GPIO_FUNCD (3 << GPIO_FUNC_SHIFT) /* Function D */ +# define _GPIO_FUNCE (4 << GPIO_FUNC_SHIFT) /* Function E */ +# define _GPIO_FUNCF (5 << GPIO_FUNC_SHIFT) /* Function F */ +# define _GPIO_FUNCG (6 << GPIO_FUNC_SHIFT) /* Function G */ +# define _GPIO_FUNCH (7 << GPIO_FUNC_SHIFT) /* Function H */ + +/* Extended input/output/peripheral mode: + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... .... .... .... + * GPIO Output: .... .... .... .... .... .... + * Peripheral: MM.. FFF. .... .... .... .... + */ + +# define GPIO_FUNCA (GPIO_PERIPHERAL | _GPIO_FUNCA) /* Function A */ +# define GPIO_FUNCB (GPIO_PERIPHERAL | _GPIO_FUNCB) /* Function B */ +# define GPIO_FUNCC (GPIO_PERIPHERAL | _GPIO_FUNCC) /* Function C */ +# define GPIO_FUNCD (GPIO_PERIPHERAL | _GPIO_FUNCD) /* Function D */ +# define GPIO_FUNCE (GPIO_PERIPHERAL | _GPIO_FUNCE) /* Function E */ +# define GPIO_FUNCF (GPIO_PERIPHERAL | _GPIO_FUNCF) /* Function F */ +# define GPIO_FUNCG (GPIO_PERIPHERAL | _GPIO_FUNCG) /* Function G */ +# define GPIO_FUNCH (GPIO_PERIPHERAL | _GPIO_FUNCH) /* Function H */ + +/* Peripheral event control + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... .... .... .... + * GPIO Output: .... .... .... .... .... .... + * Peripheral: .... ...E .... .... .... .... + */ + +#define GPIO_SCHMITT_TRIGGER (1 << 16) /* Bit 16: Enable peripheral events */ + +/* Output drive control + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... .... .... .... + * GPIO Output: .... .... DD.. .... .... .... + * Peripheral: .... .... .... .... .... .... + */ + +#define GPIO_DRIVE_SHIFT (14) /* Bits 14-15: Interrupting input control */ +#define GPIO_DRIVE_MASK (3 << GPIO_INT_SHIFT) /* Lowest drive strength*/ +# define GPIO_DRIVE_LOW (0 << GPIO_INT_SHIFT) +# define GPIO_DRIVE_MEDLOW (1 << GPIO_INT_SHIFT) +# define GPIO_DRIVE_MEDHIGH (2 << GPIO_INT_SHIFT) +# define GPIO_DRIVE_HIGH (3 << GPIO_INT_SHIFT) /* Highest drive strength */ + +/* Output slew rate control + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... .... .... .... + * GPIO Output: .... .... ..S. .... .... .... + * Peripheral: .... .... .... .... .... .... + */ + +#define GPIO_SLEW (1 << 13) /* Bit 13: Enable output slew control */ + +/* If the pin is an GPIO output, then this identifies the initial output value: + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... .... .... .... + * GPIO Output: .... .... ...V .... .... .... + * Peripheral: .... .... .... .... .... .... + */ + +#define GPIO_OUTPUT_SET (1 << 12) /* Bit 12: Inital value of output */ +#define GPIO_OUTPUT_CLEAR (0) + +/* Selections for an interrupting input and peripheral events: + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... II.. .... .... + * GPIO Output: .... .... .... .... .... .... + * Peripheral: .... .... .... II.. .... .... + */ + +#define GPIO_INT_SHIFT (10) /* Bits 10-11: Interrupting input control */ +#define GPIO_INT_MASK (3 << GPIO_INT_SHIFT) +# define GPIO_INT_CHANGE (0 << GPIO_INT_SHIFT) /* Pin change */ +# define GPIO_INT_RISING (1 << GPIO_INT_SHIFT) /* Rising edge */ +# define GPIO_INT_FALLING (2 << GPIO_INT_SHIFT) /* Falling edge */ + +/* Enable input/periphal glitch filter + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... ..G. .... .... + * GPIO Output: .... .... .... .... .... .... + * Peripheral: .... .... .... ..G. .... .... + */ + +#define GPIO_GLITCH_FILTER (1 << 9) /* Bit 9: Enable input/peripheral glitch filter */ + +/* Input Schmitt trigger + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... ...T .... .... + * GPIO Output: .... .... .... .... .... .... + * Peripheral: .... .... .... .... .... .... + */ + +#define GPIO_SCHMITT_TRIGGER (1 << 8) /* Bit 8: Enable Input Schmitt trigger */ + +/* This identifies the GPIO port: + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... .... .PP. .... + * GPIO Output: .... .... .... .... .PP. .... + * Peripheral: .... .... .... .... .PP. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */ +#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT) +# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) + +/* This identifies the bit in the port: + * + * MODE BITFIELDS + * ------------ ----------------------------- + * 2222 1111 1111 1100 0000 0000 + * 3210 9876 5432 1098 7654 3210 + * ------------ ----------------------------- + * GPIO Input: .... .... .... .... ...B BBBB + * GPIO Output: .... .... .... .... ...B BBBB + * Peripheral: .... .... .... .... ...B BBBB + */ + +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/* Must be big enough to hold the 24-bit encoding */ + +typedef uint32_t gpio_pinset_t; + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM4L_GPIO_H */ diff --git a/nuttx/arch/arm/src/sam34/sam_gpio.c b/nuttx/arch/arm/src/sam34/sam_gpio.c index 123c3d4b90..0924857b94 100644 --- a/nuttx/arch/arm/src/sam34/sam_gpio.c +++ b/nuttx/arch/arm/src/sam34/sam_gpio.c @@ -81,7 +81,7 @@ static const char g_portchar[4] = { 'A', 'B', 'C', 'D' }; * ****************************************************************************/ -static inline uintptr_t sam_gpiobase(uint16_t cfgset) +static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset) { int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; return SAM_PION_BASE(port); @@ -95,7 +95,7 @@ static inline uintptr_t sam_gpiobase(uint16_t cfgset) * ****************************************************************************/ -static inline int sam_gpiopin(uint16_t cfgset) +static inline int sam_gpiopin(gpio_pinset_t cfgset) { return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT); } @@ -109,7 +109,7 @@ static inline int sam_gpiopin(uint16_t cfgset) ****************************************************************************/ static inline int sam_configinput(uintptr_t base, uint32_t pin, - uint16_t cfgset) + gpio_pinset_t cfgset) { /* Disable interrupts on the pin */ @@ -159,7 +159,7 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin, ****************************************************************************/ static inline int sam_configoutput(uintptr_t base, uint32_t pin, - uint16_t cfgset) + gpio_pinset_t cfgset) { /* Disable interrupts on the pin */ @@ -215,7 +215,7 @@ static inline int sam_configoutput(uintptr_t base, uint32_t pin, ****************************************************************************/ static inline int sam_configperiph(uintptr_t base, uint32_t pin, - uint16_t cfgset) + gpio_pinset_t cfgset) { uint32_t regval; @@ -265,7 +265,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, * ****************************************************************************/ -int sam_configgpio(uint16_t cfgset) +int sam_configgpio(gpio_pinset_t cfgset) { uintptr_t base = sam_gpiobase(cfgset); uint32_t pin = sam_gpiopin(cfgset); @@ -301,7 +301,7 @@ int sam_configgpio(uint16_t cfgset) * ****************************************************************************/ -void sam_gpiowrite(uint16_t pinset, bool value) +void sam_gpiowrite(gpio_pinset_t pinset, bool value) { uintptr_t base = sam_gpiobase(pinset); uint32_t pin = sam_gpiopin(pinset); @@ -324,7 +324,7 @@ void sam_gpiowrite(uint16_t pinset, bool value) * ****************************************************************************/ -bool sam_gpioread(uint16_t pinset) +bool sam_gpioread(gpio_pinset_t pinset) { uintptr_t base = sam_gpiobase(pinset); uint32_t pin = sam_gpiopin(pinset); diff --git a/nuttx/arch/arm/src/sam34/sam_gpio.h b/nuttx/arch/arm/src/sam34/sam_gpio.h index 3324cd3b35..53f36c8fb3 100644 --- a/nuttx/arch/arm/src/sam34/sam_gpio.h +++ b/nuttx/arch/arm/src/sam34/sam_gpio.h @@ -47,6 +47,14 @@ #include "chip.h" +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "sam3u_gpio.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "sam4l_gpio.h" +#else +# error Unrecognized SAM architecture +#endif + /************************************************************************************ * Definitions ************************************************************************************/ @@ -63,104 +71,6 @@ # undef CONFIG_DEBUG_GPIO #endif -/* Bit-encoded input to sam_configgpio() ********************************************/ - -/* 16-bit Encoding: - * MMCC CII. VPPB BBBB - */ - -/* Input/Output mode: - * - * MM.. .... .... .... - */ - -#define GPIO_MODE_SHIFT (14) /* Bits 14-15: GPIO mode */ -#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) -# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */ -# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */ -# define GPIO_PERIPHA (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */ -# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */ - -/* These bits set the configuration of the pin: - * ..CC C... .... .... - */ - -#define GPIO_CFG_SHIFT (11) /* Bits 11-13: GPIO configuration bits */ -#define GPIO_CFG_MASK (7 << GPIO_CFG_SHIFT) -# define GPIO_CFG_DEFAULT (0 << GPIO_CFG_SHIFT) /* Default, no attribute */ -# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */ -# define GPIO_CFG_DEGLITCH (2 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */ -# define GPIO_CFG_OPENDRAIN (4 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */ - -/* Additional interrupt modes: - * .... .II. .... .... - */ - -#define GPIO_INT_SHIFT (9) /* Bits 9-10: GPIO configuration bits */ -#define GPIO_INT_MASK (3 << GPIO_INT_SHIFT) -# define GPIO_INT_LEVEL (1 << 10) /* Bit 10: Level detection interrupt */ -# define GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */ -# define GPIO_INT_HIGHLEVEL (1 << 9) /* Bit 9: High level detection interrupt */ -# define GPIO_INT_LOWLEVEL (0) /* (vs. Low level detection interrupt) */ -# define GPIO_INT_RISING (1 << 9) /* Bit 9: Rising edge detection interrupt */ -# define GPIO_INT_FALLING (0) /* (vs. Falling edge detection interrupt) */ - -/* If the pin is an GPIO output, then this identifies the initial output value: - * .... .... V... .... - */ - -#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */ -#define GPIO_OUTPUT_CLEAR (0) - -/* This identifies the GPIO port: - * .... .... .PP. .... - */ - -#define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */ -#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT) -# define GPIO_PORT_PIOA (0 << GPIO_PORT_SHIFT) -# define GPIO_PORT_PIOB (1 << GPIO_PORT_SHIFT) -# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT) - -/* This identifies the bit in the port: - * .... .... ...B BBBB - */ - -#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ -#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) -#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) -#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) -#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) -#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) -#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) -#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) -#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) -#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) -#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) -#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) -#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) -#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) -#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) -#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) -#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) -#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) -#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) -#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) -#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) -#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) -#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) -#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) -#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) -#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) -#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) -#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) -#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) -#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) -#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) -#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) -#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) -#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) - /************************************************************************************ * Public Types ************************************************************************************/ @@ -210,7 +120,7 @@ void sam_gpioirqinitialize(void); * ************************************************************************************/ -int sam_configgpio(uint16_t cfgset); +int sam_configgpio(gpio_pinset_t cfgset); /************************************************************************************ * Name: sam_gpiowrite @@ -220,7 +130,7 @@ int sam_configgpio(uint16_t cfgset); * ************************************************************************************/ -void sam_gpiowrite(uint16_t pinset, bool value); +void sam_gpiowrite(gpio_pinset_t pinset, bool value); /************************************************************************************ * Name: sam_gpioread @@ -230,7 +140,7 @@ void sam_gpiowrite(uint16_t pinset, bool value); * ************************************************************************************/ -bool sam_gpioread(uint16_t pinset); +bool sam_gpioread(gpio_pinset_t pinset); /************************************************************************************ * Name: sam_gpioirq @@ -241,7 +151,7 @@ bool sam_gpioread(uint16_t pinset); ************************************************************************************/ #ifdef CONFIG_GPIO_IRQ -void sam_gpioirq(uint16_t pinset); +void sam_gpioirq(gpio_pinset_t pinset); #else # define sam_gpioirq(pinset) #endif From 9172affc0d3603a09cf55ea169715acb87dc1f8e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 4 Jun 2013 15:12:56 -0600 Subject: [PATCH 28/41] Add SAM4L GPIO driver --- nuttx/ChangeLog | 3 + nuttx/arch/arm/src/sam34/Make.defs | 10 +- nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h | 42 +- .../src/sam34/{sam_gpio.c => sam3u_gpio.c} | 2 +- nuttx/arch/arm/src/sam34/sam4l_gpio.c | 569 ++++++++++++++++++ nuttx/arch/arm/src/sam34/sam4l_gpio.h | 24 +- 6 files changed, 609 insertions(+), 41 deletions(-) rename nuttx/arch/arm/src/sam34/{sam_gpio.c => sam3u_gpio.c} (99%) create mode 100644 nuttx/arch/arm/src/sam34/sam4l_gpio.c diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 08ef5784f7..fcde5f0c28 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4894,3 +4894,6 @@ * nuttx/arch/arm/src/sam34/sam4l_gpio.h: Created GPIO driver header file for the SAM4L. Also renamed the SAM3U header file to sam3u_gpio.h (2013-6-4). + * nuttx/arch/arm/src/sam34/sam4l_gpio.c: Created GPIO driver for + the SAM4L (2013-6-4). + diff --git a/nuttx/arch/arm/src/sam34/Make.defs b/nuttx/arch/arm/src/sam34/Make.defs index 813bcbe4c0..683751bb5d 100644 --- a/nuttx/arch/arm/src/sam34/Make.defs +++ b/nuttx/arch/arm/src/sam34/Make.defs @@ -78,11 +78,17 @@ endif CHIP_ASRCS = CHIP_CSRCS = sam_allocateheap.c sam_clockconfig.c sam_gpioirq.c -CHIP_CSRCS += sam_irq.c sam_lowputc.c sam_gpio.c sam_serial.c -CHIP_CSRCS += sam_start.c sam_timerisr.c +CHIP_CSRCS += sam_irq.c sam_lowputc.c sam_serial.c sam_start.c +CHIP_CSRCS += sam_timerisr.c # Configuration-dependent SAM3/4 files +ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y) +CHIP_CSRCS += sam4l_gpio.c +else +CHIP_CSRCS += sam3u_gpio.c +endif + ifeq ($(CONFIG_NUTTX_KERNEL),y) CHIP_CSRCS += sam_userspace.c sam_mpuinit.c endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h index d180b2b929..4927ab7066 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h @@ -58,10 +58,10 @@ /* {PMR2, PMR1, PMR0} Selected Peripheral Function * - * 000 GPIO 100 D - * 001 A 101 E - * 010 B 110 F - * 011 C 111 G + * 000 A 100 E + * 001 B 101 F + * 010 C 110 G + * 011 D 111 H * * NOTE: Labeling in the data sheet is inconsistent. In the pin multiplexing table, * It shows GPIO functions A-G with 000 apparently corresponding to the GPIO. In the @@ -96,11 +96,7 @@ /* Pin Value Register Read (4 registers)*/ -#define SAM_GPIO_PVR_OFFSET(n) (0x0060 + (((n) & ~31) >> 3)) -#define SAM_GPIO_PVR0_OFFSET 0x0060 /* Pin Value Register 0 Read*/ -#define SAM_GPIO_PVR1_OFFSET 0x0064 /* Pin Value Register 1 Read*/ -#define SAM_GPIO_PVR2_OFFSET 0x0068 /* Pin Value Register 2 Read*/ -#define SAM_GPIO_PVR3_OFFSET 0x006c /* Pin Value Register 3 Read*/ +#define SAM_GPIO_PVR_OFFSET 0x0060 /* Pin Value Register Read */ /* {PUER, PDER} Selected Function * @@ -150,17 +146,13 @@ /* Interrupt Flag Register Read (2 registers)*/ -#define SAM_GPIO_IFR_OFFSET(n) (0x00d0 + (((n) & ~31) >> 3)) -#define SAM_GPIO_IFR0_OFFSET 0x00d0 /* Interrupt Flag Register 0 Read */ -#define SAM_GPIO_IFR1_OFFSET 0x00d4 /* Interrupt Flag Register 0 Read */ +#define SAM_GPIO_IFR_OFFSET 0x00d0 /* Interrupt Flag Register 0 Read */ /* Interrupt Flag Register Clear (2 registers)*/ -#define SAM_GPIO_IFRC_OFFSET(n) (0x00d8 + (((n) & ~31) >> 3)) -#define SAM_GPIO_IFRC0_OFFSET 0x00d8 /* Interrupt Flag Register 0 Clear */ -#define SAM_GPIO_IFRC1_OFFSET 0x00dc /* Interrupt Flag Register 1 Clear */ +#define SAM_GPIO_IFRC _OFFSET 0x00d8 /* Interrupt Flag Register 0 Clear */ -/* {ODCR1, ODCR0} Interrupt Mode +/* {ODCR1, ODCR0} Output drive strength * * 00 Lowest drive strength * 01 ... @@ -230,11 +222,7 @@ /* Pin Value Register Read (4 registers)*/ -#define SAM_GPIO_PVR(n) (SAM_GPIO_BASE+SAM_GPIO_PVR_OFFSET(n)) -#define SAM_GPIO_PVR0 (SAM_GPIO_BASE+SAM_GPIO_PVR0_OFFSET) -#define SAM_GPIO_PVR1 (SAM_GPIO_BASE+SAM_GPIO_PVR1_OFFSET) -#define SAM_GPIO_PVR2 (SAM_GPIO_BASE+SAM_GPIO_PVR2_OFFSET) -#define SAM_GPIO_PVR3 (SAM_GPIO_BASE+SAM_GPIO_PVR3_OFFSET) +#define SAM_GPIO_PVR (SAM_GPIO_BASE+SAM_GPIO_PVR_OFFSET) #define SAM_GPIO_PUER (SAM_GPIO_BASE+SAM_GPIO_PUER_OFFSET) #define SAM_GPIO_PUERS (SAM_GPIO_BASE+SAM_GPIO_PUERS_OFFSET) @@ -266,17 +254,13 @@ #define SAM_GPIO_GFERC (SAM_GPIO_BASE+SAM_GPIO_GFERC_OFFSET) #define SAM_GPIO_GFERT (SAM_GPIO_BASE+SAM_GPIO_GFERT_OFFSET) -/* Interrupt Flag Register Read (2 registers)*/ +/* Interrupt Flag Register Read */ -#define SAM_GPIO_IFR(n) (SAM_GPIO_BASE+SAM_GPIO_IFR_OFFSET(n)) -#define SAM_GPIO_IFR0 (SAM_GPIO_BASE+SAM_GPIO_IFR0_OFFSET) -#define SAM_GPIO_IFR1 (SAM_GPIO_BASE+SAM_GPIO_IFR1_OFFSET) +#define SAM_GPIO_IFR (SAM_GPIO_BASE+SAM_GPIO_IFR_OFFSET) -/* Interrupt Flag Register Clear (2 registers)*/ +/* Interrupt Flag Register Clear */ -#define SAM_GPIO_IFRC(n) (SAM_GPIO_BASE+SAM_GPIO_IFRC_OFFSET(n)) -#define SAM_GPIO_IFRC0 (SAM_GPIO_BASE+SAM_GPIO_IFRC0_OFFSET) -#define SAM_GPIO_IFRC1 (SAM_GPIO_BASE+SAM_GPIO_IFRC1_OFFSET) +#define SAM_GPIO_IFRC (SAM_GPIO_BASE+SAM_GPIO_IFRC_OFFSET) #define SAM_GPIO_ODCR0 (SAM_GPIO_BASE+SAM_GPIO_ODCR0_OFFSET) #define SAM_GPIO_ODCR0S (SAM_GPIO_BASE+SAM_GPIO_ODCR0S_OFFSET) diff --git a/nuttx/arch/arm/src/sam34/sam_gpio.c b/nuttx/arch/arm/src/sam34/sam3u_gpio.c similarity index 99% rename from nuttx/arch/arm/src/sam34/sam_gpio.c rename to nuttx/arch/arm/src/sam34/sam3u_gpio.c index 0924857b94..271bb2f9b1 100644 --- a/nuttx/arch/arm/src/sam34/sam_gpio.c +++ b/nuttx/arch/arm/src/sam34/sam3u_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/sam34/sam_gpio.c + * arch/arm/src/sam34/sam3u_gpio.c * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/nuttx/arch/arm/src/sam34/sam4l_gpio.c b/nuttx/arch/arm/src/sam34/sam4l_gpio.c new file mode 100644 index 0000000000..64f1d60006 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam4l_gpio.c @@ -0,0 +1,569 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4l_gpio.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "sam_gpio.h" +#include "chip/sam4l_gpio.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +static const char g_portchar[4] = { 'A', 'B', 'C', 'D' }; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ +/**************************************************************************** + * Name: sam_gpiobase + * + * Description: + * Return the base address of the GPIO register set + * + ****************************************************************************/ + +static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset) +{ + int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + return SAM_GPION_BASE(port); +} + +/**************************************************************************** + * Name: sam_gpiopin + * + * Description: + * Returun the base address of the GPIO register set + * + ****************************************************************************/ + +static inline int sam_gpiopin(gpio_pinset_t cfgset) +{ + return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT); +} + +/**************************************************************************** + * Name: sam_configinput + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static int sam_configinput(uintptr_t base, uint32_t pin, gpio_pinset_t cfgset) +{ + /* Disable interrupts on the pin */ + + putreg32(pin, base + SAM_GPIO_IERC_OFFSET); + + /* Disable the output driver and select the GPIO function */ + + putreg32(pin, base + SAM_GPIO_ODERC_OFFSET); + putreg32(pin, base + SAM_GPIO_GPERS_OFFSET); + + /* Clear peripheral-only settings (just to make debug easier) */ + + putreg32(pin, base + SAM_GPIO_PMR0C_OFFSET); + putreg32(pin, base + SAM_GPIO_PMR1C_OFFSET); + putreg32(pin, base + SAM_GPIO_PMR2C_OFFSET); + putreg32(pin, base + SAM_GPIO_EVERC_OFFSET); + + /* Clear output-only settings (just to make debug easier) */ + + putreg32(pin, base + SAM_GPIO_ODCR0C_OFFSET); + putreg32(pin, base + SAM_GPIO_ODCR1C_OFFSET); + putreg32(pin, base + SAM_GPIO_OSRR0C_OFFSET); + + /* Clear the interrupt configuration (just to make debug easier) */ + + putreg32(pin, base + SAM_GPIO_IMR0C_OFFSET); + putreg32(pin, base + SAM_GPIO_IMR1C_OFFSET); + + /* Enable/disable the pull-up as requested */ + + if ((cfgset & GPIO_PULL_UP) != 0) + { + putreg32(pin, base + SAM_GPIO_PUERS_OFFSET); + } + else + { + putreg32(pin, base + SAM_GPIO_PUERC_OFFSET); + } + + if ((cfgset & GPIO_PULL_DOWN) != 0) + { + putreg32(pin, base + SAM_GPIO_PDERS_OFFSET); + } + else + { + putreg32(pin, base + SAM_GPIO_PDERC_OFFSET); + } + + /* Check if glitch filtering should be enabled */ + + if ((cfgset & GPIO_GLITCH_FILTER) != 0) + { + putreg32(pin, base + SAM_GPIO_GFERS_OFFSET); + } + else + { + putreg32(pin, base + SAM_GPIO_GFERC_OFFSET); + } + + /* Check if the input Schmitt trigger should be enabled */ + + if ((cfgset & GPIO_SCHMITT_TRIGGER) != 0) + { + putreg32(pin, base + SAM_GPIO_STERS_OFFSET); + } + else + { + putreg32(pin, base + SAM_GPIO_STERC_OFFSET); + } + + return OK; +} + +/**************************************************************************** + * Name: sam_configinterrupt + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline int sam_configinterrupt(uintptr_t base, uint32_t pin, + gpio_pinset_t cfgset) +{ + int ret; + + /* Just configure the pin as an input, then set the interrupt configuration. + * Here we exploit the fact that sam_configinput() enabled both rising and + * falling edges. + */ + + ret = sam_configinput(base, pin, cfgset) + if (ret = OK) + { + /* Disable rising and falling edge interrupts as requested + * {IMR1, IMR0} Interrupt Mode + * + * 00 Pin Change <-- We already have this + * 01 Rising Edge <-- GPIO_INT_RISING + * 10 Falling Edge <-- GPIO_INT_FALLING + * 11 Reserved + */ + + gpio_pinset_t edges = cfgset & GPIO_INT_MASK; + + if (eges = GPIO_INT_RISING) + { + /* Rising only.. disable interrrupts on the falling edge */ + + putreg32(pin, base + SAM_GPIO_IMR0S_OFFSET); + } + else if (edges = GPIO_INT_FALLING) + { + /* Falling only.. disable interrrupts on the rising edge */ + + putreg32(pin, base + SAM_GPIO_IMR1S_OFFSET); + } + } + + return ret; +} + +/**************************************************************************** + * Name: sam_configoutput + * + * Description: + * Configure a GPIO output pin based on bit-encoded description of the pin. + * + * Assumption: + * sam_configinput has been called to put the pin into the default input + * state: + * + * GPER -> GPIO + * PMD0-2 -> zeroed + * ODER -> disabled + * PUER+PDER -> No pull up- or down. + * IER -> Interrupt disabled + * IMR0-1 -> zeroed + * Glitch filter -> disabled + * Output drive -> lowest + * Slew control -> disabled + * Schmitt trigger -> disabled + * Peripheral events -> disabled + * + ****************************************************************************/ + +static inline int sam_configoutput(uintptr_t base, uint32_t pin, + gpio_pinset_t cfgset) +{ + /* Set the output drive strength + * + * {ODCR1, ODCR0} Output drive strength + * + * 00 Lowest drive strength + * 01 ... + * 10 ... + * 11 Highest drive strength + */ + + switch (cfgset & GPIO_DRIVE_MASK) + { + default: + case GPIO_DRIVE_LOW: /* OCDR1=0 OCDR0=0 */ + break; /* This is the current setting */ + + case GPIO_DRIVE_MEDLOW: /* OCDR1=0 OCDR0=1 */ + putreg32(pin, base + SAM_GPIO_ODCR0S_OFFSET); + break; + + case GPIO_DRIVE_MEDHIGH: /* OCDR1=1 OCDR0=0 */ + putreg32(pin, base + SAM_GPIO_ODCR1S_OFFSET); + break; + + case GPIO_DRIVE_HIGH: /* OCDR1=1 OCDR0=1 */ + putreg32(pin, base + SAM_GPIO_ODCR0S_OFFSET); + putreg32(pin, base + SAM_GPIO_ODCR1S_OFFSET); + break; + } + + /* Set the output slew control is requested */ + + if ((cfgset & GPIO_SLEW) != 0) + { + putreg32(pin, base + SAM_GPIO_OSRR0S_OFFSET); + } + + /* Enable the output driver */ + + putreg32(pin, base + SAM_GPIO_ODERS_OFFSET); + + /* And set the initial value of the output */ + + sam_gpiowrite(cfgset, ((cfgset & GPIO_OUTPUT_SET) != 0)); + return OK; +} + +/**************************************************************************** + * Name: sam_configperiph + * + * Description: + * Configure a GPIO pin driven by a peripheral based on bit-encoded + * description of the pin. + * + * Assumption: + * sam_configinput has been called to put the pin into the default input + * state: + * + * GPER -> GPIO + * PMD0-2 -> zeroed + * ODER -> disabled + * PUER+PDER -> No pull up- or down. + * IER -> Interrupt disabled + * IMR0-1 -> zeroed + * Glitch filter -> disabled + * Output drive -> lowest + * Slew control -> disabled + * Schmitt trigger -> disabled + * Peripheral events -> disabled + * + ****************************************************************************/ + +static inline int sam_configperiph(uintptr_t base, uint32_t pin, + gpio_pinset_t cfgset) +{ + * Peripheral: MM.. FFFE .... IIG. .PPB BBBB + + gpio_pinset_t edges; + + /* Select the peripheral function. + * + * {PMR2, PMR1, PMR0} selects peripheral function: + * + * 000 A 100 E + * 001 B 101 F + * 010 C 110 G + * 011 D 111 H + */ + + switch (cfgset & GPIO_FUNC_MASK) + { + default: + case _GPIO_FUNCA: /* Function A 000 */ + break; /* We already have this configuration */ + + case _GPIO_FUNCD: /* Function D 011 */ + putreg32(pin, base + SAM_GPIO_PMR1S_OFFSET); + break; + case _GPIO_FUNCB: /* Function B 001 */ + putreg32(pin, base + SAM_GPIO_PMR0S_OFFSET); + break; + + case _GPIO_FUNCG: /* Function G 110 */ + putreg32(pin, base + SAM_GPIO_PMR2S_OFFSET); + case _GPIO_FUNCC: /* Function C 010 */ + putreg32(pin, base + SAM_GPIO_PMR1S_OFFSET); + break; + + case _GPIO_FUNCE: /* Function E 100 */ + putreg32(pin, base + SAM_GPIO_PMR2S_OFFSET); + break; + case _GPIO_FUNCF: /* Function F 101 */ + putreg32(pin, base + SAM_GPIO_PMR0S_OFFSET); + break; + + case _GPIO_FUNCH: /* Function H 111 */ + putreg32(pin, base + SAM_GPIO_PMR0S_OFFSET); + putreg32(pin, base + SAM_GPIO_PMR1S_OFFSET); + putreg32(pin, base + SAM_GPIO_PMR2S_OFFSET); + break; + } + + /* Check if glitch filtering should be enabled */ + + if ((cfgset & GPIO_GLITCH_FILTER) != 0) + { + putreg32(pin, base + SAM_GPIO_GFERS_OFFSET); + } + + /* Disable rising and falling edge events as requested (of course, + * these do nothing unless events are also enabled. + * + * {IMR1, IMR0} Interrupt Mode + * + * 00 Pin Change <-- We already have this + * 01 Rising Edge <-- GPIO_INT_RISING + * 10 Falling Edge <-- GPIO_INT_FALLING + * 11 Reserved + */ + + edges = cfgset & GPIO_INT_MASK; + if (eges = GPIO_INT_RISING) + { + /* Rising only.. disable interrrupts on the falling edge */ + + putreg32(pin, base + SAM_GPIO_IMR0S_OFFSET); + } + else if (edges = GPIO_INT_FALLING) + { + /* Falling only.. disable interrrupts on the rising edge */ + + putreg32(pin, base + SAM_GPIO_IMR1S_OFFSET); + } + + /* REVISIT: Should event generation be enabled now? I am assuming so */ + + if (eges = GPIO_PERIPH_EVENTS) + { + /* Rising only.. disable interrrupts on the falling edge */ + + putreg32(pin, base + SAM_GPIO_EVERS_OFFSET); + } + + /* Finally, drive the pen from the peripheral */ + + putreg32(pin, base + SAM_GPIO_GPERC_OFFSET); + return OK; +} + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int sam_configgpio(gpio_pinset_t cfgset) +{ + gpio_pinset_t inputset; + uintptr_t base = sam_gpiobase(cfgset); + uint32_t pin = sam_gpiopin(cfgset); + int ret; + + /* Put the GPIO in a known state. A generic GPIO input pin. */ + + inputset = GPIO_INPUT | (cfgset & (GPIO_PORT_MASK | GPIO_PIN_MASK)); + ret = sam_configinput(base, pin, inputset); + if (ret == OK) + { + /* Then put the GPIO into the requested state */ + + switch (cfgset & GPIO_MODE_MASK) + { + case GPIO_INPUT: + ret = sam_configinput(base, pin, cfgset); + break; + + case GPIO_OUTPUT: + ret = sam_configoutput(base, pin, cfgset); + break; + + case GPIO_PERIPHERAL: + ret = sam_configperiph(base, pin, cfgset); + break; + + case GPIO_INTERRUPT: + ret = sam_configinterrupt(base, pin, cfgset); + break; + + default: + ret = -EINVAL; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: sam_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void sam_gpiowrite(gpio_pinset_t pinset, bool value) +{ + uintptr_t base = sam_gpiobase(pinset); + uint32_t pin = sam_gpiopin(pinset); + + if (value) + { + putreg32(pin, base + SAM_GPIO_OVRS_OFFSET); + } + else + { + putreg32(pin, base + SAM_GPIO_OVRC_OFFSET); + } +} + +/**************************************************************************** + * Name: sam_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool sam_gpioread(gpio_pinset_t pinset) +{ + uintptr_t base = sam_gpiobase(pinset); + uint32_t pin = sam_gpiopin(pinset); + + return (getreg32(base + SAM_GPIO_PVR_OFFSET) & pin) != 0; +} + +/************************************************************************************ + * Function: sam_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +int sam_dumpgpio(uint32_t pinset, const char *msg) +{ + irqstate_t flags; + uintptr_t base; + unsigned int pin; + unsigned int port; + + /* Get the base address associated with the PIO port */ + + pin = sam_gpiopin(pinset); + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + base = SAM_GPION_BASE(port); + + /* The following requires exclusive access to the GPIO registers */ + + flags = irqsave(); + lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); + lldbg(" GPER: %08x PMR0: %08x PMR1: %08x PMR2: %08x\n", + getreg32(base + SAM_GPIO_GPER_OFFSET), getreg32(base + SAM_GPIO_PMR0_OFFSET), + getreg32(base + SAM_GPIO_PMR1_OFFSET), getreg32(base + SAM_GPIO_PMR2_OFFSET)); + lldbg(" ODER: %08x OVR: %08x PVR: %08x PUER: %08x\n", + getreg32(base + SAM_GPIO_ODER_OFFSET), getreg32(base + SAM_GPIO_OVR_OFFSET), + getreg32(base + SAM_GPIO_PVR_OFFSET), getreg32(base + SAM_GPIO_PUER_OFFSET)); + lldbg(" PDER: %08x IER: %08x IMR0: %08x IMR1: %08x\n", + getreg32(base + SAM_GPIO_PDER_OFFSET), getreg32(base + SAM_GPIO_IER_OFFSET), + getreg32(base + SAM_GPIO_IMR0_OFFSET), getreg32(base + SAM_GPIO_IMR1_OFFSET)); + lldbg(" GFER: %08x IFR: %08x ODCR0: %08x ODCR1: %08x\n", + getreg32(base + SAM_GPIO_GFER_OFFSET), getreg32(base + SAM_GPIO_IFR_OFFSET), + getreg32(base + SAM_GPIO_ODCR0_OFFSET), getreg32(base + SAM_GPIO_ODCR1_OFFSET)); + lldbg(" OSRR0: %08x EVER: %08x PARAM: %08x VERS: %08x\n", + getreg32(base + SAM_GPIO_OSRR0_OFFSET), getreg32(base + SAM_GPIO_EVER_OFFSET), + getreg32(base + SAM_GPIO_PARAMETER_OFFSET), getreg32(base + SAM_GPIO_VERSION_OFFSET)); + irqrestore(flags); + return OK; +} +#endif + diff --git a/nuttx/arch/arm/src/sam34/sam4l_gpio.h b/nuttx/arch/arm/src/sam34/sam4l_gpio.h index 2a65ac134e..314d28ab18 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_gpio.h +++ b/nuttx/arch/arm/src/sam34/sam4l_gpio.h @@ -137,14 +137,14 @@ * Peripheral: MM.. FFF. .... .... .... .... */ -# define GPIO_FUNCA (GPIO_PERIPHERAL | _GPIO_FUNCA) /* Function A */ -# define GPIO_FUNCB (GPIO_PERIPHERAL | _GPIO_FUNCB) /* Function B */ -# define GPIO_FUNCC (GPIO_PERIPHERAL | _GPIO_FUNCC) /* Function C */ -# define GPIO_FUNCD (GPIO_PERIPHERAL | _GPIO_FUNCD) /* Function D */ -# define GPIO_FUNCE (GPIO_PERIPHERAL | _GPIO_FUNCE) /* Function E */ -# define GPIO_FUNCF (GPIO_PERIPHERAL | _GPIO_FUNCF) /* Function F */ -# define GPIO_FUNCG (GPIO_PERIPHERAL | _GPIO_FUNCG) /* Function G */ -# define GPIO_FUNCH (GPIO_PERIPHERAL | _GPIO_FUNCH) /* Function H */ +#define GPIO_FUNCA (GPIO_PERIPHERAL | _GPIO_FUNCA) /* Function A */ +#define GPIO_FUNCB (GPIO_PERIPHERAL | _GPIO_FUNCB) /* Function B */ +#define GPIO_FUNCC (GPIO_PERIPHERAL | _GPIO_FUNCC) /* Function C */ +#define GPIO_FUNCD (GPIO_PERIPHERAL | _GPIO_FUNCD) /* Function D */ +#define GPIO_FUNCE (GPIO_PERIPHERAL | _GPIO_FUNCE) /* Function E */ +#define GPIO_FUNCF (GPIO_PERIPHERAL | _GPIO_FUNCF) /* Function F */ +#define GPIO_FUNCG (GPIO_PERIPHERAL | _GPIO_FUNCG) /* Function G */ +#define GPIO_FUNCH (GPIO_PERIPHERAL | _GPIO_FUNCH) /* Function H */ /* Peripheral event control * @@ -158,7 +158,7 @@ * Peripheral: .... ...E .... .... .... .... */ -#define GPIO_SCHMITT_TRIGGER (1 << 16) /* Bit 16: Enable peripheral events */ +#define GPIO_PERIPH_EVENTS (1 << 16) /* Bit 16: Enable peripheral events */ /* Output drive control * @@ -226,6 +226,12 @@ # define GPIO_INT_RISING (1 << GPIO_INT_SHIFT) /* Rising edge */ # define GPIO_INT_FALLING (2 << GPIO_INT_SHIFT) /* Falling edge */ +/* These combinations control events. These help to clean up pin definitions. */ + +#define GPIO_EVENT_CHANGE (GPIO_PERIPH_EVENTS | GPIO_INT_CHANGE) /* Pin change */ +#define GPIO_EVENT_RISING (GPIO_PERIPH_EVENTS | GPIO_INT_RISING) /* Rising edge */ +#define GPIO_EVENT_FALLING (GPIO_PERIPH_EVENTS | GPIO_INT_FALLING) /* Falling edge */ + /* Enable input/periphal glitch filter * * MODE BITFIELDS From 44af85860981ee7408bbb65fe43baa8245a7e926 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 4 Jun 2013 15:23:47 -0600 Subject: [PATCH 29/41] More changes that should have gone with the last commit --- nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h | 856 +++++++++--------- nuttx/arch/arm/src/sam34/sam4l_gpio.c | 4 +- .../sam4l-xplained/src/sam4l-xplained.h | 6 +- 3 files changed, 432 insertions(+), 434 deletions(-) diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h index 1c6f4a481f..c4babee650 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h @@ -69,479 +69,479 @@ /* Audio Bitstream DAC */ -#define GPIO_ABDACB_CLK_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) -#define GPIO_ABDACB_CLK_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) -#define GPIO_ABDACB_DAC0_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) -#define GPIO_ABDACB_DAC0_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) -#define GPIO_ABDACB_DAC0_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) -#define GPIO_ABDACB_DAC0_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) -#define GPIO_ABDACB_DAC1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) -#define GPIO_ABDACB_DAC1_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) -#define GPIO_ABDACB_DAC1_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) -#define GPIO_ABDACB_DAC1_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) -#define GPIO_ABDACB_DACN0_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) -#define GPIO_ABDACB_DACN0_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) -#define GPIO_ABDACB_DACN0_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) -#define GPIO_ABDACB_DACN0_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) -#define GPIO_ABDACB_DACN1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) -#define GPIO_ABDACB_DACN1_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) -#define GPIO_ABDACB_DACN1_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) -#define GPIO_ABDACB_DACN1_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_ABDACB_CLK_1 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN31) +#define GPIO_ABDACB_CLK_2 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN12) +#define GPIO_ABDACB_DAC0_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN17) +#define GPIO_ABDACB_DAC0_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN27) +#define GPIO_ABDACB_DAC0_3 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN2) +#define GPIO_ABDACB_DAC0_4 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN9) +#define GPIO_ABDACB_DAC1_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN19) +#define GPIO_ABDACB_DAC1_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN29) +#define GPIO_ABDACB_DAC1_3 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN4) +#define GPIO_ABDACB_DAC1_4 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN13) +#define GPIO_ABDACB_DACN0_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN18) +#define GPIO_ABDACB_DACN0_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN28) +#define GPIO_ABDACB_DACN0_3 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN3) +#define GPIO_ABDACB_DACN0_4 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN10) +#define GPIO_ABDACB_DACN1_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN20) +#define GPIO_ABDACB_DACN1_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN30) +#define GPIO_ABDACB_DACN1_3 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN5) +#define GPIO_ABDACB_DACN1_4 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN14) /* Analog Comparator Interface */ -#define GPIO_ACIFC_ACAN0 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) -#define GPIO_ACIFC_ACAN1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) -#define GPIO_ACIFC_ACAP0 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) -#define GPIO_ACIFC_ACAP1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) -#define GPIO_ACIFC_ACBN0 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) -#define GPIO_ACIFC_ACBN1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) -#define GPIO_ACIFC_ACBP0 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) -#define GPIO_ACIFC_ACBP1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_ACIFC_ACAN0 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN6) +#define GPIO_ACIFC_ACAN1 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN9) +#define GPIO_ACIFC_ACAP0 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN7) +#define GPIO_ACIFC_ACAP1 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN10) +#define GPIO_ACIFC_ACBN0 (GPIO_FUNCE | GPIO_PORTB | GPIO_PIN2) +#define GPIO_ACIFC_ACBN1 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN13) +#define GPIO_ACIFC_ACBP0 (GPIO_FUNCE | GPIO_PORTB | GPIO_PIN3) +#define GPIO_ACIFC_ACBP1 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN14) /* ADC controller interface */ -#define GPIO_ADCIFE_AD0 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) -#define GPIO_ADCIFE_AD1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) -#define GPIO_ADCIFE_AD2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) -#define GPIO_ADCIFE_AD3 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) -#define GPIO_ADCIFE_AD4 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) -#define GPIO_ADCIFE_AD5 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) -#define GPIO_ADCIFE_AD6 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) -#define GPIO_ADCIFE_AD7 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) -#define GPIO_ADCIFE_AD8 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) -#define GPIO_ADCIFE_AD9 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) -#define GPIO_ADCIFE_AD10 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) -#define GPIO_ADCIFE_AD11 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) -#define GPIO_ADCIFE_AD12 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) -#define GPIO_ADCIFE_AD13 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) -#define GPIO_ADCIFE_AD14 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) -#define GPIO_ADCIFE_TRIGGER (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_ADCIFE_AD0 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN4) +#define GPIO_ADCIFE_AD1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN5) +#define GPIO_ADCIFE_AD2 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN7) +#define GPIO_ADCIFE_AD3 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN2) +#define GPIO_ADCIFE_AD4 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN3) +#define GPIO_ADCIFE_AD5 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN4) +#define GPIO_ADCIFE_AD6 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN5) +#define GPIO_ADCIFE_AD7 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN7) +#define GPIO_ADCIFE_AD8 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN8) +#define GPIO_ADCIFE_AD9 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN9) +#define GPIO_ADCIFE_AD10 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN10) +#define GPIO_ADCIFE_AD11 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN11) +#define GPIO_ADCIFE_AD12 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN12) +#define GPIO_ADCIFE_AD13 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN13) +#define GPIO_ADCIFE_AD14 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN14) +#define GPIO_ADCIFE_TRIGGER (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN5) /* Capacitive Touch Module B */ -#define GPIO_CATB_DIS_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) -#define GPIO_CATB_DIS_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) -#define GPIO_CATB_DIS_3 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) -#define GPIO_CATB_DIS_4 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) -#define GPIO_CATB_DIS_5 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) -#define GPIO_CATB_DIS_6 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) -#define GPIO_CATB_DIS_7 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) -#define GPIO_CATB_DIS_8 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) -#define GPIO_CATB_DIS_9 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) -#define GPIO_CATB_SENSE0_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) -#define GPIO_CATB_SENSE0_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) -#define GPIO_CATB_SENSE0_3 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) -#define GPIO_CATB_SENSE1_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) -#define GPIO_CATB_SENSE1_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) -#define GPIO_CATB_SENSE1_3 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) -#define GPIO_CATB_SENSE2_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) -#define GPIO_CATB_SENSE2_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) -#define GPIO_CATB_SENSE2_3 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) -#define GPIO_CATB_SENSE3_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) -#define GPIO_CATB_SENSE3_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) -#define GPIO_CATB_SENSE3_3 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) -#define GPIO_CATB_SENSE4_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) -#define GPIO_CATB_SENSE4_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) -#define GPIO_CATB_SENSE5_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) -#define GPIO_CATB_SENSE5_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) -#define GPIO_CATB_SENSE6_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) -#define GPIO_CATB_SENSE6_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) -#define GPIO_CATB_SENSE7_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) -#define GPIO_CATB_SENSE7_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) -#define GPIO_CATB_SENSE8_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) -#define GPIO_CATB_SENSE8_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) -#define GPIO_CATB_SENSE9_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) -#define GPIO_CATB_SENSE9_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) -#define GPIO_CATB_SENSE10_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) -#define GPIO_CATB_SENSE10_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) -#define GPIO_CATB_SENSE11_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) -#define GPIO_CATB_SENSE11_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) -#define GPIO_CATB_SENSE12_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) -#define GPIO_CATB_SENSE12_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) -#define GPIO_CATB_SENSE13_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) -#define GPIO_CATB_SENSE13_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) -#define GPIO_CATB_SENSE14_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) -#define GPIO_CATB_SENSE14_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) -#define GPIO_CATB_SENSE15_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) -#define GPIO_CATB_SENSE15_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) -#define GPIO_CATB_SENSE16_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) -#define GPIO_CATB_SENSE16_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) -#define GPIO_CATB_SENSE17_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -#define GPIO_CATB_SENSE17_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) -#define GPIO_CATB_SENSE18_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) -#define GPIO_CATB_SENSE18_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) -#define GPIO_CATB_SENSE19_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) -#define GPIO_CATB_SENSE19_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) -#define GPIO_CATB_SENSE20_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) -#define GPIO_CATB_SENSE20_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) -#define GPIO_CATB_SENSE21_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0) -#define GPIO_CATB_SENSE21_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) -#define GPIO_CATB_SENSE22_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) -#define GPIO_CATB_SENSE22_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) -#define GPIO_CATB_SENSE23_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) -#define GPIO_CATB_SENSE23_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) -#define GPIO_CATB_SENSE24_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) -#define GPIO_CATB_SENSE24_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) -#define GPIO_CATB_SENSE25_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) -#define GPIO_CATB_SENSE25_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) -#define GPIO_CATB_SENSE26_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN6) -#define GPIO_CATB_SENSE26_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) -#define GPIO_CATB_SENSE27_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) -#define GPIO_CATB_SENSE27_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) -#define GPIO_CATB_SENSE28_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) -#define GPIO_CATB_SENSE28_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) -#define GPIO_CATB_SENSE29_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) -#define GPIO_CATB_SENSE29_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) -#define GPIO_CATB_SENSE30_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) -#define GPIO_CATB_SENSE30_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) -#define GPIO_CATB_SENSE31_1 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) -#define GPIO_CATB_SENSE31_2 (GPIO_FUNCG | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_CATB_DIS_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN12) +#define GPIO_CATB_DIS_2 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN2) +#define GPIO_CATB_DIS_3 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN23) +#define GPIO_CATB_DIS_4 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN31) +#define GPIO_CATB_DIS_5 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN12) +#define GPIO_CATB_DIS_6 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN3) +#define GPIO_CATB_DIS_7 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN14) +#define GPIO_CATB_DIS_8 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN23) +#define GPIO_CATB_DIS_9 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_CATB_SENSE0_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN27) +#define GPIO_CATB_SENSE0_2 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_CATB_SENSE0_3 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_CATB_SENSE1_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN28) +#define GPIO_CATB_SENSE1_2 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_CATB_SENSE1_3 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN14) +#define GPIO_CATB_SENSE2_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN29) +#define GPIO_CATB_SENSE2_2 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN6) +#define GPIO_CATB_SENSE2_3 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN15) +#define GPIO_CATB_SENSE3_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN30) +#define GPIO_CATB_SENSE3_2 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_CATB_SENSE3_3 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN0) +#define GPIO_CATB_SENSE4_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN8) +#define GPIO_CATB_SENSE4_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN1) +#define GPIO_CATB_SENSE5_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN9) +#define GPIO_CATB_SENSE5_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN2) +#define GPIO_CATB_SENSE6_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN10) +#define GPIO_CATB_SENSE6_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN3) +#define GPIO_CATB_SENSE7_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN11) +#define GPIO_CATB_SENSE7_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN4) +#define GPIO_CATB_SENSE8_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN13) +#define GPIO_CATB_SENSE8_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN6) +#define GPIO_CATB_SENSE9_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN14) +#define GPIO_CATB_SENSE9_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN7) +#define GPIO_CATB_SENSE10_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN15) +#define GPIO_CATB_SENSE10_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN8) +#define GPIO_CATB_SENSE11_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN16) +#define GPIO_CATB_SENSE11_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN9) +#define GPIO_CATB_SENSE12_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN17) +#define GPIO_CATB_SENSE12_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN10) +#define GPIO_CATB_SENSE13_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN18) +#define GPIO_CATB_SENSE13_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN11) +#define GPIO_CATB_SENSE14_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN19) +#define GPIO_CATB_SENSE14_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN12) +#define GPIO_CATB_SENSE15_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN20) +#define GPIO_CATB_SENSE15_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN13) +#define GPIO_CATB_SENSE16_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN21) +#define GPIO_CATB_SENSE16_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN15) +#define GPIO_CATB_SENSE17_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN22) +#define GPIO_CATB_SENSE17_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN16) +#define GPIO_CATB_SENSE18_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN24) +#define GPIO_CATB_SENSE18_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN17) +#define GPIO_CATB_SENSE19_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN25) +#define GPIO_CATB_SENSE19_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN18) +#define GPIO_CATB_SENSE20_1 (GPIO_FUNCG | GPIO_PORTA | GPIO_PIN26) +#define GPIO_CATB_SENSE20_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN19) +#define GPIO_CATB_SENSE21_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_CATB_SENSE21_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN20) +#define GPIO_CATB_SENSE22_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN1) +#define GPIO_CATB_SENSE22_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN21) +#define GPIO_CATB_SENSE23_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN2) +#define GPIO_CATB_SENSE23_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN22) +#define GPIO_CATB_SENSE24_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN4) +#define GPIO_CATB_SENSE24_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN24) +#define GPIO_CATB_SENSE25_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN5) +#define GPIO_CATB_SENSE25_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN25) +#define GPIO_CATB_SENSE26_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN6) +#define GPIO_CATB_SENSE26_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN26) +#define GPIO_CATB_SENSE27_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN7) +#define GPIO_CATB_SENSE27_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN27) +#define GPIO_CATB_SENSE28_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN8) +#define GPIO_CATB_SENSE28_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN28) +#define GPIO_CATB_SENSE29_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN9) +#define GPIO_CATB_SENSE29_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN29) +#define GPIO_CATB_SENSE30_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN10) +#define GPIO_CATB_SENSE30_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN30) +#define GPIO_CATB_SENSE31_1 (GPIO_FUNCG | GPIO_PORTB | GPIO_PIN11) +#define GPIO_CATB_SENSE31_2 (GPIO_FUNCG | GPIO_PORTC | GPIO_PIN31) /* DAC Controller */ -#define GPIO_DACC_EXT_TRIG0 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) -#define GPIO_DACC_VOUT (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) -#define GPIO_EIC_EXTINT0 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) -#define GPIO_EIC_EXTINT1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) -#define GPIO_EIC_EXTINT1_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) -#define GPIO_EIC_EXTINT1_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) -#define GPIO_EIC_EXTINT2_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) -#define GPIO_EIC_EXTINT2_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) -#define GPIO_EIC_EXTINT2_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) -#define GPIO_EIC_EXTINT3_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) -#define GPIO_EIC_EXTINT3_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) -#define GPIO_EIC_EXTINT3_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) -#define GPIO_EIC_EXTINT4_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) -#define GPIO_EIC_EXTINT4_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) -#define GPIO_EIC_EXTINT4_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) -#define GPIO_EIC_EXTINT5_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) -#define GPIO_EIC_EXTINT5_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) -#define GPIO_EIC_EXTINT6_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) -#define GPIO_EIC_EXTINT6_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) -#define GPIO_EIC_EXTINT7_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) -#define GPIO_EIC_EXTINT7_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -#define GPIO_EIC_EXTINT8_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) -#define GPIO_EIC_EXTINT8_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_DACC_EXT_TRIG0 (GPIO_FUNCE | GPIO_PORTB | GPIO_PIN4) +#define GPIO_DACC_VOUT (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN6) +#define GPIO_EIC_EXTINT0 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN1) +#define GPIO_EIC_EXTINT1_1 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN24) +#define GPIO_EIC_EXTINT1_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN16) +#define GPIO_EIC_EXTINT1_3 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN6) +#define GPIO_EIC_EXTINT2_1 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN25) +#define GPIO_EIC_EXTINT2_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN17) +#define GPIO_EIC_EXTINT2_3 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN4) +#define GPIO_EIC_EXTINT3_1 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN26) +#define GPIO_EIC_EXTINT3_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN18) +#define GPIO_EIC_EXTINT3_3 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN5) +#define GPIO_EIC_EXTINT4_1 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN27) +#define GPIO_EIC_EXTINT4_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN19) +#define GPIO_EIC_EXTINT4_3 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN7) +#define GPIO_EIC_EXTINT5_1 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN3) +#define GPIO_EIC_EXTINT5_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN20) +#define GPIO_EIC_EXTINT6_1 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN4) +#define GPIO_EIC_EXTINT6_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN21) +#define GPIO_EIC_EXTINT7_1 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN5) +#define GPIO_EIC_EXTINT7_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN22) +#define GPIO_EIC_EXTINT8_1 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN6) +#define GPIO_EIC_EXTINT8_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN23) /* Glue Logic Controller */ -#define GPIO_GLOC_IN0_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) -#define GPIO_GLOC_IN0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) -#define GPIO_GLOC_IN1_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) -#define GPIO_GLOC_IN1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) -#define GPIO_GLOC_IN2_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -#define GPIO_GLOC_IN2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) -#define GPIO_GLOC_IN3_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) -#define GPIO_GLOC_IN3_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) -#define GPIO_GLOC_IN4_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN6) -#define GPIO_GLOC_IN4_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) -#define GPIO_GLOC_IN4_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) -#define GPIO_GLOC_IN4_4 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) -#define GPIO_GLOC_IN5_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) -#define GPIO_GLOC_IN5_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) -#define GPIO_GLOC_IN5_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) -#define GPIO_GLOC_IN5_4 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) -#define GPIO_GLOC_IN6_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) -#define GPIO_GLOC_IN6_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) -#define GPIO_GLOC_IN6_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) -#define GPIO_GLOC_IN6_4 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) -#define GPIO_GLOC_IN7_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) -#define GPIO_GLOC_IN7_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) -#define GPIO_GLOC_IN7_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) -#define GPIO_GLOC_OUT0_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) -#define GPIO_GLOC_OUT0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) -#define GPIO_GLOC_OUT1_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) -#define GPIO_GLOC_OUT1_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) -#define GPIO_GLOC_OUT1_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) -#define GPIO_GLOC_OUT1_4 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_GLOC_IN0_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN20) +#define GPIO_GLOC_IN0_2 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN6) +#define GPIO_GLOC_IN1_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN21) +#define GPIO_GLOC_IN1_2 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN4) +#define GPIO_GLOC_IN2_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN22) +#define GPIO_GLOC_IN2_2 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN5) +#define GPIO_GLOC_IN3_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN23) +#define GPIO_GLOC_IN3_2 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN7) +#define GPIO_GLOC_IN4_1 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN6) +#define GPIO_GLOC_IN4_2 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN28) +#define GPIO_GLOC_IN4_3 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN27) +#define GPIO_GLOC_IN4_4 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN15) +#define GPIO_GLOC_IN5_1 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN7) +#define GPIO_GLOC_IN5_2 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN29) +#define GPIO_GLOC_IN5_3 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN28) +#define GPIO_GLOC_IN5_4 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN16) +#define GPIO_GLOC_IN6_1 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN8) +#define GPIO_GLOC_IN6_2 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN30) +#define GPIO_GLOC_IN6_3 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN29) +#define GPIO_GLOC_IN6_4 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN17) +#define GPIO_GLOC_IN7_1 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN9) +#define GPIO_GLOC_IN7_2 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN30) +#define GPIO_GLOC_IN7_3 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN18) +#define GPIO_GLOC_OUT0_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN24) +#define GPIO_GLOC_OUT0_2 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN8) +#define GPIO_GLOC_OUT1_1 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN10) +#define GPIO_GLOC_OUT1_2 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN31) +#define GPIO_GLOC_OUT1_3 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN31) +#define GPIO_GLOC_OUT1_4 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN19) /* Inter-IC Sound (I2S) Controller */ -#define GPIO_IISC_IMCK_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) -#define GPIO_IISC_IMCK_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) -#define GPIO_IISC_IMCK_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) -#define GPIO_IISC_ISCK_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) -#define GPIO_IISC_ISCK_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) -#define GPIO_IISC_ISCK_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) -#define GPIO_IISC_ISDI_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) -#define GPIO_IISC_ISDI_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) -#define GPIO_IISC_ISDI_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) -#define GPIO_IISC_ISDO_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) -#define GPIO_IISC_ISDO_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) -#define GPIO_IISC_ISDO_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) -#define GPIO_IISC_IWS_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) -#define GPIO_IISC_IWS_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN6) -#define GPIO_IISC_IWS_3 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_IISC_IMCK_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN31) +#define GPIO_IISC_IMCK_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN5) +#define GPIO_IISC_IMCK_3 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN14) +#define GPIO_IISC_ISCK_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN27) +#define GPIO_IISC_ISCK_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN2) +#define GPIO_IISC_ISCK_3 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN9) +#define GPIO_IISC_ISDI_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN28) +#define GPIO_IISC_ISDI_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN3) +#define GPIO_IISC_ISDI_3 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN10) +#define GPIO_IISC_ISDO_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN30) +#define GPIO_IISC_ISDO_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN4) +#define GPIO_IISC_ISDO_3 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN13) +#define GPIO_IISC_IWS_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN29) +#define GPIO_IISC_IWS_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN6) +#define GPIO_IISC_IWS_3 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN12) /* LCD Controller A */ -#define GPIO_LCDCA_COM0 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) -#define GPIO_LCDCA_COM1 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) -#define GPIO_LCDCA_COM2 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) -#define GPIO_LCDCA_COM3 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) -#define GPIO_LCDCA_SEG0 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) -#define GPIO_LCDCA_SEG1 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) -#define GPIO_LCDCA_SEG2 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) -#define GPIO_LCDCA_SEG3 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) -#define GPIO_LCDCA_SEG4 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) -#define GPIO_LCDCA_SEG5 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) -#define GPIO_LCDCA_SEG6 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) -#define GPIO_LCDCA_SEG7 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) -#define GPIO_LCDCA_SEG8 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) -#define GPIO_LCDCA_SEG9 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) -#define GPIO_LCDCA_SEG10 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) -#define GPIO_LCDCA_SEG11 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) -#define GPIO_LCDCA_SEG12 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) -#define GPIO_LCDCA_SEG13 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) -#define GPIO_LCDCA_SEG14 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) -#define GPIO_LCDCA_SEG15 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) -#define GPIO_LCDCA_SEG16 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) -#define GPIO_LCDCA_SEG17 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) -#define GPIO_LCDCA_SEG18 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) -#define GPIO_LCDCA_SEG19 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) -#define GPIO_LCDCA_SEG20 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) -#define GPIO_LCDCA_SEG21 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) -#define GPIO_LCDCA_SEG22 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN6) -#define GPIO_LCDCA_SEG23 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) -#define GPIO_LCDCA_SEG24 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) -#define GPIO_LCDCA_SEG25 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) -#define GPIO_LCDCA_SEG26 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) -#define GPIO_LCDCA_SEG27 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) -#define GPIO_LCDCA_SEG28 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) -#define GPIO_LCDCA_SEG29 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) -#define GPIO_LCDCA_SEG30 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) -#define GPIO_LCDCA_SEG31 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) -#define GPIO_LCDCA_SEG32 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) -#define GPIO_LCDCA_SEG33 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) -#define GPIO_LCDCA_SEG34 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) -#define GPIO_LCDCA_SEG35 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -#define GPIO_LCDCA_SEG36 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) -#define GPIO_LCDCA_SEG37 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) -#define GPIO_LCDCA_SEG38 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) -#define GPIO_LCDCA_SEG39 (GPIO_FUNCF | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_LCDCA_COM0 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN12) +#define GPIO_LCDCA_COM1 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN11) +#define GPIO_LCDCA_COM2 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN10) +#define GPIO_LCDCA_COM3 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN9) +#define GPIO_LCDCA_SEG0 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN15) +#define GPIO_LCDCA_SEG1 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN16) +#define GPIO_LCDCA_SEG2 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN17) +#define GPIO_LCDCA_SEG3 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN18) +#define GPIO_LCDCA_SEG4 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN19) +#define GPIO_LCDCA_SEG5 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN13) +#define GPIO_LCDCA_SEG6 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN14) +#define GPIO_LCDCA_SEG7 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN15) +#define GPIO_LCDCA_SEG8 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN16) +#define GPIO_LCDCA_SEG9 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN17) +#define GPIO_LCDCA_SEG10 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN20) +#define GPIO_LCDCA_SEG11 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN21) +#define GPIO_LCDCA_SEG12 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN22) +#define GPIO_LCDCA_SEG13 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN23) +#define GPIO_LCDCA_SEG14 (GPIO_FUNCF | GPIO_PORTB | GPIO_PIN8) +#define GPIO_LCDCA_SEG15 (GPIO_FUNCF | GPIO_PORTB | GPIO_PIN9) +#define GPIO_LCDCA_SEG16 (GPIO_FUNCF | GPIO_PORTB | GPIO_PIN10) +#define GPIO_LCDCA_SEG17 (GPIO_FUNCF | GPIO_PORTB | GPIO_PIN11) +#define GPIO_LCDCA_SEG18 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN18) +#define GPIO_LCDCA_SEG19 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN19) +#define GPIO_LCDCA_SEG20 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN20) +#define GPIO_LCDCA_SEG21 (GPIO_FUNCF | GPIO_PORTB | GPIO_PIN7) +#define GPIO_LCDCA_SEG22 (GPIO_FUNCF | GPIO_PORTB | GPIO_PIN6) +#define GPIO_LCDCA_SEG23 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN8) +#define GPIO_LCDCA_SEG24 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN24) +#define GPIO_LCDCA_SEG25 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN25) +#define GPIO_LCDCA_SEG26 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN26) +#define GPIO_LCDCA_SEG27 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN27) +#define GPIO_LCDCA_SEG28 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN28) +#define GPIO_LCDCA_SEG29 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN29) +#define GPIO_LCDCA_SEG30 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN30) +#define GPIO_LCDCA_SEG31 (GPIO_FUNCF | GPIO_PORTC | GPIO_PIN31) +#define GPIO_LCDCA_SEG32 (GPIO_FUNCF | GPIO_PORTB | GPIO_PIN12) +#define GPIO_LCDCA_SEG33 (GPIO_FUNCF | GPIO_PORTB | GPIO_PIN13) +#define GPIO_LCDCA_SEG34 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN21) +#define GPIO_LCDCA_SEG35 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN22) +#define GPIO_LCDCA_SEG36 (GPIO_FUNCF | GPIO_PORTB | GPIO_PIN14) +#define GPIO_LCDCA_SEG37 (GPIO_FUNCF | GPIO_PORTB | GPIO_PIN15) +#define GPIO_LCDCA_SEG38 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN23) +#define GPIO_LCDCA_SEG39 (GPIO_FUNCF | GPIO_PORTA | GPIO_PIN24) /* Parallel Capture */ -#define GPIO_PARC_PCCK_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) -#define GPIO_PARC_PCCK_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) -#define GPIO_PARC_PCDATA0_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) -#define GPIO_PARC_PCDATA0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) -#define GPIO_PARC_PCDATA1_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) -#define GPIO_PARC_PCDATA1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) -#define GPIO_PARC_PCDATA2_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) -#define GPIO_PARC_PCDATA2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) -#define GPIO_PARC_PCDATA3_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) -#define GPIO_PARC_PCDATA3_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) -#define GPIO_PARC_PCDATA4_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) -#define GPIO_PARC_PCDATA4_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) -#define GPIO_PARC_PCDATA5_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) -#define GPIO_PARC_PCDATA5_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) -#define GPIO_PARC_PCDATA6_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) -#define GPIO_PARC_PCDATA6_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) -#define GPIO_PARC_PCDATA7_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) -#define GPIO_PARC_PCDATA7_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) -#define GPIO_PARC_PCEN1_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) -#define GPIO_PARC_PCEN1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) -#define GPIO_PARC_PCEN2_1 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) -#define GPIO_PARC_PCEN2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_PARC_PCCK_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN17) +#define GPIO_PARC_PCCK_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN21) +#define GPIO_PARC_PCDATA0_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN9) +#define GPIO_PARC_PCDATA0_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN24) +#define GPIO_PARC_PCDATA1_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN10) +#define GPIO_PARC_PCDATA1_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN25) +#define GPIO_PARC_PCDATA2_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN11) +#define GPIO_PARC_PCDATA2_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN26) +#define GPIO_PARC_PCDATA3_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN12) +#define GPIO_PARC_PCDATA3_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN27) +#define GPIO_PARC_PCDATA4_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN13) +#define GPIO_PARC_PCDATA4_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN28) +#define GPIO_PARC_PCDATA5_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN14) +#define GPIO_PARC_PCDATA5_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN29) +#define GPIO_PARC_PCDATA6_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN15) +#define GPIO_PARC_PCDATA6_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN30) +#define GPIO_PARC_PCDATA7_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN16) +#define GPIO_PARC_PCDATA7_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN31) +#define GPIO_PARC_PCEN1_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN18) +#define GPIO_PARC_PCEN1_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN22) +#define GPIO_PARC_PCEN2_1 (GPIO_FUNCD | GPIO_PORTA | GPIO_PIN19) +#define GPIO_PARC_PCEN2_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN23) /* Peripheral Event Controller */ -#define GPIO_PEVC_PAD_EVT0_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) -#define GPIO_PEVC_PAD_EVT0_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) -#define GPIO_PEVC_PAD_EVT0_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) -#define GPIO_PEVC_PAD_EVT0_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) -#define GPIO_PEVC_PAD_EVT1_1 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) -#define GPIO_PEVC_PAD_EVT1_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) -#define GPIO_PEVC_PAD_EVT1_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) -#define GPIO_PEVC_PAD_EVT1_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) -#define GPIO_PEVC_PAD_EVT2_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) -#define GPIO_PEVC_PAD_EVT2_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) -#define GPIO_PEVC_PAD_EVT2_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) -#define GPIO_PEVC_PAD_EVT2_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) -#define GPIO_PEVC_PAD_EVT3_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) -#define GPIO_PEVC_PAD_EVT3_2 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) -#define GPIO_PEVC_PAD_EVT3_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_PEVC_PAD_EVT0_1 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN8) +#define GPIO_PEVC_PAD_EVT0_2 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN12) +#define GPIO_PEVC_PAD_EVT0_3 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN24) +#define GPIO_PEVC_PAD_EVT0_4 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN7) +#define GPIO_PEVC_PAD_EVT1_1 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN9) +#define GPIO_PEVC_PAD_EVT1_2 (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN13) +#define GPIO_PEVC_PAD_EVT1_3 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN25) +#define GPIO_PEVC_PAD_EVT1_4 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN8) +#define GPIO_PEVC_PAD_EVT2_1 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN9) +#define GPIO_PEVC_PAD_EVT2_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN10) +#define GPIO_PEVC_PAD_EVT2_3 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN11) +#define GPIO_PEVC_PAD_EVT2_4 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN26) +#define GPIO_PEVC_PAD_EVT3_1 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN10) +#define GPIO_PEVC_PAD_EVT3_2 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN11) +#define GPIO_PEVC_PAD_EVT3_3 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN27) /* System Control Interface */ -#define GPIO_SCIF_GCLK0_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) -#define GPIO_SCIF_GCLK0_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) -#define GPIO_SCIF_GCLK0_3 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) -#define GPIO_SCIF_GCLK0_4 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) -#define GPIO_SCIF_GCLK1_1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) -#define GPIO_SCIF_GCLK1_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) -#define GPIO_SCIF_GCLK1_3 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) -#define GPIO_SCIF_GCLK2_1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) -#define GPIO_SCIF_GCLK2_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) -#define GPIO_SCIF_GCLK3_1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) -#define GPIO_SCIF_GCLK3_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) -#define GPIO_SCIF_GCLK_IN0_1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) -#define GPIO_SCIF_GCLK_IN0_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) -#define GPIO_SCIF_GCLK_IN0_3 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) -#define GPIO_SCIF_GCLK_IN1_1 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) -#define GPIO_SCIF_GCLK_IN1_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) -#define GPIO_SCIF_GCLK_IN1_3 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_SCIF_GCLK0_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN2) +#define GPIO_SCIF_GCLK0_2 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN19) +#define GPIO_SCIF_GCLK0_3 (GPIO_FUNCE | GPIO_PORTB | GPIO_PIN10) +#define GPIO_SCIF_GCLK0_4 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN26) +#define GPIO_SCIF_GCLK1_1 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN20) +#define GPIO_SCIF_GCLK1_2 (GPIO_FUNCE | GPIO_PORTB | GPIO_PIN11) +#define GPIO_SCIF_GCLK1_3 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN27) +#define GPIO_SCIF_GCLK2_1 (GPIO_FUNCE | GPIO_PORTB | GPIO_PIN12) +#define GPIO_SCIF_GCLK2_2 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN28) +#define GPIO_SCIF_GCLK3_1 (GPIO_FUNCE | GPIO_PORTB | GPIO_PIN13) +#define GPIO_SCIF_GCLK3_2 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN29) +#define GPIO_SCIF_GCLK_IN0_1 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN23) +#define GPIO_SCIF_GCLK_IN0_2 (GPIO_FUNCE | GPIO_PORTB | GPIO_PIN14) +#define GPIO_SCIF_GCLK_IN0_3 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN30) +#define GPIO_SCIF_GCLK_IN1_1 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN24) +#define GPIO_SCIF_GCLK_IN1_2 (GPIO_FUNCE | GPIO_PORTB | GPIO_PIN15) +#define GPIO_SCIF_GCLK_IN1_3 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN31) /* Serial Peripheral Interface */ -#define GPIO_SPI_MISO_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) -#define GPIO_SPI_MISO_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) -#define GPIO_SPI_MISO_3 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) -#define GPIO_SPI_MISO_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN3) -#define GPIO_SPI_MISO_5 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) -#define GPIO_SPI_MISO_6 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) -#define GPIO_SPI_MOSI_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -#define GPIO_SPI_MOSI_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) -#define GPIO_SPI_MOSI_3 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) -#define GPIO_SPI_MOSI_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) -#define GPIO_SPI_MOSI_5 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) -#define GPIO_SPI_NPCS0_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) -#define GPIO_SPI_NPCS0_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) -#define GPIO_SPI_NPCS0_3 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) -#define GPIO_SPI_NPCS0_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) -#define GPIO_SPI_NPCS0_5 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) -#define GPIO_SPI_NPCS1_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) -#define GPIO_SPI_NPCS1_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) -#define GPIO_SPI_NPCS1_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) -#define GPIO_SPI_NPCS1_4 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) -#define GPIO_SPI_NPCS2_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) -#define GPIO_SPI_NPCS2_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) -#define GPIO_SPI_NPCS2_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) -#define GPIO_SPI_NPCS3_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) -#define GPIO_SPI_NPCS3_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) -#define GPIO_SPI_NPCS3_3 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) -#define GPIO_SPI_SCK_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) -#define GPIO_SPI_SCK_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) -#define GPIO_SPI_SCK_3 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) -#define GPIO_SPI_SCK_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_SPI_MISO_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN21) +#define GPIO_SPI_MISO_2 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN27) +#define GPIO_SPI_MISO_3 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN4) +#define GPIO_SPI_MISO_4 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN3) +#define GPIO_SPI_MISO_5 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN14) +#define GPIO_SPI_MISO_6 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN28) +#define GPIO_SPI_MOSI_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN22) +#define GPIO_SPI_MOSI_2 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN28) +#define GPIO_SPI_MOSI_3 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN5) +#define GPIO_SPI_MOSI_4 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN15) +#define GPIO_SPI_MOSI_5 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN29) +#define GPIO_SPI_NPCS0_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN24) +#define GPIO_SPI_NPCS0_2 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN30) +#define GPIO_SPI_NPCS0_3 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN3) +#define GPIO_SPI_NPCS0_4 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN2) +#define GPIO_SPI_NPCS0_5 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN31) +#define GPIO_SPI_NPCS1_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN31) +#define GPIO_SPI_NPCS1_2 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN2) +#define GPIO_SPI_NPCS1_3 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN13) +#define GPIO_SPI_NPCS1_4 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN13) +#define GPIO_SPI_NPCS2_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN0) +#define GPIO_SPI_NPCS2_2 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN11) +#define GPIO_SPI_NPCS2_3 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN14) +#define GPIO_SPI_NPCS3_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN1) +#define GPIO_SPI_NPCS3_2 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN12) +#define GPIO_SPI_NPCS3_3 (GPIO_FUNCC | GPIO_PORTA | GPIO_PIN15) +#define GPIO_SPI_SCK_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN23) +#define GPIO_SPI_SCK_2 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN29) +#define GPIO_SPI_SCK_3 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN6) +#define GPIO_SPI_SCK_4 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN30) /* Timer/Counters */ -#define GPIO_TC0_A0_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) -#define GPIO_TC0_A0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) -#define GPIO_TC0_A1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) -#define GPIO_TC0_A1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) -#define GPIO_TC0_A2_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) -#define GPIO_TC0_A2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) -#define GPIO_TC0_B0_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) -#define GPIO_TC0_B0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) -#define GPIO_TC0_B1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) -#define GPIO_TC0_B1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) -#define GPIO_TC0_B2_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) -#define GPIO_TC0_B2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) -#define GPIO_TC0_CLK0_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) -#define GPIO_TC0_CLK0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) -#define GPIO_TC0_CLK1_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) -#define GPIO_TC0_CLK1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) -#define GPIO_TC0_CLK2_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) -#define GPIO_TC0_CLK2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) - -#define GPIO_TC1_A0_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) -#define GPIO_TC1_A0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) -#define GPIO_TC1_A1_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) -#define GPIO_TC1_A1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) -#define GPIO_TC1_A2_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) -#define GPIO_TC1_A2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) -#define GPIO_TC1_B0_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) -#define GPIO_TC1_B0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) -#define GPIO_TC1_B1_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) -#define GPIO_TC1_B1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) -#define GPIO_TC1_B2_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) -#define GPIO_TC1_B2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) -#define GPIO_TC1_CLK0_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) -#define GPIO_TC1_CLK0_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) -#define GPIO_TC1_CLK1_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) -#define GPIO_TC1_CLK1_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) -#define GPIO_TC1_CLK2_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) -#define GPIO_TC1_CLK2_2 (GPIO_FUNCD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) +#define GPIO_TC0_A0_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN8) +#define GPIO_TC0_A0_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN7) +#define GPIO_TC0_A1_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN10) +#define GPIO_TC0_A1_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN9) +#define GPIO_TC0_A2_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN12) +#define GPIO_TC0_A2_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN11) +#define GPIO_TC0_B0_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TC0_B0_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN8) +#define GPIO_TC0_B1_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN11) +#define GPIO_TC0_B1_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN10) +#define GPIO_TC0_B2_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN13) +#define GPIO_TC0_B2_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN12) +#define GPIO_TC0_CLK0_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN14) +#define GPIO_TC0_CLK0_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN13) +#define GPIO_TC0_CLK1_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN15) +#define GPIO_TC0_CLK1_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN14) +#define GPIO_TC0_CLK2_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN16) +#define GPIO_TC0_CLK2_2 (GPIO_FUNCD | GPIO_PORTB | GPIO_PIN15) + +#define GPIO_TC1_A0_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN15) +#define GPIO_TC1_A0_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN0) +#define GPIO_TC1_A1_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN17) +#define GPIO_TC1_A1_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN2) +#define GPIO_TC1_A2_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN19) +#define GPIO_TC1_A2_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN4) +#define GPIO_TC1_B0_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN16) +#define GPIO_TC1_B0_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN1) +#define GPIO_TC1_B1_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN18) +#define GPIO_TC1_B1_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN3) +#define GPIO_TC1_B2_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN20) +#define GPIO_TC1_B2_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN5) +#define GPIO_TC1_CLK0_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN21) +#define GPIO_TC1_CLK0_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN6) +#define GPIO_TC1_CLK1_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN22) +#define GPIO_TC1_CLK1_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN7) +#define GPIO_TC1_CLK2_1 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN23) +#define GPIO_TC1_CLK2_2 (GPIO_FUNCD | GPIO_PORTC | GPIO_PIN8) /* Two-wire Master Interface */ -#define GPIO_TWIM2_TWCK (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -#define GPIO_TWIM2_TWD (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) -#define GPIO_TWIM3_TWCK (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) -#define GPIO_TWIM3_TWD (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) -#define GPIO_TWIMS0_TWCK (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) -#define GPIO_TWIMS0_TWD (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) -#define GPIO_TWIMS1_TWCK (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) -#define GPIO_TWIMS1_TWD (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0) +#define GPIO_TWIM2_TWCK (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN22) +#define GPIO_TWIM2_TWD (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN21) +#define GPIO_TWIM3_TWCK (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN15) +#define GPIO_TWIM3_TWD (GPIO_FUNCC | GPIO_PORTB | GPIO_PIN14) +#define GPIO_TWIMS0_TWCK (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN24) +#define GPIO_TWIMS0_TWD (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN23) +#define GPIO_TWIMS1_TWCK (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN1) +#define GPIO_TWIMS1_TWD (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN0) /* USARTs */ -#define GPIO_USART0_CLK_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) -#define GPIO_USART0_CLK_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) -#define GPIO_USART0_CLK_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) -#define GPIO_USART0_CLK_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) -#define GPIO_USART0_CTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) -#define GPIO_USART0_CTS_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) -#define GPIO_USART0_CTS_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) -#define GPIO_USART0_RTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) -#define GPIO_USART0_RTS_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) -#define GPIO_USART0_RTS_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) -#define GPIO_USART0_RTS_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) -#define GPIO_USART0_RXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) -#define GPIO_USART0_RXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) -#define GPIO_USART0_RXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) -#define GPIO_USART0_RXD_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0) -#define GPIO_USART0_RXD_5 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) -#define GPIO_USART0_TXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) -#define GPIO_USART0_TXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) -#define GPIO_USART0_TXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) -#define GPIO_USART0_TXD_4 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) -#define GPIO_USART0_TXD_5 (GPIO_FUNCC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) - -#define GPIO_USART1_CLK_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) -#define GPIO_USART1_CLK_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) -#define GPIO_USART1_CLK_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) -#define GPIO_USART1_CTS (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) -#define GPIO_USART1_RTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) -#define GPIO_USART1_RTS_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) -#define GPIO_USART1_RTS_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) -#define GPIO_USART1_RXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) -#define GPIO_USART1_RXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) -#define GPIO_USART1_RXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) -#define GPIO_USART1_TXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) -#define GPIO_USART1_TXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) -#define GPIO_USART1_TXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) - -#define GPIO_USART2_CLK_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) -#define GPIO_USART2_CLK_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) -#define GPIO_USART2_CTS_1 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -#define GPIO_USART2_CTS_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) -#define GPIO_USART2_RTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) -#define GPIO_USART2_RTS_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) -#define GPIO_USART2_RXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) -#define GPIO_USART2_RXD_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) -#define GPIO_USART2_RXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) -#define GPIO_USART2_TXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) -#define GPIO_USART2_TXD_2 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) -#define GPIO_USART2_TXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) - -#define GPIO_USART3_CLK_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) -#define GPIO_USART3_CLK_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) -#define GPIO_USART3_CLK_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) -#define GPIO_USART3_CLK_4 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) -#define GPIO_USART3_CTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) -#define GPIO_USART3_CTS_2 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) -#define GPIO_USART3_RTS_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN6) -#define GPIO_USART3_RTS_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) -#define GPIO_USART3_RTS_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) -#define GPIO_USART3_RTS_4 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) -#define GPIO_USART3_RXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) -#define GPIO_USART3_RXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) -#define GPIO_USART3_RXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) -#define GPIO_USART3_RXD_4 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) -#define GPIO_USART3_TXD_1 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) -#define GPIO_USART3_TXD_2 (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) -#define GPIO_USART3_TXD_3 (GPIO_FUNCB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) -#define GPIO_USART3_TXD_4 (GPIO_FUNCE | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_USART0_CLK_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN10) +#define GPIO_USART0_CLK_2 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN13) +#define GPIO_USART0_CLK_3 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN4) +#define GPIO_USART0_CLK_4 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN0) +#define GPIO_USART0_CTS_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN9) +#define GPIO_USART0_CTS_2 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN11) +#define GPIO_USART0_CTS_3 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN2) +#define GPIO_USART0_RTS_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN8) +#define GPIO_USART0_RTS_2 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN12) +#define GPIO_USART0_RTS_3 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN6) +#define GPIO_USART0_RTS_4 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN1) +#define GPIO_USART0_RXD_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN11) +#define GPIO_USART0_RXD_2 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN14) +#define GPIO_USART0_RXD_3 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN5) +#define GPIO_USART0_RXD_4 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN0) +#define GPIO_USART0_RXD_5 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN2) +#define GPIO_USART0_TXD_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN12) +#define GPIO_USART0_TXD_2 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN15) +#define GPIO_USART0_TXD_3 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN7) +#define GPIO_USART0_TXD_4 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN1) +#define GPIO_USART0_TXD_5 (GPIO_FUNCC | GPIO_PORTC | GPIO_PIN3) + +#define GPIO_USART1_CLK_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN14) +#define GPIO_USART1_CLK_2 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN25) +#define GPIO_USART1_CLK_3 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN3) +#define GPIO_USART1_CTS (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN21) +#define GPIO_USART1_RTS_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN13) +#define GPIO_USART1_RTS_2 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN24) +#define GPIO_USART1_RTS_3 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN2) +#define GPIO_USART1_RXD_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN15) +#define GPIO_USART1_RXD_2 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN26) +#define GPIO_USART1_RXD_3 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN4) +#define GPIO_USART1_TXD_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN16) +#define GPIO_USART1_TXD_2 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN27) +#define GPIO_USART1_TXD_3 (GPIO_FUNCB | GPIO_PORTB | GPIO_PIN5) + +#define GPIO_USART2_CLK_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN18) +#define GPIO_USART2_CLK_2 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN8) +#define GPIO_USART2_CTS_1 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN22) +#define GPIO_USART2_CTS_2 (GPIO_FUNCE | GPIO_PORTC | GPIO_PIN8) +#define GPIO_USART2_RTS_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN17) +#define GPIO_USART2_RTS_2 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN7) +#define GPIO_USART2_RXD_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN19) +#define GPIO_USART2_RXD_2 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN25) +#define GPIO_USART2_RXD_3 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN11) +#define GPIO_USART2_TXD_1 (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN20) +#define GPIO_USART2_TXD_2 (GPIO_FUNCB | GPIO_PORTA | GPIO_PIN26) +#define GPIO_USART2_TXD_3 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN12) + +#define GPIO_USART3_CLK_1 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN8) +#define GPIO_USART3_CLK_2 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN31) +#define GPIO_USART3_CLK_3 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN14) +#define GPIO_USART3_CLK_4 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN29) +#define GPIO_USART3_CTS_1 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN7) +#define GPIO_USART3_CTS_2 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN28) +#define GPIO_USART3_RTS_1 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN6) +#define GPIO_USART3_RTS_2 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN30) +#define GPIO_USART3_RTS_3 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN13) +#define GPIO_USART3_RTS_4 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN27) +#define GPIO_USART3_RXD_1 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN9) +#define GPIO_USART3_RXD_2 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN28) +#define GPIO_USART3_RXD_3 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN9) +#define GPIO_USART3_RXD_4 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN30) +#define GPIO_USART3_TXD_1 (GPIO_FUNCA | GPIO_PORTB | GPIO_PIN10) +#define GPIO_USART3_TXD_2 (GPIO_FUNCA | GPIO_PORTC | GPIO_PIN29) +#define GPIO_USART3_TXD_3 (GPIO_FUNCB | GPIO_PORTC | GPIO_PIN10) +#define GPIO_USART3_TXD_4 (GPIO_FUNCE | GPIO_PORTA | GPIO_PIN31) /* USB 2.0 Interface */ -#define GPIO_USBC_DM (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) -#define GPIO_USBC_DP (GPIO_FUNCA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_USBC_DM (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN25) +#define GPIO_USBC_DP (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN26) /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/sam34/sam4l_gpio.c b/nuttx/arch/arm/src/sam34/sam4l_gpio.c index 64f1d60006..88f3d02cb3 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_gpio.c +++ b/nuttx/arch/arm/src/sam34/sam4l_gpio.c @@ -333,8 +333,6 @@ static inline int sam_configoutput(uintptr_t base, uint32_t pin, static inline int sam_configperiph(uintptr_t base, uint32_t pin, gpio_pinset_t cfgset) { - * Peripheral: MM.. FFFE .... IIG. .PPB BBBB - gpio_pinset_t edges; /* Select the peripheral function. @@ -414,7 +412,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, /* REVISIT: Should event generation be enabled now? I am assuming so */ - if (eges = GPIO_PERIPH_EVENTS) + if ((cfgset & GPIO_PERIPH_EVENTS) != 0) { /* Rising only.. disable interrrupts on the falling edge */ diff --git a/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h b/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h index edeb24fe10..e9efe88fea 100644 --- a/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h +++ b/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h @@ -80,7 +80,7 @@ * 2Hz, then a fatal error has been detected and the system has halted. */ -#define GPIO_LED0 (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | \ +#define GPIO_LED0 (GPIO_OUTPUT | GPIO_PULL_NONE | GPIO_PORTC | \ GPIO_OUTPUT_SET | GPIO_PIN7) /* QTouch button: The SAM4L Xplained Pro kit has one QTouch button. The connection @@ -99,8 +99,8 @@ * PC24 SW0 */ -#define GPIO_SW0 (GPIO_INPUT | GPIO_CFG_PULLUP | GPIO_CFG_DEGLITCH | \ - GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_SW0 (GPIO_INPUT | GPIO_PULL_UP | GPIO_GLITCH_FILTER | GPIO_PORTC | \ + GPIO_PIN24) #define IRQ_SW0 SAM_IRQ_PC24 /************************************************************************************ From f092889d19ae4cc2c0c35e8ffb70ebe024e36c75 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 4 Jun 2013 16:35:43 -0600 Subject: [PATCH 30/41] Add configs/sam4l-xplained/src/up_userleds.c --- nuttx/arch/arm/src/sam34/sam_clockconfig.c | 1 - nuttx/configs/sam3u-ek/include/board.h | 1 - nuttx/configs/sam3u-ek/src/up_lcd.c | 1 - nuttx/configs/sam3u-ek/src/up_leds.c | 1 - nuttx/configs/sam3u-ek/src/up_touchscreen.c | 1 - nuttx/configs/sam4l-xplained/include/board.h | 30 +++- nuttx/configs/sam4l-xplained/src/Makefile | 12 +- .../configs/sam4l-xplained/src/sam_autoleds.c | 5 - .../configs/sam4l-xplained/src/sam_userleds.c | 141 ++++++++++++++++++ 9 files changed, 180 insertions(+), 13 deletions(-) create mode 100644 nuttx/configs/sam4l-xplained/src/sam_userleds.c diff --git a/nuttx/arch/arm/src/sam34/sam_clockconfig.c b/nuttx/arch/arm/src/sam34/sam_clockconfig.c index 8a3988a405..051e22ac76 100644 --- a/nuttx/arch/arm/src/sam34/sam_clockconfig.c +++ b/nuttx/arch/arm/src/sam34/sam_clockconfig.c @@ -1,5 +1,4 @@ /**************************************************************************** - * arch/arm/src/sam34/sam_clockconfig.c * arch/arm/src/chip/sam_clockconfig.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. diff --git a/nuttx/configs/sam3u-ek/include/board.h b/nuttx/configs/sam3u-ek/include/board.h index 213a6f4e41..b5e1124793 100644 --- a/nuttx/configs/sam3u-ek/include/board.h +++ b/nuttx/configs/sam3u-ek/include/board.h @@ -1,6 +1,5 @@ /************************************************************************************ * configs/sam3u-ek/include/board.h - * include/arch/board/board.h * * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/nuttx/configs/sam3u-ek/src/up_lcd.c b/nuttx/configs/sam3u-ek/src/up_lcd.c index 2190fb15e9..ebeb35d911 100644 --- a/nuttx/configs/sam3u-ek/src/up_lcd.c +++ b/nuttx/configs/sam3u-ek/src/up_lcd.c @@ -1,6 +1,5 @@ /************************************************************************************** * configs/sam3u-ek/src/up_lcd.c - * arch/arm/src/board/up_lcd.c * * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/nuttx/configs/sam3u-ek/src/up_leds.c b/nuttx/configs/sam3u-ek/src/up_leds.c index 1c6c4aeb70..3a6d09a48a 100644 --- a/nuttx/configs/sam3u-ek/src/up_leds.c +++ b/nuttx/configs/sam3u-ek/src/up_leds.c @@ -1,6 +1,5 @@ /**************************************************************************** * configs/sam3u-ek/src/up_leds.c - * arch/arm/src/board/up_leds.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/nuttx/configs/sam3u-ek/src/up_touchscreen.c b/nuttx/configs/sam3u-ek/src/up_touchscreen.c index 71b12f571d..251d9b624b 100644 --- a/nuttx/configs/sam3u-ek/src/up_touchscreen.c +++ b/nuttx/configs/sam3u-ek/src/up_touchscreen.c @@ -1,6 +1,5 @@ /************************************************************************************ * configs/sam3u-ek/src/up_touchscreen.c - * arch/arm/src/board/up_touchscreen.c * * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/nuttx/configs/sam4l-xplained/include/board.h b/nuttx/configs/sam4l-xplained/include/board.h index cb70aff041..ca7bb0ef1f 100644 --- a/nuttx/configs/sam4l-xplained/include/board.h +++ b/nuttx/configs/sam4l-xplained/include/board.h @@ -115,8 +115,18 @@ * * This LED is controlled by PC07 and LED0 can be activated by driving the * PC07 to GND. - * - * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + */ + +/* LED index values for use with sam_setled() */ + +#define BOARD_LED0 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with sam_setleds() */ + +#define BOARD_LED0_BIT (1 << BOARD_LED0) + +/* When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will * control LED0 as defined below. Thus is LED0 is statically on, NuttX has * successfully booted and is, apparently, running normmally. If LED0 is * flashing at approximately 2Hz, then a fatal error has been detected and the @@ -198,6 +208,22 @@ extern "C" { void sam_boardinitialize(void); +/************************************************************************************ + * Name: sam_ledinit, sam_setled, and sam_setleds + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If + * CONFIG_ARCH_LEDS is not defined, then the following interfaces are available to + * control the LEDs from user applications. + * + ************************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +void sam_ledinit(void); +void sam_setled(int led, bool ledon); +void sam_setleds(uint8_t ledset); +#endif + /************************************************************************************ * Name: up_buttoninit * diff --git a/nuttx/configs/sam4l-xplained/src/Makefile b/nuttx/configs/sam4l-xplained/src/Makefile index 4b1efd0cef..15b5ff67ef 100644 --- a/nuttx/configs/sam4l-xplained/src/Makefile +++ b/nuttx/configs/sam4l-xplained/src/Makefile @@ -40,7 +40,17 @@ CFLAGS += -I$(TOPDIR)/sched ASRCS = AOBJS = $(ASRCS:.S=$(OBJEXT)) -CSRCS = sam_boot.c sam_autoleds.c sam_buttons.c sam_spi.c +CSRCS = sam_boot.c sam_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += sam_autoleds.c +else +CSRCS += sam_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += sam_buttons.c +endif COBJS = $(CSRCS:.c=$(OBJEXT)) diff --git a/nuttx/configs/sam4l-xplained/src/sam_autoleds.c b/nuttx/configs/sam4l-xplained/src/sam_autoleds.c index 1ea1afbe49..09b673a966 100644 --- a/nuttx/configs/sam4l-xplained/src/sam_autoleds.c +++ b/nuttx/configs/sam4l-xplained/src/sam_autoleds.c @@ -92,11 +92,6 @@ # define ledvdbg(x...) #endif -#define LED_OFF 0 -#define LED_ON 1 -#define LED_NOCHANGE 2 -#define LED_MASK 3 - /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/nuttx/configs/sam4l-xplained/src/sam_userleds.c b/nuttx/configs/sam4l-xplained/src/sam_userleds.c new file mode 100644 index 0000000000..bf77e2c7f7 --- /dev/null +++ b/nuttx/configs/sam4l-xplained/src/sam_userleds.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * configs/sam4l-xplained/src/sam_userleds.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* There are three LEDs on board the SAM4L Xplained Pro board: The EDBG + * controls two of the LEDs, a power LED and a status LED. There is only + * one user controllable LED, a yellow LED labeled LED0 near the SAM4L USB + * connector. + * + * This LED is controlled by PC07 and LED0 can be activated by driving the + * PC07 to GND. + * + * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + * control LED0. Otherwise, LED0 can be controlled from logic in this file. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "sam_gpio.h" +#include "sam4l-xplained.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG + * with CONFIG_DEBUG_VERBOSE too) + */ + +#ifdef CONFIG_DEBUG_LEDS +# define leddbg lldbg +# define ledvdbg llvdbg +#else +# define leddbg(x...) +# define ledvdbg(x...) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_ledinit + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the sam_ledinit() is + * available to initialize the LED0 from user application logic. + * + ****************************************************************************/ + +void sam_ledinit(void) +{ + (void)sam_configgpio(GPIO_LED0); +} + +/**************************************************************************** + * Name: sam_setled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the sam_setled() is + * available to control the LED0 from user application logic. + * + *****************************************************************************/ + +void sam_setled(int led, bool ledon) +{ + if (led == BOARD_LED0) + { + sam_gpiowrite(GPIO_LED0, !ledon); + } +} + +/**************************************************************************** + * Name: sam_setled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the sam_setleds() is + * available to control the LED0 from user application logic. NOTE: since + * there is only a single LED on-board, this is function is not very useful. + * + *****************************************************************************/ + +void sam_setleds(uint8_t ledset) +{ + sam_setled(BOARD_LED0, (ledset & BOARD_LED0_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ From 563911cc68e814bcacaf7f841b5002cdd9e7a25f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 5 Jun 2013 08:54:37 -0600 Subject: [PATCH 31/41] SAM4L GPIO port addressing fixes; SAM4L Xplained LED support; minor documentation updates --- nuttx/ChangeLog | 8 +- nuttx/Documentation/NuttxUserGuide.html | 26 +- nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h | 500 ++++++++++++++---- nuttx/arch/arm/src/sam34/sam4l_gpio.c | 18 +- .../configs/sam4l-xplained/src/sam_userleds.c | 3 +- 5 files changed, 430 insertions(+), 125 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index fcde5f0c28..88f3b26d10 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4896,4 +4896,10 @@ file to sam3u_gpio.h (2013-6-4). * nuttx/arch/arm/src/sam34/sam4l_gpio.c: Created GPIO driver for the SAM4L (2013-6-4). - + * nuttx/configs/sam4l-xplained/src/sam_userleds.c: Added. + (2013-6-4). + * configs/sam4l-xplained/src/sam_userleds.c: Add application + LED interfaces (2013-6-5). + * arch/arm/src/sam34/sam4l_gpio.c and arch/arm/src/sam34/chip/sam4l_gpio.h: + Fix GPIO port address; fix compilation errors (2013-6-5). + diff --git a/nuttx/Documentation/NuttxUserGuide.html b/nuttx/Documentation/NuttxUserGuide.html index 5d8f48767e..36428215d2 100644 --- a/nuttx/Documentation/NuttxUserGuide.html +++ b/nuttx/Documentation/NuttxUserGuide.html @@ -13,7 +13,7 @@

NuttX Operating System

User's Manual

by

Gregory Nutt

-

Last Updated: Aprill 22, 2013

+

Last Updated: June 4, 2013

@@ -8124,15 +8124,16 @@

2.11.5 Standard I/O

     #include <stdio.h>
 
+void   clearerr(register FILE *stream);
 int    fclose(FILE *stream);
 int    fflush(FILE *stream);
-FILE  *fdopen(int fd, const char *type);
-int    feof(FILE *stream);                               /* Prototyped but not implemented */
-int    ferror(FILE *stream);                             /* Prototyped but not implemented */
+int    feof(FILE *stream);
+int    ferror(FILE *stream);
 int    fileno(FAR FILE *stream);
 int    fgetc(FILE *stream);
 int    fgetpos(FILE *stream, fpos_t *pos);
 char  *fgets(char *s, int n, FILE *stream);
+FILE  *fdopen(int fd, const char *type);
 FILE  *fopen(const char *path, const char *type);
 int    fprintf(FILE *stream, const char *format, ...);
 int    fputc(int c, FILE *stream);
@@ -8143,19 +8144,30 @@ 
    2.11.5 Standard I/O
    
 long   ftell(FILE *stream);
 size_t fwrite(const void *ptr, size_t size, size_t n_items, FILE *stream);
 char  *gets(char *s);
+int    ungetc(int c, FAR FILE *stream);
 
 int    printf(const char *format, ...);
 int    puts(const char *s);
 int    rename(const char *source, const char *target);
-int    snprintf(FAR char *buf, size_t size, const char *format, ...);
 int    sprintf(char *dest, const char *format, ...);
+int    asprintf (FAR char **ptr, FAR const char *fmt, ...);
+int    snprintf(FAR char *buf, size_t size, const char *format, ...);
 int    sscanf(const char *buf, const char *fmt, ...);
-int    ungetc(int c, FILE *stream);
+void   perror(FAR const char *s);
+int    avsprintf(FAR char **ptr, const char *fmt, va_list ap);
+
 int    vprintf(const char *s, va_list ap);
 int    vfprintf(FILE *stream, const char *s, va_list ap);
+int    vsprintf(char *buf, const char *s, va_list ap);
+int    avsprintf(FAR char **ptr, const char *fmt, va_list ap);
 int    vsnprintf(FAR char *buf, size_t size, const char *format, va_list ap);
 int    vsscanf(char *buf, const char *s, va_list ap);
-int    vsprintf(char *buf, const char *s, va_list ap);
+
+FAR FILE *fdopen(int fd, FAR const char *type);
+int    dprintf(int fd, FAR const char *fmt, ...);
+int    vdprintf(int fd, FAR const char *fmt, va_list ap);
+
+int    statfs(FAR const char *path, FAR struct statfs *buf);
 
 #include <sys/stat.h>
 
diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h
index 4927ab7066..cf5631da3f 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h
@@ -94,8 +94,6 @@
 #define SAM_GPIO_OVRC_OFFSET       0x0058 /* Output Value Register Clear */
 #define SAM_GPIO_OVRT_OFFSET       0x005c /* Output Value Register Toggle */
 
-/* Pin Value Register Read (4 registers)*/
-
 #define SAM_GPIO_PVR_OFFSET        0x0060 /* Pin Value Register Read */
 
 /* {PUER, PDER} Selected Function
@@ -108,7 +106,7 @@
 
 #define SAM_GPIO_PUER_OFFSET       0x0070 /* Pull-up Enable Register Read/Write */
 #define SAM_GPIO_PUERS_OFFSET      0x0074 /* Pull-up Enable Register Set */
-#define SAM_GPIO_PUERC_OFFSET      0x0078 /* Pull-up Enable Register Clear*/ 
+#define SAM_GPIO_PUERC_OFFSET      0x0078 /* Pull-up Enable Register Clear */
 #define SAM_GPIO_PUERT_OFFSET      0x007c /* Pull-up Enable Register Toggle */
 
 #define SAM_GPIO_PDER_OFFSET       0x0080 /* Pull-down Enable Register Read/Write */
@@ -144,13 +142,8 @@
 #define SAM_GPIO_GFERC_OFFSET      0x00c8 /* Glitch Filter Enable Register Clear */
 #define SAM_GPIO_GFERT_OFFSET      0x00cc /* Glitch Filter Enable Register Toggle */
 
-/* Interrupt Flag Register Read (2 registers)*/
-
 #define SAM_GPIO_IFR_OFFSET        0x00d0 /* Interrupt Flag Register 0 Read */
-
-/* Interrupt Flag Register Clear (2 registers)*/
-
-#define SAM_GPIO_IFRC _OFFSET      0x00d8 /* Interrupt Flag Register 0 Clear */
+#define SAM_GPIO_IFRC_OFFSET       0x00d8 /* Interrupt Flag Register 0 Clear */
 
 /* {ODCR1, ODCR0} Output drive strength
  *
@@ -188,107 +181,398 @@
 #define SAM_GPIO_PARAMETER_OFFSET  0x01f8 /* Parameter Register Read */
 #define SAM_GPIO_VERSION_OFFSET    0x01fc /* Version Register Read */
 
+/* GPIO port offsets and addresses ******************************************************/
+
+#define SAM_GPIOA                  0
+#define SAM_GPIOB                  1
+#define SAM_GPIOC                  2
+
+#define SAM_GPIO_PORTSIZE          0x200
+#define SAM_GPION_OFFSET(n)        ((n) << 9)
+#define SAM_GPION_BASE(n)          (SAM_GPIO_BASE+SAM_GPION_OFFSET(n))
+#define SAM_GPIOA_BASE             SAM_GPION_BASE(SAM_GPIOA)
+#define SAM_GPIOB_BASE             SAM_GPION_BASE(SAM_GPIOB)
+#define SAM_GPIOC_BASE             SAM_GPION_BASE(SAM_GPIOC)
+
 /* GPIO register adresses ***************************************************************/
 
-#define SAM_GPIO_GPER              (SAM_GPIO_BASE+SAM_GPIO_GPER_OFFSET)
-#define SAM_GPIO_GPERS             (SAM_GPIO_BASE+SAM_GPIO_GPERS_OFFSET)
-#define SAM_GPIO_GPERC             (SAM_GPIO_BASE+SAM_GPIO_GPERC_OFFSET)
-#define SAM_GPIO_GPERT             (SAM_GPIO_BASE+SAM_GPIO_GPERT_OFFSET)
-
-#define SAM_GPIO_PMR0              (SAM_GPIO_BASE+SAM_GPIO_PMR0_OFFSET)
-#define SAM_GPIO_PMR0S             (SAM_GPIO_BASE+SAM_GPIO_PMR0S_OFFSET)
-#define SAM_GPIO_PMR0C             (SAM_GPIO_BASE+SAM_GPIO_PMR0C_OFFSET)
-#define SAM_GPIO_PMR0T             (SAM_GPIO_BASE+SAM_GPIO_PMR0T_OFFSET_
-
-#define SAM_GPIO_PMR1              (SAM_GPIO_BASE+SAM_GPIO_PMR1_OFFSET)
-#define SAM_GPIO_PMR1S             (SAM_GPIO_BASE+SAM_GPIO_PMR1S_OFFSET)
-#define SAM_GPIO_PMR1C             (SAM_GPIO_BASE+SAM_GPIO_PMR1C_OFFSET)
-#define SAM_GPIO_PMR1T             (SAM_GPIO_BASE+SAM_GPIO_PMR1T_OFFSET)
-
-#define SAM_GPIO_PMR2              (SAM_GPIO_BASE+SAM_GPIO_PMR2_OFFSET)
-#define SAM_GPIO_PMR2S             (SAM_GPIO_BASE+SAM_GPIO_PMR2S_OFFSET)
-#define SAM_GPIO_PMR2C             (SAM_GPIO_BASE+SAM_GPIO_PMR2C_OFFSET)
-#define SAM_GPIO_PMR2T             (SAM_GPIO_BASE+SAM_GPIO_PMR2T_OFFSET)
-
-#define SAM_GPIO_ODER              (SAM_GPIO_BASE+SAM_GPIO_ODER_OFFSET)
-#define SAM_GPIO_ODERS             (SAM_GPIO_BASE+SAM_GPIO_ODERS_OFFSET)
-#define SAM_GPIO_ODERC             (SAM_GPIO_BASE+SAM_GPIO_ODERC_OFFSET)
-#define SAM_GPIO_ODERT             (SAM_GPIO_BASE+SAM_GPIO_ODERT_OFFSET)
-
-#define SAM_GPIO_OVR               (SAM_GPIO_BASE+SAM_GPIO_OVR_OFFSET)
-#define SAM_GPIO_OVRS              (SAM_GPIO_BASE+SAM_GPIO_OVRS_OFFSET)
-#define SAM_GPIO_OVRC              (SAM_GPIO_BASE+SAM_GPIO_OVRC_OFFSET)
-#define SAM_GPIO_OVRT              (SAM_GPIO_BASE+SAM_GPIO_OVRT_OFFSET)
-
-/* Pin Value Register Read (4 registers)*/
-
-#define SAM_GPIO_PVR               (SAM_GPIO_BASE+SAM_GPIO_PVR_OFFSET)
-
-#define SAM_GPIO_PUER              (SAM_GPIO_BASE+SAM_GPIO_PUER_OFFSET)
-#define SAM_GPIO_PUERS             (SAM_GPIO_BASE+SAM_GPIO_PUERS_OFFSET)
-#define SAM_GPIO_PUERC             (SAM_GPIO_BASE+SAM_GPIO_PUERC_OFFSET)
-#define SAM_GPIO_PUERT             (SAM_GPIO_BASE+SAM_GPIO_PUERT_OFFSET)
-
-#define SAM_GPIO_PDER              (SAM_GPIO_BASE+SAM_GPIO_PDER_OFFSET)
-#define SAM_GPIO_PDERS             (SAM_GPIO_BASE+SAM_GPIO_PDERS_OFFSET)
-#define SAM_GPIO_PDERC             (SAM_GPIO_BASE+SAM_GPIO_PDERC_OFFSET)
-#define SAM_GPIO_PDERT             (SAM_GPIO_BASE+SAM_GPIO_PDERT_OFFSET)
-
-#define SAM_GPIO_IER               (SAM_GPIO_BASE+SAM_GPIO_IER_OFFSET)
-#define SAM_GPIO_IERS              (SAM_GPIO_BASE+SAM_GPIO_IERS_OFFSET)
-#define SAM_GPIO_IERC              (SAM_GPIO_BASE+SAM_GPIO_IERC_OFFSET)
-#define SAM_GPIO_IERT              (SAM_GPIO_BASE+SAM_GPIO_IERT_OFFSET)
-
-#define SAM_GPIO_IMR0              (SAM_GPIO_BASE+SAM_GPIO_IMR0_OFFSET)
-#define SAM_GPIO_IMR0S             (SAM_GPIO_BASE+SAM_GPIO_IMR0S_OFFSET)
-#define SAM_GPIO_IMR0C             (SAM_GPIO_BASE+SAM_GPIO_IMR0C_OFFSET)
-#define SAM_GPIO_IMR0T             (SAM_GPIO_BASE+SAM_GPIO_IMR0T_OFFSET)
-
-#define SAM_GPIO_IMR1              (SAM_GPIO_BASE+SAM_GPIO_IMR1_OFFSET)
-#define SAM_GPIO_IMR1S             (SAM_GPIO_BASE+SAM_GPIO_IMR1S_OFFSET)
-#define SAM_GPIO_IMR1C             (SAM_GPIO_BASE+SAM_GPIO_IMR1C_OFFSET)
-#define SAM_GPIO_IMR1T             (SAM_GPIO_BASE+SAM_GPIO_IMR1T_OFFSET)
-
-#define SAM_GPIO_GFER              (SAM_GPIO_BASE+SAM_GPIO_GFER_OFFSET)
-#define SAM_GPIO_GFERS             (SAM_GPIO_BASE+SAM_GPIO_GFERS_OFFSET)
-#define SAM_GPIO_GFERC             (SAM_GPIO_BASE+SAM_GPIO_GFERC_OFFSET)
-#define SAM_GPIO_GFERT             (SAM_GPIO_BASE+SAM_GPIO_GFERT_OFFSET)
-
-/* Interrupt Flag Register Read */
-
-#define SAM_GPIO_IFR               (SAM_GPIO_BASE+SAM_GPIO_IFR_OFFSET)
-
-/* Interrupt Flag Register Clear */
-
-#define SAM_GPIO_IFRC              (SAM_GPIO_BASE+SAM_GPIO_IFRC_OFFSET)
-
-#define SAM_GPIO_ODCR0             (SAM_GPIO_BASE+SAM_GPIO_ODCR0_OFFSET)
-#define SAM_GPIO_ODCR0S            (SAM_GPIO_BASE+SAM_GPIO_ODCR0S_OFFSET)
-#define SAM_GPIO_ODCR0C            (SAM_GPIO_BASE+SAM_GPIO_ODCR0C_OFFSET)
-#define SAM_GPIO_ODCR0T            (SAM_GPIO_BASE+SAM_GPIO_ODCR0T_OFFSET)
-
-#define SAM_GPIO_ODCR1             (SAM_GPIO_BASE+SAM_GPIO_ODCR1_OFFSET)
-#define SAM_GPIO_ODCR1S            (SAM_GPIO_BASE+SAM_GPIO_ODCR1S_OFFSET)
-#define SAM_GPIO_ODCR1C            (SAM_GPIO_BASE+SAM_GPIO_ODCR1C_OFFSET)
-#define SAM_GPIO_ODCR1T            (SAM_GPIO_BASE+SAM_GPIO_ODCR1T_OFFSET)
-
-#define SAM_GPIO_OSRR0             (SAM_GPIO_BASE+SAM_GPIO_OSRR0_OFFSET)
-#define SAM_GPIO_OSRR0S            (SAM_GPIO_BASE+SAM_GPIO_OSRR0S_OFFSET)
-#define SAM_GPIO_OSRR0C            (SAM_GPIO_BASE+SAM_GPIO_OSRR0C_OFFSET)
-#define SAM_GPIO_OSRR0T            (SAM_GPIO_BASE+SAM_GPIO_OSRR0T_OFFSET)
-
-#define SAM_GPIO_STER              (SAM_GPIO_BASE+SAM_GPIO_STER_OFFSET)
-#define SAM_GPIO_STERS             (SAM_GPIO_BASE+SAM_GPIO_STERS_OFFSET)
-#define SAM_GPIO_STERC             (SAM_GPIO_BASE+SAM_GPIO_STERC_OFFSET)
-#define SAM_GPIO_STERT             (SAM_GPIO_BASE+SAM_GPIO_STERT_OFFSET)
-
-#define SAM_GPIO_EVER              (SAM_GPIO_BASE+SAM_GPIO_EVER_OFFSET)
-#define SAM_GPIO_EVERS             (SAM_GPIO_BASE+SAM_GPIO_EVERS_OFFSET)
-#define SAM_GPIO_EVERC             (SAM_GPIO_BASE+SAM_GPIO_EVERC_OFFSET)
-#define SAM_GPIO_EVERT             (SAM_GPIO_BASE+SAM_GPIO_EVERT_OFFSET)
-
-#define SAM_GPIO_PARAMETER         (SAM_GPIO_BASE+SAM_GPIO_PARAMETER_OFFSET)
-#define SAM_GPIO_VERSION           (SAM_GPIO_BASE+SAM_GPIO_VERSION_OFFSET)
+#define SAM_GPIO_GPER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_GPER_OFFSET)
+#define SAM_GPIO_GPERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GPERS_OFFSET)
+#define SAM_GPIO_GPERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GPERC_OFFSET)
+#define SAM_GPIO_GPERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GPERT_OFFSET)
+
+#define SAM_GPIO_PMR0(n)           (SAM_GPION_BASE(n)+SAM_GPIO_PMR0_OFFSET)
+#define SAM_GPIO_PMR0S(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR0S_OFFSET)
+#define SAM_GPIO_PMR0C(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR0C_OFFSET)
+#define SAM_GPIO_PMR0T(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR0T_OFFSET_
+
+#define SAM_GPIO_PMR1(n)           (SAM_GPION_BASE(n)+SAM_GPIO_PMR1_OFFSET)
+#define SAM_GPIO_PMR1S(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR1S_OFFSET)
+#define SAM_GPIO_PMR1C(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR1C_OFFSET)
+#define SAM_GPIO_PMR1T(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR1T_OFFSET)
+
+#define SAM_GPIO_PMR2(n)           (SAM_GPION_BASE(n)+SAM_GPIO_PMR2_OFFSET)
+#define SAM_GPIO_PMR2S(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR2S_OFFSET)
+#define SAM_GPIO_PMR2C(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR2C_OFFSET)
+#define SAM_GPIO_PMR2T(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR2T_OFFSET)
+
+#define SAM_GPIO_ODER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_ODER_OFFSET)
+#define SAM_GPIO_ODERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_ODERS_OFFSET)
+#define SAM_GPIO_ODERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_ODERC_OFFSET)
+#define SAM_GPIO_ODERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_ODERT_OFFSET)
+
+#define SAM_GPIO_OVR(n)            (SAM_GPION_BASE(n)+SAM_GPIO_OVR_OFFSET)
+#define SAM_GPIO_OVRS(n)           (SAM_GPION_BASE(n)+SAM_GPIO_OVRS_OFFSET)
+#define SAM_GPIO_OVRC(n)           (SAM_GPION_BASE(n)+SAM_GPIO_OVRC_OFFSET)
+#define SAM_GPIO_OVRT(n)           (SAM_GPION_BASE(n)+SAM_GPIO_OVRT_OFFSET)
+
+#define SAM_GPIO_PVR(n)            (SAM_GPION_BASE(n)+SAM_GPIO_PVR_OFFSET)
+
+#define SAM_GPIO_PUER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_PUER_OFFSET)
+#define SAM_GPIO_PUERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PUERS_OFFSET)
+#define SAM_GPIO_PUERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PUERC_OFFSET)
+#define SAM_GPIO_PUERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PUERT_OFFSET)
+
+#define SAM_GPIO_PDER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_PDER_OFFSET)
+#define SAM_GPIO_PDERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PDERS_OFFSET)
+#define SAM_GPIO_PDERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PDERC_OFFSET)
+#define SAM_GPIO_PDERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PDERT_OFFSET)
+
+#define SAM_GPIO_IER(n)            (SAM_GPION_BASE(n)+SAM_GPIO_IER_OFFSET)
+#define SAM_GPIO_IERS(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IERS_OFFSET)
+#define SAM_GPIO_IERC(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IERC_OFFSET)
+#define SAM_GPIO_IERT(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IERT_OFFSET)
+
+#define SAM_GPIO_IMR0(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IMR0_OFFSET)
+#define SAM_GPIO_IMR0S(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR0S_OFFSET)
+#define SAM_GPIO_IMR0C(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR0C_OFFSET)
+#define SAM_GPIO_IMR0T(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR0T_OFFSET)
+
+#define SAM_GPIO_IMR1(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IMR1_OFFSET)
+#define SAM_GPIO_IMR1S(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR1S_OFFSET)
+#define SAM_GPIO_IMR1C(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR1C_OFFSET)
+#define SAM_GPIO_IMR1T(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR1T_OFFSET)
+
+#define SAM_GPIO_GFER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_GFER_OFFSET)
+#define SAM_GPIO_GFERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GFERS_OFFSET)
+#define SAM_GPIO_GFERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GFERC_OFFSET)
+#define SAM_GPIO_GFERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GFERT_OFFSET)
+
+#define SAM_GPIO_IFR(n)            (SAM_GPION_BASE(n)+SAM_GPIO_IFR_OFFSET)
+#define SAM_GPIO_IFRC(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IFRC_OFFSET)
+
+#define SAM_GPIO_ODCR0(n)          (SAM_GPION_BASE(n)+SAM_GPIO_ODCR0_OFFSET)
+#define SAM_GPIO_ODCR0S(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR0S_OFFSET)
+#define SAM_GPIO_ODCR0C(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR0C_OFFSET)
+#define SAM_GPIO_ODCR0T(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR0T_OFFSET)
+
+#define SAM_GPIO_ODCR1(n)          (SAM_GPION_BASE(n)+SAM_GPIO_ODCR1_OFFSET)
+#define SAM_GPIO_ODCR1S(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR1S_OFFSET)
+#define SAM_GPIO_ODCR1C(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR1C_OFFSET)
+#define SAM_GPIO_ODCR1T(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR1T_OFFSET)
+
+#define SAM_GPIO_OSRR0(n)          (SAM_GPION_BASE(n)+SAM_GPIO_OSRR0_OFFSET)
+#define SAM_GPIO_OSRR0S(n)         (SAM_GPION_BASE(n)+SAM_GPIO_OSRR0S_OFFSET)
+#define SAM_GPIO_OSRR0C(n)         (SAM_GPION_BASE(n)+SAM_GPIO_OSRR0C_OFFSET)
+#define SAM_GPIO_OSRR0T(n)         (SAM_GPION_BASE(n)+SAM_GPIO_OSRR0T_OFFSET)
+
+#define SAM_GPIO_STER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_STER_OFFSET)
+#define SAM_GPIO_STERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_STERS_OFFSET)
+#define SAM_GPIO_STERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_STERC_OFFSET)
+#define SAM_GPIO_STERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_STERT_OFFSET)
+
+#define SAM_GPIO_EVER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_EVER_OFFSET)
+#define SAM_GPIO_EVERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_EVERS_OFFSET)
+#define SAM_GPIO_EVERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_EVERC_OFFSET)
+#define SAM_GPIO_EVERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_EVERT_OFFSET)
+
+#define SAM_GPIO_PARAMETER(n)      (SAM_GPION_BASE(n)+SAM_GPIO_PARAMETER_OFFSET)
+#define SAM_GPIO_VERSION (n)       (SAM_GPION_BASE(n)+SAM_GPIO_VERSION_OFFSET)
+
+/* GPIO PORTA register adresses *********************************************************/
+
+#define SAM_GPIOA_GPER             (SAM_GPIOA_BASE+SAM_GPIO_GPER_OFFSET)
+#define SAM_GPIOA_GPERS            (SAM_GPIOA_BASE+SAM_GPIO_GPERS_OFFSET)
+#define SAM_GPIOA_GPERC            (SAM_GPIOA_BASE+SAM_GPIO_GPERC_OFFSET)
+#define SAM_GPIOA_GPERT            (SAM_GPIOA_BASE+SAM_GPIO_GPERT_OFFSET)
+
+#define SAM_GPIOA_PMR0             (SAM_GPIOA_BASE+SAM_GPIO_PMR0_OFFSET)
+#define SAM_GPIOA_PMR0S            (SAM_GPIOA_BASE+SAM_GPIO_PMR0S_OFFSET)
+#define SAM_GPIOA_PMR0C            (SAM_GPIOA_BASE+SAM_GPIO_PMR0C_OFFSET)
+#define SAM_GPIOA_PMR0T            (SAM_GPIOA_BASE+SAM_GPIO_PMR0T_OFFSET_
+
+#define SAM_GPIOA_PMR1             (SAM_GPIOA_BASE+SAM_GPIO_PMR1_OFFSET)
+#define SAM_GPIOA_PMR1S            (SAM_GPIOA_BASE+SAM_GPIO_PMR1S_OFFSET)
+#define SAM_GPIOA_PMR1C            (SAM_GPIOA_BASE+SAM_GPIO_PMR1C_OFFSET)
+#define SAM_GPIOA_PMR1T            (SAM_GPIOA_BASE+SAM_GPIO_PMR1T_OFFSET)
+
+#define SAM_GPIOA_PMR2             (SAM_GPIOA_BASE+SAM_GPIO_PMR2_OFFSET)
+#define SAM_GPIOA_PMR2S            (SAM_GPIOA_BASE+SAM_GPIO_PMR2S_OFFSET)
+#define SAM_GPIOA_PMR2C            (SAM_GPIOA_BASE+SAM_GPIO_PMR2C_OFFSET)
+#define SAM_GPIOA_PMR2T            (SAM_GPIOA_BASE+SAM_GPIO_PMR2T_OFFSET)
+
+#define SAM_GPIOA_ODER             (SAM_GPIOA_BASE+SAM_GPIO_ODER_OFFSET)
+#define SAM_GPIOA_ODERS            (SAM_GPIOA_BASE+SAM_GPIO_ODERS_OFFSET)
+#define SAM_GPIOA_ODERC            (SAM_GPIOA_BASE+SAM_GPIO_ODERC_OFFSET)
+#define SAM_GPIOA_ODERT            (SAM_GPIOA_BASE+SAM_GPIO_ODERT_OFFSET)
+
+#define SAM_GPIOA_OVR              (SAM_GPIOA_BASE+SAM_GPIO_OVR_OFFSET)
+#define SAM_GPIOA_OVRS             (SAM_GPIOA_BASE+SAM_GPIO_OVRS_OFFSET)
+#define SAM_GPIOA_OVRC             (SAM_GPIOA_BASE+SAM_GPIO_OVRC_OFFSET)
+#define SAM_GPIOA_OVRT             (SAM_GPIOA_BASE+SAM_GPIO_OVRT_OFFSET)
+
+#define SAM_GPIOA_PVR              (SAM_GPIOA_BASE+SAM_GPIO_PVR_OFFSET)
+
+#define SAM_GPIOA_PUER             (SAM_GPIOA_BASE+SAM_GPIO_PUER_OFFSET)
+#define SAM_GPIOA_PUERS            (SAM_GPIOA_BASE+SAM_GPIO_PUERS_OFFSET)
+#define SAM_GPIOA_PUERC            (SAM_GPIOA_BASE+SAM_GPIO_PUERC_OFFSET)
+#define SAM_GPIOA_PUERT            (SAM_GPIOA_BASE+SAM_GPIO_PUERT_OFFSET)
+
+#define SAM_GPIOA_PDER             (SAM_GPIOA_BASE+SAM_GPIO_PDER_OFFSET)
+#define SAM_GPIOA_PDERS            (SAM_GPIOA_BASE+SAM_GPIO_PDERS_OFFSET)
+#define SAM_GPIOA_PDERC            (SAM_GPIOA_BASE+SAM_GPIO_PDERC_OFFSET)
+#define SAM_GPIOA_PDERT            (SAM_GPIOA_BASE+SAM_GPIO_PDERT_OFFSET)
+
+#define SAM_GPIOA_IER              (SAM_GPIOA_BASE+SAM_GPIO_IER_OFFSET)
+#define SAM_GPIOA_IERS             (SAM_GPIOA_BASE+SAM_GPIO_IERS_OFFSET)
+#define SAM_GPIOA_IERC             (SAM_GPIOA_BASE+SAM_GPIO_IERC_OFFSET)
+#define SAM_GPIOA_IERT             (SAM_GPIOA_BASE+SAM_GPIO_IERT_OFFSET)
+
+#define SAM_GPIOA_IMR0             (SAM_GPIOA_BASE+SAM_GPIO_IMR0_OFFSET)
+#define SAM_GPIOA_IMR0S            (SAM_GPIOA_BASE+SAM_GPIO_IMR0S_OFFSET)
+#define SAM_GPIOA_IMR0C            (SAM_GPIOA_BASE+SAM_GPIO_IMR0C_OFFSET)
+#define SAM_GPIOA_IMR0T            (SAM_GPIOA_BASE+SAM_GPIO_IMR0T_OFFSET)
+
+#define SAM_GPIOA_IMR1             (SAM_GPIOA_BASE+SAM_GPIO_IMR1_OFFSET)
+#define SAM_GPIOA_IMR1S            (SAM_GPIOA_BASE+SAM_GPIO_IMR1S_OFFSET)
+#define SAM_GPIOA_IMR1C            (SAM_GPIOA_BASE+SAM_GPIO_IMR1C_OFFSET)
+#define SAM_GPIOA_IMR1T            (SAM_GPIOA_BASE+SAM_GPIO_IMR1T_OFFSET)
+
+#define SAM_GPIOA_GFER             (SAM_GPIOA_BASE+SAM_GPIO_GFER_OFFSET)
+#define SAM_GPIOA_GFERS            (SAM_GPIOA_BASE+SAM_GPIO_GFERS_OFFSET)
+#define SAM_GPIOA_GFERC            (SAM_GPIOA_BASE+SAM_GPIO_GFERC_OFFSET)
+#define SAM_GPIOA_GFERT            (SAM_GPIOA_BASE+SAM_GPIO_GFERT_OFFSET)
+
+#define SAM_GPIOA_IFR              (SAM_GPIOA_BASE+SAM_GPIO_IFR_OFFSET)
+#define SAM_GPIOA_IFRC             (SAM_GPIOA_BASE+SAM_GPIO_IFRC_OFFSET)
+
+#define SAM_GPIOA_ODCR0            (SAM_GPIOA_BASE+SAM_GPIO_ODCR0_OFFSET)
+#define SAM_GPIOA_ODCR0S           (SAM_GPIOA_BASE+SAM_GPIO_ODCR0S_OFFSET)
+#define SAM_GPIOA_ODCR0C           (SAM_GPIOA_BASE+SAM_GPIO_ODCR0C_OFFSET)
+#define SAM_GPIOA_ODCR0T           (SAM_GPIOA_BASE+SAM_GPIO_ODCR0T_OFFSET)
+
+#define SAM_GPIOA_ODCR1            (SAM_GPIOA_BASE+SAM_GPIO_ODCR1_OFFSET)
+#define SAM_GPIOA_ODCR1S           (SAM_GPIOA_BASE+SAM_GPIO_ODCR1S_OFFSET)
+#define SAM_GPIOA_ODCR1C           (SAM_GPIOA_BASE+SAM_GPIO_ODCR1C_OFFSET)
+#define SAM_GPIOA_ODCR1T           (SAM_GPIOA_BASE+SAM_GPIO_ODCR1T_OFFSET)
+
+#define SAM_GPIOA_OSRR0            (SAM_GPIOA_BASE+SAM_GPIO_OSRR0_OFFSET)
+#define SAM_GPIOA_OSRR0S           (SAM_GPIOA_BASE+SAM_GPIO_OSRR0S_OFFSET)
+#define SAM_GPIOA_OSRR0C           (SAM_GPIOA_BASE+SAM_GPIO_OSRR0C_OFFSET)
+#define SAM_GPIOA_OSRR0T           (SAM_GPIOA_BASE+SAM_GPIO_OSRR0T_OFFSET)
+
+#define SAM_GPIOA_STER             (SAM_GPIOA_BASE+SAM_GPIO_STER_OFFSET)
+#define SAM_GPIOA_STERS            (SAM_GPIOA_BASE+SAM_GPIO_STERS_OFFSET)
+#define SAM_GPIOA_STERC            (SAM_GPIOA_BASE+SAM_GPIO_STERC_OFFSET)
+#define SAM_GPIOA_STERT            (SAM_GPIOA_BASE+SAM_GPIO_STERT_OFFSET)
+
+#define SAM_GPIOA_EVER             (SAM_GPIOA_BASE+SAM_GPIO_EVER_OFFSET)
+#define SAM_GPIOA_EVERS            (SAM_GPIOA_BASE+SAM_GPIO_EVERS_OFFSET)
+#define SAM_GPIOA_EVERC            (SAM_GPIOA_BASE+SAM_GPIO_EVERC_OFFSET)
+#define SAM_GPIOA_EVERT            (SAM_GPIOA_BASE+SAM_GPIO_EVERT_OFFSET)
+
+#define SAM_GPIOA_PARAMETER        (SAM_GPIOA_BASE+SAM_GPIO_PARAMETER_OFFSET)
+#define SAM_GPIOA_VERSION          (SAM_GPIOA_BASE+SAM_GPIO_VERSION_OFFSET)
+
+/* GPIO PORTB register adresses *********************************************************/
+
+#define SAM_GPIOB_GPER             (SAM_GPIOB_BASE+SAM_GPIO_GPER_OFFSET)
+#define SAM_GPIOB_GPERS            (SAM_GPIOB_BASE+SAM_GPIO_GPERS_OFFSET)
+#define SAM_GPIOB_GPERC            (SAM_GPIOB_BASE+SAM_GPIO_GPERC_OFFSET)
+#define SAM_GPIOB_GPERT            (SAM_GPIOB_BASE+SAM_GPIO_GPERT_OFFSET)
+
+#define SAM_GPIOB_PMR0             (SAM_GPIOB_BASE+SAM_GPIO_PMR0_OFFSET)
+#define SAM_GPIOB_PMR0S            (SAM_GPIOB_BASE+SAM_GPIO_PMR0S_OFFSET)
+#define SAM_GPIOB_PMR0C            (SAM_GPIOB_BASE+SAM_GPIO_PMR0C_OFFSET)
+#define SAM_GPIOB_PMR0T            (SAM_GPIOB_BASE+SAM_GPIO_PMR0T_OFFSET_
+
+#define SAM_GPIOB_PMR1             (SAM_GPIOB_BASE+SAM_GPIO_PMR1_OFFSET)
+#define SAM_GPIOB_PMR1S            (SAM_GPIOB_BASE+SAM_GPIO_PMR1S_OFFSET)
+#define SAM_GPIOB_PMR1C            (SAM_GPIOB_BASE+SAM_GPIO_PMR1C_OFFSET)
+#define SAM_GPIOB_PMR1T            (SAM_GPIOB_BASE+SAM_GPIO_PMR1T_OFFSET)
+
+#define SAM_GPIOB_PMR2             (SAM_GPIOB_BASE+SAM_GPIO_PMR2_OFFSET)
+#define SAM_GPIOB_PMR2S            (SAM_GPIOB_BASE+SAM_GPIO_PMR2S_OFFSET)
+#define SAM_GPIOB_PMR2C            (SAM_GPIOB_BASE+SAM_GPIO_PMR2C_OFFSET)
+#define SAM_GPIOB_PMR2T            (SAM_GPIOB_BASE+SAM_GPIO_PMR2T_OFFSET)
+
+#define SAM_GPIOB_ODER             (SAM_GPIOB_BASE+SAM_GPIO_ODER_OFFSET)
+#define SAM_GPIOB_ODERS            (SAM_GPIOB_BASE+SAM_GPIO_ODERS_OFFSET)
+#define SAM_GPIOB_ODERC            (SAM_GPIOB_BASE+SAM_GPIO_ODERC_OFFSET)
+#define SAM_GPIOB_ODERT            (SAM_GPIOB_BASE+SAM_GPIO_ODERT_OFFSET)
+
+#define SAM_GPIOB_OVR              (SAM_GPIOB_BASE+SAM_GPIO_OVR_OFFSET)
+#define SAM_GPIOB_OVRS             (SAM_GPIOB_BASE+SAM_GPIO_OVRS_OFFSET)
+#define SAM_GPIOB_OVRC             (SAM_GPIOB_BASE+SAM_GPIO_OVRC_OFFSET)
+#define SAM_GPIOB_OVRT             (SAM_GPIOB_BASE+SAM_GPIO_OVRT_OFFSET)
+
+#define SAM_GPIOB_PVR              (SAM_GPIOB_BASE+SAM_GPIO_PVR_OFFSET)
+
+#define SAM_GPIOB_PUER             (SAM_GPIOB_BASE+SAM_GPIO_PUER_OFFSET)
+#define SAM_GPIOB_PUERS            (SAM_GPIOB_BASE+SAM_GPIO_PUERS_OFFSET)
+#define SAM_GPIOB_PUERC            (SAM_GPIOB_BASE+SAM_GPIO_PUERC_OFFSET)
+#define SAM_GPIOB_PUERT            (SAM_GPIOB_BASE+SAM_GPIO_PUERT_OFFSET)
+
+#define SAM_GPIOB_PDER             (SAM_GPIOB_BASE+SAM_GPIO_PDER_OFFSET)
+#define SAM_GPIOB_PDERS            (SAM_GPIOB_BASE+SAM_GPIO_PDERS_OFFSET)
+#define SAM_GPIOB_PDERC            (SAM_GPIOB_BASE+SAM_GPIO_PDERC_OFFSET)
+#define SAM_GPIOB_PDERT            (SAM_GPIOB_BASE+SAM_GPIO_PDERT_OFFSET)
+
+#define SAM_GPIOB_IER              (SAM_GPIOB_BASE+SAM_GPIO_IER_OFFSET)
+#define SAM_GPIOB_IERS             (SAM_GPIOB_BASE+SAM_GPIO_IERS_OFFSET)
+#define SAM_GPIOB_IERC             (SAM_GPIOB_BASE+SAM_GPIO_IERC_OFFSET)
+#define SAM_GPIOB_IERT             (SAM_GPIOB_BASE+SAM_GPIO_IERT_OFFSET)
+
+#define SAM_GPIOB_IMR0             (SAM_GPIOB_BASE+SAM_GPIO_IMR0_OFFSET)
+#define SAM_GPIOB_IMR0S            (SAM_GPIOB_BASE+SAM_GPIO_IMR0S_OFFSET)
+#define SAM_GPIOB_IMR0C            (SAM_GPIOB_BASE+SAM_GPIO_IMR0C_OFFSET)
+#define SAM_GPIOB_IMR0T            (SAM_GPIOB_BASE+SAM_GPIO_IMR0T_OFFSET)
+
+#define SAM_GPIOB_IMR1             (SAM_GPIOB_BASE+SAM_GPIO_IMR1_OFFSET)
+#define SAM_GPIOB_IMR1S            (SAM_GPIOB_BASE+SAM_GPIO_IMR1S_OFFSET)
+#define SAM_GPIOB_IMR1C            (SAM_GPIOB_BASE+SAM_GPIO_IMR1C_OFFSET)
+#define SAM_GPIOB_IMR1T            (SAM_GPIOB_BASE+SAM_GPIO_IMR1T_OFFSET)
+
+#define SAM_GPIOB_GFER             (SAM_GPIOB_BASE+SAM_GPIO_GFER_OFFSET)
+#define SAM_GPIOB_GFERS            (SAM_GPIOB_BASE+SAM_GPIO_GFERS_OFFSET)
+#define SAM_GPIOB_GFERC            (SAM_GPIOB_BASE+SAM_GPIO_GFERC_OFFSET)
+#define SAM_GPIOB_GFERT            (SAM_GPIOB_BASE+SAM_GPIO_GFERT_OFFSET)
+
+#define SAM_GPIOB_IFR              (SAM_GPIOB_BASE+SAM_GPIO_IFR_OFFSET)
+#define SAM_GPIOB_IFRC             (SAM_GPIOB_BASE+SAM_GPIO_IFRC_OFFSET)
+
+#define SAM_GPIOB_ODCR0            (SAM_GPIOB_BASE+SAM_GPIO_ODCR0_OFFSET)
+#define SAM_GPIOB_ODCR0S           (SAM_GPIOB_BASE+SAM_GPIO_ODCR0S_OFFSET)
+#define SAM_GPIOB_ODCR0C           (SAM_GPIOB_BASE+SAM_GPIO_ODCR0C_OFFSET)
+#define SAM_GPIOB_ODCR0T           (SAM_GPIOB_BASE+SAM_GPIO_ODCR0T_OFFSET)
+
+#define SAM_GPIOB_ODCR1            (SAM_GPIOB_BASE+SAM_GPIO_ODCR1_OFFSET)
+#define SAM_GPIOB_ODCR1S           (SAM_GPIOB_BASE+SAM_GPIO_ODCR1S_OFFSET)
+#define SAM_GPIOB_ODCR1C           (SAM_GPIOB_BASE+SAM_GPIO_ODCR1C_OFFSET)
+#define SAM_GPIOB_ODCR1T           (SAM_GPIOB_BASE+SAM_GPIO_ODCR1T_OFFSET)
+
+#define SAM_GPIOB_OSRR0            (SAM_GPIOB_BASE+SAM_GPIO_OSRR0_OFFSET)
+#define SAM_GPIOB_OSRR0S           (SAM_GPIOB_BASE+SAM_GPIO_OSRR0S_OFFSET)
+#define SAM_GPIOB_OSRR0C           (SAM_GPIOB_BASE+SAM_GPIO_OSRR0C_OFFSET)
+#define SAM_GPIOB_OSRR0T           (SAM_GPIOB_BASE+SAM_GPIO_OSRR0T_OFFSET)
+
+#define SAM_GPIOB_STER             (SAM_GPIOB_BASE+SAM_GPIO_STER_OFFSET)
+#define SAM_GPIOB_STERS            (SAM_GPIOB_BASE+SAM_GPIO_STERS_OFFSET)
+#define SAM_GPIOB_STERC            (SAM_GPIOB_BASE+SAM_GPIO_STERC_OFFSET)
+#define SAM_GPIOB_STERT            (SAM_GPIOB_BASE+SAM_GPIO_STERT_OFFSET)
+
+#define SAM_GPIOB_EVER             (SAM_GPIOB_BASE+SAM_GPIO_EVER_OFFSET)
+#define SAM_GPIOB_EVERS            (SAM_GPIOB_BASE+SAM_GPIO_EVERS_OFFSET)
+#define SAM_GPIOB_EVERC            (SAM_GPIOB_BASE+SAM_GPIO_EVERC_OFFSET)
+#define SAM_GPIOB_EVERT            (SAM_GPIOB_BASE+SAM_GPIO_EVERT_OFFSET)
+
+#define SAM_GPIOB_PARAMETER        (SAM_GPIOB_BASE+SAM_GPIO_PARAMETER_OFFSET)
+#define SAM_GPIOB_VERSION          (SAM_GPIOB_BASE+SAM_GPIO_VERSION_OFFSET)
+
+/* GPIO PORTC register adresses *********************************************************/
+
+#define SAM_GPIOC_GPER             (SAM_GPIOC_BASE+SAM_GPIO_GPER_OFFSET)
+#define SAM_GPIOC_GPERS            (SAM_GPIOC_BASE+SAM_GPIO_GPERS_OFFSET)
+#define SAM_GPIOC_GPERC            (SAM_GPIOC_BASE+SAM_GPIO_GPERC_OFFSET)
+#define SAM_GPIOC_GPERT            (SAM_GPIOC_BASE+SAM_GPIO_GPERT_OFFSET)
+
+#define SAM_GPIOC_PMR0             (SAM_GPIOC_BASE+SAM_GPIO_PMR0_OFFSET)
+#define SAM_GPIOC_PMR0S            (SAM_GPIOC_BASE+SAM_GPIO_PMR0S_OFFSET)
+#define SAM_GPIOC_PMR0C            (SAM_GPIOC_BASE+SAM_GPIO_PMR0C_OFFSET)
+#define SAM_GPIOC_PMR0T            (SAM_GPIOC_BASE+SAM_GPIO_PMR0T_OFFSET_
+
+#define SAM_GPIOC_PMR1             (SAM_GPIOC_BASE+SAM_GPIO_PMR1_OFFSET)
+#define SAM_GPIOC_PMR1S            (SAM_GPIOC_BASE+SAM_GPIO_PMR1S_OFFSET)
+#define SAM_GPIOC_PMR1C            (SAM_GPIOC_BASE+SAM_GPIO_PMR1C_OFFSET)
+#define SAM_GPIOC_PMR1T            (SAM_GPIOC_BASE+SAM_GPIO_PMR1T_OFFSET)
+
+#define SAM_GPIOC_PMR2             (SAM_GPIOC_BASE+SAM_GPIO_PMR2_OFFSET)
+#define SAM_GPIOC_PMR2S            (SAM_GPIOC_BASE+SAM_GPIO_PMR2S_OFFSET)
+#define SAM_GPIOC_PMR2C            (SAM_GPIOC_BASE+SAM_GPIO_PMR2C_OFFSET)
+#define SAM_GPIOC_PMR2T            (SAM_GPIOC_BASE+SAM_GPIO_PMR2T_OFFSET)
+
+#define SAM_GPIOC_ODER             (SAM_GPIOC_BASE+SAM_GPIO_ODER_OFFSET)
+#define SAM_GPIOC_ODERS            (SAM_GPIOC_BASE+SAM_GPIO_ODERS_OFFSET)
+#define SAM_GPIOC_ODERC            (SAM_GPIOC_BASE+SAM_GPIO_ODERC_OFFSET)
+#define SAM_GPIOC_ODERT            (SAM_GPIOC_BASE+SAM_GPIO_ODERT_OFFSET)
+
+#define SAM_GPIOC_OVR              (SAM_GPIOC_BASE+SAM_GPIO_OVR_OFFSET)
+#define SAM_GPIOC_OVRS             (SAM_GPIOC_BASE+SAM_GPIO_OVRS_OFFSET)
+#define SAM_GPIOC_OVRC             (SAM_GPIOC_BASE+SAM_GPIO_OVRC_OFFSET)
+#define SAM_GPIOC_OVRT             (SAM_GPIOC_BASE+SAM_GPIO_OVRT_OFFSET)
+
+#define SAM_GPIOC_PVR              (SAM_GPIOC_BASE+SAM_GPIO_PVR_OFFSET)
+
+#define SAM_GPIOC_PUER             (SAM_GPIOC_BASE+SAM_GPIO_PUER_OFFSET)
+#define SAM_GPIOC_PUERS            (SAM_GPIOC_BASE+SAM_GPIO_PUERS_OFFSET)
+#define SAM_GPIOC_PUERC            (SAM_GPIOC_BASE+SAM_GPIO_PUERC_OFFSET)
+#define SAM_GPIOC_PUERT            (SAM_GPIOC_BASE+SAM_GPIO_PUERT_OFFSET)
+
+#define SAM_GPIOC_PDER             (SAM_GPIOC_BASE+SAM_GPIO_PDER_OFFSET)
+#define SAM_GPIOC_PDERS            (SAM_GPIOC_BASE+SAM_GPIO_PDERS_OFFSET)
+#define SAM_GPIOC_PDERC            (SAM_GPIOC_BASE+SAM_GPIO_PDERC_OFFSET)
+#define SAM_GPIOC_PDERT            (SAM_GPIOC_BASE+SAM_GPIO_PDERT_OFFSET)
+
+#define SAM_GPIOC_IER              (SAM_GPIOC_BASE+SAM_GPIO_IER_OFFSET)
+#define SAM_GPIOC_IERS             (SAM_GPIOC_BASE+SAM_GPIO_IERS_OFFSET)
+#define SAM_GPIOC_IERC             (SAM_GPIOC_BASE+SAM_GPIO_IERC_OFFSET)
+#define SAM_GPIOC_IERT             (SAM_GPIOC_BASE+SAM_GPIO_IERT_OFFSET)
+
+#define SAM_GPIOC_IMR0             (SAM_GPIOC_BASE+SAM_GPIO_IMR0_OFFSET)
+#define SAM_GPIOC_IMR0S            (SAM_GPIOC_BASE+SAM_GPIO_IMR0S_OFFSET)
+#define SAM_GPIOC_IMR0C            (SAM_GPIOC_BASE+SAM_GPIO_IMR0C_OFFSET)
+#define SAM_GPIOC_IMR0T            (SAM_GPIOC_BASE+SAM_GPIO_IMR0T_OFFSET)
+
+#define SAM_GPIOC_IMR1             (SAM_GPIOC_BASE+SAM_GPIO_IMR1_OFFSET)
+#define SAM_GPIOC_IMR1S            (SAM_GPIOC_BASE+SAM_GPIO_IMR1S_OFFSET)
+#define SAM_GPIOC_IMR1C            (SAM_GPIOC_BASE+SAM_GPIO_IMR1C_OFFSET)
+#define SAM_GPIOC_IMR1T            (SAM_GPIOC_BASE+SAM_GPIO_IMR1T_OFFSET)
+
+#define SAM_GPIOC_GFER             (SAM_GPIOC_BASE+SAM_GPIO_GFER_OFFSET)
+#define SAM_GPIOC_GFERS            (SAM_GPIOC_BASE+SAM_GPIO_GFERS_OFFSET)
+#define SAM_GPIOC_GFERC            (SAM_GPIOC_BASE+SAM_GPIO_GFERC_OFFSET)
+#define SAM_GPIOC_GFERT            (SAM_GPIOC_BASE+SAM_GPIO_GFERT_OFFSET)
+
+#define SAM_GPIOC_IFR              (SAM_GPIOC_BASE+SAM_GPIO_IFR_OFFSET)
+#define SAM_GPIOC_IFRC             (SAM_GPIOC_BASE+SAM_GPIO_IFRC_OFFSET)
+
+#define SAM_GPIOC_ODCR0            (SAM_GPIOC_BASE+SAM_GPIO_ODCR0_OFFSET)
+#define SAM_GPIOC_ODCR0S           (SAM_GPIOC_BASE+SAM_GPIO_ODCR0S_OFFSET)
+#define SAM_GPIOC_ODCR0C           (SAM_GPIOC_BASE+SAM_GPIO_ODCR0C_OFFSET)
+#define SAM_GPIOC_ODCR0T           (SAM_GPIOC_BASE+SAM_GPIO_ODCR0T_OFFSET)
+
+#define SAM_GPIOC_ODCR1            (SAM_GPIOC_BASE+SAM_GPIO_ODCR1_OFFSET)
+#define SAM_GPIOC_ODCR1S           (SAM_GPIOC_BASE+SAM_GPIO_ODCR1S_OFFSET)
+#define SAM_GPIOC_ODCR1C           (SAM_GPIOC_BASE+SAM_GPIO_ODCR1C_OFFSET)
+#define SAM_GPIOC_ODCR1T           (SAM_GPIOC_BASE+SAM_GPIO_ODCR1T_OFFSET)
+
+#define SAM_GPIOC_OSRR0            (SAM_GPIOC_BASE+SAM_GPIO_OSRR0_OFFSET)
+#define SAM_GPIOC_OSRR0S           (SAM_GPIOC_BASE+SAM_GPIO_OSRR0S_OFFSET)
+#define SAM_GPIOC_OSRR0C           (SAM_GPIOC_BASE+SAM_GPIO_OSRR0C_OFFSET)
+#define SAM_GPIOC_OSRR0T           (SAM_GPIOC_BASE+SAM_GPIO_OSRR0T_OFFSET)
+
+#define SAM_GPIOC_STER             (SAM_GPIOC_BASE+SAM_GPIO_STER_OFFSET)
+#define SAM_GPIOC_STERS            (SAM_GPIOC_BASE+SAM_GPIO_STERS_OFFSET)
+#define SAM_GPIOC_STERC            (SAM_GPIOC_BASE+SAM_GPIO_STERC_OFFSET)
+#define SAM_GPIOC_STERT            (SAM_GPIOC_BASE+SAM_GPIO_STERT_OFFSET)
+
+#define SAM_GPIOC_EVER             (SAM_GPIOC_BASE+SAM_GPIO_EVER_OFFSET)
+#define SAM_GPIOC_EVERS            (SAM_GPIOC_BASE+SAM_GPIO_EVERS_OFFSET)
+#define SAM_GPIOC_EVERC            (SAM_GPIOC_BASE+SAM_GPIO_EVERC_OFFSET)
+#define SAM_GPIOC_EVERT            (SAM_GPIOC_BASE+SAM_GPIO_EVERT_OFFSET)
+
+#define SAM_GPIOC_PARAMETER        (SAM_GPIOC_BASE+SAM_GPIO_PARAMETER_OFFSET)
+#define SAM_GPIOC_VERSION          (SAM_GPIOC_BASE+SAM_GPIO_VERSION_OFFSET)
 
 /* GPIO register bit definitions ********************************************************/
 
diff --git a/nuttx/arch/arm/src/sam34/sam4l_gpio.c b/nuttx/arch/arm/src/sam34/sam4l_gpio.c
index 88f3d02cb3..977e91e608 100644
--- a/nuttx/arch/arm/src/sam34/sam4l_gpio.c
+++ b/nuttx/arch/arm/src/sam34/sam4l_gpio.c
@@ -105,6 +105,8 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset)
  *
  * Description:
  *   Configure a GPIO input pin based on bit-encoded description of the pin.
+ *   This function serves the dual role of putting all pins into a known,
+ *   initial state.  Hence, it is overkill for what really needs to be done.
  *
  ****************************************************************************/
 
@@ -200,10 +202,10 @@ static inline int sam_configinterrupt(uintptr_t base, uint32_t pin,
    * falling edges.
    */
 
-  ret = sam_configinput(base, pin, cfgset)
-  if (ret = OK)
+  ret = sam_configinput(base, pin, cfgset);
+  if (ret == OK)
     {
-      /* Disable rising and falling edge interrupts as requested 
+      /* Disable rising and falling edge interrupts as requested
        * {IMR1, IMR0} Interrupt Mode
        *
        *   00 Pin Change   <-- We already have this
@@ -214,13 +216,13 @@ static inline int sam_configinterrupt(uintptr_t base, uint32_t pin,
 
       gpio_pinset_t edges = cfgset & GPIO_INT_MASK;
 
-      if (eges = GPIO_INT_RISING)
+      if (edges == GPIO_INT_RISING)
         {
           /* Rising only.. disable interrrupts on the falling edge */
 
           putreg32(pin, base + SAM_GPIO_IMR0S_OFFSET);
         }
-      else if (edges = GPIO_INT_FALLING)
+      else if (edges == GPIO_INT_FALLING)
         {
           /* Falling only.. disable interrrupts on the rising edge */
 
@@ -363,7 +365,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
       case _GPIO_FUNCC: /* Function C 010 */
         putreg32(pin, base + SAM_GPIO_PMR1S_OFFSET);
         break;
- 
+
       case _GPIO_FUNCE: /* Function E 100 */
         putreg32(pin, base + SAM_GPIO_PMR2S_OFFSET);
         break;
@@ -397,13 +399,13 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
    */
 
   edges = cfgset & GPIO_INT_MASK;
-  if (eges = GPIO_INT_RISING)
+  if (edges == GPIO_INT_RISING)
     {
       /* Rising only.. disable interrrupts on the falling edge */
 
       putreg32(pin, base + SAM_GPIO_IMR0S_OFFSET);
     }
-  else if (edges = GPIO_INT_FALLING)
+  else if (edges == GPIO_INT_FALLING)
     {
       /* Falling only.. disable interrrupts on the rising edge */
 
diff --git a/nuttx/configs/sam4l-xplained/src/sam_userleds.c b/nuttx/configs/sam4l-xplained/src/sam_userleds.c
index bf77e2c7f7..7a2c45efc0 100644
--- a/nuttx/configs/sam4l-xplained/src/sam_userleds.c
+++ b/nuttx/configs/sam4l-xplained/src/sam_userleds.c
@@ -41,7 +41,8 @@
  * PC07 to GND.
  *
  * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will
- * control LED0.  Otherwise, LED0 can be controlled from logic in this file.
+ * control LED0.  Otherwise, LED0 can be controlled from user applications
+ * using the logic in this file.
  */
 
 /****************************************************************************

From 39fab7664fe6bbbff78d01f291b05957666f3ffc Mon Sep 17 00:00:00 2001
From: Lorenz Meier 
Date: Wed, 5 Jun 2013 18:01:07 +0200
Subject: [PATCH 32/41] Cleanup on stack check

---
 nuttx/arch/arm/src/stm32/Make.defs      |  2 +-
 nuttx/configs/px4fmu-v1/include/board.h | 15 +++++++++------
 nuttx/configs/px4io-v1/nsh/defconfig    |  1 +
 3 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs
index 3b210a8333..3b64958579 100644
--- a/nuttx/arch/arm/src/stm32/Make.defs
+++ b/nuttx/arch/arm/src/stm32/Make.defs
@@ -52,7 +52,7 @@ CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
 CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
 CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_systemreset.c
 CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c
-CMN_CSRCS += up_svcall.c up_stackcheck.c up_vfork.c
+CMN_CSRCS += up_svcall.c up_vfork.c
 
 ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
 CMN_CSRCS += up_stackcheck.c
diff --git a/nuttx/configs/px4fmu-v1/include/board.h b/nuttx/configs/px4fmu-v1/include/board.h
index a0488917ca..0fa93a1965 100644
--- a/nuttx/configs/px4fmu-v1/include/board.h
+++ b/nuttx/configs/px4fmu-v1/include/board.h
@@ -310,12 +310,15 @@
 #define GPIO_SPI3_SCK	GPIO_SPI3_SCK_2
 #define GPIO_SPI3_NSS	GPIO_SPI3_NSS_2
 
-/* XXX DMA setup not validated yet */
-//#define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1
-//#define DMAMAP_SPI3_RX DMAMAP_SPI3_TX_1
-
-//#define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_1
-//#define DMAMAP_SPI1_RX DMAMAP_SPI1_TX_1
+/* SPI DMA configuration for SPI3 (microSD) */
+#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_1
+#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_2
+/* XXX since we allocate the HP work stack from CCM RAM on normal system startup,
+   SPI1 will never run in DMA mode - so we can just give it a random config here.
+   What we really need to do is to make DMA configurable per channel, and always
+   disable it for SPI1. */
+#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1
+#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_2
 
 /*
  * Use these in place of the spi_dev_e enumeration to
diff --git a/nuttx/configs/px4io-v1/nsh/defconfig b/nuttx/configs/px4io-v1/nsh/defconfig
index 3c06a27347..2168c79b24 100755
--- a/nuttx/configs/px4io-v1/nsh/defconfig
+++ b/nuttx/configs/px4io-v1/nsh/defconfig
@@ -94,6 +94,7 @@ CONFIG_ARCH_DMA=y
 CONFIG_ARCH_MATH_H=y
 
 CONFIG_ARMV7M_CMNVECTOR=y
+CONFIG_ARMV7M_STACKCHECK=y
 
 #
 # JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):

From c0ae88bc60f65d95baf4411a61598f941a702aeb Mon Sep 17 00:00:00 2001
From: Gregory Nutt 
Date: Wed, 5 Jun 2013 10:43:33 -0600
Subject: [PATCH 33/41] Add SAM4L FLASHCALW header file

---
 nuttx/arch/arm/src/sam34/Make.defs            |   9 +-
 .../sam34/chip/{sam_eefc.h => sam3u_eefc.h}   |   8 +-
 .../sam34/chip/{sam_supc.h => sam3u_supc.h}   |   8 +-
 .../arch/arm/src/sam34/chip/sam4l_flashcalw.h | 347 ++++++++++++++++++
 .../arch/arm/src/sam34/chip/sam4l_memorymap.h |   2 +-
 ...{sam_clockconfig.c => sam3u_clockconfig.c} |   6 +-
 nuttx/arch/avr/src/at32uc3/at32uc3_flashc.h   |   4 +-
 nuttx/configs/sam4l-xplained/include/board.h  |   8 +
 8 files changed, 373 insertions(+), 19 deletions(-)
 rename nuttx/arch/arm/src/sam34/chip/{sam_eefc.h => sam3u_eefc.h} (97%)
 rename nuttx/arch/arm/src/sam34/chip/{sam_supc.h => sam3u_supc.h} (98%)
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h
 rename nuttx/arch/arm/src/sam34/{sam_clockconfig.c => sam3u_clockconfig.c} (99%)

diff --git a/nuttx/arch/arm/src/sam34/Make.defs b/nuttx/arch/arm/src/sam34/Make.defs
index 683751bb5d..182d4e5bfd 100644
--- a/nuttx/arch/arm/src/sam34/Make.defs
+++ b/nuttx/arch/arm/src/sam34/Make.defs
@@ -77,16 +77,15 @@ endif
 # Required SAM3/4 files
 
 CHIP_ASRCS  =
-CHIP_CSRCS  = sam_allocateheap.c sam_clockconfig.c sam_gpioirq.c
-CHIP_CSRCS += sam_irq.c sam_lowputc.c sam_serial.c sam_start.c
-CHIP_CSRCS += sam_timerisr.c
+CHIP_CSRCS  = sam_allocateheap.c sam_gpioirq.c sam_irq.c sam_lowputc.c
+CHIP_CSRCS += sam_serial.c sam_start.c sam_timerisr.c
 
 # Configuration-dependent SAM3/4 files
 
 ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y)
-CHIP_CSRCS += sam4l_gpio.c
+CHIP_CSRCS += sam4l_clockconfig.c sam4l_gpio.c
 else
-CHIP_CSRCS += sam3u_gpio.c
+CHIP_CSRCS += sam3u_clockconfig.c sam3u_gpio.c
 endif
 
 ifeq ($(CONFIG_NUTTX_KERNEL),y)
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_eefc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h
similarity index 97%
rename from nuttx/arch/arm/src/sam34/chip/sam_eefc.h
rename to nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h
index 546b6334ca..05ffad19be 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_eefc.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_eefc.h
+ * arch/arm/src/sam34/chip/sam3u_eefc.h
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_EEFC_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_EEFC_H
 
 /****************************************************************************************
  * Included Files
@@ -117,4 +117,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_EEFC_H */
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_supc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h
similarity index 98%
rename from nuttx/arch/arm/src/sam34/chip/sam_supc.h
rename to nuttx/arch/arm/src/sam34/chip/sam3u_supc.h
index 1be920d0d9..88f9452d8b 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_supc.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_supc.h
+ * arch/arm/src/sam34/chip/sam3u_supc.h
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SUPC_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SUPC_H
 
 /****************************************************************************************
  * Included Files
@@ -161,4 +161,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SUPC_H */
diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h b/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h
new file mode 100644
index 0000000000..1ae40fbf72
--- /dev/null
+++ b/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h
@@ -0,0 +1,347 @@
+/************************************************************************************
+ * arch/avr/src/sam34/sam4l_flashcalw.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4LFLASHCALW_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4LFLASHCALW_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include "chip.h"
+#include "chip/sam_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+/* Relative to SAM_FLASHCALW_BASE */
+
+#define SAM_FLASHCALW_FCR_OFFSET     0x0000 /* Flash Control Register */
+#define SAM_FLASHCALW_FCMD_OFFSET    0x0004 /* Flash Command Register */
+#define SAM_FLASHCALW_FSR_OFFSET     0x0008 /* Flash Status Register */
+#define SAM_FLASHCALW_FPR_OFFSET     0x000c /* Flash Parameter Register */
+#define SAM_FLASHCALW_FVR_OFFSET     0x0010 /* Flash Version Register */
+#define SAM_FLASHCALW_FGPFRHI_OFFSET 0x0014 /* Flash General Purpose Fuse Register Hi */
+#define SAM_FLASHCALW_FGPFRLO_OFFSET 0x0018 /* Flash General Purpose Fuse Register Lo */
+
+/* Relative to SAM_PICOCACHE_BASE */
+
+#define SAM_PICOCACHE_CTRL_OFFSET   0x0008 /* PicoCache Control Register */
+#define SAM_PICOCACHE_SR_OFFSET     0x000c /* PicoCache Status Register */
+#define SAM_PICOCACHE_MAINT0_OFFSET 0x0020 /* PicoCache Maintenance Register 0 */
+#define SAM_PICOCACHE_MAINT1_OFFSET 0x0024 /* PicoCache Maintenance Register 1 */
+#define SAM_PICOCACHE_MCFG_OFFSET   0x0028 /* PicoCache Monitor Configuration Register */
+#define SAM_PICOCACHE_MEN_OFFSET    0x002c /* PicoCache Monitor Enable Register */
+#define SAM_PICOCACHE_MCTRL_OFFSET  0x0030 /* PicoCache Monitor Control Register */
+#define SAM_PICOCACHE_MSR_OFFSET    0x0034 /* PicoCache Monitor Status Register */
+#define SAM_PICOCACHE_PVR_OFFSET    0x00fc /* Version Register */
+
+/* Register Addresses ***************************************************************/
+
+#define SAM_FLASHCALW_FCR           (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FCR_OFFSET)
+#define SAM_FLASHCALW_FCMD          (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FCMD_OFFSET)
+#define SAM_FLASHCALW_FSR           (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FSR_OFFSET)
+#define SAM_FLASHCALW_FPR           (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FPR_OFFSET)
+#define SAM_FLASHCALW_FSR           (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FSR_OFFSET)
+#define SAM_FLASHCALW_FGPFRHI       (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FGPFRHI_OFFSET)
+#define SAM_FLASHCALW_FGPFRLO       (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FGPFRLO_OFFSET)
+
+#define SAM_PICOCACHE_CTRL          (SAM_PICOCACHE_BASE+SAM_PICOCACHE_CTRL_OFFSET)
+#define SAM_PICOCACHE_SR            (SAM_PICOCACHE_BASE+SAM_PICOCACHE_SR_OFFSET)
+#define SAM_PICOCACHE_MAINT0        (SAM_PICOCACHE_BASE+SAM_PICOCACHE_MAINT0_OFFSET)
+#define SAM_PICOCACHE_MAINT1        (SAM_PICOCACHE_BASE+SAM_PICOCACHE_MAINT1_OFFSET)
+#define SAM_PICOCACHE_MCFG          (SAM_PICOCACHE_BASE+SAM_PICOCACHE_MCFG_OFFSET)
+#define SAM_PICOCACHE_MEN           (SAM_PICOCACHE_BASE+SAM_PICOCACHE_MEN_OFFSET)
+#define SAM_PICOCACHE_MCTRL         (SAM_PICOCACHE_BASE+SAM_PICOCACHE_MCTRL_OFFSET)
+#define SAM_PICOCACHE_MSR           (SAM_PICOCACHE_BASE+SAM_PICOCACHE_MSR_OFFSET)
+#define SAM_PICOCACHE_PVR           (SAM_PICOCACHE_BASE+SAM_PICOCACHE_PVR_OFFSET)
+
+/* Register Bit-field Definitions ***************************************************/
+
+/* Flash Control Register */
+
+#define FLASHCALW_FCR_FRDY             (1 << 0)  /* Bit 0:  Flash Ready Interrupt Enable */
+#define FLASHCALW_FCR_LOCKE            (1 << 2)  /* Bit 2:  Lock Error Interrupt Enable */
+#define FLASHCALW_FCR_PROGE            (1 << 3)  /* Bit 3:  Programming Error Interrupt Enable */
+#define FLASHCALW_FCR_ECCE             (1 << 4)  /* Bit 4:  ECC Error Interrupt Enable */
+#define FLASHCALW_FCR_FWS              (1 << 6)  /* Bit 6:  Flash Wait State */
+#define FLASHCALW_FCR_WS1OPT           (1 << 7)  /* Bit 7:  Wait State 1 Optimization */
+
+/* Flash Command Register */
+
+#define FLASHCALW_FCMD_CMD_SHIFT       (0)       /* Bits 0-5: Command */
+#define FLASHCALW_FCMD_CMD_MASK        (0x3f << FLASHCALW_FCMD_CMD_SHIFT)
+#  define FLASHCALW_FCMD_CMD_NOP       (0 << FLASHCALW_FCMD_CMD_SHIFT)  /* No operation */
+#  define FLASHCALW_FCMD_CMD_WP        (1 << FLASHCALW_FCMD_CMD_SHIFT)  /* Write Page */
+#  define FLASHCALW_FCMD_CMD_EP        (2 << FLASHCALW_FCMD_CMD_SHIFT)  /* Erase Page */
+#  define FLASHCALW_FCMD_CMD_CPB       (3 << FLASHCALW_FCMD_CMD_SHIFT)  /* Clear Page Buffer */
+#  define FLASHCALW_FCMD_CMD_LP        (4 << FLASHCALW_FCMD_CMD_SHIFT)  /* Lock region containing given Page */
+#  define FLASHCALW_FCMD_CMD_UP        (5 << FLASHCALW_FCMD_CMD_SHIFT)  /* Unlock region containing given Page */
+#  define FLASHCALW_FCMD_CMD_EA        (6 << FLASHCALW_FCMD_CMD_SHIFT)  /* Erase All */
+#  define FLASHCALW_FCMD_CMD_WGPB      (7 << FLASHCALW_FCMD_CMD_SHIFT)  /* Write General-Purpose Fuse Bit */
+#  define FLASHCALW_FCMD_CMD_EGPB      (8 << FLASHCALW_FCMD_CMD_SHIFT)  /* Erase General-Purpose Fuse Bit */
+#  define FLASHCALW_FCMD_CMD_SSB       (9 << FLASHCALW_FCMD_CMD_SHIFT)  /* Set Security Fuses */
+#  define FLASHCALW_FCMD_CMD_PGPFB     (10 << FLASHCALW_FCMD_CMD_SHIFT) /* Program GP Fuse Byte */
+#  define FLASHCALW_FCMD_CMD_EAGPF     (11 << FLASHCALW_FCMD_CMD_SHIFT) /* Erase All GPFuses */
+#  define FLASHCALW_FCMD_CMD_QPR       (12 << FLASHCALW_FCMD_CMD_SHIFT) /* Quick Page Read */
+#  define FLASHCALW_FCMD_CMD_WUP       (13 << FLASHCALW_FCMD_CMD_SHIFT) /* Write User Page */
+#  define FLASHCALW_FCMD_CMD_EUP       (14 << FLASHCALW_FCMD_CMD_SHIFT) /* Erase User Page */
+#  define FLASHCALW_FCMD_CMD_QPRUP     (15 << FLASHCALW_FCMD_CMD_SHIFT) /* Quick Page Read User Page */
+#  define FLASHCALW_FCMD_CMD_HSEN      (16 << FLASHCALW_FCMD_CMD_SHIFT) /* High Speed Mode Enable */
+#  define FLASHCALW_FCMD_CMD_HSDIS     (17 << FLASHCALW_FCMD_CMD_SHIFT) /* High Speed Mode Disable */
+#define FLASHCALW_FCMD_PAGEN_SHIFT     (8)       /* Bits 8-23: Page number */
+#define FLASHCALW_FCMD_PAGEN_MASK      (0xffff << FLASHCALW_FCMD_PAGEN_SHIFT)
+#define FLASHCALW_FCMD_KEY_SHIFT       (14)      /* Bits 24-31: Write protection key */
+#define FLASHCALW_FCMD_KEY_MASK        (0xff << FLASHCALW_FCMD_KEY_SHIFT)
+
+/* Flash Status Register */
+
+#define FLASHCALW_FSR_FRDY             (1 << 0)  /* Bit 0:  Flash Ready Status */
+#define FLASHCALW_FSR_LOCKE            (1 << 2)  /* Bit 2:  Lock Error Status */
+#define FLASHCALW_FSR_PROGE            (1 << 3)  /* Bit 3:  Programming Error Status */
+#define FLASHCALW_FSR_SECURITY         (1 << 4)  /* Bit 4:  Security Bit Status */
+#define FLASHCALW_FSR_QPRR             (1 << 5)  /* Bit 5:  Quick Page Read Result */
+#define FLASHCALW_FSR_HSMODE           (1 << 6)  /* Bit 6:  High-Speed Mode */
+#define FLASHCALW_FSR_ECCERR_SHIFT     (8)       /* Bits 8-0: ECC Error Status */
+#define FLASHCALW_FSR_ECCERR_MASK      (3 << FLASHCALW_FSR_ECCERR_SHIFT)
+#define FLASHCALW_FSR_LOCK(n)          (1 << ((n)+16)
+#define FLASHCALW_FSR_LOCK0            (1 << 16) /* Bit 16: Lock Region 0 Lock Status */
+#define FLASHCALW_FSR_LOCK1            (1 << 17) /* Bit 17: Lock Region 1 Lock Status */
+#define FLASHCALW_FSR_LOCK2            (1 << 18) /* Bit 18: Lock Region 2 Lock Status */
+#define FLASHCALW_FSR_LOCK3            (1 << 19) /* Bit 19: Lock Region 3 Lock Status */
+#define FLASHCALW_FSR_LOCK4            (1 << 20) /* Bit 20: Lock Region 4 Lock Status */
+#define FLASHCALW_FSR_LOCK5            (1 << 21) /* Bit 21: Lock Region 5 Lock Status */
+#define FLASHCALW_FSR_LOCK6            (1 << 22) /* Bit 22: Lock Region 6 Lock Status */
+#define FLASHCALW_FSR_LOCK7            (1 << 23) /* Bit 23: Lock Region 7 Lock Status */
+#define FLASHCALW_FSR_LOCK8            (1 << 24) /* Bit 24: Lock Region 8 Lock Status */
+#define FLASHCALW_FSR_LOCK9            (1 << 25) /* Bit 25: Lock Region 9 Lock Status */
+#define FLASHCALW_FSR_LOCK10           (1 << 26) /* Bit 26: Lock Region 10 Lock Status */
+#define FLASHCALW_FSR_LOCK11           (1 << 27) /* Bit 27: Lock Region 11 Lock Status */
+#define FLASHCALW_FSR_LOCK12           (1 << 28) /* Bit 28: Lock Region 12 Lock Status */
+#define FLASHCALW_FSR_LOCK13           (1 << 29) /* Bit 29: Lock Region 13 Lock Status */
+#define FLASHCALW_FSR_LOCK14           (1 << 30) /* Bit 30: Lock Region 14 Lock Status */
+#define FLASHCALW_FSR_LOCK15           (1 << 31) /* Bit 31: Lock Region 15 Lock Status */
+
+/* Flash Parameter Register */
+#define FLASHCALW_FPR_
+
+#define FLASHCALW_FPR_FSZ_SHIFT        (0)       /* Bits 0-3: Flash Size */
+#define FLASHCALW_FPR_FSZ_MASK         (15 << FLASHCALW_FPR_FSZ_SHIFT)
+#  define FLASHCALW_FPR_FSZ_4KB        (0 << FLASHCALW_FPR_FSZ_SHIFT)  /* 4 Kbytes */
+#  define FLASHCALW_FPR_FSZ_8KB        (1 << FLASHCALW_FPR_FSZ_SHIFT)  /* 8 Kbytes */
+#  define FLASHCALW_FPR_FSZ_16KB       (2 << FLASHCALW_FPR_FSZ_SHIFT)  /* 16 Kbytes */
+#  define FLASHCALW_FPR_FSZ_32KB       (3 << FLASHCALW_FPR_FSZ_SHIFT)  /* 32 Kbytes */
+#  define FLASHCALW_FPR_FSZ_48KB       (4 << FLASHCALW_FPR_FSZ_SHIFT)  /* 48 Kbytes */
+#  define FLASHCALW_FPR_FSZ_64KB       (5 << FLASHCALW_FPR_FSZ_SHIFT)  /* 64 Kbytes */
+#  define FLASHCALW_FPR_FSZ_96KB       (6 << FLASHCALW_FPR_FSZ_SHIFT)  /* 96 Kbytes */
+#  define FLASHCALW_FPR_FSZ_128KB      (7 << FLASHCALW_FPR_FSZ_SHIFT)  /* 128 Kbytes */
+#  define FLASHCALW_FPR_FSZ_192KB      (8 << FLASHCALW_FPR_FSZ_SHIFT)  /* 192 Kbytes */
+#  define FLASHCALW_FPR_FSZ_256KB      (9 << FLASHCALW_FPR_FSZ_SHIFT)  /* 256 Kbytes */
+#  define FLASHCALW_FPR_FSZ_384KB      (10 << FLASHCALW_FPR_FSZ_SHIFT) /* 384 Kbytes */
+#  define FLASHCALW_FPR_FSZ_512KB      (11 << FLASHCALW_FPR_FSZ_SHIFT) /* 512 Kbytes */
+#  define FLASHCALW_FPR_FSZ_768KB      (12 << FLASHCALW_FPR_FSZ_SHIFT) /* 768 Kbytes */
+#  define FLASHCALW_FPR_FSZ_1MB        (13 << FLASHCALW_FPR_FSZ_SHIFT) /* 1024 Kbytes */
+#  define FLASHCALW_FPR_FSZ_2MB        (14 << FLASHCALW_FPR_FSZ_SHIFT) /* 2048 Kbytes */
+#define FLASHCALW_FPR_PSZ_SHIFT        (8)       /* Bits 8-9: Page Size */
+#define FLASHCALW_FPR_PSZ_MASK         (7 << FLASHCALW_FPR_PSZ_SHIFT)
+#  define FLASHCALW_FPR_PSZ_32KB       (0 << FLASHCALW_FPR_PSZ_SHIFT)  /* 32 Kbytes */
+#  define FLASHCALW_FPR_PSZ_64KB       (1 << FLASHCALW_FPR_PSZ_SHIFT)  /* 64 Kbytes */
+#  define FLASHCALW_FPR_PSZ_128KB      (2 << FLASHCALW_FPR_PSZ_SHIFT)  /* 128 Kbytes */
+#  define FLASHCALW_FPR_PSZ_256KB      (3 << FLASHCALW_FPR_PSZ_SHIFT)  /* 256 Kbytes */
+#  define FLASHCALW_FPR_PSZ_512KGB     (4 << FLASHCALW_FPR_PSZ_SHIFT)  /* 512 Kbytes */
+#  define FLASHCALW_FPR_PSZ_1MB        (5 << FLASHCALW_FPR_PSZ_SHIFT)  /* 1024 Kbytes */
+#  define FLASHCALW_FPR_PSZ_2MB        (6 << FLASHCALW_FPR_PSZ_SHIFT)  /* 2048 Kbytes */
+#  define FLASHCALW_FPR_PSZ_4MB        (7 << FLASHCALW_FPR_PSZ_SHIFT)  /* 4096 Kbytes */
+
+/* Flash Version Register */
+
+#define FLASHCALW_FVR_VERSION_SHIFT   (0)        /* Bits 0-11: Version Number */
+#define FLASHCALW_FVR_VERSION_MASK    (0xfff << FLASHCALW_FVR_VERSION_SHIFT)
+#define FLASHCALW_FVR_VARIANT_SHIFT   (16)       /* Bits 16-19: Variant Number */
+#define FLASHCALW_FVR_VARIANT_MASK    (15 << FLASHCALW_FVR_VARIANT_SHIFT)
+
+/* Flash General Purpose Fuse Register Hi */
+
+#define FLASHCALW_FGPFRHI(n)           (1 << ((n)-32))
+#define FLASHCALW_FGPFRHI32            (1 << 0)  /* Bit 0:  General Purpose Fuse 32 */
+#define FLASHCALW_FGPFRHI33            (1 << 1)  /* Bit 1:  General Purpose Fuse 33 */
+#define FLASHCALW_FGPFRHI34            (1 << 2)  /* Bit 2:  General Purpose Fuse 34 */
+#define FLASHCALW_FGPFRHI35            (1 << 3)  /* Bit 3:  General Purpose Fuse 35 */
+#define FLASHCALW_FGPFRHI36            (1 << 4)  /* Bit 4:  General Purpose Fuse 36 */
+#define FLASHCALW_FGPFRHI37            (1 << 5)  /* Bit 5:  General Purpose Fuse 37 */
+#define FLASHCALW_FGPFRHI38            (1 << 6)  /* Bit 6:  General Purpose Fuse 38 */
+#define FLASHCALW_FGPFRHI39            (1 << 7)  /* Bit 7:  General Purpose Fuse 39 */
+#define FLASHCALW_FGPFRHI40            (1 << 8)  /* Bit 8:  General Purpose Fuse 40 */
+#define FLASHCALW_FGPFRHI41            (1 << 9)  /* Bit 9:  General Purpose Fuse 41 */
+#define FLASHCALW_FGPFRHI42            (1 << 10) /* Bit 10: General Purpose Fuse 42 */
+#define FLASHCALW_FGPFRHI43            (1 << 11) /* Bit 11: General Purpose Fuse 43 */
+#define FLASHCALW_FGPFRHI44            (1 << 12) /* Bit 12: General Purpose Fuse 44 */
+#define FLASHCALW_FGPFRHI45            (1 << 13) /* Bit 13: General Purpose Fuse 45 */
+#define FLASHCALW_FGPFRHI46            (1 << 14) /* Bit 14: General Purpose Fuse 46 */
+#define FLASHCALW_FGPFRHI47            (1 << 15) /* Bit 15: General Purpose Fuse 47 */
+#define FLASHCALW_FGPFRHI48            (1 << 16) /* Bit 16: General Purpose Fuse 48 */
+#define FLASHCALW_FGPFRHI49            (1 << 17) /* Bit 17: General Purpose Fuse 49 */
+#define FLASHCALW_FGPFRHI50            (1 << 18) /* Bit 18: General Purpose Fuse 50 */
+#define FLASHCALW_FGPFRHI51            (1 << 19) /* Bit 19: General Purpose Fuse 51 */
+#define FLASHCALW_FGPFRHI52            (1 << 20) /* Bit 20: General Purpose Fuse 52 */
+#define FLASHCALW_FGPFRHI53            (1 << 21) /* Bit 21: General Purpose Fuse 53 */
+#define FLASHCALW_FGPFRHI54            (1 << 22) /* Bit 22: General Purpose Fuse 54 */
+#define FLASHCALW_FGPFRHI55            (1 << 23) /* Bit 23: General Purpose Fuse 55 */
+#define FLASHCALW_FGPFRHI56            (1 << 24) /* Bit 24: General Purpose Fuse 56 */
+#define FLASHCALW_FGPFRHI57            (1 << 25) /* Bit 25: General Purpose Fuse 57 */
+#define FLASHCALW_FGPFRHI58            (1 << 26) /* Bit 26: General Purpose Fuse 58 */
+#define FLASHCALW_FGPFRHI59            (1 << 27) /* Bit 27: General Purpose Fuse 59 */
+#define FLASHCALW_FGPFRHI60            (1 << 28) /* Bit 28: General Purpose Fuse 60 */
+#define FLASHCALW_FGPFRHI61            (1 << 29) /* Bit 29: General Purpose Fuse 61 */
+#define FLASHCALW_FGPFRHI62            (1 << 30) /* Bit 30: General Purpose Fuse 62 */
+#define FLASHCALW_FGPFRHI63            (1 << 31) /* Bit 31: General Purpose Fuse 63 */
+
+/* Flash General Purpose Fuse Register Lo */
+
+#define FLASHCALW_FGPFRLO(n)           (1 << (n))
+#define FLASHCALW_FGPFRLO00            (1 << 0)  /* Bit 0:  General Purpose Fuse 00 */
+#define FLASHCALW_FGPFRLO01            (1 << 1)  /* Bit 1:  General Purpose Fuse 01 */
+#define FLASHCALW_FGPFRLO02            (1 << 2)  /* Bit 2:  General Purpose Fuse 02 */
+#define FLASHCALW_FGPFRLO03            (1 << 3)  /* Bit 3:  General Purpose Fuse 03 */
+#define FLASHCALW_FGPFRLO04            (1 << 4)  /* Bit 4:  General Purpose Fuse 04 */
+#define FLASHCALW_FGPFRLO05            (1 << 5)  /* Bit 5:  General Purpose Fuse 05 */
+#define FLASHCALW_FGPFRLO06            (1 << 6)  /* Bit 6:  General Purpose Fuse 06 */
+#define FLASHCALW_FGPFRLO07            (1 << 7)  /* Bit 7:  General Purpose Fuse 07 */
+#define FLASHCALW_FGPFRLO08            (1 << 8)  /* Bit 8:  General Purpose Fuse 08 */
+#define FLASHCALW_FGPFRLO09            (1 << 9)  /* Bit 9:  General Purpose Fuse 09 */
+#define FLASHCALW_FGPFRLO10            (1 << 10) /* Bit 10: General Purpose Fuse 10 */
+#define FLASHCALW_FGPFRLO11            (1 << 11) /* Bit 11: General Purpose Fuse 11 */
+#define FLASHCALW_FGPFRLO12            (1 << 12) /* Bit 12: General Purpose Fuse 12 */
+#define FLASHCALW_FGPFRLO13            (1 << 13) /* Bit 13: General Purpose Fuse 13 */
+#define FLASHCALW_FGPFRLO14            (1 << 14) /* Bit 14: General Purpose Fuse 14 */
+#define FLASHCALW_FGPFRLO15            (1 << 15) /* Bit 15: General Purpose Fuse 15 */
+#define FLASHCALW_FGPFRLO16            (1 << 16) /* Bit 16: General Purpose Fuse 16 */
+#define FLASHCALW_FGPFRLO17            (1 << 17) /* Bit 17: General Purpose Fuse 17 */
+#define FLASHCALW_FGPFRLO18            (1 << 18) /* Bit 18: General Purpose Fuse 18 */
+#define FLASHCALW_FGPFRLO19            (1 << 19) /* Bit 19: General Purpose Fuse 19 */
+#define FLASHCALW_FGPFRLO20            (1 << 20) /* Bit 20: General Purpose Fuse 20 */
+#define FLASHCALW_FGPFRLO21            (1 << 21) /* Bit 21: General Purpose Fuse 21 */
+#define FLASHCALW_FGPFRLO22            (1 << 22) /* Bit 22: General Purpose Fuse 22 */
+#define FLASHCALW_FGPFRLO23            (1 << 23) /* Bit 23: General Purpose Fuse 23 */
+#define FLASHCALW_FGPFRLO24            (1 << 24) /* Bit 24: General Purpose Fuse 24 */
+#define FLASHCALW_FGPFRLO25            (1 << 25) /* Bit 25: General Purpose Fuse 25 */
+#define FLASHCALW_FGPFRLO26            (1 << 26) /* Bit 26: General Purpose Fuse 26 */
+#define FLASHCALW_FGPFRLO27            (1 << 27) /* Bit 27: General Purpose Fuse 27 */
+#define FLASHCALW_FGPFRLO28            (1 << 28) /* Bit 28: General Purpose Fuse 28 */
+#define FLASHCALW_FGPFRLO29            (1 << 29) /* Bit 29: General Purpose Fuse 29 */
+#define FLASHCALW_FGPFRLO30            (1 << 30) /* Bit 30: General Purpose Fuse 30 */
+#define FLASHCALW_FGPFRLO31            (1 << 31) /* Bit 31: General Purpose Fuse 31 */
+
+/* PicoCache Control Register */
+
+#define PICOCACHE_CTRL_CEN             (1 << 0)  /* Bit 0:  Cache Enable */
+
+/* PicoCache Status Register */
+
+#define PICOCACHE_SR_CSTS              (1 << 0)  /* Bit 0:  Cache Controller Status */
+
+/* PicoCache Maintenance Register 0 */
+
+#define PICOCACHE_MAINT0_INVALL        (1 << 0)  /* Bit 0:  Cache Controller Invalidate All */
+
+/* PicoCache Maintenance Register 1 */
+
+#define PICOCACHE_MAINT1_INDEX_SHIFT   (4)       /* Bits 4-7: Invalidate Index */
+#define PICOCACHE_MAINT1_INDEX_MASK    (15 << PICOCACHE_MAINT1_INDEX_SHIFT)
+
+/* PicoCache Monitor Configuration Register */
+
+#define PICOCACHE_MCFG_MODE_SHIFT      (0)      /* Bits 0-1: Cache Controller Monitor Counter Mode */
+#define PICOCACHE_MCFG_MODE_MASK       (3 << PICOCACHE_MCFG_MODE_SHIFT)
+#  define PICOCACHE_MCFG_MODE_CYCLE    (0 << PICOCACHE_MCFG_MODE_SHIFT) /* CYCLE_COUNT cycle counter */
+#  define PICOCACHE_MCFG_MODE_IHIT     (1 << PICOCACHE_MCFG_MODE_SHIFT) /* IHIT_COUNT instruction hit counter */
+#  define PICOCACHE_MCFG_MODE_DHIT     (2 << PICOCACHE_MCFG_MODE_SHIFT) /* DHIT_COUNT data hit counter */
+
+/* PicoCache Monitor Enable Register */
+
+#define PICOCACHE_MEN_MENABLE        (1 << 0)  /* Bit 0:  Monitor Enable */
+
+/* PicoCache Monitor Control Register */
+
+#define PICOCACHE_MCTRL_SWRST        (1 << 0)  /* Bit 0:  Monitor Software Reset */
+
+/* PicoCache Monitor Status Register (32-bit event count) */
+
+/* Version Register */
+
+#define PICOCACHE_PVR_VERSION_SHIFT   (0)        /* Bits 0-11: Version Number */
+#define PICOCACHE_PVR_VERSION_MASK    (0xfff << PICOCACHE_PVR_FVR_VERSION_SHIFT)
+#define PICOCACHE_PVR_MFN_SHIFT       (16)       /* Bits 16-19: MFN */
+#define PICOCACHE_PVR_MFN_MASK        (15 << PICOCACHE_PVR_FVR_MFN_SHIFT)
+
+/* Flash Command Set ****************************************************************/
+
+#define FLASH_CMD_NOP                0 /* No operation */
+#define FLASH_CMD_WP                 1 /* Write Page */
+#define FLASH_CMD_EP                 2 /* Erase Page */
+#define FLASH_CMD_CPB                3 /* Clear Page Buffer */
+#define FLASH_CMD_LP                 4 /* Lock region containing given Page */
+#define FLASH_CMD_UP                 5 /* Unlock region containing given Page */
+#define FLASH_CMD_EA                 6 /* Erase All */
+#define FLASH_CMD_WGPB               7 /* Write General-Purpose Fuse Bit */
+#define FLASH_CMD_EGPB               8 /* Erase General-Purpose Fuse Bit */
+#define FLASH_CMD_SSB                9 /* Set Security Fuses */
+#define FLASH_CMD_PGPFB             10 /* Program GP Fuse Byte */
+#define FLASH_CMD_EAGPF             11 /* Erase All GPFuses */
+#define FLASH_CMD_QPR               12 /* Quick Page Read */
+#define FLASH_CMD_WUP               13 /* Write User Page */
+#define FLASH_CMD_EUP               14 /* Erase User Page */
+#define FLASH_CMD_QPRUP             15 /* Quick Page Read User Page */
+#define FLASH_CMD_HSEN              16 /* High Speed Mode Enable */
+#define FLASH_CMD_HSDIS             17 /* High Speed Mode Disable */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4LFLASHCALW_H */
+
diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam4l_memorymap.h
index 0a3acdcc2a..c85e6b4b81 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam4l_memorymap.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam4l_memorymap.h
@@ -109,7 +109,7 @@
 
 #define SAM_FLASHCALW_BASE   0x400a0000 /* 0x400a0000-0x400a03ff: FLASHCALW */
 #define SAM_PICOCACHE_BASE   0x400a0400 /* 0x400a0400-0x400a0fff: PICOCACHE */
-#define SAM_HMATRIX_BASE     0x400a1000 /* 0x400a1000-0x400a1fff: PICOCACHE */
+#define SAM_HMATRIX_BASE     0x400a1000 /* 0x400a1000-0x400a1fff: HMATRIX */
 #define SAM_PDCA_BASE        0x400a2000 /* 0x400a2000-0x400a2fff: Peripheral DMA Controller */
 #define SAM_SMAP_BASE        0x400a3000 /* 0x400a3000-0x400a3fff: SMAP */
 #define SAM_CRCCU_BASE       0x400a4000 /* 0x400a4000-0x400a4fff: CRC Calculation Unit */
diff --git a/nuttx/arch/arm/src/sam34/sam_clockconfig.c b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c
similarity index 99%
rename from nuttx/arch/arm/src/sam34/sam_clockconfig.c
rename to nuttx/arch/arm/src/sam34/sam3u_clockconfig.c
index 051e22ac76..374e4868a7 100644
--- a/nuttx/arch/arm/src/sam34/sam_clockconfig.c
+++ b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/chip/sam_clockconfig.c
+ * arch/arm/src/chip/sam3u_clockconfig.c
  *
  *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -50,9 +50,9 @@
 
 #include "sam_clockconfig.h"
 #include "chip/sam_pmc.h"
-#include "chip/sam_eefc.h"
+#include "chip/sam3u_eefc.h"
 #include "chip/sam_wdt.h"
-#include "chip/sam_supc.h"
+#include "chip/sam3u_supc.h"
 #include "chip/sam_matrix.h"
 
 /****************************************************************************
diff --git a/nuttx/arch/avr/src/at32uc3/at32uc3_flashc.h b/nuttx/arch/avr/src/at32uc3/at32uc3_flashc.h
index e66663fee3..c05f5ac18a 100644
--- a/nuttx/arch/avr/src/at32uc3/at32uc3_flashc.h
+++ b/nuttx/arch/avr/src/at32uc3/at32uc3_flashc.h
@@ -89,12 +89,12 @@
 #define FLASHC_FSR_QPRR             (1 << 5)  /* Bit 5:  Quick Page Read Result */
 #define FLASHC_FSR_FSZ_SHIFT        (13)      /* Bits 13-15: Flash Size */
 #define FLASHC_FSR_FSZ_MASK         (7 << FLASHC_FSR_FSZ_SHIFT)
-#  define FLASHC_FSR_FSZ_23KB       (0 << FLASHC_FSR_FSZ_SHIFT) /* 32 Kbytes */
+#  define FLASHC_FSR_FSZ_32KB       (0 << FLASHC_FSR_FSZ_SHIFT) /* 32 Kbytes */
 #  define FLASHC_FSR_FSZ_64KB       (1 << FLASHC_FSR_FSZ_SHIFT) /* 64 Kbytes */
 #  define FLASHC_FSR_FSZ_128KB      (2 << FLASHC_FSR_FSZ_SHIFT) /* 128 Kbytes */
 #  define FLASHC_FSR_FSZ_256KB      (3 << FLASHC_FSR_FSZ_SHIFT) /* 256 Kbytes */
 #  define FLASHC_FSR_FSZ_384KB      (4 << FLASHC_FSR_FSZ_SHIFT) /* 384 Kbytes */
-#  define FLASHC_FSR_FSZ_512KGB     (5 << FLASHC_FSR_FSZ_SHIFT) /* 512 Kbytes */
+#  define FLASHC_FSR_FSZ_512KB      (5 << FLASHC_FSR_FSZ_SHIFT) /* 512 Kbytes */
 #  define FLASHC_FSR_FSZ_768KB      (6 << FLASHC_FSR_FSZ_SHIFT) /* 768 Kbytes */
 #  define FLASHC_FSR_FSZ_1MB        (7 << FLASHC_FSR_FSZ_SHIFT) /* 1024 Kbytes */
 #define FLASHC_FSR_LOCK(n)          (1 << ((n)+16)
diff --git a/nuttx/configs/sam4l-xplained/include/board.h b/nuttx/configs/sam4l-xplained/include/board.h
index ca7bb0ef1f..4aaefd3fbc 100644
--- a/nuttx/configs/sam4l-xplained/include/board.h
+++ b/nuttx/configs/sam4l-xplained/include/board.h
@@ -78,6 +78,14 @@
 
 #define BOARD_CKGR_UCKR_UPLLCOUNT (3 << CKGR_UCKR_UPLLCOUNT_SHIFT)
 
+/* System clock dividers: Fbus = Fsys / (2 ^ BUS_div) */
+
+#define BOARD_SYSCLK_CPU_DIV       0
+#define BOARD_SYSCLK_PBA_DIV       0
+#define BOARD_SYSCLK_PBB_DIV       0
+#define BOARD_SYSCLK_PBC_DIV       0
+#define BOARD_SYSCLK_PBD_DIV       0
+
 /* Resulting frequencies */
 
 #define SAM_MAINOSC_FREQUENCY      (12000000)

From fd3e0f77e4c97cd8442ff979437c7928be36998f Mon Sep 17 00:00:00 2001
From: Gregory Nutt 
Date: Wed, 5 Jun 2013 13:35:19 -0600
Subject: [PATCH 34/41] Add power management register defintions and clock
 control logic for the SAM4L

---
 nuttx/ChangeLog                               |   7 +-
 .../arch/arm/src/sam34/chip/sam4l_flashcalw.h |   8 +-
 nuttx/arch/arm/src/sam34/chip/sam4l_pm.h      | 335 ++++++++++++
 nuttx/arch/arm/src/sam34/sam4l_clockconfig.c  | 506 ++++++++++++++++++
 nuttx/arch/arm/src/sam34/sam_clockconfig.h    |   5 +-
 nuttx/mm/README.txt                           | 170 +++---
 6 files changed, 954 insertions(+), 77 deletions(-)
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_pm.h
 create mode 100644 nuttx/arch/arm/src/sam34/sam4l_clockconfig.c

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 88f3b26d10..a332b7c21d 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -4902,4 +4902,9 @@
 	  LED interfaces (2013-6-5).
 	* arch/arm/src/sam34/sam4l_gpio.c and arch/arm/src/sam34/chip/sam4l_gpio.h:
 	  Fix GPIO port address; fix compilation errors (2013-6-5).
- 
+	* arch/arm/src/sam34/chip/sam4l_flashcalw.h:  Add header file
+	  for SAM4L FLASH and PICOCACHE definitions (2013-6-5).
+	* arch/arm/src/sam34/chip/sam4l_pm.h:  Add header file for SAM4L
+	  Power Management.  Leveraged from AVR32 (2013-6-5).
+	* arch/arm/src/sam34/sarm4l_clockconfig.c:  SAM4L clock configuration
+	  logic (leveraged from AVR32).
diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h b/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h
index 1ae40fbf72..d2503aa18d 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h
@@ -4,6 +4,8 @@
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
+ * This file is derived from nuttx/arch/avr/src/at32uc3/at32uc3_flashc.h.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -33,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4LFLASHCALW_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4LFLASHCALW_H
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_FLASHCALW_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_FLASHCALW_H
 
 /************************************************************************************
  * Included Files
@@ -343,5 +345,5 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4LFLASHCALW_H */
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_FLASHCALW_H */
 
diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h b/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h
new file mode 100644
index 0000000000..c314e8efe0
--- /dev/null
+++ b/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h
@@ -0,0 +1,335 @@
+/************************************************************************************
+ * arch/avr/src/sam34/sam4l_pm.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * This file is derived from nuttx/arch/avr/src/at32uc3/at32uc3_pm.h.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PM_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include "chip.h"
+#include "chip/sam_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define SAM_PM_MCCTRL_OFFSET       0x0000 /* Main Clock Control Register */
+#define SAM_PM_CPUSEL_OFFSET       0x0004 /* CPU Clock Select Register */
+#define SAM_PM_PBASEL_OFFSET       0x000c /* PBA Clock Select Register */
+#define SAM_PM_PBBSEL_OFFSET       0x0010 /* PBB Clock Select Register */
+#define SAM_PM_PBCSEL_OFFSET       0x0014 /* PBC Clock Select Register */
+#define SAM_PM_PBDSEL_OFFSET       0x0018 /* PBD Clock Select Register */
+#define SAM_PM_CPUMASK_OFFSET      0x0020 /* CPU Mask Register */
+#define SAM_PM_HSBMASK_OFFSET      0x0024 /* HSB Mask Register */
+#define SAM_PM_PBAMASK_OFFSET      0x0028 /* PBA Mask Register */
+#define SAM_PM_PBBMASK_OFFSET      0x002c /* PBB Mask Register */
+#define SAM_PM_PBCMASK_OFFSET      0x0030 /* PBC Mask Register */
+#define SAM_PM_PBDMASK_OFFSET      0x0034 /* PBD Mask Register */
+#define SAM_PM_PBADIVMASK_OFFSET   0x0040 /* PBA Divided Mask */
+#define SAM_PM_CFDCTRL_OFFSET      0x0054 /* Clock Failure Detector Control */
+#define SAM_PM_UNLOCK_OFFSET       0x0058 /*  Unlock Register */
+#define SAM_PM_IER_OFFSET          0x00c0 /* Interrupt Enable Register */
+#define SAM_PM_IDR_OFFSET          0x00c4 /* Interrupt Disable Register */
+#define SAM_PM_IMR_OFFSET          0x00c8 /* Interrupt Mask Register */
+#define SAM_PM_ISR_OFFSET          0x00cc /* Interrupt Status Register */
+#define SAM_PM_ICR_OFFSET          0x00d0 /* Interrupt Clear Register */
+#define SAM_PM_SR_OFFSET           0x00d4 /* Status Register Register */
+#define SAM_PM_PPCR_OFFSET         0x0160 /* Peripheral Power Control Register */
+#define SAM_PM_RCAUSE_OFFSET       0x0180 /* Reset Cause Register */
+#define SAM_PM_WCAUSE_OFFSET       0x0184 /* Wake Cause Register */
+#define SAM_PM_AWEN_OFFSET         0x0188 /* Asynchronous Wake Up Enable Register */
+#define SAM_PM_PROTCTRL_OFFSET     0x018c /* Protection Control Register */
+#define SAM_PM_FASTSLEEP_OFFSET    0x0194 /* Fast Sleep Register */
+#define SAM_PM_CONFIG_OFFSET       0x03f8 /* Configuration Register */
+#define SAM_PM_VERSION_OFFSET      0x03fc /* Version Register */
+
+/* Register Addresses ***************************************************************/
+
+#define SAM_PM_MCCTRL              (SAM_PM_BASE+SAM_PM_MCCTRL_OFFSET)
+#define SAM_PM_CPUSEL              (SAM_PM_BASE+SAM_PM_CPUSEL_OFFSET)
+#define SAM_PM_PBASEL              (SAM_PM_BASE+SAM_PM_PBASEL_OFFSET)
+#define SAM_PM_PBBSEL              (SAM_PM_BASE+SAM_PM_PBBSEL_OFFSET)
+#define SAM_PM_PBCSEL              (SAM_PM_BASE+SAM_PM_PBCSEL_OFFSET)
+#define SAM_PM_PBDSEL              (SAM_PM_BASE+SAM_PM_PBDSEL_OFFSET)
+#define SAM_PM_CPUMASK             (SAM_PM_BASE+SAM_PM_CPUMASK_OFFSET)
+#define SAM_PM_HSBMASK             (SAM_PM_BASE+SAM_PM_HSBMASK_OFFSET)
+#define SAM_PM_PBAMASK             (SAM_PM_BASE+SAM_PM_PBAMASK_OFFSET)
+#define SAM_PM_PBBMASK             (SAM_PM_BASE+SAM_PM_PBBMASK_OFFSET)
+#define SAM_PM_PBCMASK             (SAM_PM_BASE+SAM_PM_PBCMASK_OFFSET)
+#define SAM_PM_PBDMASK             (SAM_PM_BASE+SAM_PM_PBDMASK_OFFSET)
+#define SAM_PM_PBADIVMASK          (SAM_PM_BASE+SAM_PM_PBADIVMASK_OFFSET)
+#define SAM_PM_CFDCTRL             (SAM_PM_BASE+SAM_PM_CFDCTRL_OFFSET)
+#define SAM_PM_UNLOCK              (SAM_PM_BASE+SAM_PM_UNLOCK_OFFSET)
+#define SAM_PM_IER                 (SAM_PM_BASE+SAM_PM_IER_OFFSET)
+#define SAM_PM_IDR                 (SAM_PM_BASE+SAM_PM_IDR_OFFSET)
+#define SAM_PM_IMR                 (SAM_PM_BASE+SAM_PM_IMR_OFFSET)
+#define SAM_PM_ISR                 (SAM_PM_BASE+SAM_PM_ISR_OFFSET)
+#define SAM_PM_ICR                 (SAM_PM_BASE+SAM_PM_ICR_OFFSET)
+#define SAM_PM_SR                  (SAM_PM_BASE+SAM_PM_SR_OFFSET)
+#define SAM_PM_PPCR                (SAM_PM_BASE+SAM_PM_PPCR_OFFSET)
+#define SAM_PM_RCAUSE              (SAM_PM_BASE+SAM_PM_RCAUSE_OFFSET)
+#define SAM_PM_WCAUSE              (SAM_PM_BASE+SAM_PM_WCAUSE_OFFSET)
+#define SAM_PM_AWEN                (SAM_PM_BASE+SAM_PM_AWEN_OFFSET)
+#define SAM_PM_PROTCTRL            (SAM_PM_BASE+SAM_PM_PROTCTRL_OFFSET)
+#define SAM_PM_FASTSLEEP           (SAM_PM_BASE+SAM_PM_FASTSLEEP_OFFSET)
+#define SAM_PM_CONFIG              (SAM_PM_BASE+SAM_PM_CONFIG_OFFSET)
+#define SAM_PM_VERSION             (SAM_PM_BASE+SAM_PM_VERSION_OFFSET)
+
+/* Register Bit-field Definitions ***************************************************/
+
+/* Main Clock Control Register Bit-field Definitions */
+
+#define PM_MCCTRL_MCSEL_SHIFT      (0)       /* Bits 0-2: Main Clock Select */
+#define PM_MCCTRL_MCSEL_MASK       (7 << PM_MCCTRL_MCSEL_SHIFT)
+#  define PM_MCCTRL_MCSEL_RCSYS    (0 << PM_MCCTRL_MCSEL_SHIFT) /* System RC oscillator */
+#  define PM_MCCTRL_MCSEL_OSC0     (1 << PM_MCCTRL_MCSEL_SHIFT) /* Oscillator0 */
+#  define PM_MCCTRL_MCSEL_PLL      (2 << PM_MCCTRL_MCSEL_SHIFT) /* PLL */
+#  define PM_MCCTRL_MCSEL_DFLL     (3 << PM_MCCTRL_MCSEL_SHIFT) /* DFLL */
+#  define PM_MCCTRL_MCSEL_RC80M    (4 << PM_MCCTRL_MCSEL_SHIFT) /* 80MHz RC oscillator */
+#  define PM_MCCTRL_MCSEL_RCFAST   (5 << PM_MCCTRL_MCSEL_SHIFT) /* 4/8/12 MHz RC oscillator */
+#  define PM_MCCTRL_MCSEL_RC1M     (6 << PM_MCCTRL_MCSEL_SHIFT) /* 1 MHz RC oscillator */
+
+/* CPU Clock Select Register Bit-field Definitions */
+
+#define PM_CPUSEL_SHIFT            (0)       /* Bits 0-2: CPU Clock Select */
+#define PM_CPUSEL_MASK             (7 << PM_CPUSEL_CPUSEL_SHIFT)
+#define PM_CPUSEL_CPUDIV           (1 << 7)  /* Bit 7:  CPU Division */
+
+/* PBA/PBB/PBC/PBD Clock Select Register Bit-field Definitions */
+
+#define PM_PBSEL_SHIFT             (0)       /* Bits 0-2: PBx Clock Select */
+#define PM_PBSEL_MASK              (7 << PM_PBASEL_SHIFT)
+#define PM_PBSEL_DIV               (1 << 7)  /* Bit 7: PBx Division */
+
+/* CPU Mask Register Bit-field Definitions */
+
+#define PM_CPUMASK_OCD             (1 << 0)  /* Bit 0:  OCD */
+
+/* HSB Mask Register Bit-field Definitions */
+
+#define PM_HSBMASK_PDCA            (1 << 0)  /* Bit 0:  PDCA */
+#define PM_HSBMASK_FLASHCALW       (1 << 1)  /* Bit 1:  FLASHCALW */
+#define PM_HSBMASK_HRAMC1          (1 << 2)  /* Bit 2:  HRAMC1 (picoCache RAM) */
+#define PM_HSBMASK_USBC            (1 << 3)  /* Bit 3:  USBC */
+#define PM_HSBMASK_CRCCU           (1 << 4)  /* Bit 4:  CRCCU */
+#define PM_HSBMASK_APBA            (1 << 5)  /* Bit 5:  APBA bridge */
+#define PM_HSBMASK_APBB            (1 << 6)  /* Bit 5:  APBB bridge */
+#define PM_HSBMASK_APBC            (1 << 7)  /* Bit 5:  APBC bridge */
+#define PM_HSBMASK_APBD            (1 << 8)  /* Bit 5:  APBD bridge */
+#define PM_HSBMASK_AESA            (1 << 9)  /* Bit 5:  AESA */
+
+/* PBA Mask Register Bit-field Definitions */
+
+#define PM_PBAMASK_IISC            (1 << 0)  /* Bit 0:  IISC */
+#define PM_PBAMASK_SPI             (1 << 1)  /* Bit 1:  SPI */
+#define PM_PBAMASK_TC0             (1 << 2)  /* Bit 2:  TC0 */
+#define PM_PBAMASK_TC1             (1 << 3)  /* Bit 3:  TC1 */
+#define PM_PBAMASK_TWIM0           (1 << 4)  /* Bit 4:  TWIM0 */
+#define PM_PBAMASK_TWIS0           (1 << 5)  /* Bit 5:  TWIS0 */
+#define PM_PBAMASK_TWIM1           (1 << 6)  /* Bit 6:  TWIM1 */
+#define PM_PBAMASK_TWIS1           (1 << 7)  /* Bit 7:  TWIS1 */
+#define PM_PBAMASK_USART0          (1 << 8)  /* Bit 8:  USART0 */
+#define PM_PBAMASK_USART1          (1 << 9)  /* Bit 9:  USART1 */
+#define PM_PBAMASK_USART2          (1 << 10) /* Bit 10: USART2 */
+#define PM_PBAMASK_USART3          (1 << 11) /* Bit 11: USART3 */
+#define PM_PBAMASK_ADCIFE          (1 << 12) /* Bit 12: ADCIFE */
+#define PM_PBAMASK_DACC            (1 << 13) /* Bit 13: DACC */
+#define PM_PBAMASK_ACIFC           (1 << 14) /* Bit 14: ACIFC */
+#define PM_PBAMASK_GLOC            (1 << 15) /* Bit 15: GLOC */
+#define PM_PBAMASK_ABDACB          (1 << 16) /* Bit 16: ABDACB */
+#define PM_PBAMASK_TRNG            (1 << 17) /* Bit 17: TRNG */
+#define PM_PBAMASK_PARC            (1 << 18) /* Bit 18: PARC */
+#define PM_PBAMASK_CATB            (1 << 19) /* Bit 19: CATB */
+#define PM_PBAMASK_TWIM2           (1 << 21) /* Bit 21: TWIM2 */
+#define PM_PBAMASK_TWIM3           (1 << 22) /* Bit 22: TWIM3 */
+#define PM_PBAMASK_LCDCA           (1 << 23) /* Bit 23: LCDCA*/
+
+/* PBB Mask Register Bit-field Definitions */
+
+#define PM_PBBMASK_FLASHCALW       (1 << 0)  /* Bit 0:  FLASHCALW */
+#define PM_PBBMASK_HRAMC1          (1 << 1)  /* Bit 1:  HRAMC1 */
+#define PM_PBBMASK_HMATRIX         (1 << 2)  /* Bit 2:  HMATRIX */
+#define PM_PBBMASK_PDCA            (1 << 3)  /* Bit 3:  PDCA */
+#define PM_PBBMASK_CRCCU           (1 << 4)  /* Bit 4:  CRCCU */
+#define PM_PBBMASK_USBC            (1 << 5)  /* Bit 5:  USBC */
+#define PM_PBBMASK_PEVC            (1 << 6)  /* Bit 6:  PEVC */
+
+/* PBC Mask Register Bit-field Definitions */
+
+#define PM_PBCMASK_PM              (1 << 0)  /* Bit 0:  PM */
+#define PM_PBCMASK_CHIPID          (1 << 1)  /* Bit 1:  CHIPID */
+#define PM_PBCMASK_SCIF            (1 << 2)  /* Bit 2:  SCIF */
+#define PM_PBCMASK_FREQM           (1 << 3)  /* Bit 3:  FREQM */
+#define PM_PBCMASK_GPIO            (1 << 4)  /* Bit 4:  GPIO */
+
+/* PBD Mask Register Bit-field Definitions */
+
+#define PM_PBDMASK_BPM             (1 << 0)  /* Bit 0:  BPM */
+#define PM_PBDMASK_BSCIF           (1 << 1)  /* Bit 1:  BSCIF */
+#define PM_PBDMASK_AST             (1 << 2)  /* Bit 2:  AST */
+#define PM_PBDMASK_WDT             (1 << 3)  /* Bit 3:  WDT */
+#define PM_PBDMASK_EIC             (1 << 4)  /* Bit 4:  EIC */
+#define PM_PBDMASK_PICOUART        (1 << 5)  /* Bit 5:  PICOUART */
+
+/* PBA Divided Mask */
+
+#define PM_PBADIVMASK_TIMER_CLOCK2 (1 << 0) /* Bit 0: TIMER_CLOCK2 (TC0-1) */
+#define PM_PBADIVMASK_CLK_USART    (1 << 2) /* Bit 2: CLK_USART/DIV (USART0-3) */
+#define PM_PBADIVMASK_TIMER_CLOCK3 (1 << 2) /* Bit 2: TIMER_CLOCK3 (TC0-1) */
+#define PM_PBADIVMASK_TIMER_CLOCK4 (1 << 4) /* Bit 4: TIMER_CLOCK4 (TC0-1) */
+#define PM_PBADIVMASK_TIMER_CLOCK5 (1 << 6) /* Bit 5: TIMER_CLOCK5 (TC0-1) */
+
+/* Clock Failure Detector Control */
+
+#define PM_CFDCTRL_CFDEN           (1 << 0)  /* Bit 0:  Clock Failure Detection Enable */
+#define PM_CFDCTRL_SFV             (1 << 31) /* Bit 31: Store Final Value */
+
+/* Unlock Register */
+
+#define PM_UNLOCK_ADDR_SHIFT       (0)       /* Bits 0-9: Unlock Address */
+#define PM_UNLOCK_ADDR_MASK        (0x3ff << PM_UNLOCK_ADDR_SHIFT)
+#define PM_UNLOCK_KEY_SHIFT        (24)      /* Bits 24-31: Unlock Key */
+#define PM_UNLOCK_KEY_MASK         (0xff << PM_UNLOCK_KEY_SHIFT)
+
+/* Interrupt Enable Register Bit-field Definitions */
+/* Interrupt Disable Register Bit-field Definitions */
+/* Interrupt Mask Register Bit-field Definitions */
+/* Interrupt Status Register Bit-field Definitions */
+/* Interrupt Clear Register Bit-field Definitions */
+/* Status Register Register */
+
+#define PM_INT_CFD                (1 << 0)  /* Bit 0:  CFD */
+#define PM_INT_CKRDY              (1 << 5)  /* Bit 5:  CKRDY */
+#define PM_INT_WAKE               (1 << 8)  /* Bit 8:  WAKE */
+
+/* Peripheral Power Control Register */
+
+#define PM_PPCR_RSTPUN            (1 << 0)  /* Bit 0:  Reset Pullup */
+#define PM_PPCR_CATBRCMASK        (1 << 1)  /* Bit 1:  CAT Request Clock Mask */
+#define PM_PPCR_ACIFCRCMASK       (1 << 2)  /* Bit 2:  ACIFC Request Clock Mask */
+#define PM_PPCR_ASTRCMASK         (1 << 3)  /* Bit 3:  AST Request Clock Mask */
+#define PM_PPCR_TWIS0RCMASK       (1 << 4)  /* Bit 4:  TWIS0 Request Clock Mask */
+#define PM_PPCR_TWIS1RCMASK       (1 << 5)  /* Bit 5:  TWIS1 Request Clock Mask */
+#define PM_PPCR_PEVCRCMASK        (1 << 6)  /* Bit 6:  PEVC Request Clock Mask */
+#define PM_PPCR_ADCIFERCMASK      (1 << 7)  /* Bit 7:  ADCIFE Request Clock Mask */
+#define PM_PPCR_VREGRCMASK        (1 << 8)  /* Bit 8:  VREG Request Clock Mask */
+#define PM_PPCR_FWBGREF           (1 << 9)  /* Bit 9:  Flash Wait BGREF */
+#define PM_PPCR_FWBOD18           (1 << 10) /* Bit 10: Flash Wait BOD18 */
+
+/* Reset Cause Register */
+
+#define PM_RCAUSE_POR                 (1 << 0)  /* Bit 0:  Power-on Reset */
+#define PM_RCAUSE_BOD                 (1 << 1)  /* Bit 1:  Brown-out Reset */
+#define PM_RCAUSE_EXT                 (1 << 2)  /* Bit 2:  External Reset Pin */
+#define PM_RCAUSE_WDT                 (1 << 3)  /* Bit 3:  Watchdog Reset */
+#define PM_RCAUSE_BKUP                (1 << 6)  /* Bit 6:  Backup reset */
+#define PM_RCAUSE_OCDRST              (1 << 8)  /* Bit 8:  OCD Reset */
+#define PM_RCAUSE_POR33               (1 << 10) /* Bit 10: Power-on 3.3v Reset */
+#define PM_RCAUSE_BOD33               (1 << 13) /* Bit 13: Brown-out 3.3v Reset */
+
+/* Wake Cause Register */
+
+#define PM_WCAUSE_TWIS0               (1 << 0)  /* Bit 0:  0 TWI Slave 0 */
+#define PM_WCAUSE_TWIS1               (1 << 1)  /* Bit 1:  1 TWI Slave 1 */
+#define PM_WCAUSE_USBC                (1 << 2)  /* Bit 2:  2 USBC */
+#define PM_WCAUSE_PSOK                (1 << 3)  /* Bit 3:  3 PSOK */
+#define PM_WCAUSE_BOD18               (1 << 4)  /* Bit 4:  4 BOD18 IRQ */
+#define PM_WCAUSE_BOD33               (1 << 5)  /* Bit 5:  5 BOD33 IRQ */
+#define PM_WCAUSE_PICOUART            (1 << 6)  /* Bit 6:  6 PICOUART */
+#define PM_WCAUSE_LCDCA               (1 << 7)  /* Bit 7:  7 LCDCA */
+#define PM_WCAUSE_EIC                 (1 << 16) /* Bit 16: 16 EIC */
+#define PM_WCAUSE_AST                 (1 << 17) /* Bit 17: 17 AST */
+
+/* Asynchronous Wake Up Enable Register Bit-field Definitions */
+
+#define PM_AWEN_TWIS0                 (1 << 0)  /* Bit 0:  TWI Slave 0 */
+#define PM_AWEN_TWIS1                 (1 << 1)  /* Bit 1:  TWI Slave 1 */
+#define PM_AWEN_USBC                  (1 << 2)  /* Bit 2:  USBC */
+#define PM_AWEN_PSOK                  (1 << 3)  /* Bit 3:  PSOK */
+#define PM_AWEN_BOD18                 (1 << 4)  /* Bit 4:  BOD18 IRQ */
+#define PM_AWEN_BOD33                 (1 << 5)  /* Bit 5:  BOD33 IRQ */
+#define PM_AWEN_PICOUART              (1 << 6)  /* Bit 6:  PICOUART */
+#define PM_AWEN_LCDCA                 (1 << 7)  /* Bit 7:  LCDCA */
+
+/* Protection Control Register */
+
+/* Fast Sleep Register */
+#define PM_FASTSLEEP_
+#define PM_FASTSLEEP_OSC              (1 << 0)  /* Bit 0:  Oscillator */
+#define PM_FASTSLEEP_PLL              (1 << 0)  /* Bit 0:  PLL */
+#define PM_FASTSLEEP_FASTRCOSC_SHIFT  (0)       /* Bits 0-9: FASTRCOSC */
+#define PM_FASTSLEEP_FASTRCOSC_MASK   (31 << PM_FASTSLEEP_FASTRCOSC_SHIFT)
+#  define PM_FASTSLEEP_RC80           (1 << PM_FASTSLEEP_FASTRCOSC_SHIFT)
+#  define PM_FASTSLEEP_RCFAST         (2 << PM_FASTSLEEP_FASTRCOSC_SHIFT)
+#  define PM_FASTSLEEP_RC1M           (4 << PM_FASTSLEEP_FASTRCOSC_SHIFT)
+#define PM_FASTSLEEP_DFLL             (1 << 0)  /* Bit 0:  DFLL */
+
+/* Configuration Register */
+
+#define PM_CONFIG_PBA                 (1 << 0)  /* Bit 0:  APBA Implemented */
+#define PM_CONFIG_PBB                 (1 << 1)  /* Bit 1:  APBB Implemented */
+#define PM_CONFIG_PBC                 (1 << 2)  /* Bit 2:  APBC Implemented */
+#define PM_CONFIG_PBD                 (1 << 3)  /* Bit 3:  APBD Implemented */
+#define PM_CONFIG_HSBPEVC             (1 << 7)  /* Bit 7:  HSB PEVC Clock Implemented */
+
+/* Version Register */
+
+#define PM_VERSION_SHIFT              (0)        /* Bits 0-11: Version Number */
+#define PM_VERSION_MASK               (0xfff << PM_VERSION_VERSION_SHIFT)
+#define PM_VERSION_VARIANT_SHIFT      (16)       /* Bits 16-19: Variant Number */
+#define PM_VERSION_VARIANT_MASK       (15 << PM_VERSION_VARIANT_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PM_H */
+
diff --git a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c
new file mode 100644
index 0000000000..cee3e10eea
--- /dev/null
+++ b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c
@@ -0,0 +1,506 @@
+/****************************************************************************
+ * arch/avr/src/sam34/sam4l_clockconfig.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * This file is derived from nuttx/arch/avr/src/at32uc3/at32uc3_clkinit.c
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include "up_arch.h"
+
+#include "up_internal.h"
+#include "chip/sam4l_pm.h"
+#include "chip/sam4l_flashcalw.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+#if defined(SAM_CLOCK_OSC0) || \
+    (defined (SAM_CLOCK_PLL0) && defined(SAM_CLOCK_PLL0_OSC0)) || \
+    (defined (SAM_CLOCK_PLL1) && defined(SAM_CLOCK_PLL1_OSC0))
+#  define NEED_OSC0
+#endif
+
+#if defined(SAM_CLOCK_OSC1) || \
+    (defined (SAM_CLOCK_PLL0) && defined(SAM_CLOCK_PLL0_OSC1)) || \
+    (defined (SAM_CLOCK_PLL1) && defined(SAM_CLOCK_PLL1_OSC1))
+#  define NEED_OSC1
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_enableosc32
+ *
+ * Description:
+ *   Initialiaze the 32KHz oscillaor.  This oscillaor is used by the RTC
+ *   logic to provide the sysem timer.
+ *
+ ****************************************************************************/
+
+#ifdef SAM_CLOCK_OSC32
+static inline void up_enableosc32(void)
+{
+  uint32_t regval;
+
+  /* Select the 32KHz oscillator crystal */
+
+  regval = getreg32(SAM_PM_OSCCTRL32);
+  regval &= ~PM_OSCCTRL32_MODE_MASK;
+  regval |= PM_OSCCTRL32_MODE_XTAL;
+  putreg32(regval, SAM_PM_OSCCTRL32);
+
+  /* Enable the 32-kHz clock */
+
+  regval = getreg32(SAM_PM_OSCCTRL32);
+  regval &= ~PM_OSCCTRL32_STARTUP_MASK;
+  regval |= PM_OSCCTRL32_EN|(SAM_OSC32STARTUP << PM_OSCCTRL32_STARTUP_SHIFT);
+  putreg32(regval, SAM_PM_OSCCTRL32);
+}
+#endif
+
+/****************************************************************************
+ * Name: up_enableosc0
+ *
+ * Description:
+ *   Initialiaze OSC0 settings per the definitions in the board.h file.
+ *
+ ****************************************************************************/
+
+#ifdef NEED_OSC0
+static inline void up_enableosc0(void)
+{
+  uint32_t regval;
+
+  /* Enable OSC0 in the correct crystal mode by setting the mode value in OSCCTRL0 */
+
+  regval  = getreg32(SAM_PM_OSCCTRL0);
+  regval &= ~PM_OSCCTRL_MODE_MASK;
+#if SAM_FOSC0 < 900000
+  regval |= PM_OSCCTRL_MODE_XTALp9;  /* Crystal XIN 0.4-0.9MHz */
+#elif SAM_FOSC0 < 3000000
+  regval |= PM_OSCCTRL_MODE_XTAL3;   /* Crystal XIN 0.9-3.0MHz */
+#elif SAM_FOSC0 < 8000000
+  regval |= PM_OSCCTRL_MODE_XTAL8;   /* Crystal XIN 3.0-8.0MHz */
+#else
+  regval |= PM_OSCCTRL_MODE_XTALHI;  /* Crystal XIN above 8.0MHz */
+#endif
+  putreg32(regval, SAM_PM_OSCCTRL0);
+
+  /* Enable OSC0 using the startup time provided in board.h.  This startup time
+   * is critical and depends on the characteristics of the crystal.
+   */
+
+  regval  = getreg32(SAM_PM_OSCCTRL0);
+  regval &= ~PM_OSCCTRL_STARTUP_MASK;
+  regval |= (SAM_OSC0STARTUP << PM_OSCCTRL_STARTUP_SHIFT);
+  putreg32(regval, SAM_PM_OSCCTRL0);
+
+  /* Enable OSC0 */
+
+  regval = getreg32(SAM_PM_MCCTRL);
+  regval |= PM_MCCTRL_OSC0EN;
+  putreg32(regval, SAM_PM_MCCTRL);
+
+  /* Wait for OSC0 to be ready */
+
+  while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_OSC0RDY) == 0);
+}
+#endif
+
+/****************************************************************************
+ * Name: up_enableosc1
+ *
+ * Description:
+ *   Initialiaze OSC0 settings per the definitions in the board.h file.
+ *
+ ****************************************************************************/
+
+#ifdef NEED_OSC1
+static inline void up_enableosc1(void)
+{
+  uint32_t regval;
+
+  /* Enable OSC1 in the correct crystal mode by setting the mode value in OSCCTRL1 */
+
+  regval  = getreg32(SAM_PM_OSCCTRL1);
+  regval &= ~PM_OSCCTRL_MODE_MASK;
+#if SAM_FOSC1 < 900000
+  regval |= PM_OSCCTRL_MODE_XTALp9;  /* Crystal XIN 0.4-0.9MHz */
+#elif SAM_FOSC1 < 3000000
+  regval |= PM_OSCCTRL_MODE_XTAL3;   /* Crystal XIN 0.9-3.0MHz */
+#elif SAM_FOSC1 < 8000000
+  regval |= PM_OSCCTRL_MODE_XTAL8;   /* Crystal XIN 3.0-8.0MHz */
+#else
+  regval |= PM_OSCCTRL_MODE_XTALHI;  /* Crystal XIN above 8.0MHz */
+#endif
+  putreg32(regval, SAM_PM_OSCCTRL1);
+
+  /* Enable OSC1 using the startup time provided in board.h.  This startup time
+   * is critical and depends on the characteristics of the crystal.
+   */
+
+  regval  = getreg32(SAM_PM_OSCCTRL1);
+  regval &= ~PM_OSCCTRL_STARTUP_MASK;
+  regval |= (SAM_OSC1STARTUP << PM_OSCCTRL_STARTUP_SHIFT);
+  putreg32(regval, SAM_PM_OSCCTRL1);
+
+  /* Enable OSC1 */
+
+  regval = getreg32(SAM_PM_MCCTRL);
+  regval |= PM_MCCTRL_OSC1EN;
+  putreg32(regval, SAM_PM_MCCTRL);
+
+  /* Wait for OSC1 to be ready */
+
+  while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_OSC1RDY) == 0);
+}
+#endif
+
+/****************************************************************************
+ * Name: up_enablepll0
+ *
+ * Description:
+ *   Initialiaze PLL0 settings per the definitions in the board.h file.
+ *
+ ****************************************************************************/
+
+#ifdef SAM_CLOCK_PLL0
+static inline void up_enablepll0(void)
+{
+  /* Setup PLL0 */
+
+  regval = (SAM_PLL0_DIV << PM_PLL_PLLDIV_SHIFT) | (SAM_PLL0_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT)
+
+  /* Select PLL0/1 oscillator */
+
+#if SAM_CLOCK_PLL_OSC1
+  regval |= PM_PLL_PLLOSC;
+#endif
+
+  putreg32(regval, SAM_PM_PLL0);
+
+  /* Set PLL0 options */
+
+  regval = getreg32(SAM_PM_PLL0);
+  regval &= ~PM_PLL_PLLOPT_MASK
+#if SAM_PLL0_FREQ < 160000000
+  regval |= PM_PLL_PLLOPT_VCO;
+#endif
+#if SAM_PLL0_DIV2 != 0
+  regval |= PM_PLL_PLLOPT_XTRADIV;
+#endif
+#if SAM_PLL0_WBWM != 0
+  regval |= PM_PLL_PLLOPT_WBWDIS;
+#endif
+  putreg32(regval, SAM_PM_PLL0)
+
+  /* Enable PLL0 */
+
+  regval = getreg32(SAM_PM_PLL0);
+  regval |= PM_PLL_PLLEN;
+  putreg32(regval, SAM_PM_PLL0)
+
+  /* Wait for PLL0 locked. */
+
+  while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_LOCK0) == 0);
+}
+#endif
+
+/****************************************************************************
+ * Name: up_enablepll1
+ *
+ * Description:
+ *   Initialiaze PLL1 settings per the definitions in the board.h file.
+ *
+ ****************************************************************************/
+
+#ifdef SAM_CLOCK_PLL1
+static inline void up_enablepll1(void)
+{
+  /* Setup PLL1 */
+
+  regval = (SAM_PLL1_DIV << PM_PLL_PLLDIV_SHIFT) | (SAM_PLL1_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT)
+
+  /* Select PLL0/1 oscillator */
+
+#if SAM_CLOCK_PLL_OSC1
+  regval |= PM_PLL_PLLOSC;
+#endif
+
+  putreg32(regval, SAM_PM_PLL1);
+
+  /* Set PLL1 options */
+
+  regval = getreg32(SAM_PM_PLL1);
+  regval &= ~PM_PLL_PLLOPT_MASK
+#if SAM_PLL1_FREQ < 160000000
+  regval |= PM_PLL_PLLOPT_VCO;
+#endif
+#if SAM_PLL1_DIV2 != 0
+  regval |= PM_PLL_PLLOPT_XTRADIV;
+#endif
+#if SAM_PLL1_WBWM != 0
+  regval |= PM_PLL_PLLOPT_WBWDIS;
+#endif
+  putreg32(regval, SAM_PM_PLL1)
+
+  /* Enable PLL1 */
+
+  regval = getreg32(SAM_PM_PLL1);
+  regval |= PM_PLL_PLLEN;
+  putreg32(regval, SAM_PM_PLL1)
+
+  /* Wait for PLL1 locked. */
+
+  while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_LOCK1) == 0);
+}
+#endif
+
+/****************************************************************************
+ * Name: up_clksel
+ *
+ * Description:
+ *   Configure derived clocks.
+ *
+ ****************************************************************************/
+
+static inline void up_clksel(void)
+{
+  uint32_t regval = 0;
+
+#if SAM_CKSEL_CPUDIV != 0
+  regval |= PM_CKSEL_CPUDIV;
+  regval |= (SAM_CKSEL_CPUDIV << PM_CKSEL_CPUSEL_SHIFT)
+#endif
+
+#if SAM_CKSEL_HSBDIV != 0
+  regval |= PM_CKSEL_HSBDIV;
+  regval |= (SAM_CKSEL_HSBDIV << PM_CKSEL_HSBSEL_SHIFT)
+#endif
+
+#if SAM_CKSEL_PBADIV != 0
+  regval |= PM_CKSEL_PBADIV;
+  regval |= (SAM_CKSEL_PBADIV << PM_CKSEL_PBASEL_SHIFT)
+#endif
+
+#if SAM_CKSEL_PBBDIV != 0
+  regval |= PM_CKSEL_PBBDIV;
+  regval |= (SAM_CKSEL_PBBDIV << PM_CKSEL_PBBSEL_SHIFT)
+#endif
+
+  putreg32(regval, SAM_PM_CKSEL);
+
+  /* Wait for CLKRDY */
+
+  while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_CKRDY) == 0);
+}
+
+/****************************************************************************
+ * Name: up_fws
+ *
+ * Description:
+ *   Setup FLASH wait states.
+ *
+ ****************************************************************************/
+
+static void up_fws(uint32_t cpuclock)
+{
+  uint32_t regval;
+
+  regval = getreg32(SAM_FLASHCALW_FCR);
+  if (cpuclock > SAM_FLASHCALW_FWS0_MAXFREQ)
+    {
+      regval |= FLASHCALW_FCR_FWS;
+    }
+  else
+    {
+      regval &= ~FLASHCALW_FCR_FWS;
+    }
+  putreg32(regval, SAM_FLASHCALW_FCR);
+}
+
+/****************************************************************************
+ * Name: up_mainclk
+ *
+ * Description:
+ *   Select the main clock.
+ *
+ ****************************************************************************/
+
+static inline void up_mainclk(uint32_t mcsel)
+{
+  uint32_t regval;
+
+  regval = getreg32(SAM_PM_MCCTRL);
+  regval &= ~PM_MCCTRL_MCSEL_MASK;
+  regval |= mcsel;
+  putreg32(regval, SAM_PM_MCCTRL);
+}
+
+/****************************************************************************
+ * Name: up_usbclock
+ *
+ * Description:
+ *   Setup the USBB GCLK.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBDEV
+static inline void up_usbclock(void)
+{
+  uint32_t regval = 0;
+
+#if defined(SAM_CLOCK_USB_PLL0) || defined(SAM_CLOCK_USB_PLL1)
+  regval |= PM_GCCTRL_PLLSEL;
+#endif
+#if defined(SAM_CLOCK_USB_OSC1) || defined(SAM_CLOCK_USB_PLL1)
+  regval |= PM_GCCTRL_OSCSEL;
+#endif
+#if SAM_CLOCK_USB_DIV > 0
+
+
+  u_avr32_pm_gcctrl.GCCTRL.diven  = diven;
+  u_avr32_pm_gcctrl.GCCTRL.div    = div;
+#endif
+  putreg32(regval, SAM_PM_GCCTRL(SAM_PM_GCLK_USBB))
+
+  /* Enable USB GCLK */
+
+  regval = getreg32(SAM_PM_GCCTRL(SAM_PM_GCLK_USBB))
+  regval |= PM_GCCTRL_CEN;
+  putreg32(regval, SAM_PM_GCCTRL(SAM_PM_GCLK_USBB))
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_clockconfig
+ *
+ * Description:
+ *   Called to initialize the SAM3/4.  This does whatever setup is needed to
+ *   put the SoC in a usable state.  This includes the initialization of
+ *   clocking using the settings in board.h.
+ *
+ ****************************************************************************/
+
+void sam_clockconfig(void)
+{
+#ifdef SAM_CLOCK_OSC32
+  /* Enable the 32KHz oscillator (need by the RTC module) */
+
+  up_enableosc32();
+#endif
+
+#ifdef NEED_OSC0
+  /* Enable OSC0 using the settings in board.h */
+
+  up_enableosc0();
+
+  /* Set up FLASH wait states */
+
+  up_fws(SAM_FOSC0);
+
+  /* Then switch the main clock to OSC0 */
+
+  up_mainclk(PM_MCCTRL_MCSEL_OSC0);
+#endif
+
+#ifdef NEED_OSC1
+  /* Enable OSC1 using the settings in board.h */
+
+  up_enableosc1();
+#endif
+
+#ifdef SAM_CLOCK_PLL0
+  /* Enable PLL0 using the settings in board.h */
+
+  up_enablepll0();
+
+  /* Set up FLASH wait states */
+
+  up_fws(SAM_CPU_CLOCK);
+
+  /* Then switch the main clock to PLL0 */
+
+  up_mainclk(PM_MCCTRL_MCSEL_PLL0);
+#endif
+
+#ifdef SAM_CLOCK_PLL1
+  /* Enable PLL1 using the settings in board.h */
+
+  up_enablepll1();
+#endif
+
+  /* Configure derived clocks */
+
+  up_clksel();
+
+  /* Set up the USBB GCLK */
+
+#ifdef CONFIG_USBDEV
+  void up_usbclock();
+#endif
+}
+
+
+
diff --git a/nuttx/arch/arm/src/sam34/sam_clockconfig.h b/nuttx/arch/arm/src/sam34/sam_clockconfig.h
index 4ed9e6b878..91f692290c 100644
--- a/nuttx/arch/arm/src/sam34/sam_clockconfig.h
+++ b/nuttx/arch/arm/src/sam34/sam_clockconfig.h
@@ -79,10 +79,7 @@ extern "C"
  * Description:
  *   Called to initialize the SAM3/4.  This does whatever setup is needed to put the
  *   SoC in a usable state.  This includes the initialization of clocking using the
- *   settings in board.h.  (After power-on reset, the sam3u is initially running on
- *   a 4MHz internal RC clock).  This function also performs other low-level chip
- *   initialization of the chip including EFC, master clock, IRQ and watchdog
- *   configuration.
+ *   settings in board.h.
  *
  ************************************************************************************/
 
diff --git a/nuttx/mm/README.txt b/nuttx/mm/README.txt
index d2f307849e..de15e0a5da 100644
--- a/nuttx/mm/README.txt
+++ b/nuttx/mm/README.txt
@@ -3,78 +3,110 @@ mm/README.txt
 
 This directory contains the NuttX memory management logic.  This include:
 
-1) The standard memory management functions as prototyped in stdlib.h as
-   specified in the  Base definitions volume of IEEE Std 1003.1-2001.  This
-   include the files:
+1) Standard Memory Management Functions:
 
-   o Standard Interfaces: mm_malloc.c, mm_calloc.c, mm_realloc.c,
+     The standard memory management functions as prototyped in stdlib.h as
+     specified in the  Base definitions volume of IEEE Std 1003.1-2001.  This
+     include the files:
+
+     o Standard Interfaces: mm_malloc.c, mm_calloc.c, mm_realloc.c,
        mm_memalign.c, mm_free.c
-   o Less-Standard Interfaces: mm_zalloc.c, mm_mallinfo.c
-   o Internal Implementation: mm_initialize.c mm_sem.c  mm_addfreechunk.c
+     o Less-Standard Interfaces: mm_zalloc.c, mm_mallinfo.c
+     o Internal Implementation: mm_initialize.c mm_sem.c  mm_addfreechunk.c
        mm_size2ndx.c mm_shrinkchunk.c, mm_internal.h
-   o Build and Configuration files: Kconfig, Makefile
+     o Build and Configuration files: Kconfig, Makefile
 
    Memory Models:
 
-   o Small Memory Model.  If the MCU supports only 16-bit data addressing
-     then the small memory model is automatically used.  The maximum size
-     of the heap is then 64K.  The small memory model can also be forced
-     MCUs with wider addressing by defining CONFIG_SMALL_MEMORY in the
-     NuttX configuration file.
-   o Large Memory Model.  Otherwise, the allocator uses a model that
-     supports a heap of up to 4G.
-
-   This implementation uses a variable length allocator with the following
-   properties:
-
-   o Overhead:  Either 8- or 4-bytes per allocation for large and small
-     models, respectively.
-   o Alignment:  All allocations are aligned to 8- or 4-bytes for large
-     and small models, respectively.
-
-2) Granule Allocator.  A non-standard granule allocator is also available
-   in this directory  The granule allocator allocates memory in units
-   of a fixed sized block ("granule").  Allocations may be aligned to a user-
-   provided address boundary.
-
-   The granule allocator interfaces are defined in nuttx/include/nuttx/gran.h.
-   The granule allocator consists of these files in this directory:
-
-     mm_gran.h, mm_granalloc.c, mm_grancritical.c, mm_granfree.c
-     mm_graninit.c
-
-   The granule allocator is not used anywhere within the base NuttX code
-   as of this writing.  The intent of the granule allocator is to provide
-   a tool to support platform-specific management of aligned DMA memory.
-
-   NOTE: Because each granule may be aligned and each allocation is in
-   units of the granule size, selection of the granule size is important:
-   Larger granules will give better performance and less overhead but more
-   losses of memory due to quantization waste.  Additional memory waste
-   can occur from alignment;  Of course, heap alignment should no be
-   used unless (a) you are using the granule allocator to manage DMA memory
-   and (b) your hardware has specific memory alignment requirements.
-
-   The current implementation also restricts the maximum allocation size
-   to 32 granules.  That restriction could be eliminated with some
-   additional coding effort, but currently requires larger granule
-   sizes for larger allocations.
-
-  Geneneral Usage Example.  This is an example using the GCC section
-  attribute to position a DMA heap in memory (logic in the linker script
-  would assign the section .dmaheap to the DMA memory.
- 
-    FAR uint32_t g_dmaheap[DMAHEAP_SIZE] __attribute__((section(.dmaheap)));
- 
-  The heap is created by calling gran_initialize.  Here the granual size
-  is set to 64 bytes and the alignment to 16 bytes:
- 
-    GRAN_HANDLE handle = gran_initialize(g_dmaheap, DMAHEAP_SIZE, 6, 4);
- 
-  Then the GRAN_HANDLE can be used to allocate memory (There is no
-  GRAN_HANDLE if CONFIG_GRAN_SINGLE=y):
- 
-    FAR uint8_t *dma_memory = (FAR uint8_t *)gran_alloc(handle, 47);
- 
-  The actual memory allocates will be 64 byte (wasting 17 bytes) and
-  will be aligned at least to (1 << log2align).
+     o Small Memory Model.  If the MCU supports only 16-bit data addressing
+       then the small memory model is automatically used.  The maximum size
+       of the heap is then 64K.  The small memory model can also be forced
+       MCUs with wider addressing by defining CONFIG_SMALL_MEMORY in the
+       NuttX configuration file.
+     o Large Memory Model.  Otherwise, the allocator uses a model that
+       supports a heap of up to 4G.
+
+     This implementation uses a variable length allocator with the following
+     properties:
+
+     o Overhead:  Either 8- or 4-bytes per allocation for large and small
+       models, respectively.
+     o Alignment:  All allocations are aligned to 8- or 4-bytes for large
+       and small models, respectively.
+
+   Multiple Heaps:
+
+     This allocator can be used to manage multiple heaps (albeit with some
+     non-standard interfaces).  A heap is represented by struct mm_heap_s
+     as defined in the file include/nuttx/mm.h.  To create another heap
+     instance, you would allocate a heap structure, most likely statically
+     in memory:
+
+       include 
+       static struct mm_heap_s g_myheap;
+
+     Then initialize the heap using:
+
+       mm_initialize(&g_myheap, myheap_start, myheap_size);
+
+     Where mm_initialize() and all related interfaces are prototyped in the
+     header file include/nuttx/mm.h.
+
+     After the new heap instance has been initialized, it can then be used
+     with these almost familiar interfaces: mm_malloc(), mm_realloc(), mm_free(),
+     etc.  These are 'almost familiar' because they are analogous of the
+     standard malloc(), realloc(), free(), etc. except that they expect a
+     reference to the initialized heap structure as the first parameter.
+
+     In fact, the standard malloc(), realloc(), free() use this same mechanism,
+     but with a global heap structure called g_mmheap.
+
+2) Granule Allocator.
+
+     A non-standard granule allocator is also available in this directory  The
+     granule allocator allocates memory in units of a fixed sized block ("granule").
+     Allocations may be aligned to a user-provided address boundary.
+
+     The granule allocator interfaces are defined in nuttx/include/nuttx/gran.h.
+     The granule allocator consists of these files in this directory:
+
+       mm_gran.h, mm_granalloc.c, mm_grancritical.c, mm_granfree.c
+       mm_graninit.c
+
+     The granule allocator is not used anywhere within the base NuttX code
+     as of this writing.  The intent of the granule allocator is to provide
+     a tool to support platform-specific management of aligned DMA memory.
+
+     NOTE: Because each granule may be aligned and each allocation is in
+     units of the granule size, selection of the granule size is important:
+     Larger granules will give better performance and less overhead but more
+     losses of memory due to quantization waste.  Additional memory waste
+     can occur from alignment;  Of course, heap alignment should no be
+     used unless (a) you are using the granule allocator to manage DMA memory
+     and (b) your hardware has specific memory alignment requirements.
+
+     The current implementation also restricts the maximum allocation size
+     to 32 granules.  That restriction could be eliminated with some
+     additional coding effort, but currently requires larger granule
+     sizes for larger allocations.
+
+   General Usage Example.
+
+     This is an example using the GCC section attribute to position a DMA
+     heap in memory (logic in the linker script would assign the section
+     .dmaheap to the DMA memory.
+
+        FAR uint32_t g_dmaheap[DMAHEAP_SIZE] __attribute__((section(.dmaheap)));
+
+     The heap is created by calling gran_initialize.  Here the granule size
+     is set to 64 bytes and the alignment to 16 bytes:
+
+       GRAN_HANDLE handle = gran_initialize(g_dmaheap, DMAHEAP_SIZE, 6, 4);
+
+     Then the GRAN_HANDLE can be used to allocate memory (There is no
+     GRAN_HANDLE if CONFIG_GRAN_SINGLE=y):
+
+       FAR uint8_t *dma_memory = (FAR uint8_t *)gran_alloc(handle, 47);
+
+     The actual memory allocates will be 64 byte (wasting 17 bytes) and
+     will be aligned at least to (1 << log2align).

From a64d048bd159d1c21859a45954c953c5ce7ff6c2 Mon Sep 17 00:00:00 2001
From: Gregory Nutt 
Date: Wed, 5 Jun 2013 16:41:52 -0600
Subject: [PATCH 35/41] Updates to SAM4L clocking. Still not finished

---
 nuttx/arch/arm/src/sam34/Kconfig             |   5 +
 nuttx/arch/arm/src/sam34/chip/sam4l_pm.h     |  10 +-
 nuttx/arch/arm/src/sam34/sam4l_clockconfig.c | 320 ++++++++++++++++---
 nuttx/arch/arm/src/sam34/sam_clockconfig.h   |  84 ++++-
 4 files changed, 362 insertions(+), 57 deletions(-)

diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig
index 3991798a70..b26dec6598 100644
--- a/nuttx/arch/arm/src/sam34/Kconfig
+++ b/nuttx/arch/arm/src/sam34/Kconfig
@@ -141,6 +141,11 @@ config ARCH_CHIP_SAM4S
 
 menu "AT91SAM3 Peripheral Support"
 
+config SAM_PICOCACHE
+	bool "PICOCACHE"
+	depends on ARCH_CHIP_SAM4L
+	default y
+
 config SAM34_DMA
 	bool "DMA"
 	default n
diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h b/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h
index c314e8efe0..16941397c2 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h
@@ -132,13 +132,15 @@
 /* CPU Clock Select Register Bit-field Definitions */
 
 #define PM_CPUSEL_SHIFT            (0)       /* Bits 0-2: CPU Clock Select */
-#define PM_CPUSEL_MASK             (7 << PM_CPUSEL_CPUSEL_SHIFT)
-#define PM_CPUSEL_CPUDIV           (1 << 7)  /* Bit 7:  CPU Division */
+#define PM_CPUSEL_MASK             (7 << PM_CPUSEL_SHIFT)
+#  define PM_CPUSEL(n)             ((n) << PM_CPUSEL_SHIFT)
+#define PM_CPUSEL_DIV              (1 << 7)  /* Bit 7:  CPU Division */
 
 /* PBA/PBB/PBC/PBD Clock Select Register Bit-field Definitions */
 
 #define PM_PBSEL_SHIFT             (0)       /* Bits 0-2: PBx Clock Select */
-#define PM_PBSEL_MASK              (7 << PM_PBASEL_SHIFT)
+#define PM_PBSEL_MASK              (7 << PM_PBSEL_SHIFT)
+#  define PM_PBSEL(n)              ((n) << PM_PBSEL_SHIFT)
 #define PM_PBSEL_DIV               (1 << 7)  /* Bit 7: PBx Division */
 
 /* CPU Mask Register Bit-field Definitions */
@@ -228,8 +230,10 @@
 
 #define PM_UNLOCK_ADDR_SHIFT       (0)       /* Bits 0-9: Unlock Address */
 #define PM_UNLOCK_ADDR_MASK        (0x3ff << PM_UNLOCK_ADDR_SHIFT)
+#  define PM_UNLOCK_ADDR(n)        ((n) << PM_UNLOCK_ADDR_SHIFT)
 #define PM_UNLOCK_KEY_SHIFT        (24)      /* Bits 24-31: Unlock Key */
 #define PM_UNLOCK_KEY_MASK         (0xff << PM_UNLOCK_KEY_SHIFT)
+#  define PM_UNLOCK_KEY(n)         ((n) << PM_UNLOCK_KEY_SHIFT)
 
 /* Interrupt Enable Register Bit-field Definitions */
 /* Interrupt Disable Register Bit-field Definitions */
diff --git a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c
index cee3e10eea..1bd4dbfedc 100644
--- a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c
+++ b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c
@@ -41,6 +41,7 @@
 
 #include 
 
+#include 
 #include 
 
 #include "up_arch.h"
@@ -49,6 +50,8 @@
 #include "chip/sam4l_pm.h"
 #include "chip/sam4l_flashcalw.h"
 
+#include "sam_clockconfig.h"
+
 /****************************************************************************
  * Private Definitions
  ****************************************************************************/
@@ -86,16 +89,41 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: up_enableosc32
+ * Name: sam_picocache
+ *
+ * Description:
+ *   Initialiaze the PICOCACHE.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAM_PICOCACHE
+static inline void sam_picocache(void)
+{
+  /* Enable clocking to the PICOCACHE */
+
+  sam_hsb_enableperipheral(PM_HSBMASK_HRAMC1);
+  sam_pbb_enableperipheral(PM_PBBMASK_HRAMC1);
+
+  /* Enable the PICOCACHE and wait for it to become ready */
+
+  putreg32(PICOCACHE_CTRL_CEN, SAM_PICOCACHE_CTRL);
+  while ((getreg32(SAM_PICOCACHE_SR) & PICOCACHE_SR_CSTS) == 0);
+}
+#else
+#  define sam_picocache()
+#endif
+
+/****************************************************************************
+ * Name: sam_enableosc32
  *
  * Description:
- *   Initialiaze the 32KHz oscillaor.  This oscillaor is used by the RTC
+ *   Initialiaze the 32KHz oscillator.  This oscillator is used by the RTC
  *   logic to provide the sysem timer.
  *
  ****************************************************************************/
 
 #ifdef SAM_CLOCK_OSC32
-static inline void up_enableosc32(void)
+static inline void sam_enableosc32(void)
 {
   uint32_t regval;
 
@@ -116,7 +144,7 @@ static inline void up_enableosc32(void)
 #endif
 
 /****************************************************************************
- * Name: up_enableosc0
+ * Name: sam_enableosc0
  *
  * Description:
  *   Initialiaze OSC0 settings per the definitions in the board.h file.
@@ -124,7 +152,7 @@ static inline void up_enableosc32(void)
  ****************************************************************************/
 
 #ifdef NEED_OSC0
-static inline void up_enableosc0(void)
+static inline void sam_enableosc0(void)
 {
   uint32_t regval;
 
@@ -165,7 +193,7 @@ static inline void up_enableosc0(void)
 #endif
 
 /****************************************************************************
- * Name: up_enableosc1
+ * Name: sam_enableosc1
  *
  * Description:
  *   Initialiaze OSC0 settings per the definitions in the board.h file.
@@ -173,7 +201,7 @@ static inline void up_enableosc0(void)
  ****************************************************************************/
 
 #ifdef NEED_OSC1
-static inline void up_enableosc1(void)
+static inline void sam_enableosc1(void)
 {
   uint32_t regval;
 
@@ -214,7 +242,7 @@ static inline void up_enableosc1(void)
 #endif
 
 /****************************************************************************
- * Name: up_enablepll0
+ * Name: sam_enablepll0
  *
  * Description:
  *   Initialiaze PLL0 settings per the definitions in the board.h file.
@@ -222,7 +250,7 @@ static inline void up_enableosc1(void)
  ****************************************************************************/
 
 #ifdef SAM_CLOCK_PLL0
-static inline void up_enablepll0(void)
+static inline void sam_enablepll0(void)
 {
   /* Setup PLL0 */
 
@@ -264,7 +292,7 @@ static inline void up_enablepll0(void)
 #endif
 
 /****************************************************************************
- * Name: up_enablepll1
+ * Name: sam_enablepll1
  *
  * Description:
  *   Initialiaze PLL1 settings per the definitions in the board.h file.
@@ -272,7 +300,7 @@ static inline void up_enablepll0(void)
  ****************************************************************************/
 
 #ifdef SAM_CLOCK_PLL1
-static inline void up_enablepll1(void)
+static inline void sam_enablepll1(void)
 {
   /* Setup PLL1 */
 
@@ -314,53 +342,84 @@ static inline void up_enablepll1(void)
 #endif
 
 /****************************************************************************
- * Name: up_clksel
+ * Name: sam_setdividers
  *
  * Description:
  *   Configure derived clocks.
  *
  ****************************************************************************/
 
-static inline void up_clksel(void)
+static inline void sam_setdividers(uint32_t cpudiv, uint32_t pbadiv,
+                                   uint32_t pbbdiv, uint32_t pbcdiv,
+                                   uint32_t pbddiv)
 {
-  uint32_t regval = 0;
+  irqstate_t flags;
+  uint32_t cpusel = 0;
+  uint32_t pbasel = 0;
+  uint32_t pbbsel = 0;
+  uint32_t pbcsel = 0;
+  uint32_t pbdsel = 0;
 
-#if SAM_CKSEL_CPUDIV != 0
-  regval |= PM_CKSEL_CPUDIV;
-  regval |= (SAM_CKSEL_CPUDIV << PM_CKSEL_CPUSEL_SHIFT)
-#endif
+  /* Get the register setting for each divider value */
 
-#if SAM_CKSEL_HSBDIV != 0
-  regval |= PM_CKSEL_HSBDIV;
-  regval |= (SAM_CKSEL_HSBDIV << PM_CKSEL_HSBSEL_SHIFT)
-#endif
+  if (cpudiv > 0)
+    {
+      cpusel = (PM_CPUSEL(cpudiv - 1)) | PM_CPUSEL_DIV;
+    }
 
-#if SAM_CKSEL_PBADIV != 0
-  regval |= PM_CKSEL_PBADIV;
-  regval |= (SAM_CKSEL_PBADIV << PM_CKSEL_PBASEL_SHIFT)
-#endif
+  if (pbadiv > 0)
+    {
+      pbasel = (PM_PBSEL(pbadiv - 1)) | PM_PBSEL_DIV;
+    }
 
-#if SAM_CKSEL_PBBDIV != 0
-  regval |= PM_CKSEL_PBBDIV;
-  regval |= (SAM_CKSEL_PBBDIV << PM_CKSEL_PBBSEL_SHIFT)
-#endif
+  if (pbbdiv > 0)
+    {
+      pbbsel = (PM_PBSEL(pbbdiv - 1)) | PM_PBSEL_DIV;
+    }
+
+  if (pbcdiv > 0)
+    {
+      pbcsel = (PM_PBSEL(pbcdiv - 1)) | PM_PBSEL_DIV;
+    }
+
+  if (pbddiv > 0)
+    {
+      pbdsel = (PM_PBSEL(pbddiv - 1)) | PM_PBSEL_DIV;
+    }
 
-  putreg32(regval, SAM_PM_CKSEL);
+  /* Then set the divider values. The following operations need to be atomic
+   * for the unlock-write sequeuences.
+   */
+
+  flags = irqsave();
+
+  putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUSEL_OFFSET), SAM_PM_UNLOCK);
+  putreg32(cpusel, SAM_PM_CPUSEL);
+
+  putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBASEL_OFFSET), SAM_PM_UNLOCK);
+  putreg32(pbasel, SAM_PM_PBASEL);
 
-  /* Wait for CLKRDY */
+  putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBSEL_OFFSET), SAM_PM_UNLOCK);
+  putreg32(pbbsel, SAM_PM_PBBSEL);
 
-  while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_CKRDY) == 0);
+  putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCSEL_OFFSET), SAM_PM_UNLOCK);
+  putreg32(pbcsel, SAM_PM_PBCSEL);
+
+  putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDSEL_OFFSET), SAM_PM_UNLOCK);
+  putreg32(pbdsel, SAM_PM_PBDSEL);
+
+  irqrestore(flags);
 }
 
 /****************************************************************************
- * Name: up_fws
+ * Name: sam_fws
  *
  * Description:
  *   Setup FLASH wait states.
  *
  ****************************************************************************/
 
-static void up_fws(uint32_t cpuclock)
+static void sam_fws(uint32_t cpuclock)
 {
   uint32_t regval;
 
@@ -373,18 +432,19 @@ static void up_fws(uint32_t cpuclock)
     {
       regval &= ~FLASHCALW_FCR_FWS;
     }
+
   putreg32(regval, SAM_FLASHCALW_FCR);
 }
 
 /****************************************************************************
- * Name: up_mainclk
+ * Name: sam_mainclk
  *
  * Description:
  *   Select the main clock.
  *
  ****************************************************************************/
 
-static inline void up_mainclk(uint32_t mcsel)
+static inline void sam_mainclk(uint32_t mcsel)
 {
   uint32_t regval;
 
@@ -395,7 +455,7 @@ static inline void up_mainclk(uint32_t mcsel)
 }
 
 /****************************************************************************
- * Name: up_usbclock
+ * Name: sam_usbclock
  *
  * Description:
  *   Setup the USBB GCLK.
@@ -403,7 +463,7 @@ static inline void up_mainclk(uint32_t mcsel)
  ****************************************************************************/
 
 #ifdef CONFIG_USBDEV
-static inline void up_usbclock(void)
+static inline void sam_usbclock(void)
 {
   uint32_t regval = 0;
 
@@ -445,62 +505,216 @@ static inline void up_usbclock(void)
 
 void sam_clockconfig(void)
 {
+  /* Enable clocking to the PICOCACHE */
+
+  sam_picocache();
+
+  /* Configure dividers derived clocks.  These divider definitions must be
+   * provided in the board.h header file.
+   */
+
+  sam_setdividers(BOARD_SYSCLK_CPU_DIV, BOARD_SYSCLK_PBA_DIV,
+                  BOARD_SYSCLK_PBB_DIV, BOARD_SYSCLK_PBC_DIV,
+                  BOARD_SYSCLK_PBD_DIV);
+
 #ifdef SAM_CLOCK_OSC32
   /* Enable the 32KHz oscillator (need by the RTC module) */
 
-  up_enableosc32();
+  sam_enableosc32();
 #endif
 
 #ifdef NEED_OSC0
   /* Enable OSC0 using the settings in board.h */
 
-  up_enableosc0();
+  sam_enableosc0();
 
   /* Set up FLASH wait states */
 
-  up_fws(SAM_FOSC0);
+  sam_fws(SAM_FOSC0);
 
   /* Then switch the main clock to OSC0 */
 
-  up_mainclk(PM_MCCTRL_MCSEL_OSC0);
+  sam_mainclk(PM_MCCTRL_MCSEL_OSC0);
 #endif
 
 #ifdef NEED_OSC1
   /* Enable OSC1 using the settings in board.h */
 
-  up_enableosc1();
+  sam_enableosc1();
 #endif
 
 #ifdef SAM_CLOCK_PLL0
   /* Enable PLL0 using the settings in board.h */
 
-  up_enablepll0();
+  sam_enablepll0();
 
   /* Set up FLASH wait states */
 
-  up_fws(SAM_CPU_CLOCK);
+  sam_fws(SAM_CPU_CLOCK);
 
   /* Then switch the main clock to PLL0 */
 
-  up_mainclk(PM_MCCTRL_MCSEL_PLL0);
+  sam_mainclk(PM_MCCTRL_MCSEL_PLL0);
 #endif
 
 #ifdef SAM_CLOCK_PLL1
   /* Enable PLL1 using the settings in board.h */
 
-  up_enablepll1();
+  sam_enablepll1();
 #endif
 
-  /* Configure derived clocks */
-
-  up_clksel();
-
   /* Set up the USBB GCLK */
 
 #ifdef CONFIG_USBDEV
-  void up_usbclock();
+  void sam_usbclock();
 #endif
 }
 
+/****************************************************************************
+ * Name: sam_modifyperipheral
+ *
+ * Description:
+ *   This is a convenience function that is intended to be used to enable
+ *   or disable peripheral module clocking.
+ *
+ ****************************************************************************/
+
+void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Make sure that the following operations are atomic */
+
+  flags = irqsave();
+
+  /* Enable/disabling clocking */
+
+  regval  = getreg32(regaddr);
+  regval &= ~clrbits;
+  regval |= setbits;
+  putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE), SAM_PM_UNLOCK);
+  putreg32(regval, regaddr);
+
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: sam_pba_enableperipheral
+ *
+ * Description:
+ *   This is a convenience function to enable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+void sam_pba_enableperipheral(uint32_t bitset)
+{
+  irqstate_t flags;
+
+  /* The following operations must be atomic */
+
+  flags = irqsave();
+
+  /* Enable the APBA bridge if necessary */
+
+  if (getreg32(SAM_PM_PBAMASK) == 0)
+    {
+      sam_hsb_enableperipheral(PM_HSBMASK_APBA);
+    }
+
+  irqrestore(flags);
+
+  /* Enable the module */
+
+  sam_enableperipheral(SAM_PM_PBAMASK, bitset);
+}
+
+/****************************************************************************
+ * Name: sam_pba_disableperipheral
+ *
+ * Description:
+ *   This is a convenience function to disable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+void sam_pba_disableperipheral(uint32_t bitset)
+{
+  irqstate_t flags;
+
+  /* Disable clocking to the module */
+
+  sam_disableperipheral(SAM_PM_PBAMASK, bitset);
+
+  /* Disable the APBA bridge if possible */
+
+  flags = irqsave();
+
+  if (getreg32(SAM_PM_PBAMASK) == 0)
+    {
+      sam_hsb_disableperipheral(PM_HSBMASK_APBA);
+    }
+
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: sam_pbb_enableperipheral
+ *
+ * Description:
+ *   This is a convenience function to enable a peripheral on the APBB
+ *   bridge.
+ *
+ ****************************************************************************/
+
+void sam_pbb_enableperipheral(uint32_t bitset)
+{
+  irqstate_t flags;
+
+  /* The following operations must be atomic */
+
+  flags = irqsave();
+
+  /* Enable the APBB bridge if necessary */
+
+  if (getreg32(SAM_PM_PBBMASK) == 0)
+    {
+      sam_hsb_enableperipheral(PM_HSBMASK_APBB);
+    }
+
+  irqrestore(flags);
+
+  /* Enable the module */
+
+  sam_enableperipheral(SAM_PM_PBBMASK, bitset);
+}
+
+/****************************************************************************
+ * Name: sam_pbb_disableperipheral
+ *
+ * Description:
+ *   This is a convenience function to disable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+void sam_pbb_disableperipheral(uint32_t bitset)
+{
+  irqstate_t flags;
+
+  /* Disable clocking to the peripheral module */
+
+  sam_disableperipheral(SAM_PM_PBBMASK, bitset);
+
+  /* Disable the APBB bridge if possible */
 
+  flags = irqsave();
 
+  if (getreg32(SAM_PM_PBBMASK) == 0)
+    {
+      sam_hsb_disableperipheral(PM_HSBMASK_APBB);
+    }
+
+  irqrestore(flags);
+}
diff --git a/nuttx/arch/arm/src/sam34/sam_clockconfig.h b/nuttx/arch/arm/src/sam34/sam_clockconfig.h
index 91f692290c..194e9a9fc3 100644
--- a/nuttx/arch/arm/src/sam34/sam_clockconfig.h
+++ b/nuttx/arch/arm/src/sam34/sam_clockconfig.h
@@ -43,9 +43,26 @@
 #include 
 
 /************************************************************************************
- * Definitions
+ * Pre-processor Definitions
  ************************************************************************************/
 
+/* SAM4L helper functions */
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+#  define sam_enableperipheral(a,s)    sam_modifyperipheral(a,0,s)
+#  define sam_disableperipheral(a,s)   sam_modifyperipheral(a,s,0)
+
+#  define sam_cpu_enableperipheral(s)  sam_enableperipheral(SAM_PM_CPUMASK,s)
+#  define sam_hsb_enableperipheral(s)  sam_enableperipheral(SAM_PM_HSBMASK,s)
+#  define sam_pbc_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBCMASK,s)
+#  define sam_pbd_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBDMASK,s)
+
+#  define sam_cpu_disableperipheral(s) sam_disableperipheral(SAM_PM_CPUMASK,s)
+#  define sam_hsb_disableperipheral(s) sam_disableperipheral(SAM_PM_HSBMASK,s)
+#  define sam_pbc_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBCMASK,s)
+#  define sam_pbd_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBDMASK,s)
+#endif
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/
@@ -85,6 +102,71 @@ extern "C"
 
 void sam_clockconfig(void);
 
+/****************************************************************************
+ * Name: sam_modifyperipheral
+ *
+ * Description:
+ *   This is a convenience function that is intended to be used to enable
+ *   or disable module clocking.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits);
+#endif
+
+/****************************************************************************
+ * Name: sam_pba_enableperipheral
+ *
+ * Description:
+ *   This is a convenience function to enable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_pba_enableperipheral(uint32_t bitset);
+#endif
+
+/****************************************************************************
+ * Name: sam_pba_disableperipheral
+ *
+ * Description:
+ *   This is a convenience function to disable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_pba_disableperipheral(uint32_t bitset);
+#endif
+
+/****************************************************************************
+ * Name: sam_pbb_enableperipheral
+ *
+ * Description:
+ *   This is a convenience function to enable a peripheral on the APBB
+ *   bridge.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_pbb_enableperipheral(uint32_t bitset);
+#endif
+
+/****************************************************************************
+ * Name: sam_pbb_disableperipheral
+ *
+ * Description:
+ *   This is a convenience function to disable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_pbb_disableperipheral(uint32_t bitset);
+#endif
+
 #undef EXTERN
 #if defined(__cplusplus)
 }

From 303cf6c26e2f96c1909ca977b8ce86b0b761b444 Mon Sep 17 00:00:00 2001
From: Gregory Nutt 
Date: Wed, 5 Jun 2013 18:48:30 -0600
Subject: [PATCH 36/41] Move SAM4L peripheral clock logic to a separate file

---
 nuttx/ChangeLog                              |   3 +
 nuttx/arch/arm/src/sam34/Make.defs           |   2 +-
 nuttx/arch/arm/src/sam34/chip/sam4l_pm.h     |  12 +
 nuttx/arch/arm/src/sam34/sam4l_clockconfig.c | 149 --------
 nuttx/arch/arm/src/sam34/sam4l_periphclks.c  | 272 +++++++++++++++
 nuttx/arch/arm/src/sam34/sam4l_periphclks.h  | 349 +++++++++++++++++++
 nuttx/arch/arm/src/sam34/sam_clockconfig.h   |  82 -----
 7 files changed, 637 insertions(+), 232 deletions(-)
 create mode 100644 nuttx/arch/arm/src/sam34/sam4l_periphclks.c
 create mode 100644 nuttx/arch/arm/src/sam34/sam4l_periphclks.h

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index a332b7c21d..0141d60c6f 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -4908,3 +4908,6 @@
 	  Power Management.  Leveraged from AVR32 (2013-6-5).
 	* arch/arm/src/sam34/sarm4l_clockconfig.c:  SAM4L clock configuration
 	  logic (leveraged from AVR32).
+	* nuttx/arch/arm/src/sam34/sam4l_periphclks.c/h:  Add common
+	  logic to enabled/disable SAM4L peripheral clocking (2013-6-5).
+
diff --git a/nuttx/arch/arm/src/sam34/Make.defs b/nuttx/arch/arm/src/sam34/Make.defs
index 182d4e5bfd..6f192960fc 100644
--- a/nuttx/arch/arm/src/sam34/Make.defs
+++ b/nuttx/arch/arm/src/sam34/Make.defs
@@ -83,7 +83,7 @@ CHIP_CSRCS += sam_serial.c sam_start.c sam_timerisr.c
 # Configuration-dependent SAM3/4 files
 
 ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y)
-CHIP_CSRCS += sam4l_clockconfig.c sam4l_gpio.c
+CHIP_CSRCS += sam4l_clockconfig.c sam4l_periphclks.c sam4l_gpio.c
 else
 CHIP_CSRCS += sam3u_clockconfig.c sam3u_gpio.c
 endif
diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h b/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h
index 16941397c2..ba78b3a957 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h
@@ -186,6 +186,14 @@
 #define PM_PBAMASK_TWIM3           (1 << 22) /* Bit 22: TWIM3 */
 #define PM_PBAMASK_LCDCA           (1 << 23) /* Bit 23: LCDCA*/
 
+/* These are the PBMA peripherals that use divided clocks enabled in the
+ * PBADIVMASK register.
+ */
+
+#define PM_PBAMASK_TIMERS (PM_PBAMASK_TC0 | PM_PBAMASK_TC1)
+#define PM_PBAMASK_UARTS  (PM_PBAMASK_USART0 | PM_PBAMASK_USART1 | \
+                           PM_PBAMASK_USART2 | PM_PBAMASK_USART3)
+
 /* PBB Mask Register Bit-field Definitions */
 
 #define PM_PBBMASK_FLASHCALW       (1 << 0)  /* Bit 0:  FLASHCALW */
@@ -221,6 +229,10 @@
 #define PM_PBADIVMASK_TIMER_CLOCK4 (1 << 4) /* Bit 4: TIMER_CLOCK4 (TC0-1) */
 #define PM_PBADIVMASK_TIMER_CLOCK5 (1 << 6) /* Bit 5: TIMER_CLOCK5 (TC0-1) */
 
+#define PM_PBADIVMASK_TIMER_CLOCKS \
+  (PM_PBADIVMASK_TIMER_CLOCK2 | PM_PBADIVMASK_TIMER_CLOCK3 | \
+   PM_PBADIVMASK_TIMER_CLOCK4 | PM_PBADIVMASK_TIMER_CLOCK5)
+
 /* Clock Failure Detector Control */
 
 #define PM_CFDCTRL_CFDEN           (1 << 0)  /* Bit 0:  Clock Failure Detection Enable */
diff --git a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c
index 1bd4dbfedc..2857c7fb10 100644
--- a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c
+++ b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c
@@ -569,152 +569,3 @@ void sam_clockconfig(void)
   void sam_usbclock();
 #endif
 }
-
-/****************************************************************************
- * Name: sam_modifyperipheral
- *
- * Description:
- *   This is a convenience function that is intended to be used to enable
- *   or disable peripheral module clocking.
- *
- ****************************************************************************/
-
-void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits)
-{
-  irqstate_t flags;
-  uint32_t regval;
-
-  /* Make sure that the following operations are atomic */
-
-  flags = irqsave();
-
-  /* Enable/disabling clocking */
-
-  regval  = getreg32(regaddr);
-  regval &= ~clrbits;
-  regval |= setbits;
-  putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE), SAM_PM_UNLOCK);
-  putreg32(regval, regaddr);
-
-  irqrestore(flags);
-}
-
-/****************************************************************************
- * Name: sam_pba_enableperipheral
- *
- * Description:
- *   This is a convenience function to enable a peripheral on the APBA
- *   bridge.
- *
- ****************************************************************************/
-
-void sam_pba_enableperipheral(uint32_t bitset)
-{
-  irqstate_t flags;
-
-  /* The following operations must be atomic */
-
-  flags = irqsave();
-
-  /* Enable the APBA bridge if necessary */
-
-  if (getreg32(SAM_PM_PBAMASK) == 0)
-    {
-      sam_hsb_enableperipheral(PM_HSBMASK_APBA);
-    }
-
-  irqrestore(flags);
-
-  /* Enable the module */
-
-  sam_enableperipheral(SAM_PM_PBAMASK, bitset);
-}
-
-/****************************************************************************
- * Name: sam_pba_disableperipheral
- *
- * Description:
- *   This is a convenience function to disable a peripheral on the APBA
- *   bridge.
- *
- ****************************************************************************/
-
-void sam_pba_disableperipheral(uint32_t bitset)
-{
-  irqstate_t flags;
-
-  /* Disable clocking to the module */
-
-  sam_disableperipheral(SAM_PM_PBAMASK, bitset);
-
-  /* Disable the APBA bridge if possible */
-
-  flags = irqsave();
-
-  if (getreg32(SAM_PM_PBAMASK) == 0)
-    {
-      sam_hsb_disableperipheral(PM_HSBMASK_APBA);
-    }
-
-  irqrestore(flags);
-}
-
-/****************************************************************************
- * Name: sam_pbb_enableperipheral
- *
- * Description:
- *   This is a convenience function to enable a peripheral on the APBB
- *   bridge.
- *
- ****************************************************************************/
-
-void sam_pbb_enableperipheral(uint32_t bitset)
-{
-  irqstate_t flags;
-
-  /* The following operations must be atomic */
-
-  flags = irqsave();
-
-  /* Enable the APBB bridge if necessary */
-
-  if (getreg32(SAM_PM_PBBMASK) == 0)
-    {
-      sam_hsb_enableperipheral(PM_HSBMASK_APBB);
-    }
-
-  irqrestore(flags);
-
-  /* Enable the module */
-
-  sam_enableperipheral(SAM_PM_PBBMASK, bitset);
-}
-
-/****************************************************************************
- * Name: sam_pbb_disableperipheral
- *
- * Description:
- *   This is a convenience function to disable a peripheral on the APBA
- *   bridge.
- *
- ****************************************************************************/
-
-void sam_pbb_disableperipheral(uint32_t bitset)
-{
-  irqstate_t flags;
-
-  /* Disable clocking to the peripheral module */
-
-  sam_disableperipheral(SAM_PM_PBBMASK, bitset);
-
-  /* Disable the APBB bridge if possible */
-
-  flags = irqsave();
-
-  if (getreg32(SAM_PM_PBBMASK) == 0)
-    {
-      sam_hsb_disableperipheral(PM_HSBMASK_APBB);
-    }
-
-  irqrestore(flags);
-}
diff --git a/nuttx/arch/arm/src/sam34/sam4l_periphclks.c b/nuttx/arch/arm/src/sam34/sam4l_periphclks.c
new file mode 100644
index 0000000000..abd766695a
--- /dev/null
+++ b/nuttx/arch/arm/src/sam34/sam4l_periphclks.c
@@ -0,0 +1,272 @@
+/****************************************************************************
+ * arch/avr/src/sam34/sam4l_periphclks.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * This file is derived from nuttx/arch/avr/src/at32uc3/at32uc3_clkinit.c
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include "up_arch.h"
+
+#include "up_internal.h"
+#include "chip/sam4l_pm.h"
+
+#include "sam4l_periphclks.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_modifyperipheral
+ *
+ * Description:
+ *   This is a convenience function that is intended to be used to enable
+ *   or disable peripheral module clocking.
+ *
+ ****************************************************************************/
+
+void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Make sure that the following operations are atomic */
+
+  flags = irqsave();
+
+  /* Enable/disabling clocking */
+
+  regval  = getreg32(regaddr);
+  regval &= ~clrbits;
+  regval |= setbits;
+  putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE), SAM_PM_UNLOCK);
+  putreg32(regval, regaddr);
+
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: sam_pba_modifydivmask
+ *
+ * Description:
+ *   This is a convenience function that is intended to be used to modify
+ *   bits in the PBA divided clock (DIVMASK) register.
+ *
+ ****************************************************************************/
+
+void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Make sure that the following operations are atomic */
+
+  flags = irqsave();
+
+  /* Modify the PBA DIVMASK */
+
+  regval  = getreg32(SAM_PM_PBADIVMASK);
+  regval &= ~clrbits;
+  regval |= setbits;
+  putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET), SAM_PM_UNLOCK);
+  putreg32(regval, SAM_PM_PBADIVMASK);
+
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: sam_pba_enableperipheral
+ *
+ * Description:
+ *   This is a convenience function to enable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+void sam_pba_enableperipheral(uint32_t bitset)
+{
+  irqstate_t flags;
+
+  /* The following operations must be atomic */
+
+  flags = irqsave();
+
+  /* Enable the APBA bridge if necessary */
+
+  if (getreg32(SAM_PM_PBAMASK) == 0)
+    {
+      sam_hsb_enableperipheral(PM_HSBMASK_APBA);
+    }
+
+  irqrestore(flags);
+
+  /* Enable the module */
+
+  sam_enableperipheral(SAM_PM_PBAMASK, bitset);
+}
+
+/****************************************************************************
+ * Name: sam_pba_disableperipheral
+ *
+ * Description:
+ *   This is a convenience function to disable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+void sam_pba_disableperipheral(uint32_t bitset)
+{
+  irqstate_t flags;
+
+  /* Disable clocking to the module */
+
+  sam_disableperipheral(SAM_PM_PBAMASK, bitset);
+
+  /* Disable the APBA bridge if possible */
+
+  flags = irqsave();
+
+  if (getreg32(SAM_PM_PBAMASK) == 0)
+    {
+      sam_hsb_disableperipheral(PM_HSBMASK_APBA);
+    }
+
+   /* Disable PBA UART divided clock if none of the UARTS are in use */
+
+  if ((getreg32(SAM_PM_PBAMASK) & PM_PBAMASK_UARTS) == 0)
+    {
+      sam_pba_disabledivmask(PM_PBADIVMASK_CLK_USART);
+    }
+
+   /* Disable PBA TIMER divided clocks if none of the UARTS are in use */
+
+  if ((getreg32(SAM_PM_PBAMASK) & PM_PBAMASK_TIMERS) == 0)
+    {
+      sam_pba_disabledivmask(PM_PBADIVMASK_TIMER_CLOCKS);
+    }
+
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: sam_pbb_enableperipheral
+ *
+ * Description:
+ *   This is a convenience function to enable a peripheral on the APBB
+ *   bridge.
+ *
+ ****************************************************************************/
+
+void sam_pbb_enableperipheral(uint32_t bitset)
+{
+  irqstate_t flags;
+
+  /* The following operations must be atomic */
+
+  flags = irqsave();
+
+  /* Enable the APBB bridge if necessary */
+
+  if (getreg32(SAM_PM_PBBMASK) == 0)
+    {
+      sam_hsb_enableperipheral(PM_HSBMASK_APBB);
+    }
+
+  irqrestore(flags);
+
+  /* Enable the module */
+
+  sam_enableperipheral(SAM_PM_PBBMASK, bitset);
+}
+
+/****************************************************************************
+ * Name: sam_pbb_disableperipheral
+ *
+ * Description:
+ *   This is a convenience function to disable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+void sam_pbb_disableperipheral(uint32_t bitset)
+{
+  irqstate_t flags;
+
+  /* Disable clocking to the peripheral module */
+
+  sam_disableperipheral(SAM_PM_PBBMASK, bitset);
+
+  /* Disable the APBB bridge if possible */
+
+  flags = irqsave();
+
+  if (getreg32(SAM_PM_PBBMASK) == 0)
+    {
+      sam_hsb_disableperipheral(PM_HSBMASK_APBB);
+    }
+
+  irqrestore(flags);
+}
diff --git a/nuttx/arch/arm/src/sam34/sam4l_periphclks.h b/nuttx/arch/arm/src/sam34/sam4l_periphclks.h
new file mode 100644
index 0000000000..895556e5de
--- /dev/null
+++ b/nuttx/arch/arm/src/sam34/sam4l_periphclks.h
@@ -0,0 +1,349 @@
+/************************************************************************************
+ * arch/arm/src/sam34/sam4l_periphclks.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H
+#define __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* SAM4L helper macros */
+
+#define sam_enableperipheral(a,s)    sam_modifyperipheral(a,0,s)
+#define sam_disableperipheral(a,s)   sam_modifyperipheral(a,s,0)
+
+#define sam_cpu_enableperipheral(s)  sam_enableperipheral(SAM_PM_CPUMASK,s)
+#define sam_hsb_enableperipheral(s)  sam_enableperipheral(SAM_PM_HSBMASK,s)
+#define sam_pbc_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBCMASK,s)
+#define sam_pbd_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBDMASK,s)
+
+#define sam_cpu_disableperipheral(s) sam_disableperipheral(SAM_PM_CPUMASK,s)
+#define sam_hsb_disableperipheral(s) sam_disableperipheral(SAM_PM_HSBMASK,s)
+#define sam_pbc_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBCMASK,s)
+#define sam_pbd_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBDMASK,s)
+
+#define sam_pba_enabledivmask(s)     sam_pba_modifydivmask(0,s)
+#define sam_pba_disabledivmask(s)    sam_pba_modifydivmask(s,0)
+
+/* Macros to enable clocking to individual peripherals */
+
+#define sam_aesa_enableclk()         sam_hsb_enableperipheral(PM_HSBMASK_AESA)
+#define sam_iisc_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_IISC)
+#define sam_spi_enableclk()          sam_pba_enableperipheral(PM_PBAMASK_SPI)
+
+#define sam_tc0_enableclk() \
+  do { \
+    sam_pba_enableperipheral(PM_PBAMASK_TC0); \
+    sam_pba_enabledivmask(PM_PBADIVMASK_TIMER_CLOCKS); \
+  } while (0)
+
+#define sam_tc1_enableclk() \
+  do { \
+    sam_pba_enableperipheral(PM_PBAMASK_TC1); \
+    sam_pba_enabledivmask(PM_PBADIVMASK_TIMER_CLOCKS); \
+  } while (0)
+
+#define sam_twim0_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_TWIM0)
+#define sam_twis0_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_TWIS0)
+#define sam_twim1_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_TWIM1)
+#define sam_twis1_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_TWIS1)
+
+#define sam_usart0_enableclk() \
+  do { \
+    sam_pba_enableperipheral(PM_PBAMASK_USART0); \
+    sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \
+  } while (0)
+
+#define sam_usart1_enableclk() \
+  do { \
+    sam_pba_enableperipheral(PM_PBAMASK_USART1); \
+    sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \
+  } while (0)
+
+#define sam_usart2_enableclk() \
+  do { \
+    sam_pba_enableperipheral(PM_PBAMASK_USART2); \
+    sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \
+  } while (0)
+
+#define sam_usart3_enableclk() \
+  do { \
+    sam_pba_enableperipheral(PM_PBAMASK_USART3); \
+    sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \
+  } while (0)
+
+#define sam_adcife_enableclk()        sam_pba_enableperipheral(PM_PBAMASK_ADCIFE)
+#define sam_dacc_enableclk()          sam_pba_enableperipheral(PM_PBAMASK_DACC)
+#define sam_acifc_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_ACIFC)
+#define sam_gloc_enableclk()          sam_pba_enableperipheral(PM_PBAMASK_GLOC)
+#define sam_abdacb_enableclk()        sam_pba_enableperipheral(PM_PBAMASK_ABDACB)
+#define sam_trng_enableclk()          sam_pba_enableperipheral(PM_PBAMASK_TRNG)
+#define sam_parc_enableclk()          sam_pba_enableperipheral(PM_PBAMASK_PARC)
+#define sam_catb_enableclk()          sam_pba_enableperipheral(PM_PBAMASK_CATB)
+#define sam_twim2_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_TWIM2)
+#define sam_twim3_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_TWIM3)
+#define sam_lcdca_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_LCDCA)
+
+#define sam_flashcalw_enableclk() \
+  do { \
+    sam_hsb_enableperipheral(PM_HSBMASK_FLASHCALW); \
+    sam_pbb_enableperipheral(PM_PBBMASK_FLASHCALW); \
+  } while (0)
+
+#define sam_picocache_enableclk() \
+  do { \
+    sam_hsb_enableperipheral(PM_HSBMASK_HRAMC1); \
+    sam_pbb_enableperipheral(PM_PBBMASK_HRAMC1); \
+  } while (0)
+
+#define sam_hmatrix_enableclk()       sam_pbb_enableperipheral(PM_PBBMASK_HMATRIX)
+
+#define sam_pdca_enableclk() \
+  do { \
+    sam_hsb_enableperipheral(PM_HSBMASK_PDCA); \
+    sam_pbb_enableperipheral(PM_PBBMASK_PDCA); \
+  } while (0)
+
+#define sam_crccu_enableclk() \
+  do { \
+    sam_hsb_enableperipheral(PM_HSBMASK_CRCCU); \
+    sam_pbb_enableperipheral(PM_PBBMASK_CRCCU); \
+  } while (0)
+
+#define sam_usbc_enableclk() \
+  do { \
+    sam_hsb_enableperipheral(PM_HSBMASK_USBC); \
+    sam_pbb_enableperipheral(PM_PBBMASK_USBC); \
+  } while (0)
+
+#define sam_pevc_enableclk()          sam_pbb_enableperipheral(PM_PBBMASK_PEVC)
+#define sam_pm_enableclk()            sam_pbc_enableperipheral(PM_PBCMASK_PM)
+#define sam_chipid_enableclk()        sam_pbc_enableperipheral(PM_PBCMASK_CHIPID)
+#define sam_scif_enableclk()          sam_pbc_enableperipheral(PM_PBCMASK_SCIF)
+#define sam_freqm_enableclk()         sam_pbc_enableperipheral(PM_PBCMASK_FREQM)
+#define sam_gpio_enableclk()          sam_pbc_enableperipheral(PM_PBCMASK_GPIO)
+#define sam_bpm_enableclk()           sam_pbd_enableperipheral(PM_PBDMASK_BPM)
+#define sam_bscif_enableclk()         sam_pbd_enableperipheral(PM_PBDMASK_BSCIF)
+#define sam_ast_enableclk()           sam_pbd_enableperipheral(PM_PBDMASK_AST)
+#define sam_wdt_enableclk()           sam_pbd_enableperipheral(PM_PBDMASK_WDT)
+#define sam_eic_enableclk()           sam_pbd_enableperipheral(PM_PBDMASK_EIC)
+#define sam_picouart_enableclk()      sam_pbd_enableperipheral(PM_PBDMASK_PICOUART)
+
+/* Macros to disable clocking to individual peripherals */
+
+#define sam_aesa_disableclk()         sam_hsb_disableperipheral(PM_HSBMASK_AESA)
+#define sam_iisc_disableclk()         sam_pba_disableperipheral(PM_PBAMASK_IISC)
+#define sam_spi_disableclk()          sam_pba_disableperipheral(PM_PBAMASK_SPI)
+#define sam_tc0_disableclk()          sam_pba_disableperipheral(PM_PBAMASK_TC0)
+#define sam_tc1_disableclk()          sam_pba_disableperipheral(PM_PBAMASK_TC1)
+#define sam_twim0_disableclk()        sam_pba_disableperipheral(PM_PBAMASK_TWIM0)
+#define sam_twis0_disableclk()        sam_pba_disableperipheral(PM_PBAMASK_TWIS0)
+#define sam_twim1_disableclk()        sam_pba_disableperipheral(PM_PBAMASK_TWIM1)
+#define sam_twis1_disableclk()        sam_pba_disableperipheral(PM_PBAMASK_TWIS1)
+#define sam_usart0_disableclk()       sam_pba_disableperipheral(PM_PBAMASK_USART0)
+#define sam_usart1_disableclk()       sam_pba_disableperipheral(PM_PBAMASK_USART1)
+#define sam_usart2_disableclk()       sam_pba_disableperipheral(PM_PBAMASK_USART2)
+#define sam_usart3_disableclk()       sam_pba_disableperipheral(PM_PBAMASK_USART3)
+#define sam_adcife_disableclk()       sam_pba_disableperipheral(PM_PBAMASK_ADCIFE)
+#define sam_dacc_disableclk()         sam_pba_disableperipheral(PM_PBAMASK_DACC)
+#define sam_acifc_disableclk()        sam_pba_disableperipheral(PM_PBAMASK_ACIFC)
+#define sam_gloc_disableclk()         sam_pba_disableperipheral(PM_PBAMASK_GLOC)
+#define sam_abdacb_disableclk()       sam_pba_disableperipheral(PM_PBAMASK_ABDACB)
+#define sam_trng_disableclk()         sam_pba_disableperipheral(PM_PBAMASK_TRNG)
+#define sam_parc_disableclk()         sam_pba_disableperipheral(PM_PBAMASK_PARC)
+#define sam_catb_disableclk()         sam_pba_disableperipheral(PM_PBAMASK_CATB)
+#define sam_twim2_disableclk()        sam_pba_disableperipheral(PM_PBAMASK_TWIM2)
+#define sam_twim3_disableclk()        sam_pba_disableperipheral(PM_PBAMASK_TWIM3)
+#define sam_lcdca_disableclk()        sam_pba_disableperipheral(PM_PBAMASK_LCDCA)
+#define sam_flashcalw_disableclk()    sam_pba_disableperipheral(PM_HSBMASK_FLASHCALW)
+
+#define sam_picocache_disableclk() \
+  do { \
+    sam_hsb_disableperipheral(PM_HSBMASK_HRAMC1); \
+    sam_pbb_disableperipheral(PM_PBBMASK_HRAMC1); \
+  } while (0)
+
+#define sam_hmatrix_disableclk()      sam_pbb_disableperipheral(PM_PBBMASK_HMATRIX)
+
+#define sam_pdca_disableclk() \
+  do { \
+    sam_hsb_disableperipheral(PM_HSBMASK_PDCA); \
+    sam_pbb_disableperipheral(PM_PBBMASK_PDCA); \
+  } while (0)
+
+#define sam_crccu_disableclk() \
+  do { \
+    sam_hsb_disableperipheral(PM_HSBMASK_CRCCU); \
+    sam_pbb_disableperipheral(PM_PBBMASK_CRCCU); \
+  } while (0)
+
+#define sam_usbc_disableclk() \
+  do { \
+    sam_hsb_disableperipheral(PM_HSBMASK_USBC); \
+    sam_pbb_disableperipheral(PM_PBBMASK_USBC); \
+  } while (0)
+
+#define sam_pevc_disableclk()         sam_pbb_disableperipheral(PM_PBBMASK_PEVC)
+#define sam_pm_disableclk()           sam_pbc_disableperipheral(PM_PBCMASK_PM)
+#define sam_chipid_disableclk()       sam_pbc_disableperipheral(PM_PBCMASK_CHIPID)
+#define sam_scif_disableclk()         sam_pbc_disableperipheral(PM_PBCMASK_SCIF)
+#define sam_freqm_disableclk()        sam_pbc_disableperipheral(PM_PBCMASK_FREQM)
+#define sam_gpio_disableclk()         sam_pbc_disableperipheral(PM_PBCMASK_GPIO)
+#define sam_bpm_disableclk()          sam_pbd_disableperipheral(PM_PBDMASK_BPM)
+#define sam_bscif_disableclk()        sam_pbd_disableperipheral(PM_PBDMASK_BSCIF)
+#define sam_ast_disableclk()          sam_pbd_disableperipheral(PM_PBDMASK_AST)
+#define sam_wdt_disableclk()          sam_pbd_disableperipheral(PM_PBDMASK_WDT)
+#define sam_eic_disableclk()          sam_pbd_disableperipheral(PM_PBDMASK_EIC)
+#define sam_picouart_disableclk()     sam_pbd_disableperipheral(PM_PBDMASK_PICOUART)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: sam_modifyperipheral
+ *
+ * Description:
+ *   This is a convenience function that is intended to be used to enable
+ *   or disable module clocking.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits);
+#endif
+
+/****************************************************************************
+ * Name: sam_pba_modifydivmask
+ *
+ * Description:
+ *   This is a convenience function that is intended to be used to modify
+ *   bits in the PBA divided clock (DIVMASK) register.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits);
+#endif
+
+/****************************************************************************
+ * Name: sam_pba_enableperipheral
+ *
+ * Description:
+ *   This is a convenience function to enable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_pba_enableperipheral(uint32_t bitset);
+#endif
+
+/****************************************************************************
+ * Name: sam_pba_disableperipheral
+ *
+ * Description:
+ *   This is a convenience function to disable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_pba_disableperipheral(uint32_t bitset);
+#endif
+
+/****************************************************************************
+ * Name: sam_pbb_enableperipheral
+ *
+ * Description:
+ *   This is a convenience function to enable a peripheral on the APBB
+ *   bridge.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_pbb_enableperipheral(uint32_t bitset);
+#endif
+
+/****************************************************************************
+ * Name: sam_pbb_disableperipheral
+ *
+ * Description:
+ *   This is a convenience function to disable a peripheral on the APBA
+ *   bridge.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+void sam_pbb_disableperipheral(uint32_t bitset);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H */
diff --git a/nuttx/arch/arm/src/sam34/sam_clockconfig.h b/nuttx/arch/arm/src/sam34/sam_clockconfig.h
index 194e9a9fc3..fb3d3f6eeb 100644
--- a/nuttx/arch/arm/src/sam34/sam_clockconfig.h
+++ b/nuttx/arch/arm/src/sam34/sam_clockconfig.h
@@ -46,23 +46,6 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
-/* SAM4L helper functions */
-
-#ifdef CONFIG_ARCH_CHIP_SAM4L
-#  define sam_enableperipheral(a,s)    sam_modifyperipheral(a,0,s)
-#  define sam_disableperipheral(a,s)   sam_modifyperipheral(a,s,0)
-
-#  define sam_cpu_enableperipheral(s)  sam_enableperipheral(SAM_PM_CPUMASK,s)
-#  define sam_hsb_enableperipheral(s)  sam_enableperipheral(SAM_PM_HSBMASK,s)
-#  define sam_pbc_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBCMASK,s)
-#  define sam_pbd_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBDMASK,s)
-
-#  define sam_cpu_disableperipheral(s) sam_disableperipheral(SAM_PM_CPUMASK,s)
-#  define sam_hsb_disableperipheral(s) sam_disableperipheral(SAM_PM_HSBMASK,s)
-#  define sam_pbc_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBCMASK,s)
-#  define sam_pbd_enableperipheral(s)  sam_enableperipheral(SAM_PM_PBDMASK,s)
-#endif
-
 /************************************************************************************
  * Public Types
  ************************************************************************************/
@@ -102,71 +85,6 @@ extern "C"
 
 void sam_clockconfig(void);
 
-/****************************************************************************
- * Name: sam_modifyperipheral
- *
- * Description:
- *   This is a convenience function that is intended to be used to enable
- *   or disable module clocking.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_CHIP_SAM4L
-void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits);
-#endif
-
-/****************************************************************************
- * Name: sam_pba_enableperipheral
- *
- * Description:
- *   This is a convenience function to enable a peripheral on the APBA
- *   bridge.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_CHIP_SAM4L
-void sam_pba_enableperipheral(uint32_t bitset);
-#endif
-
-/****************************************************************************
- * Name: sam_pba_disableperipheral
- *
- * Description:
- *   This is a convenience function to disable a peripheral on the APBA
- *   bridge.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_CHIP_SAM4L
-void sam_pba_disableperipheral(uint32_t bitset);
-#endif
-
-/****************************************************************************
- * Name: sam_pbb_enableperipheral
- *
- * Description:
- *   This is a convenience function to enable a peripheral on the APBB
- *   bridge.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_CHIP_SAM4L
-void sam_pbb_enableperipheral(uint32_t bitset);
-#endif
-
-/****************************************************************************
- * Name: sam_pbb_disableperipheral
- *
- * Description:
- *   This is a convenience function to disable a peripheral on the APBA
- *   bridge.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_CHIP_SAM4L
-void sam_pbb_disableperipheral(uint32_t bitset);
-#endif
-
 #undef EXTERN
 #if defined(__cplusplus)
 }

From 79ce6ade93dde1773bf519aaccdb377b2e6b09ed Mon Sep 17 00:00:00 2001
From: Lorenz Meier 
Date: Thu, 6 Jun 2013 17:40:32 +0200
Subject: [PATCH 37/41] Tracking NuttX config changes

---
 nuttx/configs/px4fmu-v1/nsh/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/nuttx/configs/px4fmu-v1/nsh/defconfig b/nuttx/configs/px4fmu-v1/nsh/defconfig
index f75fd0d19d..3470034f4a 100644
--- a/nuttx/configs/px4fmu-v1/nsh/defconfig
+++ b/nuttx/configs/px4fmu-v1/nsh/defconfig
@@ -77,6 +77,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_CHIP_STM32=y
 # CONFIG_ARCH_CHIP_STR71X is not set
 CONFIG_ARCH_CORTEXM4=y
+CONFIG_ARCH_HAVE_FPU=y
 CONFIG_ARCH_FAMILY="armv7-m"
 CONFIG_ARCH_CHIP="stm32"
 CONFIG_ARMV7M_USEBASEPRI=y

From 18d0ea69ca9ccb9147079ef1c729a746b2fe8e36 Mon Sep 17 00:00:00 2001
From: Lorenz Meier 
Date: Fri, 7 Jun 2013 13:03:05 +0200
Subject: [PATCH 38/41] Removed stack checking from IO

---
 nuttx/configs/px4io-v1/Kconfig          | 6 +++---
 nuttx/configs/px4io-v1/common/Make.defs | 4 ----
 nuttx/configs/px4io-v1/nsh/defconfig    | 2 +-
 3 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/nuttx/configs/px4io-v1/Kconfig b/nuttx/configs/px4io-v1/Kconfig
index 331bbb0dab..fbf74d7f0d 100644
--- a/nuttx/configs/px4io-v1/Kconfig
+++ b/nuttx/configs/px4io-v1/Kconfig
@@ -5,16 +5,16 @@
 
 if ARCH_BOARD_PX4IO_V1
 
-config CONFIG_HRT_TIMER
+config HRT_TIMER
 	bool "High resolution timer support"
 	default y
 	---help---
 		Enable high resolution timer for PPM capture and system clocks.
 
-config CONFIG_HRT_PPM
+config HRT_PPM
 	bool "PPM input capture"
 	default y
-	depends on CONFIG_HRT_TIMER
+	depends on HRT_TIMER
 	---help---
 		Enable PPM input capture via HRT (for CPPM / PPM sum RC inputs)
 
diff --git a/nuttx/configs/px4io-v1/common/Make.defs b/nuttx/configs/px4io-v1/common/Make.defs
index 7f782b5b22..74b183067c 100644
--- a/nuttx/configs/px4io-v1/common/Make.defs
+++ b/nuttx/configs/px4io-v1/common/Make.defs
@@ -63,10 +63,6 @@ ARCHCPUFLAGS		 = -mcpu=cortex-m3 \
 			   -mthumb \
 			   -march=armv7-m
 
-# enable precise stack overflow tracking
-#INSTRUMENTATIONDEFINES	 = -finstrument-functions \
-#			   -ffixed-r10
-
 # use our linker script
 LDSCRIPT		 = ld.script
 
diff --git a/nuttx/configs/px4io-v1/nsh/defconfig b/nuttx/configs/px4io-v1/nsh/defconfig
index 2168c79b24..5256722333 100755
--- a/nuttx/configs/px4io-v1/nsh/defconfig
+++ b/nuttx/configs/px4io-v1/nsh/defconfig
@@ -94,7 +94,7 @@ CONFIG_ARCH_DMA=y
 CONFIG_ARCH_MATH_H=y
 
 CONFIG_ARMV7M_CMNVECTOR=y
-CONFIG_ARMV7M_STACKCHECK=y
+# CONFIG_ARMV7M_STACKCHECK is not set
 
 #
 # JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):

From c255df1df9c1cd51e6d0e71ee5f2e92a22eac5cf Mon Sep 17 00:00:00 2001
From: Lorenz Meier 
Date: Thu, 13 Jun 2013 09:14:40 +0200
Subject: [PATCH 39/41] Merged in upstream, took upstream UART driver without
 changes, needs re-evaluation (minor diffs to local version)

---
 apps/ChangeLog.txt                            |    4 +
 apps/examples/Makefile                        |   38 +-
 apps/examples/README.txt                      |   31 +-
 apps/examples/lcdrw/Makefile                  |    2 +-
 apps/examples/nrf24l01_term/Makefile          |    2 +-
 apps/examples/nx/Kconfig                      |    7 -
 apps/examples/nx/Makefile                     |    2 +-
 apps/examples/nximage/Makefile                |    2 +-
 apps/examples/nxtext/Kconfig                  |    7 -
 apps/examples/nxtext/Makefile                 |    2 +-
 apps/examples/ostest/Kconfig                  |    7 -
 apps/examples/ostest/Makefile                 |    2 +-
 apps/examples/tiff/Makefile                   |    2 +-
 apps/examples/tiff/tiff_main.c                |    3 +-
 apps/examples/touchscreen/tc.h                |    4 +-
 apps/examples/touchscreen/tc_main.c           |    6 +-
 apps/examples/usbstorage/Kconfig              |   12 +-
 apps/examples/usbstorage/Makefile             |    2 +-
 apps/examples/usbstorage/usbmsc.h             |    8 +-
 apps/examples/usbstorage/usbmsc_main.c        |   14 +-
 apps/examples/usbterm/Makefile                |    4 +-
 apps/system/i2c/Kconfig                       |    9 +-
 apps/system/i2c/README.txt                    |    4 +-
 apps/system/i2c/i2ctool.h                     |    2 +-
 nuttx/ChangeLog                               |   55 +-
 nuttx/Documentation/NuttX.html                |   83 +-
 nuttx/Documentation/NuttxPortingGuide.html    |  169 ++-
 nuttx/Documentation/README.html               |    4 +-
 nuttx/Kconfig                                 |    2 +-
 nuttx/README.txt                              |    2 +
 nuttx/arch/arm/Kconfig                        |    1 +
 nuttx/arch/arm/include/sam34/chip.h           |  290 +++-
 nuttx/arch/arm/include/sam34/irq.h            |    2 +
 nuttx/arch/arm/include/sam34/sam3u_irq.h      |    4 +-
 nuttx/arch/arm/include/sam34/sam4s_irq.h      |  286 ++++
 nuttx/arch/arm/src/armv7-m/nvic.h             |    4 +-
 nuttx/arch/arm/src/lpc17xx/Kconfig            |   28 -
 nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c    |    2 +-
 nuttx/arch/arm/src/lpc17xx/lpc17_serial.c     |   10 +-
 nuttx/arch/arm/src/lpc17xx/lpc17_serial.h     |   14 +-
 nuttx/arch/arm/src/sam34/Kconfig              |  342 ++++-
 nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h    |   38 +-
 .../chip/{sam_matrix.h => sam3u_matrix.h}     |  129 +-
 .../arch/arm/src/sam34/chip/sam3u_memorymap.h |    8 +-
 nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h  |   24 +-
 nuttx/arch/arm/src/sam34/chip/sam3u_pio.h     |   13 +-
 nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h     |  478 +++++++
 nuttx/arch/arm/src/sam34/chip/sam3u_supc.h    |  238 ++--
 nuttx/arch/arm/src/sam34/chip/sam3u_uart.h    |  433 ++++++
 nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h |    2 +-
 .../src/sam34/chip/{sam_wdt.h => sam3u_wdt.h} |   16 +-
 nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h     |  178 +++
 nuttx/arch/arm/src/sam34/chip/sam4l_bscif.h   |  316 ++++
 .../arch/arm/src/sam34/chip/sam4l_flashcalw.h |   34 +-
 .../arch/arm/src/sam34/chip/sam4l_picouart.h  |  121 ++
 nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h  |    2 +-
 nuttx/arch/arm/src/sam34/chip/sam4l_pm.h      |    2 +-
 nuttx/arch/arm/src/sam34/chip/sam4l_scif.h    |  432 ++++++
 nuttx/arch/arm/src/sam34/chip/sam4l_usart.h   |  447 ++++++
 nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h     |  137 ++
 .../arch/arm/src/sam34/chip/sam4s_memorymap.h |  153 ++
 nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h  |  314 ++++
 nuttx/arch/arm/src/sam34/chip/sam4s_pio.h     |   11 +-
 nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h |   92 ++
 nuttx/arch/arm/src/sam34/chip/sam_chipid.h    |   27 +-
 nuttx/arch/arm/src/sam34/chip/sam_hsmci.h     |   78 +-
 nuttx/arch/arm/src/sam34/chip/sam_memorymap.h |    2 +
 nuttx/arch/arm/src/sam34/chip/sam_pinmap.h    |    4 +
 nuttx/arch/arm/src/sam34/chip/sam_pmc.h       |  315 ----
 nuttx/arch/arm/src/sam34/chip/sam_pwm.h       |   14 +
 nuttx/arch/arm/src/sam34/chip/sam_rstc.h      |    3 +
 nuttx/arch/arm/src/sam34/chip/sam_rtc.h       |   87 +-
 nuttx/arch/arm/src/sam34/chip/sam_rtt.h       |   13 +
 nuttx/arch/arm/src/sam34/chip/sam_smc.h       |  669 +++++----
 nuttx/arch/arm/src/sam34/chip/sam_spi.h       |   39 +-
 nuttx/arch/arm/src/sam34/chip/sam_ssc.h       |   21 +-
 nuttx/arch/arm/src/sam34/chip/sam_tc.h        |  113 +-
 nuttx/arch/arm/src/sam34/chip/sam_twi.h       |    9 +-
 nuttx/arch/arm/src/sam34/chip/sam_uart.h      |  391 -----
 nuttx/arch/arm/src/sam34/sam3u_clockconfig.c  |   49 +-
 nuttx/arch/arm/src/sam34/sam3u_gpio.c         |  136 +-
 nuttx/arch/arm/src/sam34/sam3u_gpio.h         |   30 +-
 nuttx/arch/arm/src/sam34/sam3u_periphclks.h   |  149 ++
 nuttx/arch/arm/src/sam34/sam4l_clockconfig.c  | 1267 ++++++++++++++---
 nuttx/arch/arm/src/sam34/sam4l_periphclks.c   |  427 +++++-
 nuttx/arch/arm/src/sam34/sam4l_periphclks.h   |  123 +-
 nuttx/arch/arm/src/sam34/sam4s_gpio.h         |  201 +++
 nuttx/arch/arm/src/sam34/sam4s_periphclks.h   |  157 ++
 nuttx/arch/arm/src/sam34/sam_allocateheap.c   |   26 +-
 nuttx/arch/arm/src/sam34/sam_dmac.c           |    4 +-
 nuttx/arch/arm/src/sam34/sam_gpio.h           |    2 +
 nuttx/arch/arm/src/sam34/sam_gpioirq.c        |   16 +-
 nuttx/arch/arm/src/sam34/sam_hsmci.c          |    9 +-
 nuttx/arch/arm/src/sam34/sam_irq.c            |  101 +-
 nuttx/arch/arm/src/sam34/sam_lowputc.c        |  162 ++-
 nuttx/arch/arm/src/sam34/sam_periphclks.h     |   92 ++
 nuttx/arch/arm/src/sam34/sam_serial.c         |  706 ++++-----
 nuttx/arch/arm/src/sam34/sam_spi.c            |   35 +-
 nuttx/arch/arm/src/sam34/sam_start.c          |   44 +-
 nuttx/arch/arm/src/sam34/sam_timerisr.c       |   18 +-
 nuttx/arch/arm/src/sam34/sam_vectors.S        |   25 +-
 nuttx/arch/arm/src/stm32/stm32_otgfshost.c    |    4 +-
 nuttx/arch/arm/src/stm32/stm32_serial.c       |  138 +-
 nuttx/arch/avr/src/at32uc3/at32uc3_clkinit.c  |   24 +-
 nuttx/configs/Kconfig                         |   13 +
 nuttx/configs/cloudctrl/src/up_usbmsc.c       |    4 +-
 .../configs/compal_e99/nsh_highram/defconfig  |    3 -
 nuttx/configs/ekk-lm3s9b96/ostest/defconfig   |    1 -
 .../configs/ez80f910200kitg/ostest/defconfig  |    1 -
 nuttx/configs/ez80f910200zco/ostest/defconfig |    1 -
 nuttx/configs/fire-stm32v2/nsh/defconfig      |    2 -
 nuttx/configs/fire-stm32v2/src/up_usbmsc.c    |    4 +-
 nuttx/configs/freedom-kl25z/ostest/defconfig  |    1 -
 nuttx/configs/hymini-stm32v/README.txt        |    2 +-
 nuttx/configs/hymini-stm32v/nsh2/defconfig    |    3 -
 nuttx/configs/hymini-stm32v/ostest/defconfig  |    1 -
 nuttx/configs/hymini-stm32v/src/up_usbmsc.c   |    6 +-
 .../configs/hymini-stm32v/usbserial/defconfig |    1 -
 .../hymini-stm32v/usbstorage/defconfig        |    1 -
 nuttx/configs/kwikstik-k40/ostest/defconfig   |    1 -
 nuttx/configs/kwikstik-k40/src/up_usbmsc.c    |    4 +-
 nuttx/configs/lm3s6965-ek/ostest/defconfig    |    1 -
 .../lm4f120-launchpad/ostest/defconfig        |    1 -
 nuttx/configs/lpc4330-xplorer/nsh/defconfig   |    1 -
 .../configs/lpc4330-xplorer/ostest/defconfig  |    1 -
 .../configs/mikroe-stm32f4/fulldemo/defconfig |    2 -
 .../configs/mikroe-stm32f4/kostest/defconfig  |    1 -
 nuttx/configs/mikroe-stm32f4/nx/defconfig     |    1 -
 nuttx/configs/mikroe-stm32f4/nxtext/defconfig |    1 -
 .../src/mikroe-stm32f4-internal.h             |    1 -
 nuttx/configs/nutiny-nuc120/ostest/defconfig  |    1 -
 nuttx/configs/open1788/README.txt             |   15 +-
 nuttx/configs/open1788/ostest/defconfig       |    1 -
 nuttx/configs/p112/ostest/defconfig           |    1 -
 .../configs/pcblogic-pic32mx/ostest/defconfig |    1 -
 nuttx/configs/pic32-starterkit/nsh/defconfig  |    3 -
 nuttx/configs/pic32-starterkit/nsh2/defconfig |    3 -
 .../configs/pic32-starterkit/ostest/defconfig |    3 -
 .../configs/pic32-starterkit/src/up_usbmsc.c  |    6 +-
 .../configs/pic32-starterkit/src/up_usbterm.c |    4 +-
 nuttx/configs/pic32mx7mmb/nsh/defconfig       |    7 -
 nuttx/configs/pic32mx7mmb/ostest/defconfig    |    3 -
 nuttx/configs/pic32mx7mmb/src/up_usbmsc.c     |    6 +-
 nuttx/configs/pic32mx7mmb/src/up_usbterm.c    |    4 +-
 nuttx/configs/sam3u-ek/README.txt             |  161 ++-
 nuttx/configs/sam3u-ek/include/board.h        |   38 +-
 nuttx/configs/sam3u-ek/knsh/defconfig         |   94 +-
 nuttx/configs/sam3u-ek/nsh/defconfig          |  103 +-
 nuttx/configs/sam3u-ek/nx/defconfig           |  105 +-
 nuttx/configs/sam3u-ek/ostest/defconfig       |   94 +-
 nuttx/configs/sam3u-ek/src/Makefile           |    2 +-
 nuttx/configs/sam3u-ek/src/sam3u-ek.h         |    7 +-
 nuttx/configs/sam3u-ek/src/up_lcd.c           |    6 +-
 nuttx/configs/sam3u-ek/src/up_nsh.c           |   39 +-
 nuttx/configs/sam3u-ek/src/up_touchscreen.c   |    4 +-
 nuttx/configs/sam4l-xplained/README.txt       |  183 ++-
 nuttx/configs/sam4l-xplained/include/board.h  |  179 ++-
 .../nsh}/Make.defs                            |    4 +-
 .../nsh}/defconfig                            |  327 ++---
 .../nsh}/setenv.sh                            |   32 +-
 nuttx/configs/sam4l-xplained/ostest/defconfig |   93 +-
 .../configs/sam4l-xplained/scripts/ld.script  |   36 +-
 nuttx/configs/sam4l-xplained/src/Makefile     |    4 +
 .../sam4l-xplained/src/sam4l-xplained.h       |   12 +-
 .../configs/sam4l-xplained/src/sam_autoleds.c |   36 +-
 .../sam4l-xplained/src/sam_cxxinitialize.c    |  154 ++
 nuttx/configs/sam4s-xplained/Kconfig          |    7 +
 nuttx/configs/sam4s-xplained/README.txt       |  599 ++++++++
 nuttx/configs/sam4s-xplained/include/board.h  |  323 +++++
 nuttx/configs/sam4s-xplained/nsh/Make.defs    |  109 ++
 nuttx/configs/sam4s-xplained/nsh/defconfig    |  676 +++++++++
 nuttx/configs/sam4s-xplained/nsh/setenv.sh    |   63 +
 nuttx/configs/sam4s-xplained/ostest/Make.defs |  109 ++
 nuttx/configs/sam4s-xplained/ostest/defconfig |  604 ++++++++
 nuttx/configs/sam4s-xplained/ostest/setenv.sh |   63 +
 .../configs/sam4s-xplained/scripts/ld.script  |  121 ++
 nuttx/configs/sam4s-xplained/src/Makefile     |  100 ++
 .../sam4s-xplained/src/sam4s-xplained.h       |  132 ++
 .../configs/sam4s-xplained/src/sam_autoleds.c |  155 ++
 .../sam4s-xplained/src/sam_boot.c}            |   62 +-
 .../configs/sam4s-xplained/src/sam_buttons.c  |  155 ++
 .../sam4s-xplained/src/sam_cxxinitialize.c    |  154 ++
 .../configs/sam4s-xplained/src/sam_userleds.c |  141 ++
 nuttx/configs/shenzhou/src/up_usbmsc.c        |    4 +-
 nuttx/configs/sim/nsh2/defconfig              |    3 -
 nuttx/configs/sim/ostest/defconfig            |    1 -
 nuttx/configs/sim/touchscreen/defconfig       |    1 -
 nuttx/configs/stm3210e-eval/README.txt        |    2 +-
 .../configs/stm3210e-eval/composite/defconfig |    1 -
 nuttx/configs/stm3210e-eval/nsh2/defconfig    |    5 -
 nuttx/configs/stm3210e-eval/nx/defconfig      |    2 -
 .../configs/stm3210e-eval/nxconsole/defconfig |    3 -
 nuttx/configs/stm3210e-eval/nxlines/defconfig |    3 -
 nuttx/configs/stm3210e-eval/nxtext/defconfig  |    3 -
 nuttx/configs/stm3210e-eval/pm/defconfig      |    5 -
 nuttx/configs/stm3210e-eval/src/up_usbmsc.c   |    6 +-
 .../stm3210e-eval/usbstorage/defconfig        |    1 -
 nuttx/configs/stm3220g-eval/dhcpd/defconfig   |    1 -
 nuttx/configs/stm3220g-eval/nettest/defconfig |    1 -
 nuttx/configs/stm3220g-eval/nsh/defconfig     |    6 -
 nuttx/configs/stm3220g-eval/nsh2/defconfig    |    6 -
 nuttx/configs/stm3220g-eval/ostest/defconfig  |    6 -
 nuttx/configs/stm3220g-eval/telnetd/defconfig |    1 -
 nuttx/configs/stm3240g-eval/dhcpd/defconfig   |    1 -
 nuttx/configs/stm3240g-eval/nettest/defconfig |    1 -
 nuttx/configs/stm3240g-eval/nsh/defconfig     |    6 -
 nuttx/configs/stm3240g-eval/nsh2/defconfig    |    1 -
 .../configs/stm3240g-eval/nxconsole/defconfig |    5 -
 nuttx/configs/stm3240g-eval/nxwm/defconfig    |    6 -
 nuttx/configs/stm3240g-eval/ostest/defconfig  |    1 -
 nuttx/configs/stm3240g-eval/telnetd/defconfig |    1 -
 .../configs/stm3240g-eval/webserver/defconfig |    6 -
 .../stm32f100rc_generic/ostest/defconfig      |    1 -
 .../configs/stm32f3discovery/ostest/defconfig |    1 -
 .../stm32f4discovery/kostest/defconfig        |    1 -
 .../configs/stm32f4discovery/ostest/defconfig |    1 -
 .../stm32f4discovery/winbuild/defconfig       |    1 -
 .../stm32ldiscovery/src/stm32_autoleds.c      |    5 +-
 .../stm32ldiscovery/src/stm32_userleds.c      |    3 +-
 nuttx/configs/sure-pic32mx/ostest/defconfig   |    1 -
 .../sure-pic32mx/src/pic32mx_usbterm.c        |    2 +-
 nuttx/configs/twr-k60n512/ostest/defconfig    |    1 -
 nuttx/configs/twr-k60n512/src/up_usbmsc.c     |    6 +-
 nuttx/configs/ubw32/ostest/defconfig          |    1 -
 nuttx/configs/ubw32/src/up_usbterm.c          |    4 +-
 nuttx/configs/xtrs/ostest/defconfig           |    1 -
 .../configs/z16f2800100zcog/ostest/defconfig  |    1 -
 nuttx/configs/z80sim/ostest/defconfig         |    1 -
 nuttx/configs/z8encore000zco/ostest/defconfig |    1 -
 nuttx/configs/z8f64200100kit/ostest/defconfig |    1 -
 nuttx/drivers/input/ads7843e.c                |    5 +
 nuttx/drivers/serial/Kconfig                  |  863 +++++++----
 nuttx/include/nuttx/serial/serial.h           |    2 +-
 nuttx/mm/Kconfig                              |    9 +-
 234 files changed, 13766 insertions(+), 3460 deletions(-)
 create mode 100644 nuttx/arch/arm/include/sam34/sam4s_irq.h
 rename nuttx/arch/arm/src/sam34/chip/{sam_matrix.h => sam3u_matrix.h} (72%)
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam3u_uart.h
 rename nuttx/arch/arm/src/sam34/chip/{sam_wdt.h => sam3u_wdt.h} (91%)
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_bscif.h
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_picouart.h
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_scif.h
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_usart.h
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4s_memorymap.h
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h
 create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h
 delete mode 100644 nuttx/arch/arm/src/sam34/chip/sam_pmc.h
 delete mode 100644 nuttx/arch/arm/src/sam34/chip/sam_uart.h
 create mode 100644 nuttx/arch/arm/src/sam34/sam3u_periphclks.h
 create mode 100644 nuttx/arch/arm/src/sam34/sam4s_gpio.h
 create mode 100644 nuttx/arch/arm/src/sam34/sam4s_periphclks.h
 create mode 100644 nuttx/arch/arm/src/sam34/sam_periphclks.h
 rename nuttx/configs/{sam3u-ek/touchscreen => sam4l-xplained/nsh}/Make.defs (97%)
 rename nuttx/configs/{sam3u-ek/touchscreen => sam4l-xplained/nsh}/defconfig (71%)
 rename nuttx/configs/{sam3u-ek/touchscreen => sam4l-xplained/nsh}/setenv.sh (65%)
 create mode 100644 nuttx/configs/sam4l-xplained/src/sam_cxxinitialize.c
 create mode 100644 nuttx/configs/sam4s-xplained/Kconfig
 create mode 100644 nuttx/configs/sam4s-xplained/README.txt
 create mode 100644 nuttx/configs/sam4s-xplained/include/board.h
 create mode 100644 nuttx/configs/sam4s-xplained/nsh/Make.defs
 create mode 100644 nuttx/configs/sam4s-xplained/nsh/defconfig
 create mode 100755 nuttx/configs/sam4s-xplained/nsh/setenv.sh
 create mode 100644 nuttx/configs/sam4s-xplained/ostest/Make.defs
 create mode 100644 nuttx/configs/sam4s-xplained/ostest/defconfig
 create mode 100755 nuttx/configs/sam4s-xplained/ostest/setenv.sh
 create mode 100755 nuttx/configs/sam4s-xplained/scripts/ld.script
 create mode 100644 nuttx/configs/sam4s-xplained/src/Makefile
 create mode 100644 nuttx/configs/sam4s-xplained/src/sam4s-xplained.h
 create mode 100644 nuttx/configs/sam4s-xplained/src/sam_autoleds.c
 rename nuttx/{arch/arm/src/sam34/chip/sam_pio.h => configs/sam4s-xplained/src/sam_boot.c} (75%)
 create mode 100644 nuttx/configs/sam4s-xplained/src/sam_buttons.c
 create mode 100644 nuttx/configs/sam4s-xplained/src/sam_cxxinitialize.c
 create mode 100644 nuttx/configs/sam4s-xplained/src/sam_userleds.c

diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt
index 71f7da62ac..4be57aaf28 100644
--- a/apps/ChangeLog.txt
+++ b/apps/ChangeLog.txt
@@ -574,3 +574,7 @@
 	  nRF24L01 driver.  From Laurent Latil (2013-6-1).
 	* apps/nshlib/Kconfig:  Add some missing NSH configuration values.
 	  From Lorenz Meier (2013-6-2).
+	* Standardize on CONFIG_NSH_BUILTIN_APPS.  Remove all other variants
+	  of the build-as-an-NSH-application configuration settings
+	  (2013-6-12).
+
diff --git a/apps/examples/Makefile b/apps/examples/Makefile
index eadb2db21c..46e2efd278 100644
--- a/apps/examples/Makefile
+++ b/apps/examples/Makefile
@@ -49,45 +49,15 @@ SUBDIRS += wget wgetjson xmlrpc
 # Sub-directories that might need context setup.  Directories may need
 # context setup for a variety of reasons, but the most common is because
 # the example may be built as an NSH built-in function.
-#
-# Directories that may be built as NSH built-in functions may have their
-# own configuration setting (like CONFIG_EXAMPLES_HELLOXX_BUILTIN), but
-# many only depend on the generic CONFIG_NSH_BUILTIN_APPS setting.  And
-# there a few which an ONLY be built as NSH built-in applications; these
-# are included in the list unconditionally.
 
 CNTXTDIRS = pwm
 
 ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
 CNTXTDIRS += adc can cdcacm composite cxxtest dhcpd discover flash_test ftpd
-CNTXTDIRS += hello helloxx json keypadtestmodbus mtdpart nettest nxhello
-CNTXTDIRS += nxlines nrf24l01_term relays qencoder slcd smart_test tcpecho
-CNTXTDIRS += telnetd touchscreen watchdog wgetjson
-endif
-
-ifeq ($(CONFIG_EXAMPLES_LCDRW_BUILTIN),y)
-CNTXTDIRS += lcdrw
-endif
-ifeq ($(CONFIG_EXAMPLES_NX_BUILTIN),y)
-CNTXTDIRS += nx
-endif
-ifeq ($(CONFIG_EXAMPLES_NXIMAGE_BUILTIN),y)
-CNTXTDIRS += nximage
-endif
-ifeq ($(CONFIG_EXAMPLES_NXTEXT_BUILTIN),y)
-CNTXTDIRS += nxtext
-endif
-ifeq ($(CONFIG_EXAMPLES_OSTEST_BUILTIN),y)
-CNTXTDIRS += ostest
-endif
-ifeq ($(CONFIG_EXAMPLES_TIFF_BUILTIN),y)
-CNTXTDIRS += tiff
-endif
-ifeq ($(CONFIG_EXAMPLES_USBMSC_BUILTIN),y)
-CNTXTDIRS += usbstorage
-endif
-ifeq ($(CONFIG_EXAMPLES_USBTERM_BUILTIN),y)
-CNTXTDIRS += usbterm
+CNTXTDIRS += hello helloxx json keypadtestmodbus lcdrw mtdpart nettest nx
+CNTXTDIRS += nxhello nximage nxlines nxtext nrf24l01_term ostest relays
+CNTXTDIRS += qencoder slcd smart_test tcpecho telnetd tiff touchscreen
+CNTXTDIRS += usbstorage usbterm watchdog wgetjson
 endif
 
 all: nothing
diff --git a/apps/examples/README.txt b/apps/examples/README.txt
index 7e3b0d0f07..8ef6b4a10a 100644
--- a/apps/examples/README.txt
+++ b/apps/examples/README.txt
@@ -23,14 +23,6 @@ examples
     - CONFIG_NSH_BUILTIN_APPS - Enable support for external registered,
       "named" applications that can be executed from the NSH
       command line (see apps/README.txt for more information).
-    - CONFIG_EXAMPLES_XYZ_BUILTIN -- Build the XYZ example as a "built-in"
-      that can be executed from the NSH command line (where XYZ is
-      the specific example.  See the following for examples that
-      support this option).
-
-      NOTE: The use of CONFIG_EXAMPLES_XYZ_BUILTIN is being phased
-      out.  For many example, the definition of CONFIG_NSH_BUILTIN_APPS
-      is sufficient built the example as an NSH built-in application.
 
   Older configurations.
 
@@ -543,7 +535,7 @@ examples/helloxx
 
   NuttX configuration settings specific to this examp;le:
 
-    CONFIG_EXAMPLES_HELLOXX_BUILTIN -- Build the helloxx example as a
+    CONFIG_NSH_BUILTIN_APPS -- Build the helloxx example as a
       "built-in"  that can be executed from the NSH command line.
     CONFIG_EXAMPLES_HELLOXX_NOSTACKCONST - Set if the system does not
       support construction of objects on the stack.
@@ -794,7 +786,7 @@ examples/nx
   defined in include/nuttx/nx/nx.h.  The following configuration options
   can be selected:
 
-    CONFIG_EXAMPLES_NX_BUILTIN -- Build the NX example as a "built-in"
+    CONFIG_NSH_BUILTIN_APPS -- Build the NX example as a "built-in"
       that can be executed from the NSH command line
     CONFIG_EXAMPLES_NX_VPLANE -- The plane to select from the frame-
       buffer driver for use in the test.  Default: 0
@@ -947,7 +939,7 @@ examplex/nxhello
 
   The following configuration options can be selected:
 
-    CONFIG_EXAMPLES_NXHELLO_BUILTIN -- Build the NXHELLO example as a "built-in"
+    CONFIG_NSH_BUILTIN_APPS -- Build the NXHELLO example as a "built-in"
       that can be executed from the NSH command line
     CONFIG_EXAMPLES_NXHELLO_VPLANE -- The plane to select from the frame-
       buffer driver for use in the test.  Default: 0
@@ -980,7 +972,7 @@ examples/nximage
   of the display.  This only works for RGB23 (888), RGB16 (656), RGB8 (332),
   and 8-bit greyscale for now.
 
-    CONFIG_EXAMPLES_NXIMAGE_BUILTIN -- Build the NXIMAGE example as a "built-in"
+    CONFIG_NSH_BUILTIN_APPS -- Build the NXIMAGE example as a "built-in"
       that can be executed from the NSH command line
     CONFIG_EXAMPLES_NXIMAGE_VPLANE -- The plane to select from the frame-
       buffer driver for use in the test.  Default: 0
@@ -1087,7 +1079,7 @@ examples/nxtext
 
   The following configuration options can be selected:
 
-    CONFIG_EXAMPLES_NXTEXT_BUILTIN -- Build the NXTEXT example as a "built-in"
+    CONFIG_NSH_BUILTIN_APPS -- Build the NXTEXT example as a "built-in"
       that can be executed from the NSH command line
     CONFIG_EXAMPLES_NXTEXT_VPLANE -- The plane to select from the frame-
       buffer driver for use in the test.  Default: 0
@@ -1165,7 +1157,7 @@ examples/ostest
   The behavior of the ostest can be modified with the following
   settings in the configs//defconfig file:
 
-  * CONFIG_EXAMPLES_OSTEST_BUILTIN
+  * CONFIG_NSH_BUILTIN_APPS
       Build the OS test example as an NSH built-in application.
   * CONFIG_EXAMPLES_OSTEST_LOOPS
       Used to control the number of executions of the test.  If
@@ -1611,7 +1603,6 @@ examples/tiff
   built-on, i.e., if the following is defined:
 
     CONFIG_NSH_BUILTIN_APPS=y
-    CONFIG_EXAMPLES_TIFF_BUILTIN=y
 
   At a miniumum, to run in an embedded environment, you will probably have to
   change the configured paths to the TIFF files defined in the example.
@@ -1635,7 +1626,7 @@ examples/touchscreen
   and will print the touchscreen output as it is received from the
   simulated touchscreen driver.
 
-    CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN - Build the touchscreen test as
+    CONFIG_NSH_BUILTIN_APPS - Build the touchscreen test as
       an NSH built-in function.  Default: Built as a standalone problem
     CONFIG_EXAMPLES_TOUCHSCREEN_MINOR - The minor device number.  Minor=N
       corresponds to touchscreen device /dev/inputN.  Note this value must
@@ -1643,7 +1634,7 @@ examples/touchscreen
     CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH - The path to the touchscreen
      device.  This must be consistent with CONFIG_EXAMPLES_TOUCHSCREEN_MINOR.
      Default: "/dev/input0"
-    CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES - If CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN
+    CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES - If CONFIG_NSH_BUILTIN_APPS
      is defined, then the number of samples is provided on the command line
      and this value is ignored.  Otherwise, this number of samples is
      collected and the program terminates.  Default:  Samples are collected
@@ -1814,7 +1805,7 @@ examples/usbstorage
 
   Configuration options:
 
-  CONFIG_EXAMPLES_USBMSC_BUILTIN
+  CONFIG_NSH_BUILTIN_APPS
     This example can be built as two NSH "built-in" commands if this option
     is selected: 'msconn' will connect the USB mass storage device; 'msdis'
     will disconnect the USB storage device.
@@ -1854,7 +1845,7 @@ examples/usbstorage
 
   Error results are always shown in the trace output
 
-  NOTE 1: When built as an NSH add-on command (CONFIG_EXAMPLES_USBMSC_BUILTIN=y),
+  NOTE 1: When built as an NSH add-on command (CONFIG_NSH_BUILTIN_APPS=y),
   Caution should be used to assure that the SD drive (or other storage device) is
   not in use when the USB storage device is configured.  Specifically, the SD
   driver should be unmounted like:
@@ -1901,7 +1892,7 @@ examples/usbterm
 
   Configuration options:
 
-    CONFIG_EXAMPLES_USBTERM_BUILTIN - Build the usbterm example as an NSH
+    CONFIG_NSH_BUILTIN_APPS - Build the usbterm example as an NSH
       built-in command.  NOTE:  This is not fully functional as of this
       writing.. It should work, but there is no mechanism in place yet
       to exit the USB terminal program and return to NSH.
diff --git a/apps/examples/lcdrw/Makefile b/apps/examples/lcdrw/Makefile
index aab04acf5e..59726f7c05 100644
--- a/apps/examples/lcdrw/Makefile
+++ b/apps/examples/lcdrw/Makefile
@@ -83,7 +83,7 @@ $(COBJS): %$(OBJEXT): %.c
 	$(call ARCHIVE, $(BIN), $(OBJS))
 	@touch .built
 
-ifeq ($(CONFIG_EXAMPLES_LCDRW_BUILTIN),y)
+ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
 $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile
 	$(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main)
 
diff --git a/apps/examples/nrf24l01_term/Makefile b/apps/examples/nrf24l01_term/Makefile
index cac8f5a6a4..bf8ea760ae 100644
--- a/apps/examples/nrf24l01_term/Makefile
+++ b/apps/examples/nrf24l01_term/Makefile
@@ -83,7 +83,7 @@ $(COBJS): %$(OBJEXT): %.c
 	$(call ARCHIVE, $(BIN), $(OBJS))
 	@touch .built
 
-#ifeq ($(CONFIG_EXAMPLES_NXHELLO_BUILTIN),y)
+#ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
 $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile
 	$(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main)
 
diff --git a/apps/examples/nx/Kconfig b/apps/examples/nx/Kconfig
index 4dcc42579f..59ee98a183 100644
--- a/apps/examples/nx/Kconfig
+++ b/apps/examples/nx/Kconfig
@@ -11,13 +11,6 @@ config EXAMPLES_NX
 
 if EXAMPLES_NX
 
-config EXAMPLES_NX_BUILTIN
-	bool "NSH Built-IN"
-	depends on NSH_BUILTIN_APPS
-	---help---
-		Build the NX example as a "built-in" that can be executed from the
-		NSH command line    
-
 config EXAMPLES_NX_VPLANE
 	int "Video Plane"
 	default 0
diff --git a/apps/examples/nx/Makefile b/apps/examples/nx/Makefile
index 13a9388219..ea802d9e77 100644
--- a/apps/examples/nx/Makefile
+++ b/apps/examples/nx/Makefile
@@ -86,7 +86,7 @@ $(COBJS): %$(OBJEXT): %.c
 	$(call ARCHIVE, $(BIN), $(OBJS))
 	@touch .built
 
-ifeq ($(CONFIG_EXAMPLES_NX_BUILTIN),y)
+ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
 $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile
 	$(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main)
 
diff --git a/apps/examples/nximage/Makefile b/apps/examples/nximage/Makefile
index 7bdaa46d23..42ab1adeb2 100644
--- a/apps/examples/nximage/Makefile
+++ b/apps/examples/nximage/Makefile
@@ -83,7 +83,7 @@ $(COBJS): %$(OBJEXT): %.c
 	$(call ARCHIVE, $(BIN), $(OBJS))
 	@touch .built
 
-ifeq ($(CONFIG_EXAMPLES_NXIMAGE_BUILTIN),y)
+ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
 $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile
 	$(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main)
 
diff --git a/apps/examples/nxtext/Kconfig b/apps/examples/nxtext/Kconfig
index d7c6d507a6..90f4e5cd28 100644
--- a/apps/examples/nxtext/Kconfig
+++ b/apps/examples/nxtext/Kconfig
@@ -13,13 +13,6 @@ if EXAMPLES_NXTEXT
 
 comment "Basic Configuration of the example"
 
-config EXAMPLES_NXTEXT_BUILTIN
-	bool "NSH Built-IN"
-	depends on NSH_BUILTIN_APPS
-	---help---
-		Build the NX Text example as a "built-in" that can be executed from the
-		NSH command line.
-
 config EXAMPLES_NXTEXT_VPLANE
 	int "Video Plane"
 	default 0
diff --git a/apps/examples/nxtext/Makefile b/apps/examples/nxtext/Makefile
index dfb165608d..cabae0520d 100644
--- a/apps/examples/nxtext/Makefile
+++ b/apps/examples/nxtext/Makefile
@@ -87,7 +87,7 @@ $(COBJS): %$(OBJEXT): %.c
 	$(call ARCHIVE, $(BIN), $(OBJS))
 	@touch .built
 
-ifeq ($(CONFIG_EXAMPLES_NXTEXT_BUILTIN),y)
+ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
 $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile
 	$(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main)
 
diff --git a/apps/examples/ostest/Kconfig b/apps/examples/ostest/Kconfig
index c3fe8f21df..0e0f2b016e 100644
--- a/apps/examples/ostest/Kconfig
+++ b/apps/examples/ostest/Kconfig
@@ -11,13 +11,6 @@ config EXAMPLES_OSTEST
 
 if EXAMPLES_OSTEST
 
-config EXAMPLES_OSTEST_BUILTIN
-	bool "NSH built-in application"
-	default y if NSH_LIBRARY
-	default n if !NSH_LIBRARY
-	---help---
-		Build the OS test example as an NSH built-in application.
-
 config EXAMPLES_OSTEST_LOOPS
 	int "OS test loop"
 	default 1
diff --git a/apps/examples/ostest/Makefile b/apps/examples/ostest/Makefile
index e0265fc314..e8b6a176db 100644
--- a/apps/examples/ostest/Makefile
+++ b/apps/examples/ostest/Makefile
@@ -137,7 +137,7 @@ $(COBJS): %$(OBJEXT): %.c
 	$(call ARCHIVE, $(BIN), $(OBJS))
 	@touch .built
 
-ifeq ($(CONFIG_EXAMPLES_OSTEST_BUILTIN),y)
+ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
 $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile
 	$(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main)
 
diff --git a/apps/examples/tiff/Makefile b/apps/examples/tiff/Makefile
index 17b3bb92cf..7be74a5872 100644
--- a/apps/examples/tiff/Makefile
+++ b/apps/examples/tiff/Makefile
@@ -83,7 +83,7 @@ $(COBJS): %$(OBJEXT): %.c
 	$(call ARCHIVE, $(BIN), $(OBJS))
 	@touch .built
 
-ifeq ($(CONFIG_EXAMPLES_TIFF_BUILTIN),y)
+ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
 $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile
 	$(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main)
 
diff --git a/apps/examples/tiff/tiff_main.c b/apps/examples/tiff/tiff_main.c
index 1bf931a436..357e29bf8a 100644
--- a/apps/examples/tiff/tiff_main.c
+++ b/apps/examples/tiff/tiff_main.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * apps/graphics/tiff/tiff_main.c
  *
- *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -56,7 +56,6 @@
  * built-on, i.e., if the following is defined:
  *
  *   CONFIG_NSH_BUILTIN_APPS=y
- *   CONFIG_EXAMPLES_TIFF_BUILTIN=y
  *
  * Other configuration options:
  *
diff --git a/apps/examples/touchscreen/tc.h b/apps/examples/touchscreen/tc.h
index 055353ddd8..1757fe0c86 100644
--- a/apps/examples/touchscreen/tc.h
+++ b/apps/examples/touchscreen/tc.h
@@ -46,7 +46,7 @@
  * Definitions
  ****************************************************************************/
 /* Configuration ************************************************************/
-/* CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN - Build the touchscreen test as
+/* CONFIG_NSH_BUILTIN_APPS - Build the touchscreen test as
  *   an NSH built-in function.  Default: Built as a standalone problem
  * CONFIG_EXAMPLES_TOUCHSCREEN_MINOR - The minor device number.  Minor=N
  *   corresponds to touchscreen device /dev/input0.  Note this value must
@@ -54,7 +54,7 @@
  * CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH - The path to the touchscreen
  *   device.  This must be consistent with CONFIG_EXAMPLES_TOUCHSCREEN_MINOR.
  *   Default: "/dev/input0"
- * CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES - If CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN
+ * CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES - If CONFIG_NSH_BUILTIN_APPS
  *   is defined, then the number of samples is provided on the command line
  *   and this value is ignored.  Otherwise, this number of samples is
  *   collected and the program terminates.  Default:  Zero (Samples are collected
diff --git a/apps/examples/touchscreen/tc_main.c b/apps/examples/touchscreen/tc_main.c
index d49902612b..d786a6775c 100644
--- a/apps/examples/touchscreen/tc_main.c
+++ b/apps/examples/touchscreen/tc_main.c
@@ -88,7 +88,7 @@ int tc_main(int argc, char *argv[])
 {
   struct touch_sample_s sample;
   ssize_t nbytes;
-#if defined(CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN) || CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES > 0
+#if defined(CONFIG_NSH_BUILTIN_APPS) || CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES > 0
   long nsamples;
 #endif
   int fd;
@@ -99,7 +99,7 @@ int tc_main(int argc, char *argv[])
    * samples that we collect before returning.  Otherwise, we never return
    */
 
-#if defined(CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN)
+#if defined(CONFIG_NSH_BUILTIN_APPS)
   nsamples = 1;
   if (argc > 1)
     {
@@ -139,7 +139,7 @@ int tc_main(int argc, char *argv[])
    * touchscreen samples.
    */
 
-#if defined(CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN)
+#if defined(CONFIG_NSH_BUILTIN_APPS)
   for (; nsamples > 0; nsamples--)
 #elif CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES > 0
   for (nsamples = 0; nsamples < CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES; nsamples++)
diff --git a/apps/examples/usbstorage/Kconfig b/apps/examples/usbstorage/Kconfig
index 823ae2953b..c338ae99e7 100644
--- a/apps/examples/usbstorage/Kconfig
+++ b/apps/examples/usbstorage/Kconfig
@@ -9,14 +9,7 @@ config EXAMPLES_USBMSC
 	---help---
 		Enable the USB mass storage class example
 
-config EXAMPLES_USBMSC_BUILTIN
-	bool "NSH built-in command"
-	default y
-	depends on EXAMPLES_USBMSC && NSH_BUILTIN_APPS
-	---help---
-		This example can be built as two NSH "built-in" commands if this
-		option is selected: 'msconn' will connect the USB mass storage
-		device; 'msdis' will disconnect the USB storage device.
+if EXAMPLES_USBMSC
 
 config EXAMPLES_USBMSC_NLUNS
 	int "Number of LUNs"
@@ -134,3 +127,6 @@ config EXAMPLES_USBMSC_TRACEINTERRUPTS
 		then the example code will also manage the USB trace output.  The
 		amount of trace output can be controlled this configuration value:
 		This setting will show USB device controller interrupt-related events.
+
+endif
+
diff --git a/apps/examples/usbstorage/Makefile b/apps/examples/usbstorage/Makefile
index 6c486bf9c4..76198efa02 100644
--- a/apps/examples/usbstorage/Makefile
+++ b/apps/examples/usbstorage/Makefile
@@ -87,7 +87,7 @@ $(COBJS): %$(OBJEXT): %.c
 	$(call ARCHIVE, $(BIN), $(OBJS))
 	@touch .built
 
-ifeq ($(CONFIG_EXAMPLES_USBMSC_BUILTIN),y)
+ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
 $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat: $(DEPCONFIG) Makefile
 	$(call REGISTER,$(APPNAME1),$(PRIORITY1),$(STACKSIZE1),$(APPNAME1)_main)
 
diff --git a/apps/examples/usbstorage/usbmsc.h b/apps/examples/usbstorage/usbmsc.h
index 95453198ae..b3652ab0a0 100644
--- a/apps/examples/usbstorage/usbmsc.h
+++ b/apps/examples/usbstorage/usbmsc.h
@@ -109,17 +109,17 @@
  * order to avoid name collisions.
  */
 
-#if defined(CONFIG_EXAMPLES_USBMSC_BUILTIN) || defined(CONFIG_EXAMPLES_USBMSC_DEBUGMM)
+#if defined(CONFIG_NSH_BUILTIN_APPS) || defined(CONFIG_EXAMPLES_USBMSC_DEBUGMM)
 struct usbmsc_state_s
 {
   /* This is the handle that references to this particular USB storage driver
    * instance.  It is only needed if the USB mass storage device example is
-   * built using CONFIG_EXAMPLES_USBMSC_BUILTIN.  In this case, the value
+   * built using CONFIG_NSH_BUILTIN_APPS.  In this case, the value
    * of the driver handle must be remembered between the 'msconn' and 'msdis'
    * commands.
    */
 
-#ifdef CONFIG_EXAMPLES_USBMSC_BUILTIN
+#ifdef CONFIG_NSH_BUILTIN_APPS
   FAR void *mshandle;
 #endif
 
@@ -143,7 +143,7 @@ struct usbmsc_state_s
  * order to avoid name collisions.
  */
 
-#if defined(CONFIG_EXAMPLES_USBMSC_BUILTIN) || defined(CONFIG_EXAMPLES_USBMSC_DEBUGMM)
+#if defined(CONFIG_NSH_BUILTIN_APPS) || defined(CONFIG_EXAMPLES_USBMSC_DEBUGMM)
 extern struct usbmsc_state_s g_usbmsc;
 #endif
 
diff --git a/apps/examples/usbstorage/usbmsc_main.c b/apps/examples/usbstorage/usbmsc_main.c
index ac7b82d017..5c0ae232ee 100644
--- a/apps/examples/usbstorage/usbmsc_main.c
+++ b/apps/examples/usbstorage/usbmsc_main.c
@@ -98,7 +98,7 @@
  * order to avoid name collisions.
  */
 
-#if defined(CONFIG_EXAMPLES_USBMSC_BUILTIN) || defined(CONFIG_EXAMPLES_USBMSC_DEBUGMM)
+#if defined(CONFIG_NSH_BUILTIN_APPS) || defined(CONFIG_EXAMPLES_USBMSC_DEBUGMM)
 struct usbmsc_state_s g_usbmsc;
 #endif
 
@@ -383,7 +383,7 @@ static int usbmsc_enumerate(struct usbtrace_s *trace, void *arg)
  *
  * Description:
  *   This is the main program that configures the USB mass storage device
- *   and exports the LUN(s).  If CONFIG_EXAMPLES_USBMSC_BUILTIN is defined
+ *   and exports the LUN(s).  If CONFIG_NSH_BUILTIN_APPS is defined
  *   in the NuttX configuration, then this program can be executed by
  *   entering the "msconn" command at the NSH console.
  *
@@ -398,7 +398,7 @@ int msconn_main(int argc, char *argv[])
    * do a little error checking to assure that we are not being called re-entrantly.
    */
 
-#ifdef CONFIG_EXAMPLES_USBMSC_BUILTIN
+#ifdef CONFIG_NSH_BUILTIN_APPS
 
    /* Check if there is a non-NULL USB mass storage device handle (meaning that the
     * USB mass storage device is already configured).
@@ -504,7 +504,7 @@ int msconn_main(int argc, char *argv[])
    * then we have not real option but to exit now.
    */
 
-#if !defined(CONFIG_EXAMPLES_USBMSC_BUILTIN) && !defined(CONFIG_DISABLE_SIGNALS)
+#if !defined(CONFIG_NSH_BUILTIN_APPS) && !defined(CONFIG_DISABLE_SIGNALS)
 
   /* Otherwise, this thread will hang around and monitor the USB storage activity */
 
@@ -527,7 +527,7 @@ int msconn_main(int argc, char *argv[])
       message("msconn_main: Still alive\n");
 #  endif
     }
-#elif defined(CONFIG_EXAMPLES_USBMSC_BUILTIN)
+#elif defined(CONFIG_NSH_BUILTIN_APPS)
 
    /* Return the USB mass storage device handle so it can be used by the 'misconn'
     * command.
@@ -555,13 +555,13 @@ int msconn_main(int argc, char *argv[])
  *
  * Description:
  *   This is a program entry point that will disconnet the USB mass storage
- *   device.  This program is only available if CONFIG_EXAMPLES_USBMSC_BUILTIN
+ *   device.  This program is only available if CONFIG_NSH_BUILTIN_APPS
  *   is defined in the NuttX configuration.  In that case, this program can
  *   be executed by entering the "msdis" command at the NSH console.
  *
  ****************************************************************************/
 
-#ifdef CONFIG_EXAMPLES_USBMSC_BUILTIN
+#ifdef CONFIG_NSH_BUILTIN_APPS
 int msdis_main(int argc, char *argv[])
 {
   /* First check if the USB mass storage device is already connected */
diff --git a/apps/examples/usbterm/Makefile b/apps/examples/usbterm/Makefile
index 91e80686e2..bf27558c52 100644
--- a/apps/examples/usbterm/Makefile
+++ b/apps/examples/usbterm/Makefile
@@ -1,7 +1,7 @@
 ############################################################################
 # apps/examples/usbterm/Makefile
 #
-#   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt 
 #
 # Redistribution and use in source and binary forms, with or without
@@ -83,7 +83,7 @@ $(COBJS): %$(OBJEXT): %.c
 	$(call ARCHIVE, $(BIN), $(OBJS))
 	@touch .built
 
-ifeq ($(CONFIG_EXAMPLES_USBTERM_BUILTIN),y)
+ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
 $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile
 	$(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main)
 
diff --git a/apps/system/i2c/Kconfig b/apps/system/i2c/Kconfig
index 745378b372..5898f7e7b3 100644
--- a/apps/system/i2c/Kconfig
+++ b/apps/system/i2c/Kconfig
@@ -11,12 +11,7 @@ config SYSTEM_I2CTOOL
 	---help---
 		Enable support for the I2C tool.
 
-config I2CTOOL_BUILTIN
-	bool "NSH built-in command"
-	default y
-	depends on SYSTEM_I2CTOOL && NSH_BUILTIN_APPS
-	---help---
-		Build the tools as an NSH built-in command
+if SYSTEM_I2CTOOL
 
 config I2CTOOL_MINBUS
 	int "Minimum bus number"
@@ -59,3 +54,5 @@ config I2CTOOL_DEFFREQ
 	depends on SYSTEM_I2CTOOL
 	---help---
 		Default I2C frequency (default: 4000000)
+
+endif
diff --git a/apps/system/i2c/README.txt b/apps/system/i2c/README.txt
index 1d6f220255..ee49e7d84c 100644
--- a/apps/system/i2c/README.txt
+++ b/apps/system/i2c/README.txt
@@ -46,7 +46,7 @@ the apps/nshlib/README.txt file for information about add-ons.
 
 Configuration Options
 ---------------------
-CONFIG_I2CTOOL_BUILTIN - Build the tools as an NSH built-in command
+CONFIG_NSH_BUILTIN_APPS - Build the tools as an NSH built-in command
 CONFIG_I2CTOOL_MINBUS - Smallest bus index supported by the hardware (default 0).
 CONFIG_I2CTOOL_MAXBUS - Largest bus index supported by the hardware (default 3)
 CONFIG_I2CTOOL_MINADDR - Minium device address (default: 0x03)
@@ -391,7 +391,7 @@ options in the NuttX configuration.  This configuration is the defconfig
 file in your configuration directory that is copied to the NuttX top-level
 directory as .config when NuttX is configured.
 
-  CONFIG_I2CTOOL_BUILTIN: Build the tools as an NSH built-in command
+  CONFIG_NSH_BUILTIN_APPS: Build the tools as an NSH built-in command
   CONFIG_I2CTOOL_MINBUS: Smallest bus index supported by the hardware (default 0).
   CONFIG_I2CTOOL_MAXBUS: Largest bus index supported by the hardware (default 3)
   CONFIG_I2CTOOL_MINADDR: Minium device address (default: 0x03)
diff --git a/apps/system/i2c/i2ctool.h b/apps/system/i2c/i2ctool.h
index 4ff26d03ed..d8cc07203c 100644
--- a/apps/system/i2c/i2ctool.h
+++ b/apps/system/i2c/i2ctool.h
@@ -55,7 +55,7 @@
  * Definitions
  ****************************************************************************/
 /* Configuration ************************************************************/
-/* CONFIG_I2CTOOL_BUILTIN - Build the tools as an NSH built-in command
+/* CONFIG_NSH_BUILTIN_APPS - Build the tools as an NSH built-in command
  * CONFIG_I2CTOOL_MINBUS - Smallest bus index supported by the hardware (default 0).
  * CONFIG_I2CTOOL_MAXBUS - Largest bus index supported by the hardware (default 3)
  * CONFIG_I2CTOOL_MINADDR - Minium device address (default: 0x03)
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 0141d60c6f..078ea01597 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3848,7 +3848,7 @@
 	* configs/olimex-lpc1766stk/wlan:  Remove non-functional
 	  configuration.
 	* configs/stm32f4discovery/src and nuttx/drivers/lcd/ug-2864hsweg01.c:
-	  Updates and correctinos for the UG-2864HSWEG01 from Darcy Gong.
+	  Updates and corrections for the UG-2864HSWEG01 from Darcy Gong.
 	* configs/lm326965-ek:  All configurations converted to use the
 	  kconfig-frontends configuration tool.
 	* configs/Kconfig: NSH_MMCSDSPIPORTNO should depend on MMCSD_SPI,
@@ -4910,4 +4910,55 @@
 	  logic (leveraged from AVR32).
 	* nuttx/arch/arm/src/sam34/sam4l_periphclks.c/h:  Add common
 	  logic to enabled/disable SAM4L peripheral clocking (2013-6-5).
-
+	* nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h and sam4l_scif.h:  Add
+	  register definitions for the SAM4L BMP and SCIF blocks (2013-6-6).
+	* nuttx/arch/arm/src/sam34/sam4l_clockconfig.c:  Now selects an
+	  optimal power scaling mode (2013-6-6).
+	* nuttx/arch/arm/src/stm32/stm32_serial.c and nuttx/include/termios.h:
+	  Change for hardware flow control support for STM32. It also fixes
+	  incorrect operation of USART2 and UART5 in current master.  Submitted
+	  by Lorenz Meier but includes changes by Mike Smith (2013-6-6).
+	* nuttx/arch/arm/src/stm32/stm32_otgfshost.c:  A backward conditional
+	  prevent detection of disonnection events.  Reported by Scott (2013-6-6).
+	* nuttx/arch/arm/src/sam34/chip/sam4l_bscif.h: Add registers definitions
+	  for the SAM4L BSCIF module (2013-6-6).
+	* nuttx/arch/arm/src/sam34/sam4l_clockconfig.c and chip/sam4l_wdt.h:
+	  Finally finished the SAM4L clock configuration logic; Added a
+	  WDT register definition header file (2013-6-8).
+	* nuttx/arch/arm/src/sam34/chip/sam4l_usart.h and sam4l_picouart.h:
+	  Add UART/USART register defintion files for the SAM4L (2013-6-8).
+	* arm/src/sam34/chip/sam3u_periphclks.h:  More macros and definitions
+	  to generalize peripheral clocking and to hide differences between
+	  the SAM3U and the SAM4L (2013-6-8).
+	* configs/sam4l-xplained/ostest:  The SAM4L now passed the OS test
+	  (2013-6-9).
+	* configs/sam4l-xplained/nsh:  Added an NSH configuration for the
+	  SAM4L Xplained Pro board (2013-6-9).
+	* configs/sam4l-xplained/src/sam_cxxinitialize.c:  Added C++ support
+	  to the SAM4L Xplained Pro board configuration (2013-6-9).
+	* arm/src/sam34/chip/sam_irq.c:  Extend IRQ support to handle the
+	  larger number of NVIC interrupts used by the SAM4L (2013-6-9).
+	* arch/arm/src/sam45/chip:  Beginning updates of SAM3U header files
+	  to include support for the SAM4S: WDT, SUPC, EEFC, MATRIX, PMC,
+	  UARTs, USARTs, HSMCI, SPI (2013-6-10).
+	* arch/arm/src/chip/sam4s_memorymap.h, sam4s_irq.h, and sam4s_vectors.h:
+	  Add SAM4S memory map and interrupt definitions (2013-6-10)
+	* configs/sam4s-xplained:  Add framework for the SAM4S Xplained board.
+	  There is not much there on initial checkin (2013-6-10).
+	* arch/arm/src/sam34: SAM3S support: GPIO, chip characteristics,
+	  peripheral Kconfig (2013-6-11).
+	* arch/arm/src/sam34/chip/sam4s_pinmap.h:  Add SAM4S pin configuration
+	  definitions (2013-6-11).
+	* arch/arm/src/sam34/sam4s_periphclks.h:  Add macros to manage SAM4S
+	  peripheral clocks (2013-6-11).
+	* configs/sam4s-xplained: Configuration builds error-free (2013-6-11).
+	* configs/sam4s-xplained/nsh:  Added an NSH configuration for the
+	  SAM4S Xplained board.  Both the OS test and the NSH configurations
+	  no execute error-free.  Delay loops calibrated for both the SAM4L
+	  and SAM4S boards (2013-6-12).
+	* Standardize on CONFIG_NSH_BUILTIN_APPS.  Remove all other variants
+	  of the build-as-an-NSH-application configuration settings
+	  (2013-6-12).
+	* arch/arm/src/sam34/sam_periphclks.h:  A header file that just
+	  includes the right header file.  This cleans up the messy logic
+	  in all of the C files and puts the mess in one place (2013-6-12).
diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html
index c8922cf36a..25c340d487 100644
--- a/nuttx/Documentation/NuttX.html
+++ b/nuttx/Documentation/NuttX.html
@@ -8,7 +8,7 @@
   
     
       
    NuttX RTOS
    
-      
    Last Updated: May 29, 2013
    
+      
    Last Updated: June 12, 2013
    
     
   
 
@@ -1578,7 +1578,7 @@ 
    NuttX-6.27 Release Notes
    
       
  • ARM926EJS (3) 
    • 
       
  • ARM Cortex-M0/M0+ (2)
    • 
       
  • ARM Cortex-M3 (19)
    • 
-      
  • ARM Cortex-M4 (7)
    • 
+      
  • ARM Cortex-M4 (9)
    •
  • Atmel AVR
  • Freescale @@ -2950,7 +2952,7 @@

    NuttX-6.27 Release Notes

      STATUS: - As of this writing, the basic port is code complete and fully verified configurations exit for the basic NuttX OS test and for the NuttShell NSH). + As of this writing, the basic port is code complete and fully verified configurations exist for the basic NuttX OS test and for the NuttShell NSH). The first fully functional LM4F120 LaunchPad port was released in NuttX-6.27.

    @@ -2960,6 +2962,77 @@

    NuttX-6.27 Release Notes


    + +
    + +

    + Atmel AT91SAM4L. + This port uses the Atmel SAM4L Xplained Pro development board. + This board features the ATSAM4LC4C MCU running at 48MHz with 256KB of FLASH and 32KB of internal SRAM. +

    +
      +

      + STATUS: + As of this writing, the basic port is code complete and fully verified configurations exist for the basic NuttX OS test and for the NuttShell NSH). + The first fully functional SAM4L Xplained Pro port was released in NuttX-6.28. +

      +

      + Memory Usage. + The ATSAM4LC4C comes in a 100-pin package and has 256KB FLASH and 32KB of SRAM. + Below is the current memory usage for the NSH configuration (June 9, 2013). + This is not a minimal implementation, but a full-featured NSH configuration. +

      +

      + Static memory usage can be shown with size command: +

      + 
        +$ size nuttx
+   text    data     bss     dec     hex filename
+  43572     122    2380   46074    b3fa nuttx
+
      +

      + NuttX, the NSH application, and GCC libraries use 42.6KB of FLASH leaving 213.4B of FLASH (83.4%) free from additional application development. + Static SRAM usage is about 2.3KB (<7%) and leaves 29.7KB (92.7%) available for heap at runtime. +

      + SRAM usage at run-time can be shown with the NSH free command. + This runtime memory usage includes the static memory usage plus all dynamic memory allocation for things like stacks and I/O buffers: + 
        +NuttShell (NSH) NuttX-6.28
+nsh> free
+             total       used       free    largest
+Mem:         29232       5920      23312      23312
+
      +

      + You can see that 22.8KB (71.1%) of the SRAM heap is staill available for further application development while NSH is running. +

      +
    + + + +
    +
    + + +
    + +

    + Atmel AT91SAM4S. + This port uses the Atmel SAM4S Xplained development board. + This board features the ATSAM4S16C MCU running at 120MHz with 1MB of FLASH and 128KB of internal SRAM. +

    +
      +

      + STATUS: + As of this writing, the basic port is code complete and fully verified configurations exist for the basic NuttX OS test and for the NuttShell NSH). + The first fully functional SAM4S Xplained port was released in NuttX-6.28. +

      +
    + + + +
    +
    +
    @@ -3417,10 +3490,6 @@

    NuttX-6.27 Release Notes

    - -
    -
    - diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index 845f4e5d52..236215fffb 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -12,7 +12,7 @@

    NuttX RTOS Porting Guide

    -

    Last Updated: March 20, 2013

    +

    Last Updated: June 11, 2013

    @@ -46,7 +46,8 @@

    Table of Contents

    2.4.2.1 Board Specific Logic
    2.4.2.2 Board Specific Configuration Sub-Directories - 2.4.3 Supported Boards + 2.4.3 Supported Boards
    + 2.4.4 Adding a New Board Configuration 2.5 nuttx/drivers/
    2.6 nuttx/fs/
    @@ -795,13 +796,13 @@

    2.4.3 Supported Boards

  • configs/ea3131: - Embedded Artists EA3131 Development bard. This board is based on the + Embedded Artists EA3131 Development bard. This board is based on the an NXP LPC3131 MCU. This OS is built with the arm-nuttx-elf toolchain. STATUS: This port is complete and mature.
  • configs/eagle100: - Micromint Eagle-100 Development board. This board is based on the + Micromint Eagle-100 Development board. This board is based on the an ARM Cortex-M3 MCU, the Luminary LM3S6918. This OS is built with the arm-nuttx-elf toolchain. STATUS: This port is complete and mature.
    • @@ -819,7 +820,7 @@

    2.4.3 Supported Boards

  • configs/lm3s6965-ek: - Stellaris LM3S6965 Evaluation Kit. This board is based on the + Stellaris LM3S6965 Evaluation Kit. This board is based on the an ARM Cortex-M3 MCU, the Luminary/TI LM3S6965. This OS is built with the arm-nuttx-elf toolchain. STATUS: This port is complete and mature.
    • @@ -926,7 +927,7 @@

    2.4.3 Supported Boards

  • configs/rgmp: - RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project for + RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project for running GPOS and RTOS simultaneously on multi-processor platforms. You can port your favorite RTOS to RGMP together with an unmodified Linux to form a hybrid operating system. This makes your application able to use both RTOS @@ -978,7 +979,7 @@

    2.4.3 Supported Boards

  • configs/xtrs: TRS80 Model 3. This port uses a vintage computer based on the Z80. - An emulator for this computer is available to run TRS80 programs on a + An emulator for this computer is available to run TRS80 programs on a Linux platform (http://www.tim-mann.org/xtrs.html).
    • @@ -1021,6 +1022,84 @@

    2.4.3 Supported Boards

    is available to build these toolchains under Linux or Cygwin.

    +

    2.4.4 Adding a New Board Configuration

    +

    + Okay, so you have created a new board configuration directory. + Now, how do you hook this board into the configuration system so that you can select with make menuconfig? +

    +

    + You will need modify the file configs/Kconfig. + Let's look at the STM32F4-Discovery configuration in the Kconfig file and see how we would add a new board directory to the configuration. + For this configuration let's say that you new board resides in the directory configs/myboard; + It uses an MCU selected with CONFIG_ARCH_CHIP_MYMCU; and you want the board to be selected with CONFIG_ARCH_BOARD_MYBOARD. + Then here is how you can clone the STM32F4-Discovery configuration in configs/Kconfig to support your new board configuration. +

    +

    + In configs/Kconfig for the stm32f4-discovery, you will see a configuration definition like this: +

    +

      +config ARCH_BOARD_STM32F4_DISCOVERY
+    bool "STMicro STM32F4-Discovery board"
+    depends on ARCH_CHIP_STM32F407VG
+    select ARCH_HAVE_LEDS
+    select ARCH_HAVE_BUTTONS
+    select ARCH_HAVE_IRQBUTTONS
+    ---help---
+        STMicro STM32F4-Discovery board based on the STMicro STM32F407VGT6 MCU.
+
    +

    + The above selects the STM32F4-Discovery board. + The select lines say that the board has both LEDs and buttons and that the board can generate interrupts from the button presses. + You can just copy the above configuration definition to a new location (notice that they the configurations are in alphabetical order). + Then you should edit the configuration to support your board. + The final configuration definition might look something like: +

    +
      +config ARCH_BOARD_MYBOARD
+    bool "My very own board configuration"
+    depends on ARCH_CHIP_MYMCU
+    select ARCH_HAVE_LEDS
+    select ARCH_HAVE_BUTTONS
+    select ARCH_HAVE_IRQBUTTONS
+    ---help---
+        This options selects the board configuration for my very own board
+        based on the MYMCU processor.
+
    +

    + Later in the configs/Kconfig file, you will see a long, long string configuration with lots of defaults like this: +

    +
      +config ARCH_BOARD
+    string
+    default "amber"               if ARCH_BOARD_AMBER
+    default "avr32dev1"           if ARCH_BOARD_AVR32DEV1
+    default "c5471evm"            if ARCH_BOARD_C5471EVM
+...
+    default "stm32f4discovery"    if ARCH_BOARD_STM32F4_DISCOVERY
+...
+
    +

    + This logic will assign string value to a configuration variable called CONFIG_ARCH_BOARD that will name the directory where the board-specific files reside. + In our case, these files reside in configs/myboard and we add the following to the long list of defaults (again in alphabetical order): +

    +
      +    default "myboar"              if ARCH_BOARD_MYBOARD
+
    +

    + Now the build system knows where to find your board configuration! +

    +

    + And finally, add something like this near the bottom of configs/myboard: +

    +
      +if ARCH_BOARD_MYBOARD
+source "configs/myboard/Kconfig"
+endif
+
    +

    + This includes additional, board-specific configuration variabled defintion in configs/myboard/Kconfig. +

    +

    2.5 nuttx/drivers

    @@ -1078,7 +1157,7 @@

    2.5 nuttx/drivers

    | |-- Kconfig | |-- Make.defs | `-- (Common USB host driver source files) -|-- wirelss/ +|-- wireless/ | |-- Kconfig | |-- Make.defs | `-- (Common wireless driver source files) @@ -1666,7 +1745,7 @@

    4.1.4 up_create_stack()

    4.1.5 up_use_stack()

    -

    Prototype: +

    Prototype: STATUS up_use_stack(FAR struct tcb_s *tcb, FAR void *stack, size_t stack_size);

    @@ -1864,7 +1943,7 @@

    4.1.11 up_reprioritize_rtr()Description. Called when the priority of a running or - ready-to-run task changes and the reprioritization will + ready-to-run task changes and the reprioritization will cause a context switch. Two cases:

      @@ -2146,7 +2225,7 @@

      4.1.21.2 Hardware

        CONFIG_RTC -
        Enables general support for a hardware RTC. +
        Enables general support for a hardware RTC. Specific architectures may require other specific settings.
        CONFIG_RTC_DATETIME
        There are two general types of RTC: (1) A simple battery backed counter that keeps the time when power @@ -2164,7 +2243,7 @@

        4.1.21.2 Hardware

        If CONFIG_RTC_HIRES is defined, then the frequency of the high resolution RTC must be provided. If CONFIG_RTC_HIRES is not defined, CONFIG_RTC_FREQUENCY is assumed to be one.
        CONFIG_RTC_ALARM -
        Enable if the RTC hardware supports setting of an alarm. +
        Enable if the RTC hardware supports setting of an alarm. A callback function will be executed when the alarm goes off

      @@ -2175,13 +2254,13 @@

      4.1.21.2 Hardware

      Initialize the hardware RTC per the selected configuration. This function is called once during the OS initialization sequence -
    1. up_rtc_time(). +
    2. up_rtc_time(). Get the current time in seconds. This is similar to the standard time() function. This interface is only required if the low-resolution RTC/counter hardware implementation selected. It is only used by the RTOS during intialization to set up the system time when CONFIG_RTC is set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
      3. -
    3. up_rtc_gettime(). +
    4. up_rtc_gettime(). Get the current time from the high resolution RTC clock/counter. This interface is only supported by the hight-resolution RTC/counter hardware implementation. It is used to replace the system timer (g_system_tick). @@ -2250,11 +2329,11 @@

      4.1.22 Address Environments

      Returns the virtual base address of the address environment.
    5. - 4.1.22.3 up_addrenv_select(): + 4.1.22.3 up_addrenv_select(): Instantiate an address environment.
    6. - 4.1.22.4 up_addrenv_restore(): + 4.1.22.4 up_addrenv_restore(): Restore an address environment.
    7. @@ -2315,7 +2394,7 @@

      4.1.22.2 up_addrenv_vaddr()

      Description:

        - Return the virtual address associated with the newly create address environment. + Return the virtual address associated with the newly create address environment. This function is used by the binary loaders in order get an address that can be used to initialize the new task.

      Input Parameters:

      @@ -2531,9 +2610,9 @@

      4.3.1 Header Files

      4.3.2 LED Definitions

      - The implementation of LED support is very specific to a board architecture. - Some boards have several LEDS, others have only one or two. - Some have none. + The implementation of LED support is very specific to a board architecture. + Some boards have several LEDS, others have only one or two. + Some have none. Others LED matrices and show alphanumeric data, etc. The NuttX logic does not refer to specific LEDS, rather, it refers to an event to be shown on the LEDS in whatever manner is appropriate for the board; @@ -2705,7 +2784,7 @@

      6.0 NuttX Device Drivers

      These different device driver types are discussed in the following paragraphs. Note: device driver support requires that the in-memory, pseudo file system - is enabled by setting the CONFIG_NFILE_DESCRIPTORS in the NuttX configuration file to a + is enabled by setting the CONFIG_NFILE_DESCRIPTORS in the NuttX configuration file to a non-zero value.

      @@ -3451,7 +3530,7 @@

      6.3.9 USB Host-Side Drivers

      As part of its operation during the binding operation, the USB host class driver will register an instances of a standard NuttX driver under the /dev directory. To repeat the above example, the USB host mass storage class driver (drivers/usbhost/usbhost_storage.c) will register a standard, NuttX block driver interface (like /dev/sda) - that can be used to mount a file system just as with any other other block driver instance. + that can be used to mount a file system just as with any other other block driver instance.

      Examples: @@ -3487,7 +3566,7 @@

      6.3.10 USB Device-Side Drivers

      Examples: - arch/arm/src/dm320/dm320_usbdev.c, arch/arm/src/lpc17xx/lpc17_usbdev.c, + arch/arm/src/dm320/dm320_usbdev.c, arch/arm/src/lpc17xx/lpc17_usbdev.c, arch/arm/src/lpc214x/lpc214x_usbdev.c, arch/arm/src/lpc313x/lpc313x_usbdev.c, and arch/arm/src/stm32/stm32_usbdev.c.

      @@ -3914,11 +3993,11 @@

      6.3.16 Keyboard/Keypad Drivers

      stream: An instance of lib_instream_s to perform the actual low-level get operation.
    8. - pch: The location to save the returned value. + pch: The location to save the returned value. This may be either a normal, character code or a special command (i.e., a value from enum kbd_getstate_s.
    9. - state: A user provided buffer to support parsing. + state: A user provided buffer to support parsing. This structure should be cleared the first time that kbd_decode() is called.
      10. @@ -3989,12 +4068,12 @@

      6.4.1 Overview

      • - Reports of relevant driver or other system activity. + Reports of relevant driver or other system activity.

      • - Registration and callback mechanism to interface with individual device drivers. + Registration and callback mechanism to interface with individual device drivers.

      • @@ -4192,7 +4271,7 @@

        6.4.3.1 prepare()

        Zero (OK) means the event was successfully processed and that the driver is prepared for the PM state change. Non-zero means that the driver is not prepared to perform the tasks needed achieve this power setting and will cause the state change to be aborted. NOTE: The prepare() method will also be called when reverting from lower back to higher power consumption modes (say because another driver refused a lower power state change). - Drivers are not permitted to return non-zero values when reverting back to higher power + Drivers are not permitted to return non-zero values when reverting back to higher power consumption modes!

        @@ -4391,7 +4470,7 @@

        Build Options

        If the 2 pass build option is selected, then these options configure the make system build a extra link object. This link object is assumed to be an incremental (relative) link object, but could be a static library (archive) (some modification to this Makefile would be required if CONFIG_PASS1_TARGET generates an archive). - Pass 1 1ncremental (relative) link objects should be put into the processor-specific source directory + Pass 1 1ncremental (relative) link objects should be put into the processor-specific source directory where other link objects will be created - ff the pass1 obect is an archive, it could go anywhere.

          @@ -4423,7 +4502,7 @@

          Build Options

        • CONFIG_PASS1_OBJECT: May be used to include an extra, pass1 object into the final link. - This would probably be the object generated from the CONFIG_PASS1_TARGET. + This would probably be the object generated from the CONFIG_PASS1_TARGET. It may be available at link time in the arch/<architecture>/src directory.
        @@ -4584,7 +4663,7 @@

        General OS setup

        be disabled by setting this value to zero.
      • - CONFIG_SCHED_INSTRUMENTATION: enables instrumentation in + CONFIG_SCHED_INSTRUMENTATION: enables instrumentation in scheduler to monitor system performance
      • @@ -5024,7 +5103,7 @@

        General OS setup

        In some architectures, it may be necessary to take some memory from the end of RAM for page tables or other system usage. The configuration settings and linker directives must be cognizant of that: - CONFIG_PAGING_NDATA should be defined to prevent the data region from extending all the way to the end of memory. + CONFIG_PAGING_NDATA should be defined to prevent the data region from extending all the way to the end of memory.
      • CONFIG_PAGING_DEFPRIO: @@ -5058,7 +5137,7 @@

        General OS setup

        Default: No timeouts monitored.

        • - Some architecture-specific settings. + Some architecture-specific settings. Defaults are architecture specific. If you don't know what you are doing, it is best to leave these undefined and try the system defaults:

        @@ -5198,7 +5277,7 @@

        Allow for architecture optimized implementations

        • CONFIG_MEMCPY_VIK: Select this option to use the optimized memcpy() function by Daniel Vik. - Select this option for improved performance at the expense of increased size. + Select this option for improved performance at the expense of increased size. See licensing information in the top-level COPYING file. Default: n.
        @@ -5440,7 +5519,7 @@

        File Systems

        CONFIG_FS_NXFFS: Enable NuttX FLASH file system (NXFF) support.
      • - CONFIG_NXFFS_ERASEDSTATE: The erased state of FLASH. + CONFIG_NXFFS_ERASEDSTATE: The erased state of FLASH. This must have one of the values of 0xff or 0x00. Default: 0xff.
        • @@ -5491,7 +5570,7 @@

        RTC

        • CONFIG_RTC: - Enables general support for a hardware RTC. + Enables general support for a hardware RTC. Specific architectures may require other specific settings.
        • @@ -5517,7 +5596,7 @@

          RTC

        • CONFIG_RTC_ALARM: - Enable if the RTC hardware supports setting of an alarm. + Enable if the RTC hardware supports setting of an alarm. A callback function will be executed when the alarm goes off
        @@ -5740,7 +5819,7 @@

        Input Devices

      • CONFIG_STMPE811_NPOLLWAITERS: - Maximum number of threads that can be waiting on poll() (ignored if + Maximum number of threads that can be waiting on poll() (ignored if CONFIG_DISABLE_POLL is set).
      • @@ -6033,7 +6112,7 @@

        THTTPD

        text MIME types.
      • - CONFIG_THTTPD_IOBUFFERSIZE: + CONFIG_THTTPD_IOBUFFERSIZE:
      • CONFIG_THTTPD_INDEX_NAMES: A list of index filenames to check. The @@ -6087,7 +6166,7 @@

        THTTPD

        You can also leave both options undefined, and thttpd will not do anything special about tildes. Enabling both options is an error. Typical values, if they're defined, are "users" for - CONFIG_THTTPD_TILDE_MAP1 and "public_html" forCONFIG_THTTPD_TILDE_MAP2. + CONFIG_THTTPD_TILDE_MAP1 and "public_html" forCONFIG_THTTPD_TILDE_MAP2.
      • CONFIG_THTTPD_GENERATE_INDICES: @@ -6157,7 +6236,7 @@

        USB Device Controller Driver

      -

      USB Serial Device Class Driver (Prolific PL2303 Emulation)

      +

      USB Serial Device Class Driver (Prolific PL2303 Emulation)

      • CONFIG_PL2303: Enable compilation of the USB serial driver @@ -6197,14 +6276,14 @@

        USB serial device class driver (Standard CDC ACM class)

      • CONFIG_CDCACM_IFNOBASE: - If the CDC driver is part of a composite device, then this may need to + If the CDC driver is part of a composite device, then this may need to be defined to offset the CDC/ACM interface numbers so that they are unique and contiguous. When used with the Mass Storage driver, the correct value for this offset is zero.
      • CONFIG_CDCACM_STRBASE: - If the CDC driver is part of a composite device, then this may need to + If the CDC driver is part of a composite device, then this may need to be defined to offset the CDC/ACM string numbers so that they are unique and contiguous. When used with the Mass Storage driver, the correct value for this offset is four (this value actuallly only needs @@ -6275,7 +6354,7 @@

        USB Storage Device Configuration

      • CONFIG_USBMSC_IFNOBASE: - If the CDC driver is part of a composite device, then this may need to + If the CDC driver is part of a composite device, then this may need to be defined to offset the mass storage interface number so that it is unique and contiguous. When used with the CDC/ACM driver, the correct value for this offset is two (because of the two CDC/ACM @@ -6283,7 +6362,7 @@

        USB Storage Device Configuration

      • CONFIG_USBMSC_STRBASE: - If the CDC driver is part of a composite device, then this may need to + If the CDC driver is part of a composite device, then this may need to be defined to offset the mass storage string numbers so that they are unique and contiguous. When used with the CDC/ACM driver, the correct value for this offset is four (or perhaps 5 or 6, depending diff --git a/nuttx/Documentation/README.html b/nuttx/Documentation/README.html index 7161abf070..5879339c92 100644 --- a/nuttx/Documentation/README.html +++ b/nuttx/Documentation/README.html @@ -8,7 +8,7 @@

        NuttX README Files

        -

        Last Updated: February 22, 2013

        +

        Last Updated: June 10, 2013

        @@ -186,6 +186,8 @@

        NuttX README Files

        | | | `- README.txt | | |- sam4l-xplained/ | | | `- README.txt + | | |- sam4s-xplained/ + | | | `- README.txt | | |- shenzhou/ | | | `- README.txt | | |- sim/ diff --git a/nuttx/Kconfig b/nuttx/Kconfig index 28f0464fdf..ac1c68cc75 100644 --- a/nuttx/Kconfig +++ b/nuttx/Kconfig @@ -497,7 +497,7 @@ config DEBUG_AUDIO default n ---help--- Enable low level debug SYSLOG output from the audio subsystem and - device drivers. (disabled by default). Support for this debug option + device drivers. (disabled by default). Support for this debug option is architecgture-specific and may not be available for some MCUs. endif diff --git a/nuttx/README.txt b/nuttx/README.txt index 142ca872ac..1fc124e7d7 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -1114,6 +1114,8 @@ nuttx | | `- README.txt | |- sam4l-xplained/ | | `- README.txt + | |- sam4s-xplained/ + | | `- README.txt | |- sim/ | | |- include/README.txt | | |- src/README.txt diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig index 92a4275ce0..9e9a77df22 100644 --- a/nuttx/arch/arm/Kconfig +++ b/nuttx/arch/arm/Kconfig @@ -115,6 +115,7 @@ config ARCH_CHIP_NUC1XX config ARCH_CHIP_SAM34 bool "Atmel AT91SAM3/SAM4" select ARCH_HAVE_MPU + select ARCH_HAVE_RAMFUNCS ---help--- Atmel AT91SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures diff --git a/nuttx/arch/arm/include/sam34/chip.h b/nuttx/arch/arm/include/sam34/chip.h index e5c5fa6748..d40952d7af 100644 --- a/nuttx/arch/arm/include/sam34/chip.h +++ b/nuttx/arch/arm/include/sam34/chip.h @@ -54,20 +54,20 @@ /* Internal memory */ -# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */ -# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ -# define CONFIG_SAM34_SRAM1_SIZE (16*1024) /* 16Kb */ -# define CONFIG_SAM34_NFCSRAM_SIZE (4*1024) /* 4Kb */ +# define SAM34_FLASH_SIZE (256*1024) /* 256KB */ +# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ +# define SAM34_SRAM1_SIZE (16*1024) /* 16KB */ +# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */ /* Peripherals */ -# define SAM34_NDMACHAN 4 /* 4 DMA Channels */ -# define SAM34_NMCI2 1 /* 1 memory card interface */ -# define SAM32_NSLCD 0 /* No segment LCD interface */ -# define SAM32_NAESA 0 /* No advanced encryption standard */ -# define SAM32_NUDPHS 1 /* One USB high speed device */ -# define SAM32_NUDPFS 0 /* No USB full speed device */ -# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ +# define SAM34_NDMACHAN 4 /* 4 DMA Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 1 /* One USB high speed device */ +# define SAM32_NUDPFS 0 /* No USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ /* AT91SAM4L Family *****************************************************************/ /* Sub-family differences: @@ -123,84 +123,85 @@ /* Internal memory */ -# define CONFIG_SAM34_FLASH_SIZE (128*1024) /* 128Kb */ -# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ -# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ -# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_FLASH_SIZE (128*1024) /* 128KB */ +# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ /* Peripherals */ -# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ -# define SAM34_NMCI2 0 /* No memory card interface */ -# define SAM32_NSLCD 1 /* 1 segment LCD interface */ -# define SAM32_NAESA 1 /* 1 advanced encryption standard */ -# define SAM32_NUDPHS 0 /* No USB high speed device */ -# define SAM32_NUDPFS 1 /* 1 USB full speed device */ -# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 1 /* 1 segment LCD interface */ +# define SAM32_NAESA 1 /* 1 advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ #elif defined(CONFIG_ARCH_CHIP_ATSAM4LC4C) || defined (CONFIG_ARCH_CHIP_ATSAM4LC4B) || \ defined(CONFIG_ARCH_CHIP_ATSAM4LC4A) /* Internal memory */ -# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */ -# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ -# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ -# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_FLASH_SIZE (256*1024) /* 256KB */ +# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ /* Peripherals */ -# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ -# define SAM34_NMCI2 0 /* No memory card interface */ -# define SAM32_NSLCD 1 /* 1 segment LCD interface */ -# define SAM32_NAESA 1 /* 1 advanced encryption standard */ -# define SAM32_NUDPHS 0 /* No USB high speed device */ -# define SAM32_NUDPFS 1 /* 1 USB full speed device */ -# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 1 /* 1 segment LCD interface */ +# define SAM32_NAESA 1 /* 1 advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ #elif defined(CONFIG_ARCH_CHIP_ATSAM4LS2C) || defined (CONFIG_ARCH_CHIP_ATSAM4LS2B) || \ defined(CONFIG_ARCH_CHIP_ATSAM4LS2A) /* Internal memory */ -# define CONFIG_SAM34_FLASH_SIZE (128*1024) /* 128Kb */ -# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ -# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ -# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_FLASH_SIZE (128*1024) /* 128KB */ +# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ /* Peripherals */ -# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ -# define SAM34_NMCI2 0 /* No memory card interface */ -# define SAM32_NSLCD 0 /* No segment LCD interface */ -# define SAM32_NAESA 0 /* No advanced encryption standard */ -# define SAM32_NUDPHS 0 /* No USB high speed device */ -# define SAM32_NUDPFS 1 /* 1 USB full speed device */ -# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ #elif defined(CONFIG_ARCH_CHIP_ATSAM4LS4C) || defined (CONFIG_ARCH_CHIP_ATSAM4LS4B) || \ defined(CONFIG_ARCH_CHIP_ATSAM4LS4A) /* Internal memory */ -# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */ -# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ -# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ -# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_FLASH_SIZE (256*1024) /* 256KB */ +# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ /* Peripherals */ -# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ -# define SAM34_NMCI2 0 /* No memory card interface */ -# define SAM32_NSLCD 0 /* No segment LCD interface */ -# define SAM32_NAESA 0 /* No advanced encryption standard */ -# define SAM32_NUDPHS 0 /* No USB high speed device */ -# define SAM32_NUDPFS 1 /* 1 USB full speed device */ -# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ /* AT91SAM4S Family *****************************************************************/ /* * FEATURE SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B + * ------------- --------- --------- --------- --------- --------- --------- -------- -------- ------- ------- * Flash 2x1MB 2x1MB 2x512KB 1x1MB 1x1MB 1x1MB 1x1MB 1x1MB 1x512KB 1x512KB * SRAM 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB * HCACHE 2KB 2KB 2KB 2KB 2KB 2KB - - - - @@ -217,25 +218,184 @@ */ #elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32C) -# error To be provided +/* Internal memory */ + +# define SAM34_FLASH_SIZE (2*1024*1024) /* 2x1MB */ +# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 22 /* 22 PDC Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + #elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32B) -# error To be provided +/* Internal memory */ + +# define SAM34_FLASH_SIZE (2*1024*1024) /* 2x1MB */ +# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 22 /* 22 PDC Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + #elif defined(CONFIG_ARCH_CHIP_ATSAM4SD16C) -# error To be provided +/* Internal memory */ + +# define SAM34_FLASH_SIZE (1024*1024) /* 2x512KB */ +# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 22 /* 22 PDC Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + #elif defined(CONFIG_ARCH_CHIP_ATSAM4SD16B) -# error To be provided +/* Internal memory */ + +# define SAM34_FLASH_SIZE (1024*1024) /* 2x512KB */ +# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 22 /* 22 PDC Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + #elif defined(CONFIG_ARCH_CHIP_ATSAM4SA16C) -# error To be provided +/* Internal memory */ + +# define SAM34_FLASH_SIZE (1024*1024) /* 1MB */ +# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 22 /* 22 PDC Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + #elif defined(CONFIG_ARCH_CHIP_ATSAM4SA16B) -# error To be provided +/* Internal memory */ + +# define SAM34_FLASH_SIZE (1024*1024) /* 1MB */ +# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 22 /* 22 PDC Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + #elif defined(CONFIG_ARCH_CHIP_ATSAM4S16C) -# error To be provided +/* Internal memory */ + +# define SAM34_FLASH_SIZE (1024*1024) /* 1MB */ +# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 22 /* 22 PDC Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + #elif defined(CONFIG_ARCH_CHIP_ATSAM4S16B) -# error To be provided +/* Internal memory */ + +# define SAM34_FLASH_SIZE (1024*1024) /* 1MB */ +# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 22 /* 22 PDC Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + #elif defined(CONFIG_ARCH_CHIP_ATSAM4S8C) -# error To be provided +/* Internal memory */ + +# define SAM34_FLASH_SIZE (512*1024) /* 512KB */ +# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 22 /* 22 PDC Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + #elif defined(CONFIG_ARCH_CHIP_ATSAM4S8B) -# error To be provided +/* Internal memory */ + +# define SAM34_FLASH_SIZE (512*1024) /* 512KB */ +# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */ +# define SAM34_SRAM1_SIZE (0) /* None */ +# define SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 22 /* 22 PDC Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ #else # error "Unknown SAM3/4 chip type" diff --git a/nuttx/arch/arm/include/sam34/irq.h b/nuttx/arch/arm/include/sam34/irq.h index ea93b22b7d..4925273eb2 100644 --- a/nuttx/arch/arm/include/sam34/irq.h +++ b/nuttx/arch/arm/include/sam34/irq.h @@ -81,6 +81,8 @@ # include #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include #else # error Unrecognized SAM architecture #endif diff --git a/nuttx/arch/arm/include/sam34/sam3u_irq.h b/nuttx/arch/arm/include/sam34/sam3u_irq.h index 58f2afd946..9f7c4d771b 100644 --- a/nuttx/arch/arm/include/sam34/sam3u_irq.h +++ b/nuttx/arch/arm/include/sam34/sam3u_irq.h @@ -58,7 +58,7 @@ #define SAM_PID_PMC (5) /* Power Management Controller */ #define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */ #define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */ -#define SAM_PID_UART (8) /* Universal Asynchronous Receiver Transmitter */ +#define SAM_PID_UART0 (8) /* Universal Asynchronous Receiver Transmitter */ #define SAM_PID_SMC (9) /* Static Memory Controller */ #define SAM_PID_PIOA (10) /* Parallel I/O Controller A */ #define SAM_PID_PIOB (11) /* Parallel I/O Controller B */ @@ -92,7 +92,7 @@ #define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */ #define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* Enhanced Embedded Flash Controller 0 */ #define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* Enhanced Embedded Flash Controller 1 */ -#define SAM_IRQ_UART (SAM_IRQ_EXTINT+SAM_PID_UART) /* Universal Asynchronous Receiver Transmitter */ +#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter */ #define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* Static Memory Controller */ #define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */ #define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */ diff --git a/nuttx/arch/arm/include/sam34/sam4s_irq.h b/nuttx/arch/arm/include/sam34/sam4s_irq.h new file mode 100644 index 0000000000..9bef95f4da --- /dev/null +++ b/nuttx/arch/arm/include/sam34/sam4s_irq.h @@ -0,0 +1,286 @@ +/**************************************************************************************** + * arch/arm/include/sam34/sam4s_irq.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM4S_IRQ_H +#define __ARCH_ARM_INCLUDE_SAM34_SAM4S_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +/**************************************************************************************** + * Definitions + ****************************************************************************************/ + +/* SAM4S Peripheral Identifiers */ + +#define SAM_PID_SUPC (0) /* Supply Controller */ +#define SAM_PID_RSTC (1) /* Reset Controller */ +#define SAM_PID_RTC (2) /* Real Time Clock */ +#define SAM_PID_RTT (3) /* Real Time Timer */ +#define SAM_PID_WDT (4) /* Watchdog Timer */ +#define SAM_PID_PMC (5) /* Power Management Controller */ +#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */ +#define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */ +#define SAM_PID_UART0 (8) /* Universal Asynchronous Receiver Transmitter 0 */ +#define SAM_PID_UART1 (9) /* Universal Asynchronous Receiver Transmitter 1 */ +#define SAM_PID_SMC (10) /* Static Memory Controller */ +#define SAM_PID_PIOA (11) /* Parallel I/O Controller A */ +#define SAM_PID_PIOB (12) /* Parallel I/O Controller B */ +#define SAM_PID_PIOC (13) /* Parallel I/O Controller C */ +#define SAM_PID_USART0 (14) /* USART 0 */ +#define SAM_PID_USART1 (15) /* USART 1 */ +#define SAM_PID_RESERVED_16 (16) /* Reserved */ +#define SAM_PID_RESERVED_17 (17) /* Reserved */ +#define SAM_PID_HSMCI (18) /* High Speed Multimedia Card Interface */ +#define SAM_PID_TWI0 (19) /* Two-Wire Interface 0 */ +#define SAM_PID_TWI1 (20) /* Two-Wire Interface 1 */ +#define SAM_PID_SPI (21) /* Serial Peripheral Interface */ +#define SAM_PID_SSC (22) /* Synchronous Serial Controller */ +#define SAM_PID_TC0 (23) /* Timer Counter 0 */ +#define SAM_PID_TC1 (24) /* Timer Counter 1 */ +#define SAM_PID_TC2 (25) /* Timer Counter 2 */ +#define SAM_PID_TC3 (26) /* Timer Counter 3 */ +#define SAM_PID_TC4 (27) /* Timer Counter 4 */ +#define SAM_PID_TC5 (28) /* Timer Counter 5 */ +#define SAM_PID_ADC (29) /* Analog To Digital Converter */ +#define SAM_PID_DACC (30) /* Digital To Analog Converter */ +#define SAM_PID_PWM (31) /* Pulse Width Modulation */ +#define SAM_PID_CRCCU (32) /* CRC Calculation Unit */ +#define SAM_PID_ACC (33) /* Analog Comparator */ +#define SAM_PID_UDP (34) /* USB Device Port */ +#define NR_PIDS (35) /* Number of peripheral identifiers */ + +/* External interrupts (vectors >= 16) */ + +#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* PID 0: Supply Controller */ +#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* PID 1: Reset Controller */ +#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* PID 2: Real Time Clock */ +#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* PID 3: Real Time Timer */ +#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* PID 4: Watchdog Timer */ +#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* PID 5: Power Management Controller */ +#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* PID 6: Enhanced Embedded Flash Controller 0 */ +#define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* PID 7: Enhanced Embedded Flash Controller 1 */ +#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* PID 8: Universal Asynchronous Receiver Transmitter 0 */ +#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* PID 9: Universal Asynchronous Receiver Transmitter 1 */ +#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* PID 10: Static Memory Controller */ +#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* PID 11: Parallel I/O Controller A */ +#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* PID 12: Parallel I/O Controller B */ +#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* PID 13: Parallel I/O Controller C */ +#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* PID 14: USART 0 */ +#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* PID 15: USART 1 */ +#define SAM_IRQ_RESERVED_16 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_16) /* PID 16: Reserved */ +#define SAM_IRQ_RESERVED_17 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_17) /* PID 17: Reserved */ +#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* PID 18: High Speed Multimedia Card Interface */ +#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* PID 19: Two-Wire Interface 0 */ +#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* PID 20: Two-Wire Interface 1 */ +#define SAM_IRQ_SPI (SAM_IRQ_EXTINT+SAM_PID_SPI) /* PIC 21: Serial Peripheral Interface */ +#define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* PID 22: Synchronous Serial Controller */ +#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* PID 23: Timer Counter 0 */ +#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* PID 24: Timer Counter 1 */ +#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* PID 25: Timer Counter 2 */ +#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+SAM_PID_TC3) /* PID 26: Timer Counter 3 */ +#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+SAM_PID_TC4) /* PID 27: Timer Counter 4 */ +#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* PID 28: Timer Counter 5 */ +#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* PID 29: Analog To Digital Converter */ +#define SAM_IRQ_DACC (SAM_IRQ_EXTINT+SAM_PID_DACC) /* PID 30: Digital To Analog Converter */ +#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* PID 31: Pulse Width Modulation */ +#define SAM_IRQ_CRCCU (SAM_IRQ_EXTINT+SAM_PID_CRCCU) /* PID 32: CRC Calculation Unit */ +#define SAM_IRQ_ACC (SAM_IRQ_EXTINT+SAM_PID_ACC) /* PID 33: Analog Comparator */ +#define SAM_IRQ_UDP (SAM_IRQ_EXTINT+SAM_PID_UDP) /* PID 34: USB Device Port */ + +#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */ +#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT + NR_PIDS) /* The number of real IRQs */ + +/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */ + +#ifdef CONFIG_GPIOA_IRQ +# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT) +# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */ +# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */ +# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */ +# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */ +# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */ +# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */ +# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */ +# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */ +# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */ +# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */ +# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */ +# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */ +# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */ +# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */ +# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */ +# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */ +# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */ +# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */ +# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */ +# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */ +# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */ +# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */ +# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */ +# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */ +# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */ +# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */ +# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */ +# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */ +# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */ +# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */ +# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */ +# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOAIRQS 0 +#endif + +#ifdef CONFIG_GPIOB_IRQ +# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_IRQ_GPIOA_PINS) +# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */ +# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */ +# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */ +# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */ +# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */ +# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */ +# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */ +# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */ +# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */ +# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */ +# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */ +# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */ +# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */ +# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */ +# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */ +# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */ +# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */ +# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */ +# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */ +# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */ +# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */ +# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */ +# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */ +# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */ +# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */ +# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */ +# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */ +# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */ +# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */ +# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */ +# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */ +# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOBIRQS 0 +#endif + +#ifdef CONFIG_GPIOC_IRQ +# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_IRQ_GPIOA_PINS + SAM_IRQ_GPIOB_PINS) +# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */ +# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */ +# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */ +# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */ +# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */ +# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */ +# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */ +# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */ +# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */ +# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */ +# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */ +# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */ +# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */ +# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */ +# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */ +# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */ +# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */ +# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */ +# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */ +# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */ +# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */ +# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */ +# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */ +# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */ +# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */ +# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */ +# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */ +# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */ +# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */ +# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */ +# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */ +# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOCIRQS 0 +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT + \ + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Inline functions + ****************************************************************************************/ + +/**************************************************************************************** + * Public Variables + ****************************************************************************************/ + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM4S_IRQ_H */ + diff --git a/nuttx/arch/arm/src/armv7-m/nvic.h b/nuttx/arch/arm/src/armv7-m/nvic.h index e6d6f8e9e1..2d76e4e6b6 100644 --- a/nuttx/arch/arm/src/armv7-m/nvic.h +++ b/nuttx/arch/arm/src/armv7-m/nvic.h @@ -399,8 +399,8 @@ /* Interrrupt controller type (INCTCTL_TYPE) */ -#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 4-0: Number of interrupt intputs / 32 */ -#define NVIC_ICTR_INTLINESNUM_MASK (0x1f << NVIC_ICTR_INTLINESNUM_SHIFT) +#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 0-3: Number of interrupt inputs / 32 - 1 */ +#define NVIC_ICTR_INTLINESNUM_MASK (15 << NVIC_ICTR_INTLINESNUM_SHIFT) /* SysTick control and status register (SYSTICK_CTRL) */ diff --git a/nuttx/arch/arm/src/lpc17xx/Kconfig b/nuttx/arch/arm/src/lpc17xx/Kconfig index 6f8967054c..ff383bae4a 100644 --- a/nuttx/arch/arm/src/lpc17xx/Kconfig +++ b/nuttx/arch/arm/src/lpc17xx/Kconfig @@ -335,20 +335,6 @@ config SERIAL_TERMIOS If this is not defined, then the terminal settings (baud, parity, etc). are not configurable at runtime; serial streams cannot be flushed, etc.. -config UART0_FLOWCONTROL - bool "UART0 flow control" - depends on LPC17_UART0 - default n - ---help--- - Enable UART0 flow control - -config UART1_FLOWCONTROL - bool "UART1 flow control" - depends on LPC17_UART1 - default n - ---help--- - Enable UART1 flow control - config UART1_RINGINDICATOR bool "UART1 ring indicator" depends on LPC17_UART1 @@ -356,20 +342,6 @@ config UART1_RINGINDICATOR ---help--- Enable UART1 ring indicator -config UART2_FLOWCONTROL - bool "UART0 flow control" - depends on LPC17_UART2 - default n - ---help--- - Enable UART2 flow control - -config UART3_FLOWCONTROL - bool "UART3 flow control" - depends on LPC17_UART3 - default n - ---help--- - Enable UART3 flow control - endmenu menu "ADC driver options" diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c b/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c index 9ff0eab60c..3926c87126 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c @@ -359,7 +359,7 @@ void lpc17_lowsetup(void) #elif defined(CONFIG_UART1_SERIAL_CONSOLE) lpc17_configgpio(GPIO_UART1_TXD); lpc17_configgpio(GPIO_UART1_RXD); -#ifdef CONFIG_UART1_FLOWCONTROL +#if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL) lpc17_configgpio(GPIO_UART1_CTS); lpc17_configgpio(GPIO_UART1_DCD); lpc17_configgpio(GPIO_UART1_DSR); diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c index 6bf519ac30..ed1a378147 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c @@ -736,7 +736,7 @@ static inline void lpc17_uart1config(void) lpc17_configgpio(GPIO_UART1_TXD); lpc17_configgpio(GPIO_UART1_RXD); -#ifdef CONFIG_UART1_FLOWCONTROL +#if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL) lpc17_configgpio(GPIO_UART1_CTS); lpc17_configgpio(GPIO_UART1_RTS); lpc17_configgpio(GPIO_UART1_DCD); @@ -943,10 +943,16 @@ static int up_setup(struct uart_dev_s *dev) /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */ -#ifdef CONFIG_UART1_FLOWCONTROL +#if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL) if (priv->uartbase == LPC17_UART1_BASE) { +#if defined(CONFIG_UART1_IFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL) up_serialout(priv, LPC17_UART_MCR_OFFSET, (UART_MCR_RTSEN|UART_MCR_CTSEN)); +#elif defined(CONFIG_UART1_IFLOWCONTROL) + up_serialout(priv, LPC17_UART_MCR_OFFSET, UART_MCR_RTSEN); +#else + up_serialout(priv, LPC17_UART_MCR_OFFSET, UART_MCR_CTSEN); +#endif } #endif diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h index 95e8155de8..3db62f7f8a 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_serial.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -96,11 +96,15 @@ /* Check UART flow control (Only supported by UART1) */ -# undef CONFIG_UART0_FLOWCONTROL -# undef CONFIG_UART2_FLOWCONTROL -# undef CONFIG_UART3_FLOWCONTROL +# undef CONFIG_UART0_IFLOWCONTROL +# undef CONFIG_UART0_OFLOWCONTROL +# undef CONFIG_UART2_IFLOWCONTROL +# undef CONFIG_UART2_OFLOWCONTROL +# undef CONFIG_UART3_IFLOWCONTROL +# undef CONFIG_UART3_OFLOWCONTROL #ifndef CONFIG_LPC17_UART1 -# undef CONFIG_UART1_FLOWCONTROL +# undef CONFIG_UART1_IFLOWCONTROL +# undef CONFIG_UART1_OFLOWCONTROL #endif /* We cannot allow the DLM/DLL divisor to become to small or will will lose too diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig index b26dec6598..bcc5ebab9c 100644 --- a/nuttx/arch/arm/src/sam34/Kconfig +++ b/nuttx/arch/arm/src/sam34/Kconfig @@ -3,10 +3,10 @@ # see misc/tools/kconfig-language.txt. # -comment "AT91SAM3/SAM4 Configuration Options" +comment "AT91SAM3/4 Configuration Options" choice - prompt "AT91SAM3 Chip Selection" + prompt "AT91SAM3/4 Chip Selection" default ARCH_CHIP_AT91SAM3U4E depends on ARCH_CHIP_SAM34 @@ -75,52 +75,52 @@ config ARCH_CHIP_ATSAM4LS4A select ARCH_CORTEXM4 select ARCH_CHIP_SAM4L -config CONFIG_ARCH_CHIP_ATSAM4SD32C +config ARCH_CHIP_ATSAM4SD32C bool "ATSAM4SD32C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4SD32B +config ARCH_CHIP_ATSAM4SD32B bool "ATSAM4SD32B" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4SD16C +config ARCH_CHIP_ATSAM4SD16C bool "ATSAM4SD16C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4SD16B +config ARCH_CHIP_ATSAM4SD16B bool "ATSAM4SD16B" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4SA16C +config ARCH_CHIP_ATSAM4SA16C bool "ATSAM4SA16C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4SA16B +config ARCH_CHIP_ATSAM4SA16B bool "ATSAM4SA16B" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4S16C +config ARCH_CHIP_ATSAM4S16C bool "ATSAM4S16C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4S16B +config ARCH_CHIP_ATSAM4S16B bool "ATSAM4S16B" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4S8C +config ARCH_CHIP_ATSAM4S8C bool "ATSAM4S8C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4S8B +config ARCH_CHIP_ATSAM4S8B bool "ATSAM4S8B" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S @@ -134,59 +134,305 @@ config ARCH_CHIP_SAM3U config ARCH_CHIP_SAM4L bool default n + select ARCH_RAMFUNCS config ARCH_CHIP_SAM4S bool default n -menu "AT91SAM3 Peripheral Support" +menu "AT91SAM3/4 Peripheral Support" config SAM_PICOCACHE bool "PICOCACHE" - depends on ARCH_CHIP_SAM4L default y + depends on ARCH_CHIP_SAM4L -config SAM34_DMA - bool "DMA" +config SAM34_OCD + bool "On-chip DEBUG" + depends on ARCH_CHIP_SAM4L + default y if DEBUG_SYMBOLS + default n if !DEBUG_SYMBOLS + +config SAM34_APBA + bool "APBA bridge" default n - select ARCH_DMA + depends on ARCH_CHIP_SAM4L -config SAM34_NAND - bool "NAND support" +config SAM34_AESA + bool "Advanced Encryption Standard (AESA)" default n + depends on ARCH_CHIP_SAM4L -config SAM34_HSMCI - bool "HSMCI" +config SAM34_IISC + bool "Inter-IC Sound (I2S) Controller" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_SPI + bool "Serial Peripheral Interface (SPI)" + default n + +config SAM34_SSC + bool "Synchronous Serial Controller (SSC)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + +config SAM34_TC0 + bool "Timer/Counter 0 (TC0)" + default n + +config SAM34_TC1 + bool "Timer/Counter 1 (TC1)" + default n + +config SAM34_TC2 + bool "Timer/Counter 2 (TC2)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + +config SAM34_TC3 + bool "Timer/Counter 3 (TC3)" + default n + depends on ARCH_CHIP_SAM4S + +config SAM34_TC4 + bool "Timer/Counter 4 (TC4)" default n + depends on ARCH_CHIP_SAM4S -config SAM34_UART - bool "UART" +config SAM34_TC5 + bool "Timer/Counter 5 (TC5)" + default n + depends on ARCH_CHIP_SAM4S + +config SAM34_PWM + bool "Pulse Width Modulation (PWM) Controller" + default n + depends on ARCH_CHIP_SAM3U|| ARCH_CHIP_SAM4S + +config SAM34_TWIM0 + bool "Two-wire Master Interface 0 (TWIM0)" + default n + +config SAM34_TWIS0 + bool "Two-wire Slave Interface 0 (TWIS0)" + default n + +config SAM34_TWIM1 + bool "Two-wire Master Interface 1 (TWIM1)" + default n + +config SAM34_TWIS1 + bool "Two-wire Slave Interface 1 (TWIS1)" + default n + +config SAM34_TWIM2 + bool "Two-wire Master Interface 2 (TWIM2)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_TWIM3 + bool "Two-wire Master Interface 3 (TWIM3)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_UART0 + bool "UART 0" default y + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + select ARCH_HAVE_UART0 + +config SAM34_UART1 + bool "UART 1" + default n + depends on ARCH_CHIP_SAM4S + select ARCH_HAVE_UART1 + +config SAM34_PICOUART + bool "PicoUART" + default n + depends on ARCH_CHIP_SAM4L select ARCH_HAVE_UART config SAM34_USART0 - bool "USART0" + bool "USART 0" default n + select ARCH_HAVE_USART0 config SAM34_USART1 - bool "USART1" + bool "USART 1" default n + select ARCH_HAVE_USART1 config SAM34_USART2 - bool "USART2" + bool "USART 2" default n + select ARCH_HAVE_USART2 + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L config SAM34_USART3 - bool "USART3" + bool "USART 3" default n + select ARCH_HAVE_USART3 + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L -config SAM34_SPI - bool "SPI" +config SAM34_ADC12B + bool "12-bit ADC Controller" + default n + +config SAM34_ADC + bool "10-bit ADC Controller" + default n + depends on ARCH_CHIP_SAM3U + +config SAM34_DACC + bool "Digital To Analog Converter (DAC)" + default n + depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S + +config SAM34_ACC + bool "Analog Comparator (AC)" + default n + depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S + +config SAM34_GLOC + bool "GLOC" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_ABDACB + bool "Audio Bitstream DAC (ABDAC)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_TRNG + bool "True Random Number Generator (TRNG)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_PARC + bool "Parallel Capture (PARC)" default n + depends on ARCH_CHIP_SAM4L + +config SAM34_CATB + bool "Capacitive Touch Module B (CATB)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_LCDCA + bool "LCD Controller A (LCDCA)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_HRAMC1 + bool "HRAMC1 (picoCache RAM)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_SMC + bool "Static Memory Controller (SMC)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + +config SAM34_NAND + bool "NAND support" + default n + depends on ARCH_CHIP_SAM3U + +config SAM34_HMATRIX + bool "HMATRIX" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_PDCA + bool "Peripheral DMA controller (PDC)" + default n + depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S + select ARCH_DMA + +config SAM34_DMA + bool "DMA controller" + default n + depends on ARCH_CHIP_SAM3U + select ARCH_DMA + +config SAM34_CRCCU + bool "CRC Calculation Unit" + default n + depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S + +config SAM34_UDPHS + bool "USB Device High Speed" + default n + depends on ARCH_CHIP_SAM3U + +config SAM34_UDP + bool "USB Device Full Speed" + default n + depends on ARCH_CHIP_SAM4S + +config SAM34_USBC + bool "USB 2.0 Interface" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_PEVC + bool "Peripheral Event Controller" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_CHIPID + bool "Chip ID" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_FREQM + bool "Frequency Meter (FREQM)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_AST + bool "Asynchronous Timer (AST)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_RTC + bool "Real Time Clock (RTC)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + +config SAM34_RTT + bool "Real Time Timer (RTT)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + +config SAM34_WDT + bool "Watchdog Timer (WDT)" + default n + +config SAM34_EIC + bool "External Interrupt Controller (EIC)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_HSMCI + bool "High Speed Multimedia Card Interface (HSMCI)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S endmenu -menu "AT91SAM3 UART Configuration" +config SAM32_RESET_PERIPHCLKS + bool "Enable all peripheral clocks on reset" + default n + depends on ARCH_CHIP_SAM4L + ---help--- + By default, only a few necessary peripheral clocks are enabled at + reset. If this setting is enabled, then all clocking will be enabled + to all of the selected peripherals on reset. + +comment "AT91SAM3/4 USART Configuration" config USART0_ISUART bool "USART0 is a UART" @@ -212,9 +458,13 @@ config USART3_ISUART depends on SAM34_USART3 select ARCH_HAVE_USART2 -endmenu +comment "AT91SAM3/4 GPIO Interrupt Configuration" +config GPIO_IRQ + bool "GPIO pin interrupts" + ---help--- + Enable support for interrupting GPIO pins -menu "AT91SAM3 GPIO Interrupt Configuration" +if GPIO_IRQ config GPIOA_IRQ bool "GPIOA interrupts" @@ -228,4 +478,30 @@ config GPIOC_IRQ bool "GPIOC interrupts" default n -endmenu +endif + +if SAM34_WDT +comment "AT91SAM3/4 Watchdog Configuration"| + +config WDT_ENABLED_ON_RESET + bool "Enabled on reset" + default n + ---help--- + The WDT can be enabled at reset. This is controlled by the WDTAUTO + fuse. The WDT will be set in basic mode, RCSYS is set as source for + CLK_CNT, and PSEL will be set to a value giving Tpsel above 100 ms + (SAM4L) + + This setting informs that start-up logic that the watchdog is + enabled. + +config WDT_DISABLE_ON_RESET + bool "Disable on reset" + default n + depends on WDT_ENABLED_ON_RESET + ---help--- + If the WDT can be enabled at reset then this setting may be used to + configure and disable the watchdog timer very early in the boot + sequence. + +endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h index 05ffad19be..974aef0cd5 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_eefc.h + * Enhanced Embedded Flash Controller (EEFC) defintions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -74,20 +75,38 @@ #define SAM_EEFC1_FRR (SAM_EEFC1_BASE+SAM_EEFC_FRR_OFFSET) /* EEFC register bit definitions ********************************************************/ +/* EEFC Flash Mode Register */ #define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */ #define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */ #define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FMR_SCOD (1 << 16) /* Bit 16: Sequential Code Optimization Disable */ +#endif + #define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FMR_CLOE (1 << 26) /* Bit 26: Code Loops Optimization Enable */ +#endif + +/* EEFC Flash Command Register */ + #define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */ #define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT) + # define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */ # define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */ # define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */ # define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */ # define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */ # define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FCR_FCMD_EPA (7 << EEFC_FCR_FCMD_SHIFT) /* Erase Pages */ +#endif + # define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */ # define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */ # define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */ @@ -96,15 +115,32 @@ # define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */ # define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */ # define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FCR_FCMD_GCALB (16 << EEFC_FCR_FCMD_SHIFT) /* Get CALIB Bit */ +# define EEFC_FCR_FCMD_ES (17 << EEFC_FCR_FCMD_SHIFT) /* Erase Sector */ +# define EEFC_FCR_FCMD_WUS (18 << EEFC_FCR_FCMD_SHIFT) /* Write User Signature */ +# define EEFC_FCR_FCMD_EUS (19 << EEFC_FCR_FCMD_SHIFT) /* Erase User Signature */ +# define EEFC_FCR_FCMD_STUS (20 << EEFC_FCR_FCMD_SHIFT) /* Start Read User Signature */ +# define EEFC_FCR_FCMD_SPUS (21 << EEFC_FCR_FCMD_SHIFT) /* Stop Read User Signature */ +#endif + #define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */ #define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) #define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */ -#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT) +#define EEFC_FCR_FKEY_MASK (0xff << EEFC_FCR_FKEY_SHIFT) +# define EEFC_FCR_FKEY_PASSWD (0x5a << EEFC_FCR_FKEY_SHIFT) + +/* EEFC Flash Status Register */ #define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */ #define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */ #define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FSR_FLERR (1 << 3) /* Bit 3: Flash Error Status */ +#endif + /**************************************************************************************** * Public Types ****************************************************************************************/ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_matrix.h b/nuttx/arch/arm/src/sam34/chip/sam3u_matrix.h similarity index 72% rename from nuttx/arch/arm/src/sam34/chip/sam_matrix.h rename to nuttx/arch/arm/src/sam34/chip/sam3u_matrix.h index 6fed14092e..6a82740061 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_matrix.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_matrix.h @@ -1,5 +1,6 @@ /**************************************************************************************** - * arch/arm/src/sam34/chip/sam_matric.h + * arch/arm/src/sam34/chip/sam_34matrix.h + * Bux matrix definitions for the SAM3U and SAM4S * * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +34,8 @@ * ****************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H /**************************************************************************************** * Included Files @@ -64,12 +65,16 @@ #define SAM_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */ #define SAM_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */ #define SAM_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */ -#define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ -#define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ -#define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ -#define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ -#define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ - /* 0x0068-0x007c: Reserved */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ +# define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ +# define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ +# define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ +# define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ + /* 0x0068-0x007c: Reserved (SAM3U) */ +#endif + /* 0x0054-0x007c: Reserved (SAM4S) */ #define SAM_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3)) #define SAM_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */ /* 0x0084: Reserved */ @@ -80,19 +85,29 @@ #define SAM_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */ /* 0x009c: Reserved */ #define SAM_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) /* 0x00a4: Reserved */ -#define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ +# define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ /* 0x00ac: Reserved */ -#define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ +# define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ /* 0x00b4: Reserved */ -#define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ +# define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ /* 0x00bc: Reserved */ -#define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ +# define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ /* 0x00c4: Reserved */ -#define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ +# define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ /* 0x00cc-0x00fc: Reserved */ -#define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ - /* 0x0104-0x010c: Reserved */ +# define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ + /* 0x0104-0x01e0: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) + /* 0x00a4-0x110: Reserved */ +# define SAM_MATRIX_CCFG_SYSIO_OFFSET 0x0114 /* System I/O Configuration Register */ + /* 0x0118: Reserved */ +# define SAM_MATRIX_CCFG_SMCNFCS_OFFSET 0x011c /* SMC Chip Select NAND Flash Assignment Register */ + /* 0x0120-0x01e0: Reserved */ +#endif + #define SAM_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */ #define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */ /* 0x0110 - 0x01fc: Reserved */ @@ -112,11 +127,13 @@ #define SAM_MATRIX_SCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG2_OFFSET) #define SAM_MATRIX_SCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET) #define SAM_MATRIX_SCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET) -#define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET) -#define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET) -#define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET) -#define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET) -#define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET) +# define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET) +# define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET) +# define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET) +# define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET) +#endif #define SAM_MATRIX_PRAS(n) (SAM_MATRIX_BASE+SAM_MATRIX_PRAS_OFFSET(n)) #define SAM_MATRIX_PRAS0 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS0_OFFSET) @@ -124,17 +141,26 @@ #define SAM_MATRIX_PRAS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS2_OFFSET) #define SAM_MATRIX_PRAS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET) #define SAM_MATRIX_PRAS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET) -#define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET) -#define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET) -#define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET) -#define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET) -#define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET) +# define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET) +# define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET) +# define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET) +# define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET) +#endif + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET) +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_MATRIX_CCFG_SYSIO (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SYSIO_OFFSET) +# define SAM_MATRIX_CCFG_SMCNFCS (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SMCNFCS_OFFSET) +#endif -#define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET) #define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET) #define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET) /* MATRIX register bit definitions ******************************************************/ +/* Master Configuration Registers */ #define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */ #define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT) @@ -144,6 +170,8 @@ # define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */ # define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */ +/* Bus Matrix Slave Configuration Registers */ + #define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */ #define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT) #define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */ @@ -165,12 +193,13 @@ # define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) # define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) # define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) - #define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */ #define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT) # define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */ # define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */ +/* Bus Matrix Priority Registers For Slaves */ + #define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2) #define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x)) #define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */ @@ -184,16 +213,46 @@ #define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */ #define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT) -#define MATRIX_MRCR_RCB(x) (1 << (x)) -#define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ -#define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ -#define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ -#define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */ -#define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */ +/* System I/O Configuration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define MATRIX_CCFG_SYSIO_SYSIO4 (1 << 4) /* Bit 4: PB4 or TDI Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO5 (1 << 5) /* Bit 5: PB5 or TDO/TRACESWO Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO6 (1 << 6) /* Bit 6: PB6 or TMS/SWDIO Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO7 (1 << 7) /* Bit 7: PB7 or TCK/SWCLK Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO10 (1 << 10) /* Bit 10: PB10 or DDM Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO11 (1 << 11) /* Bit 11: PB11 or DDP Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO12 (1 << 12) /* Bit 12: PB12 or ERASE Assignment */ +#endif + +/* SMC Chip Select NAND Flash Assignment Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS0 (1 << 0) /* Bit 0: SMC NAND Flash Chip Select 0 Assignment */ +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS1 (1 << 1) /* Bit 1: SMC NAND Flash Chip Select 2 Assignment */ +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS2 (1 << 2) /* Bit 2: SMC NAND Flash Chip Select 2 Assignment */ +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS3 (1 << 3) /* Bit 3: SMC NAND Flash Chip Select 3 Assignment */ +#endif + +/* Master Remap Control Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define MATRIX_MRCR_RCB(x) (1 << (x)) +# define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ +# define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ +# define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ +# define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */ +# define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */ +#endif + +/* Write Protect Mode Register */ #define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ #define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */ #define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT) +# define MATRIX_WPMR_WPKEY (0x004d4154 << MATRIX_WPMR_WPKEY_SHIFT) + +/* Write Protect Status Register */ #define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */ #define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ @@ -211,4 +270,4 @@ * Public Functions ****************************************************************************************/ -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h index 7e66c0b50f..e1b9822b24 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h @@ -91,7 +91,7 @@ # define SAM_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */ /* 0x400e2600-0x400fffff: Reserved */ /* 0x40100000-0x41ffffff: Reserved */ -# define SAM_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ +# define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ /* 0x44000000-0x5fffffff: Reserved */ #define SAM_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */ # define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ @@ -111,14 +111,14 @@ #define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ #define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ #define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ -#define SAM_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */ +#define SAM_UART0_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART 0 */ #define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ #define SAM_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/ -# define SAM_EEFCN_BASE(n) (0x400e0800+((n)<<9)) +# define SAM_EEFCN_BASE(n) (0x400e0800 + ((n) << 9)) # define SAM_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */ # define SAM_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */ #define SAM_PIO_BASE 0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */ -# define SAM_PION_BASE(n) (0x400e0c00+((n)<<9)) +# define SAM_PION_BASE(n) (0x400e0c00 + ((n) << 9)) # define SAM_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */ # define SAM_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */ # define SAM_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h index fbcffbfd0f..e508a3b4c6 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h @@ -122,12 +122,12 @@ #define GPIO_MCI_DA (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN4) #define GPIO_MCI_DAT0IN (GPIO_INPUT|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN5) -#define GPIO_PWMC_PWMH0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN0) -#define GPIO_PWMC_PWML0 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN7) -#define GPIO_PWMC_PWMH1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN1) -#define GPIO_PWMC_PWML1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN8) -#define GPIO_PWMC_PWMH2 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN2) -#define GPIO_PWMC_PWML2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) +#define GPIO_PWM0_H (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN0) +#define GPIO_PWM0_L (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN7) +#define GPIO_PWM1_H (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN1) +#define GPIO_PWM1_L (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN8) +#define GPIO_PWM2_H (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN2) +#define GPIO_PWM2_L (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) #define GPIO_SPI0_MISO (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN13) #define GPIO_SPI0_MOSI (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN14) @@ -149,13 +149,13 @@ #define GPIO_PCK0 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21) -#define GPIO_TWI_TWD0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) -#define GPIO_TWI_TWCK0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN10) -#define GPIO_TWI_TWD1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24) -#define GPIO_TWI_TWCK1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25) +#define GPIO_TWI0_D (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) +#define GPIO_TWI0_CK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN10) +#define GPIO_TW1I_D (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24) +#define GPIO_TWI1_CK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25) -#define GPIO_UART_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN12) -#define GPIO_UART_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN11) +#define GPIO_UART0_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN12) +#define GPIO_UART0_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN11) #define GPIO_USART0_CTS (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN8) #define GPIO_USART0_DCD (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN11) diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h index 14ceb0724f..bc037bd5a9 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_pio.h + * Parallel Input/Output (PIO) Controller definitions for the SAM3U * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -299,15 +300,15 @@ /* PIO Write Protect Mode Register */ -#define PIO_WPMR_WPEN 1 << 0) /* Bit 0: Write Protect Enable */ -#define PIO_WPMR_WPKEY_SHIFT 8) /* Bits 8-31: Write Protect KEY */ -#define PIO_WPMR_WPKEY_MASK 0xffffff << PIO_WPMR_WPKEY_SHIFT) +#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT) /* PIO Write Protect Status Register */ -#define PIO_WPSR_WPVS 1 << 0) /* Bit 0: Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC_SHIFT 8) /* Bits 8-23: Write Protect Violation Source */ -#define PIO_WPSR_WPVSRC_MASK 0xffff << PIO_WPSR_WPVSRC_SHIFT) +#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT) /**************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h new file mode 100644 index 0000000000..500ad57010 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h @@ -0,0 +1,478 @@ +/******************************************************************************************** + * arch/arm/src/sam34/chip/sam3u_pmc.h + * Power Management Controller (PMC) for the SAM3U and SAM4S + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* PMC register offsets *********************************************************************/ + +#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ +#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ +#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ + /* 0x000c: Reserved */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_PCER0_OFFSET 0x0010 /* Peripheral Clock Enable Register 0 */ +# define SAM_PMC_PCDR0_OFFSET 0x0014 /* Peripheral Clock Disable Register 0 */ +# define SAM_PMC_PCSR0_OFFSET 0x0018 /* Peripheral Clock Status Register 0 */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ +# define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ +# define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ +#endif + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ +#endif + /* 0x001c: Reserved (SAM4S)*/ +#define SAM_PMC_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ +#define SAM_PMC_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ +#define SAM_PMC_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_CKGR_PLLBR_OFFSET 0x002c /* PLLB Register */ +#endif + /* 0x002c: Reserved (SAM3U)*/ +#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) + /* 0x0034 Reserved */ +# define SAM_PMC_USB_OFFSET 0x0038 /* USB Clock Register PMC_USB */ + /* 0x003c Reserved */ +#endif + /* 0x0034-0x003c Reserved (SAM3U) */ +#define SAM_PMC_PCK_OFFSET(n) (0x0040 + ((n) << 2)) +#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ +#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ +#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ + /* 0x004c-0x005c: Reserved */ +#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ +#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ +#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */ +#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ +#define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ +#define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ +#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ + /* 0x007c-0x00e0: Reserved */ +#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) + /* 0x00ec-0x00fc Reserved */ +# define SAM_PMC_PCER1_OFFSET 0x0100 /* Peripheral Clock Enable Register 1 */ +# define SAM_PMC_PCDR1_OFFSET 0x0104 /* Peripheral Clock Disable Register 1 */ +# define SAM_PMC_PCSR1_OFFSET 0x0108 /* Peripheral Clock Status Register 1 */ + /* 0x010c Reserved */ +# define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */ + /* 0x003c Reserved */ +#endif + +/* PMC register adresses ********************************************************************/ + +#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET) +#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET) +#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_PCER0 (SAM_PMC_BASE+SAM_PMC_PCER0_OFFSET) +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET) +#endif + +#define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET) +#define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_CKGR_UCKR (SAM_PMC_BASE+SAM_PMC_CKGR_UCKR_OFFSET) +#endif + +#define SAM_PMC_CKGR_MOR (SAM_PMC_BASE+SAM_PMC_CKGR_MOR_OFFSET) +#define SAM_PMC_CKGR_MCFR (SAM_PMC_BASE+SAM_PMC_CKGR_MCFR_OFFSET) +#define SAM_PMC_CKGR_PLLAR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLAR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_CKGR_PLLBR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLBR_OFFSET) +# define SAM_PMC_USB (SAM_PMC_BASE+SAM_PMC_USB_OFFSET) +#endif + +#define SAM_PMC_MCKR (SAM_PMC_BASE+SAM_PMC_MCKR_OFFSET) +#define SAM_PMC_PCK(n) (SAM_PMC_BASE+SAM_PMC_PCK_OFFSET(n)) +#define SAM_PMC_PCK0 (SAM_PMC_BASE+SAM_PMC_PCK0_OFFSET) +#define SAM_PMC_PCK1 (SAM_PMC_BASE+SAM_PMC_PCK1_OFFSET) +#define SAM_PMC_PCK2 (SAM_PMC_BASE+SAM_PMC_PCK2_OFFSET) +#define SAM_PMC_IER (SAM_PMC_BASE+SAM_PMC_IER_OFFSET) +#define SAM_PMC_IDR (SAM_PMC_BASE+SAM_PMC_IDR_OFFSET) +#define SAM_PMC_SR (SAM_PMC_BASE+SAM_PMC_SR_OFFSET) +#define SAM_PMC_IMR (SAM_PMC_BASE+SAM_PMC_IMR_OFFSET) +#define SAM_PMC_FSMR (SAM_PMC_BASE+SAM_PMC_FSMR_OFFSET) +#define SAM_PMC_FSPR (SAM_PMC_BASE+SAM_PMC_FSPR_OFFSET) +#define SAM_PMC_FOCR (SAM_PMC_BASE+SAM_PMC_FOCR_OFFSET) +#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET) +#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_PCER1 (SAM_PMC_BASE+SAM_PMC_PCER1_OFFSET) +# define SAM_PMC_PCDR1 (SAM_PMC_BASE+SAM_PMC_PCDR1_OFFSET) +# define SAM_PMC_PCSR1 (SAM_PMC_BASE+SAM_PMC_PCSR1_OFFSET) +# define SAM_PMC_OCR (SAM_PMC_BASE+SAM_PMC_OCR_OFFSET) +#endif + +/* PMC register bit definitions *************************************************************/ + +/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System + * Clock Status Register common bit-field definitions + */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_UDP (1 << 7) /* Bit 7: USB Device Port Clock Enable */ +#endif + +#define PMC_PCK(n) (1 << ((n) + 8) +#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */ +#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */ +#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */ + +/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC + * Peripheral Clock Status Register common bit-field definitions. + */ + +#define PMC_PIDL(n) (1 << (n)) +#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ +#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ +#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ +#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ +#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ +#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ +#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ +#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ +#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ +#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ +#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ +#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ +#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ +#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ +#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ +#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ +#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ +#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ +#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ +#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ +#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ +#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ +#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ +#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ +#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ +#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ +#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ +#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ +#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ +#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ + +/* PMC UTMI Clock Configuration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ +# define PMC_CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ +# define PMC_CKGR_UCKR_UPLLCOUNT_MASK (15 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT) +#endif + +/* PMC Clock Generator Main Oscillator Register */ + +#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ +#define PMC_CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ +#define PMC_CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */ +#define PMC_CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ +#define PMC_CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */ +#define PMC_CKGR_MOR_MOSCRCF_MASK (7 << PMC_CKGR_MOR_MOSCRCF_SHIFT) +# define PMC_CKGR_MOR_MOSCRCF_4MHz (0 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 4MHz (default) */ +# define PMC_CKGR_MOR_MOSCRCF_8MHz (1 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 8MHz */ +# define PMC_CKGR_MOR_MOSCRCF_12MHz (2 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 12MHz */ +#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ +#define PMC_CKGR_MOR_MOSCXTST_MASK (0x1ff << PMC_CKGR_MOR_MOSCXTST_SHIFT) +#define PMC_CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ +#define PMC_CKGR_MOR_KEY_MASK (0xff << PMC_CKGR_MOR_KEY_SHIFT) +# define PMC_CKGR_MOR_KEY (0x37 << PMC_CKGR_MOR_KEY_SHIFT) +#define PMC_CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ +#define PMC_CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ + +/* PMC Clock Generator Main Clock Frequency Register */ + +#define PMC_CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ +#define PMC_CKGR_MCFR_MAINF_MASK (0xffff << PMC_CKGR_MCFR_MAINF_SHIFT) +#define PMC_CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */ +#endif + +/* PMC Clock Generator PLLA Register */ + +#define PMC_CKGR_PLLAR_DIV_SHIFT (0) /* Bits 0-7: Divider */ +#define PMC_CKGR_PLLAR_DIV_MASK (0xff << PMC_CKGR_PLLAR_DIV_SHIFT) +# define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */ +# define PMC_CKGR_PLLAR_DIV_BYPASS (1 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */ +# define PMC_CKGR_PLLAR_DIV(n) ((n) << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ + +#define PMC_CKGR_PLLAR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ +#define PMC_CKGR_PLLAR_COUNT_MASK (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */ +# define PMC_CKGR_PLLAR_STMODE_MASK (3 << PMC_CKGR_PLLAR_STMODE_SHIFT) +# define PMC_CKGR_PLLAR_STMODE_FAST (0 << PMC_CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */ +# define PMC_CKGR_PLLAR_STMODE_NORMAL (2 << PMC_CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */ +#endif + +#define PMC_CKGR_PLLAR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ +#define PMC_CKGR_PLLAR_MUL_MASK (0x7ff << PMC_CKGR_PLLAR_MUL_SHIFT) +#define PMC_CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ + +/* PLLB Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_CKGR_PLLBR_DIV_SHIFT (0) /* Bits 0-7: Divider */ +# define PMC_CKGR_PLLBR_DIV_MASK (0xff << PMC_CKGR_PLLBR_DIV_SHIFT) +# define PMC_CKGR_PLLBR_DIV_ZERO (0 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is 0 */ +# define PMC_CKGR_PLLBR_DIV_BYPASS (1 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */ +# define PMC_CKGR_PLLBR_DIV(n) ((n) << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ +# define PMC_CKGR_PLLBR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ +# define PMC_CKGR_PLLBR_COUNT_MASK (63 << PMC_CKGR_PLLBR_COUNT_SHIFT) +# define PMC_CKGR_PLLBR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ +# define PMC_CKGR_PLLBR_MUL_MASK (0x7ff << PMC_CKGR_PLLBR_MUL_SHIFT) +#endif + +/* USB Clock Register PMC_USB */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_USB_USBS (1 << 0) /* Bit 0: USB Input Clock Selection */ +# define PMC_USB_USBS_PLLA (0) +# define PMC_USB_USBS_PLLB PMC_USB_USBS +# define PMC_USB_USBDIV_SHIFT (8) /* Bits 8-11: Divider for USB Clock */ +# define PMC_USB_USBDIV_MASK (15 << PMC_USB_USBDIV_SHIFT) +#endif + +/* PMC Master Clock Register */ + +#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ +#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) +# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ +# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ +# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ + +# if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_MCKR_CSS_PLLB (3 << PMC_MCKR_CSS_SHIFT) /* PLLB Clock */ +# elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ +# endif + +#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ +#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) +# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ +# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_MCKR_PRES_DIV32 (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ +# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_MCKR_PLLADIV2 (1 << 13) /* Bit 13: PLLA Divider */ +# define PMC_MCKR_PLLBDIV2 (1 << 14) /* Bit 14: PLLB Divider */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */ +#endif + +/* PMC Programmable Clock Register (0,1,2) */ + +#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ +#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) +# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ +# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ +# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_PCK_CSS_PLLB (3 << PMC_PCK_CSS_MASK) /* PLLB Clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ +#endif + +# define PMC_PCK_CSS_MCK (4 << PMC_PCK_CSS_MASK) /* Master Clock */ + +#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ +#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) +# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ +# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ + +/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, + * and PMC Interrupt Mask Register common bit-field definitions + */ + +#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ +#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_INT_LOCKB (1 << 2) /* Bit 2: PLL B Lock Interrupt */ +#endif + +#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ +#endif + +#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */ +#define PMC_INT_PCKRDY(n) (1 << ((n)+8) +#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ +#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ +#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ +#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ +#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ +#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ +#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ +#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ + +/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field + * definitions + */ + +#define PMC_FSTI(n) (1 << (n)) +#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */ +#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */ +#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */ +#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */ +#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */ +#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */ +#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */ +#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */ +#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */ +#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */ +#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */ +#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */ +#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */ +#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */ +#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */ +#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */ +#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */ +#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */ +#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_FSMR_FLPM_SHIFT (21) /* Bit 21-22: Low Power Mode (MR only) */ +# define PMC_FSMR_FLPM_MASK (3 << PMC_FSMR_FLPM_SHIFT) +# define PMC_FSMR_FLPM_PWRDOWN (0 << PMC_FSMR_FLPM_SHIFT) /* Flash Standby Mode */ +# define PMC_FSMR_FLPM_STANDBY (1 << PMC_FSMR_FLPM_SHIFT) /* Flash deep power down mode */ +# define PMC_FSMR_FLPM_IDLE (2 << PMC_FSMR_FLPM_SHIFT) /* Idle mode */ +#endif + +/* Fast Startup Polarity Register */ + +#define PMC_FSTP(n) (1 << (n)) /* Fast Startup Input Polarityn, n=0..15 */ + +/* PMC Fault Output Clear Register */ + +#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ + +/* PMC Write Protect Mode Register */ + +#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) +# define PMC_WPMR_WPKEY (0x00504d43 << PMC_WPMR_WPKEY_SHIFT) + +/* PMC Write Protect Status Register */ + +#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) + +/* Peripheral Clock Enable Register 1 */ +/* Peripheral Clock Disable Register 1 */ +/* Peripheral Clock Status Register 1 */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_PIDH(n) (1 << ((n) - 32)) +# define PMC_PID32 (1 << 0) /* Bit 0: PID32 */ +# define PMC_PID33 (1 << 1) /* Bit 1: PID33 */ +# define PMC_PID34 (1 << 2) /* Bit 2: PID34 */ +#endif + +/* Oscillator Calibration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_OCR_CAL4_SHIFT (0) /* Bits 0-6: 4MHzRC Oscillator Calibration */ +# define PMC_OCR_CAL4_MASK (0x7f << PMC_OCR_CAL4_SHIFT) +# define PMC_OCR_SEL4 (1 << 7) /* Bit 7: Select 4MHz RC Oscillator Calibration */ +# define PMC_OCR_CAL8_SHIFT (8) /* Bits 8-14: 8MHzRC Oscillator Calibration */ +# define PMC_OCR_CAL8_MASK (0x7f << PMC_OCR_CAL8_SHIFT) +# define PMC_OCR_SEL8 (1 << 15) /* Bit 15: Select 8MHz RC Oscillator Calibration */ +# define PMC_OCR_CAL12_SHIFT (16) /* Bits 16-22: 12MHzRC Oscillator Calibration */ +# define PMC_OCR_CAL12_MASK (0x7f << PMC_OCR_CAL12_SHIFT) +# define PMC_OCR_SEL12 (1 << 23) /* Bit 23: Select 12MHz RC Oscillator Calibration */ +#endif + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h index 88f9452d8b..aea7577176 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_supc.h + * Supply Controller (SUPC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -51,93 +52,159 @@ /* SUPC register offsets ****************************************************************/ -#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ -#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ -#define SAM_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */ -#define SAM_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */ -#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ -#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ +#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ +#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ +#define SAM_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */ +#define SAM_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */ +#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ +#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ /* SUPC register adresses ***************************************************************/ -#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET) -#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET) -#define SAM_SUPC_MR (SAM_SUPC_BASE+SAM_SUPC_MR_OFFSET) -#define SAM_SUPC_WUMR (SAM_SUPC_BASE+SAM_SUPC_WUMR_OFFSET) -#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET) -#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET) +#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET) +#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET) +#define SAM_SUPC_MR (SAM_SUPC_BASE+SAM_SUPC_MR_OFFSET) +#define SAM_SUPC_WUMR (SAM_SUPC_BASE+SAM_SUPC_WUMR_OFFSET) +#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET) +#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET) /* SUPC register bit definitions ********************************************************/ +/* Supply Controller Control Register */ + +#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ +#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */ +#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT) +# define SUPR_CR_KEY (0xa5 << SUPC_CR_KEY_SHIFT) + +/* Supply Controller Supply Monitor Mode Register */ + +#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) + +# if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_SMMR_SMTH_1p6V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.56 < 1.6 < 1.64 */ +# define SUPC_SMMR_SMTH_1p7V (1 << SUPC_SMMR_SMTH_SHIFT) /* 1.68 < 1.72 < 1.76 */ +# define SUPC_SMMR_SMTH_1p8V (2 << SUPC_SMMR_SMTH_SHIFT) /* 1.79 < 1.84 < 1.89 */ +# define SUPC_SMMR_SMTH_2p0V (3 << SUPC_SMMR_SMTH_SHIFT) /* 1.91 < 1.96 < 2.01 */ +# define SUPC_SMMR_SMTH_2p1V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.03 < 2.08 < 2.13 */ +# define SUPC_SMMR_SMTH_2p2V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.15 < 2.2 < 2.23 */ +# define SUPC_SMMR_SMTH_2p3V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.26 < 2.32 < 2.38 */ +# define SUPC_SMMR_SMTH_2p4V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.38 < 2.44 < 2.50 */ +# define SUPC_SMMR_SMTH_2p6V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.50 < 2.56 < 2.62 */ +# define SUPC_SMMR_SMTH_2p7V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.61 < 2.68 < 2.75 */ +# define SUPC_SMMR_SMTH_2p8V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.73 < 2.8 < 2.87 */ +# define SUPC_SMMR_SMTH_2p9V (11 << SUPC_SMMR_SMTH_SHIFT) /* 2.85 < 2.92 < 2.99 */ +# define SUPC_SMMR_SMTH_3p0V (12 << SUPC_SMMR_SMTH_SHIFT) /* 2.96 < 3.04 < 3.12 */ +# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.08 < 3.16 < 3.24 */ +# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.20 < 3.28 < 3.36 */ +# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.32 < 3.4 < 3.49 */ +# elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ +# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ +# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ +# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */ +# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */ +# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */ +# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */ +# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */ +# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */ +# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */ +# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */ +# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */ +# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */ +# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */ +# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */ +# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */ +#endif + +#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) +# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ +# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ +# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ +# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ +# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ + +/* Supply Controller Mode Register */ + +#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ +#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_MR_ONREG (1 << 14) /* Bit 14: Voltage Regulator enable */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ +#endif + +#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */ +#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */ +#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT) + +/* Supply Controller Wake Up Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */ +#endif + +#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_WUMR_LPDBCEN0 (1 << 5) /* Bit 5: Low power Debouncer ENable WKUP0 */ +# define SUPC_WUMR_LPDBCEN1 (1 << 6) /* Bit 6: Low power Debouncer ENable WKUP1 */ +# define SUPC_WUMR_LPDBCCLR (1 << 7) /* Bit 7: Low power Debouncer Clear */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ +# define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) +# define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ +# define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ +#endif + +#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ +#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) +# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ +# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_WUMR_LPDBC_SHIFT (16) /* Bits 16-18: Low Power Debouncer Period */ +# define SUPC_WUMR_LPDBC_MASK (7 << SUPC_WUMR_LPDBC_SHIFT) +# define SUPC_WUMR_LPDBC_DISABLE (0 << SUPC_WUMR_LPDBC_SHIFT) /* Disable low power debouncer */ +# define SUPC_WUMR_LPDBC_2_RTCOUT0 (1 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 2 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_3_RTCOUT0 (2 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 3 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_4_RTCOUT0 (3 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 4 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_5_RTCOUT0 (4 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 5 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_6_RTCOUT0 (5 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 6 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_7_RTCOUT0 (6 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 7 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_8_RTCOUT0 (7 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 8 RTCOUT0 */ +#endif + +/* System Controller Wake Up Inputs Register */ + +#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */ +#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT) +# define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT) +#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */ +#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT) +# define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT) + +/* Supply Controller Status Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ +#endif -#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ -#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */ -#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ -#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT) - -#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) -# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ -# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ -# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ -# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */ -# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */ -# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */ -# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */ -# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */ -# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */ -# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */ -# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */ -# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */ -# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */ -# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */ -# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */ -# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */ -#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) -# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ -# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ -# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ -# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ -# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ - -#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ -#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ -#define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ -#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */ -#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */ -#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT) - -#define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */ -#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ -#define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) - #define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ - #define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) -# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ -# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ - -#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */ -#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT) -#define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT) -#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */ -#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT) -#define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT) - -#define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ #define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */ #define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */ #define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */ @@ -145,7 +212,14 @@ #define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */ #define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */ #define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */ -#define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_SR_LPDBCS0 (1 << 13) /* Bit 13: Low Power Debouncer Wake Up Status on WKUP0 */ +# define SUPC_SR_LPDBCS1 (1 << 14) /* Bit 14: Low Power Debouncer Wake Up Status on WKUP1 */ +#endif + #define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */ #define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT) diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h b/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h new file mode 100644 index 0000000000..bf2dbff2d2 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h @@ -0,0 +1,433 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam3u_uart.h + * Universal Asynchronous Receiver Transmitter (UART) and Universal Synchronous Asynchronous + * Receiver Transmitter (USART) definitions for the SAM3U and SAM4S + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* UART register offsets ************************************************************************/ + +#define SAM_UART_CR_OFFSET 0x0000 /* Control Register (Common) */ +#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */ +#define SAM_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */ +#define SAM_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */ +#define SAM_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */ +#define SAM_UART_SR_OFFSET 0x0014 /* [Channel] Status Register (Common) */ +#define SAM_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */ +#define SAM_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */ +#define SAM_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */ + /* 0x0024-0x003c: Reserved (UART) */ +#define SAM_UART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */ +#define SAM_UART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */ + /* 0x002c-0x003c: Reserved (USART) */ +#define SAM_UART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */ +#define SAM_UART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */ + /* 0x0048: Reserved (USART) */ +#define SAM_UART_IFR_OFFSET 0x004c /* IrDA Filter Register (USART only) */ +#define SAM_UART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */ +#define SAM_UART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */ +#define SAM_UART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */ + /* 0x005c-0xf8: Reserved (USART) */ +#define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */ + /* 0x0100-0x0124: PDC Area (Common) */ + +/* UART register adresses ***********************************************************************/ + +#define SAM_UART0_CR (SAM_UART0_BASE+SAM_UART_CR_OFFSET) +#define SAM_UART0_MR (SAM_UART0_BASE+SAM_UART_MR_OFFSET) +#define SAM_UART0_IER (SAM_UART0_BASE+SAM_UART_IER_OFFSET) +#define SAM_UART0_IDR (SAM_UART0_BASE+SAM_UART_IDR_OFFSET) +#define SAM_UART0_IMR (SAM_UART0_BASE+SAM_UART_IMR_OFFSET) +#define SAM_UART0_SR (SAM_UART0_BASE+SAM_UART_SR_OFFSET) +#define SAM_UART0_RHR (SAM_UART0_BASE+SAM_UART_RHR_OFFSET) +#define SAM_UART0_THR (SAM_UART0_BASE+SAM_UART_THR_OFFSET) +#define SAM_UART0_BRGR (SAM_UART0_BASE+SAM_UART_BRGR_OFFSET) + +#define SAM_UART1_CR (SAM_UART1_BASE+SAM_UART_CR_OFFSET) +#define SAM_UART1_MR (SAM_UART1_BASE+SAM_UART_MR_OFFSET) +#define SAM_UART1_IER (SAM_UART1_BASE+SAM_UART_IER_OFFSET) +#define SAM_UART1_IDR (SAM_UART1_BASE+SAM_UART_IDR_OFFSET) +#define SAM_UART1_IMR (SAM_UART1_BASE+SAM_UART_IMR_OFFSET) +#define SAM_UART1_SR (SAM_UART1_BASE+SAM_UART_SR_OFFSET) +#define SAM_UART1_RHR (SAM_UART1_BASE+SAM_UART_RHR_OFFSET) +#define SAM_UART1_THR (SAM_UART1_BASE+SAM_UART_THR_OFFSET) +#define SAM_UART1_BRGR (SAM_UART1_BASE+SAM_UART_BRGR_OFFSET) + +#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET) +#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET) +#define SAM_USART_IER(n) (SAM_USARTN_BASE(n)+SAM_UART_IER_OFFSET) +#define SAM_USART_IDR(n) (SAM_USARTN_BASE(n)+SAM_UART_IDR_OFFSET) +#define SAM_USART_IMR(n) (SAM_USARTN_BASE(n)+SAM_UART_IMR_OFFSET) +#define SAM_USART_SR(n) (SAM_USARTN_BASE(n)+SAM_UART_SR_OFFSET) +#define SAM_USART_RHR(n) (SAM_USARTN_BASE(n)+SAM_UART_RHR_OFFSET) +#define SAM_USART_THR(n) (SAM_USARTN_BASE(n)+SAM_UART_THR_OFFSET) +#define SAM_USART_BRGR(n) (SAM_USARTN_BASE(n)+SAM_UART_BRGR_OFFSET) +#define SAM_USART_RTOR(n) (SAM_USARTN_BASE(n)+SAM_UART_RTOR_OFFSET) +#define SAM_USART_TTGR(n) (SAM_USARTN_BASE(n)+SAM_UART_TTGR_OFFSET) +#define SAM_USART_FIDI(n) (SAM_USARTN_BASE(n)+SAM_UART_FIDI_OFFSET) +#define SAM_USART_NER(n) (SAM_USARTN_BASE(n)+SAM_UART_NER_OFFSET) +#define SAM_USART_IFR(n) (SAM_USARTN_BASE(n)+SAM_UART_IFR_OFFSET) +#define SAM_USART_MAN(n) (SAM_USARTN_BASE(n)+SAM_UART_MAN_OFFSET) +#define SAM_USART_WPMR(n) (SAM_USARTN_BASE(n)+SAM_UART_WPMR_OFFSET) +#define SAM_USART_WPSR(n) (SAM_USARTN_BASE(n)+SAM_UART_WPSR_OFFSET) +#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_UART_VERSION_OFFSET) + +#define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART0_MR (SAM_USART0_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART0_SR (SAM_USART0_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART0_RHR (SAM_USART0_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART0_THR (SAM_USART0_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART0_BRGR (SAM_USART0_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART0_RTOR (SAM_USART0_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART0_TTGR (SAM_USART0_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART0_FIDI (SAM_USART0_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART0_NER (SAM_USART0_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART0_IFR (SAM_USART0_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART0_MAN (SAM_USART0_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART0_WPMR (SAM_USART0_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART0_WPSR (SAM_USART0_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART1_MR (SAM_USART1_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART1_SR (SAM_USART1_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART1_RHR (SAM_USART1_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART1_THR (SAM_USART1_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART1_BRGR (SAM_USART1_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART1_RTOR (SAM_USART1_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART1_TTGR (SAM_USART1_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART1_FIDI (SAM_USART1_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART1_NER (SAM_USART1_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART1_IFR (SAM_USART1_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART1_MAN (SAM_USART1_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART1_WPMR (SAM_USART1_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART1_WPSR (SAM_USART1_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART2_MR (SAM_USART2_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART2_SR (SAM_USART2_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART2_RHR (SAM_USART2_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART2_THR (SAM_USART2_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART2_BRGR (SAM_USART2_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART2_RTOR (SAM_USART2_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART2_TTGR (SAM_USART2_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART2_FIDI (SAM_USART2_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART2_NER (SAM_USART2_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART2_IFR (SAM_USART2_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART2_MAN (SAM_USART2_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART2_WPMR (SAM_USART2_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART2_WPSR (SAM_USART2_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART3_MR (SAM_USART3_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART3_SR (SAM_USART3_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART3_RHR (SAM_USART3_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART3_THR (SAM_USART3_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART3_BRGR (SAM_USART3_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART3_RTOR (SAM_USART3_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART3_TTGR (SAM_USART3_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART3_FIDI (SAM_USART3_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART3_NER (SAM_USART3_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART3_IFR (SAM_USART3_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART3_MAN (SAM_USART3_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART3_WPMR (SAM_USART3_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_UART_VERSION_OFFSET) + +/* UART register bit definitions ****************************************************************/ + +/* UART Control Register */ + +#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver (Common) */ +#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter (Common) */ +#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable (Common) */ +#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable (Common) */ +#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable (Common) */ +#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable (Common) */ +#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */ +#define UART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART only) */ +#define UART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART only) */ +#define UART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART only) */ +#define UART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART only) */ +#define UART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART only) */ +#define UART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */ +#define UART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */ +#define UART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */ +#define UART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART SPI mode only) */ +#define UART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */ +#define UART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART SPI mode only) */ + +/* UART Mode Register and USART Mode Register (UART MODE) */ + +#define UART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */ +#define UART_MR_MODE_MASK (15 << UART_MR_MODE_SHIFT) +# define UART_MR_MODE_NORMAL (0 << UART_MR_MODE_SHIFT) /* Normal */ +# define UART_MR_MODE_RS485 (1 << UART_MR_MODE_SHIFT) /* RS485 */ +# define UART_MR_MODE_HWHS (2 << UART_MR_MODE_SHIFT) /* Hardware Handshaking */ +# define UART_MR_MODE_ISO7816_0 (4 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ +# define UART_MR_MODE_ISO7816_1 (6 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ +# define UART_MR_MODE_IRDA (8 << UART_MR_MODE_SHIFT) /* IrDA */ +# define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master (SPI mode only) */ +# define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave (SPI mode only) */ +#define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */ +#define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT) +# define UART_MR_USCLKS_MCK (0 << UART_MR_USCLKS_SHIFT) /* MCK */ +# define UART_MR_USCLKS_MCKDIV (1 << UART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ +# define UART_MR_USCLKS_SCK (3 << UART_MR_USCLKS_SHIFT) /* SCK */ +#define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */ +#define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT) +# define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */ +# define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits */ +# define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */ +# define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */ +#define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */ +#define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART SPI mode only) */ +#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */ +#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) +# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */ +# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity (Common) */ +# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (Common) */ +# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */ +# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */ +# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */ +#define UART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */ +#define UART_MR_NBSTOP_MASK (3 << UART_MR_NBSTOP_SHIFT) +# define UART_MR_NBSTOP_1 (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ +# define UART_MR_NBSTOP_1p5 (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ +# define UART_MR_NBSTOP_2 (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ +#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */ +#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) +# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ +# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ +# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ +# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ +#define UART_MR_MSBF (1 << 16) /* Bit 16: Most Significant Bit first (USART only) */ +#define UART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity (USART SPI mode only) */ +#define UART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */ +#define UART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */ +#define UART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */ +#define UART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_MR_WRDBT (1 << 20) /* Bit 20: Wait Read Data Before Transfer (SPI mode only) */ +#endif + +#define UART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */ +#define UART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */ +#define UART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */ +#define UART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */ +#define UART_MR_MAXITER_MASK (7 << UART_MR_MAXITER_SHIFT) +#define UART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */ +#define UART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */ +#define UART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */ +#define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */ + +/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask + * Register, and UART Status Register common bit field definitions + */ + +#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */ +#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt (Common) */ +#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */ +#define UART_INT_ENDRX (1 << 3) /* Bit 3: End of Receive Transfer Interrupt (Common) */ +#define UART_INT_ENDTX (1 << 4) /* Bit 4: End of Transmit Interrupt (Common) */ +#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt (Common) */ +#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt (Common) */ +#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt (Common) */ +#define UART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */ +#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */ +#define UART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */ +#define UART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART SPI mode only) */ +#define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */ +#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */ +#define UART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_INT_RIIC (1 << 16) /* Bit 16: Ring Indicator Input Change Enable */ +# define UART_INT_DSRIC (1 << 17) /* Bit 17: Data Set Ready Input Change Enable */ +# define UART_INT_DCDIC (1 << 18) /* Bit 18: Data Carrier Detect Input Change Interrupt Enable */ +#endif + +#define UART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_SR_RI (1 << 20) /* Bit 20: Image of RI Input */ +# define UART_SR_DSR (1 << 21) /* Bit 21: Image of DSR Input */ +# define UART_SR_DCD (1 << 22) /* Bit 22: Image of DCD Input */ +# define UART_SR_CTS (1 << 23) /* Bit 23: Image of CTS Input */ +#endif + +#define UART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */ + +/* UART Receiver Holding Register */ + +#if 0 +# define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-7: Received Character (UART only) */ +# define UART_RHR_RXCHR_MASK (0xff << UART_RHR_RXCHR_SHIFT) +#endif +#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character (USART only) */ +#define UART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT) +#define UART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync (USART only) */ + +/* UART Transmit Holding Register */ + +#if 0 +# define UART_THR_TXCHR_SHIFT (0) /* Bits 0-7: Character to be Transmitted (UART only) */ +# define UART_THR_TXCHR_MASK (0xff << UART_THR_TXCHR_SHIFT) +#endif +#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted (USART only) */ +#define UART_THR_TXCHR_MASK (0x1ff << UART_THR_TXCHR_SHIFT) +#define UART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */ + +/* UART Baud Rate Generator Register */ + +#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor (Common) */ +#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT) +#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part (USART only) */ +#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT) + +/* USART Receiver Time-out Register (USART only) */ + +#define UART_RTOR_TO_SHIFT (0) /* Bits 0-15: Time-out Value (USART only) */ +#define UART_RTOR_TO_MASK (0xffff << UART_RTOR_TO_SHIFT) + +/* USART Transmitter Timeguard Register (USART only) */ + +#define UART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value (USART only) */ +#define UART_TTGR_TG_MASK (0xff << UART_TTGR_TG_SHIFT) + +/* USART FI DI RATIO Register (USART only) */ + +#define UART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value (USART only) */ +#define UART_FIDI_RATIO_MASK (0x7ff << UART_FIDI_RATIO_SHIFT) + +/* USART Number of Errors Register (USART only) */ + +#define UART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors (USART only) */ +#define UART_NER_NBERRORS_MASK (0xff << UART_NER_NBERRORS_SHIFT) + +/* USART IrDA FILTER Register (USART only) */ + +#define UART_IFR_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter (USART only) */ +#define UART_IFR_IRDAFILTER_MASK (0xff << UART_IFR_IRDAFILTER_SHIFT) + +/* USART Manchester Configuration Register (USART only) */ + +#define UART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length (USART only) */ +#define UART_MAN_TXPL_MASK (15 << UART_MAN_TXPL_SHIFT) +#define UART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern (USART only) */ +#define UART_MAN_TXPP_MASK (3 << UART_MAN_TXPP_SHIFT) +# define UART_MAN_TXPP_ALLONE (0 << UART_MAN_TXPP_SHIFT) /* ALL_ONE */ +# define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */ +# define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */ +# define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */ +#define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ +#define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ +#define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT) +#define UART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */ +#define UART_MAN_RXPP_MASK (3 << UART_MAN_RXPP_SHIFT) +# define UART_MAN_RXPP_ALLONE (0 << UART_MAN_RXPP_SHIFT) /* ALL_ONE */ +# define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */ +# define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */ +# define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */ +#define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_MAN_ONE (1 << 29) /* Bit 29: Must Be Set to 1 */ +#endif + +#define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ + +/* USART Write Protect Mode Register (USART only) */ + +#define UART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */ +#define UART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */ +#define UART_WPMR_WPKEY_MASK (0x00ffffff << UART_WPMR_WPKEY_SHIFT) +# define UART_WPMR_WPKEY (0x00555341 << UART_WPMR_WPKEY_SHIFT) + +/* USART Write Protect Status Register (USART only) */ + +#define UART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */ +#define UART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */ +#define UART_WPSR_WPVSRC_MASK (0xffff << UART_WPSR_WPVSRC_SHIFT) + +/* USART Version Register */ + +#define UART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number (USART only) */ +#define UART_VERSION_VERSION_MASK (0xfff << UART_VERSION_VERSION_SHIFT) +#define UART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */ +#define UART_VERSION_MFN_MASK (7 << UART_VERSION_MFN_SHIFT) + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h b/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h index fd4c1a39e6..2af4ac734a 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h @@ -62,7 +62,7 @@ VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */ VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */ VECTOR(sam_eefc1, SAM_IRQ_EEFC1) /* Vector 16+7: Enhanced Embedded Flash Controller 1 */ - VECTOR(sam_uart, SAM_IRQ_UART) /* Vector 16+8: Universal Asynchronous Receiver Transmitter */ + VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter */ VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+9: Static Memory Controller */ VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+10: Parallel I/O Controller A */ VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+11: Parallel I/O Controller B */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_wdt.h b/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h similarity index 91% rename from nuttx/arch/arm/src/sam34/chip/sam_wdt.h rename to nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h index ffe0cb96db..04132cd4b0 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_wdt.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h @@ -1,5 +1,6 @@ /**************************************************************************************** - * arch/arm/src/sam34/chip/sam_wdt.h + * arch/arm/src/sam34/chip/sam3u_wdt.h + * Watchdog Timer (WDT) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +34,8 @@ * ****************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H /**************************************************************************************** * Included Files @@ -62,22 +63,27 @@ #define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) /* WDT register bit definitions ********************************************************/ +/* Watchdog Timer Control Register */ #define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ #define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ #define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) +/* Watchdog Timer Mode Register */ + #define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */ #define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT) #define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ #define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ #define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ #define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ -#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */ +#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value */ #define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT) #define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ #define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ +/* Watchdog Timer Status Register */ + #define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ #define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ @@ -93,4 +99,4 @@ * Public Functions ****************************************************************************************/ -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h b/nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h new file mode 100644 index 0000000000..05ba546c93 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h @@ -0,0 +1,178 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_bpm.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BPM_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BPM_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* BPM register offsets ****************************************************************/ + +#define SAM_BPM_IER_OFFSET 0x0000 /* Interrupt Enable Register */ +#define SAM_BPM_IDR_OFFSET 0x0004 /* Interrupt Disable Register */ +#define SAM_BPM_IMR_OFFSET 0x0008 /* Interrupt Mask Register */ +#define SAM_BPM_ISR_OFFSET 0x000c /* Interrupt Status Register */ +#define SAM_BPM_ICR_OFFSET 0x0010 /* Interrupt Clear Register */ +#define SAM_BPM_SR_OFFSET 0x0014 /* Status Register */ +#define SAM_BPM_UNLOCK_OFFSET 0x0018 /* Unlock Register */ +#define SAM_BPM_PMCON_OFFSET 0x001c /* Power Mode Control Register */ +#define SAM_BPM_BKUPWCAUSE_OFFSET 0x0028 /* Backup Wake up Cause Register */ +#define SAM_BPM_BKUPWEN_OFFSET 0x002c /* Backup Wake up Enable Register */ +#define SAM_BPM_BKUPPMUX_OFFSET 0x0030 /* Backup Pin Muxing Register */ +#define SAM_BPM_IORET_OFFSET 0x0034 /* Input Output Retention Register */ +#define SAM_BPM_VERSION_OFFSET 0x00fc /* Version Register */ + +/* BPM register adresses ***************************************************************/ + +#define SAM_BPM_IER (SAM_BPM_BASE+SAM_BPM_IER_OFFSET) +#define SAM_BPM_IDR (SAM_BPM_BASE+SAM_BPM_IDR_OFFSET) +#define SAM_BPM_IMR (SAM_BPM_BASE+SAM_BPM_IMR_OFFSET) +#define SAM_BPM_ISR (SAM_BPM_BASE+SAM_BPM_ISR_OFFSET) +#define SAM_BPM_ICR (SAM_BPM_BASE+SAM_BPM_ICR_OFFSET) +#define SAM_BPM_SR (SAM_BPM_BASE+SAM_BPM_SR_OFFSET) +#define SAM_BPM_UNLOCK (SAM_BPM_BASE+SAM_BPM_UNLOCK_OFFSET) +#define SAM_BPM_PMCON (SAM_BPM_BASE+SAM_BPM_PMCON_OFFSET) +#define SAM_BPM_BKUPWCAUSE (SAM_BPM_BASE+SAM_BPM_BKUPWCAUSE_OFFSET) +#define SAM_BPM_BKUPWEN (SAM_BPM_BASE+SAM_BPM_BKUPWEN_OFFSET) +#define SAM_BPM_BKUPPMUX (SAM_BPM_BASE+SAM_BPM_BKUPPMUX_OFFSET) +#define SAM_BPM_IORET (SAM_BPM_BASE+SAM_BPM_IORET_OFFSET) +#define SAM_BPM_VERSION (SAM_BPM_BASE+SAM_BPM_VERSION_OFFSET) + +/* BPM register bit definitions ********************************************************/ + +/* Interrupt Enable Register */ +/* Interrupt Disable Register */ +/* Interrupt Mask Register */ +/* Interrupt Status Register */ +/* Interrupt Clear Register */ +/* Status Register */ + +#define BPM_INT_PSOK (1 << 0) /* Bit 0: Power Scaling OK */ +#define BPM_INT_AE (1 << 31) /* Bit 31: Access Error */ + +/* Unlock Register */ + +#define BPM_UNLOCK_ADDR_SHIFT (0) /* Bits 0-9: Unlock Address */ +#define BPM_UNLOCK_ADDR_MASK (0x3ff << BPM_UNLOCK_ADDR_SHIFT) +# define BPM_UNLOCK_ADDR(n) ((n) << BPM_UNLOCK_ADDR_SHIFT) +#define BPM_UNLOCK_KEY_SHIFT (24) /* Bits 24-31: Unlock Key */ +#define BPM_UNLOCK_KEY_MASK (0xff << BPM_UNLOCK_KEY_SHIFT) +# define BPM_UNLOCK_KEY(n) ((n) << BPM_UNLOCK_KEY_SHIFT) + +/* Power Mode Control Register */ + +#define BPM_PMCON_PS_SHIFT (0) /* Bits 0-1: Power Scaling Configuration Value */ +#define BPM_PMCON_PS_MASK (3 << BPM_PMCON_PS_SHIFT) +# define BPM_PMCON_PS0 (0 << BPM_PMCON_PS_SHIFT) +# define BPM_PMCON_PS1 (1 << BPM_PMCON_PS_SHIFT) +# define BPM_PMCON_PS2 (2 << BPM_PMCON_PS_SHIFT) +#define BPM_PMCON_PSCREQ (1 << 2) /* Bit 2: Power Scaling Change Request */ +#define BPM_PMCON_PSCM (1 << 3) /* Bit 3: Power Scaling Change Mode */ +#define BPM_PMCON_BKUP (1 << 8) /* Bit 8: BACKUP Mode */ +#define BPM_PMCON_RET (1 << 9) /* Bit 9: RETENTION Mode */ +#define BPM_PMCON_SLEEP_SHIFT (12) /* Bits 12-13: SLEEP mode Configuration */ +#define BPM_PMCON_SLEEP_MASK (3 << BPM_PMCON_SLEEP_SHIFT) +# define BPM_PMCON_SLEEP_SLEEP0 (0 << BPM_PMCON_SLEEP_SHIFT) /* CPU clock stopped */ +# define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */ +# define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */ +# define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */ +#define BPM_PMCON_CK32S (1 << 16) /* Bit 16: 32kHz-1kHz Clock Source Selection */ +#define BPM_PMCON_FASTWKUP (1 << 24) /* Bit 24: Fast Wakeup */ + +/* Backup Wake up Cause Register */ + +#define BPM_BKUPWCAUSE_EIC (1 << 0) /* Bit 0: EIC */ +#define BPM_BKUPWCAUSE_AST (1 << 1) /* Bit 1: AST */ +#define BPM_BKUPWCAUSE_WDT (1 << 2) /* Bit 2: WDT interrupt */ +#define BPM_BKUPWCAUSE_BOD33 (1 << 3) /* Bit 3: BOD33 interrupt */ +#define BPM_BKUPWCAUSE_BOD18 (1 << 4) /* Bit 4: BOD18 interrupt */ +#define BPM_BKUPWCAUSE_PICOUART (1 << 5) /* Bit 5: PICOUART interrupt */ + +/* Backup Wake up Enable Register */ + +#define BPM_BKUPWEN_EICEN (1 << 0) /* Bit 0: EIC */ +#define BPM_BKUPWEN_ASTEN (1 << 1) /* Bit 1: AST */ +#define BPM_BKUPWEN_WDTEN (1 << 2) /* Bit 2: WDT interrupt */ +#define BPM_BKUPWEN_BOD33EN (1 << 3) /* Bit 3: BOD33 interrupt */ +#define BPM_BKUPWEN_BOD18EN (1 << 4) /* Bit 4: BOD18 interrupt */ +#define BPM_BKUPWEN_PICOUARTEN (1 << 5) /* Bit 5: PICOUART interrupt */ + +/* Backup Pin Muxing Register */ + +#define BPM_BKUPPMUX_EIC0 (1 << 0) /* Bit 0: PB01 EIC[0] */ +#define BPM_BKUPPMUX_EIC1 (1 << 1) /* Bit 1: PA06 EIC[1] */ +#define BPM_BKUPPMUX_EIC2 (1 << 2) /* Bit 2: PA04 EIC[2] */ +#define BPM_BKUPPMUX_EIC3 (1 << 3) /* Bit 3: PA05 EIC[3] */ +#define BPM_BKUPPMUX_EIC4 (1 << 4) /* Bit 4: PA07 EIC[4] */ +#define BPM_BKUPPMUX_EIC5 (1 << 5) /* Bit 5: PC03 EIC[5] */ +#define BPM_BKUPPMUX_EIC6 (1 << 6) /* Bit 6: PC04 EIC[6] */ +#define BPM_BKUPPMUX_EIC7 (1 << 7) /* Bit 7: PC05 EIC[7] */ +#define BPM_BKUPPMUX_EIC8 (1 << 8) /* Bit 8: PC06 EIC[8] */ + +/* Input Output Retention Register */ + +#define BPM_IORET_RET (1 << 0) /* Bit 0: : Retention on I/O lines after wakeup */ + +/* Version Register */ + +#define BPM_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ +#define BPM_VERSION_MASK (0xfff << BPM_VERSION_VERSION_SHIFT) +#define BPM_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ +#define BPM_VERSION_VARIANT_MASK (15 << BPM_VERSION_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BPM_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_bscif.h b/nuttx/arch/arm/src/sam34/chip/sam4l_bscif.h new file mode 100644 index 0000000000..a1663aa7a6 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_bscif.h @@ -0,0 +1,316 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_bscif.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* BSCIF register offsets ***************************************************************/ + +#define SAM_BSCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */ +#define SAM_BSCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */ +#define SAM_BSCIF_IMR_OFFSET 0x0008 /* Interrupt Mask Register */ +#define SAM_BSCIF_ISR_OFFSET 0x000c /* Interrupt Status Register */ +#define SAM_BSCIF_ICR_OFFSET 0x0010 /* Interrupt Clear Register */ +#define SAM_BSCIF_PCLKSR_OFFSET 0x0014 /* Power and Clocks Status Register */ +#define SAM_BSCIF_UNLOCK_OFFSET 0x0018 /* Unlock Register */ +#define SAM_BSCIF_CSCR_OFFSET 0x001c /* Chip Specific Configuration Register */ +#define SAM_BSCIF_OSCCTRL32_OFFSET 0x0020 /* Oscillator 32 Control Register */ +#define SAM_BSCIF_RC32KCR_OFFSET 0x0024 /* 32kHz RC Oscillator Control Register */ +#define SAM_BSCIF_RC32KTUNE_OFFSET 0x0028 /* 32kHz RC Oscillator Tuning Register */ +#define SAM_BSCIF_BOD33CTRL_OFFSET 0x002c /* BOD33 Control Register */ +#define SAM_BSCIF_BOD33LEVEL_OFFSET 0x0030 /* BOD33 Level Register */ +#define SAM_BSCIF_BOD33SAMPLING_OFFSET 0x0034 /* BOD33 Sampling Control Register */ +#define SAM_BSCIF_BOD18CTRL_OFFSET 0x0038 /* BOD18 Control Register */ +#define SAM_BSCIF_BOD18LEVEL_OFFSET 0x003c /* BOD18 Level Register */ +#define SAM_BSCIF_BOD18SAMPLING_OFFSET 0x0040 /* BOD18 Sampling Control Register */ +#define SAM_BSCIF_VREGCR_OFFSET 0x0044 /* Voltage Regulator Configuration Register */ +#define SAM_BSCIF_RC1MCR_OFFSET 0x0058 /* 1MHz RC Clock Configuration Register */ +#define SAM_BSCIF_BGCTRL_OFFSET 0x0060 /* Bandgap Control Register */ +#define SAM_BSCIF_BGS_OFFSET 0x0064 /* Bandgap Status Register */ +#define SAM_BSCIF_BR_OFFSET(n) (0x0078+((n)<<2) /* 0x0078-0x0084 Backup register n=0..3 */ +#define SAM_BSCIF_BR0_OFFSET 0x0078 /* Backup register 0 */ +#define SAM_BSCIF_BR1_OFFSET 0x007c /* Backup register 1 */ +#define SAM_BSCIF_BR2_OFFSET 0x0080 /* Backup register 2 */ +#define SAM_BSCIF_BR3_OFFSET 0x0004 /* Backup register 3 */ +#define SAM_BSCIF_BRIFBVERSION_OFFSET 0x03e4 /* Backup Register Interface Version Register */ +#define SAM_BSCIF_BGREFIFBVERSION_OFFSET 0x03e8 /* BGREFIF Version Register */ +#define SAM_BSCIF_VREGIFGVERSION_OFFSET 0x03ec /* Voltage Regulator Version Register */ +#define SAM_BSCIF_BODIFCVERSION_OFFSET 0x03f0 /* BOD Version Register */ +#define SAM_BSCIF_RC32KIFBVERSION_OFFSET 0x03f4 /* 32kHz RC Oscillator Version Register */ +#define SAM_BSCIF_OSC32IFAVERSION_OFFSET 0x03f8 /* 32 kHz Oscillator Version Register */ +#define SAM_BSCIF_VERSION_OFFSET 0x03fc /* BSCIF Version Register */ + +/* BSCIF register adresses **************************************************************/ + +#define SAM_BSCIF_IER (SAM_BSCIF_BASE+SAM_BSCIF_IER_OFFSET) +#define SAM_BSCIF_IDR (SAM_BSCIF_BASE+SAM_BSCIF_IDR_OFFSET) +#define SAM_BSCIF_IMR (SAM_BSCIF_BASE+SAM_BSCIF_IMR_OFFSET) +#define SAM_BSCIF_ISR (SAM_BSCIF_BASE+SAM_BSCIF_ISR_OFFSET) +#define SAM_BSCIF_ICR (SAM_BSCIF_BASE+SAM_BSCIF_ICR_OFFSET) +#define SAM_BSCIF_PCLKSR (SAM_BSCIF_BASE+SAM_BSCIF_PCLKSR_OFFSET) +#define SAM_BSCIF_UNLOCK (SAM_BSCIF_BASE+SAM_BSCIF_UNLOCK_OFFSET) +#define SAM_BSCIF_CSCR (SAM_BSCIF_BASE+SAM_BSCIF_CSCR_OFFSET) +#define SAM_BSCIF_OSCCTRL32 (SAM_BSCIF_BASE+SAM_BSCIF_OSCCTRL32_OFFSET) +#define SAM_BSCIF_RC32KCR (SAM_BSCIF_BASE+SAM_BSCIF_RC32KCR_OFFSET) +#define SAM_BSCIF_RC32KTUNE (SAM_BSCIF_BASE+SAM_BSCIF_RC32KTUNE_OFFSET) +#define SAM_BSCIF_BOD33CTRL (SAM_BSCIF_BASE+SAM_BSCIF_BOD33CTRL_OFFSET) +#define SAM_BSCIF_BOD33LEVEL (SAM_BSCIF_BASE+SAM_BSCIF_BOD33LEVEL_OFFSET) +#define SAM_BSCIF_BOD33SAMPLING (SAM_BSCIF_BASE+SAM_BSCIF_BOD33SAMPLING_OFFSET) +#define SAM_BSCIF_BOD18CTRL (SAM_BSCIF_BASE+SAM_BSCIF_BOD18CTRL_OFFSET) +#define SAM_BSCIF_BOD18LEVEL (SAM_BSCIF_BASE+SAM_BSCIF_BOD18LEVEL_OFFSET) +#define SAM_BSCIF_BOD18SAMPLING (SAM_BSCIF_BASE+SAM_BSCIF_BOD18SAMPLING_OFFSET) +#define SAM_BSCIF_VREGCR (SAM_BSCIF_BASE+SAM_BSCIF_VREGCR_OFFSET) +#define SAM_BSCIF_RC1MCR (SAM_BSCIF_BASE+SAM_BSCIF_RC1MCR_OFFSET) +#define SAM_BSCIF_BGCTRL (SAM_BSCIF_BASE+SAM_BSCIF_BGCTRL_OFFSET) +#define SAM_BSCIF_BGS (SAM_BSCIF_BASE+SAM_BSCIF_BGS_OFFSET) +#define SAM_BSCIF_BR(n) (SAM_BSCIF_BASE+SAM_BSCIF_BR_OFFSET(n)) +#define SAM_BSCIF_BR0 (SAM_BSCIF_BASE+SAM_BSCIF_BR0_OFFSET) +#define SAM_BSCIF_BR1 (SAM_BSCIF_BASE+SAM_BSCIF_BR1_OFFSET) +#define SAM_BSCIF_BR2 (SAM_BSCIF_BASE+SAM_BSCIF_BR2_OFFSET) +#define SAM_BSCIF_BR3 (SAM_BSCIF_BASE+SAM_BSCIF_BR3_OFFSET) +#define SAM_BSCIF_BRIFBVERSION (SAM_BSCIF_BASE+SAM_BSCIF_BRIFBVERSION_OFFSET) +#define SAM_BSCIF_BGREFIFBVERSION (SAM_BSCIF_BASE+SAM_BSCIF_BGREFIFBVERSION_OFFSET) +#define SAM_BSCIF_VREGIFGVERSION (SAM_BSCIF_BASE+SAM_BSCIF_VREGIFGVERSION_OFFSET) +#define SAM_BSCIF_BODIFCVERSION (SAM_BSCIF_BASE+SAM_BSCIF_BODIFCVERSION_OFFSET) +#define SAM_BSCIF_RC32KIFBVERSION (SAM_BSCIF_BASE+SAM_BSCIF_RC32KIFBVERSION_OFFSET) +#define SAM_BSCIF_OSC32IFAVERSION (SAM_BSCIF_BASE+SAM_BSCIF_OSC32IFAVERSION_OFFSET) +#define SAM_BSCIF_VERSION (SAM_BSCIF_BASE+SAM_BSCIF_VERSION_OFFSET) + +/* BSCIF register bit definitions *******************************************************/ + +/* Interrupt Enable Register */ +/* Interrupt Disable Register */ +/* Interrupt Mask Register */ +/* Interrupt Status Register */ +/* Interrupt Clear Register */ + +#define BSCIF_INT_OSC32RDY (1 << 0) /* Bit 0 */ +#define BSCIF_INT_RC32KRDY (1 << 1) /* Bit 1 */ +#define BSCIF_INT_RC32KLOCK (1 << 2) /* Bit 2 */ +#define BSCIF_INT_RC32KREFE (1 << 3) /* Bit 3 */ +#define BSCIF_INT_RC32KSAT (1 << 4) /* Bit 4 */ +#define BSCIF_INT_BOD33DET (1 << 5) /* Bit 5 */ +#define BSCIF_INT_BOD18DET (1 << 6) /* Bit 6 */ +#define BSCIF_INT_BOD33SYNRDY (1 << 7) /* Bit 7 */ +#define BSCIF_INT_BOD18SYNRDY (1 << 8) /* Bit 8 */ +#define BSCIF_INT_SSWRDY (1 << 9) /* Bit 9: Buck voltage regulator has stopped switching */ +#define BSCIF_INT_VREGOK (1 << 10) /* Bit 10 */ +#define BSCIF_INT_LPBGRDY (1 << 12) /* Bit 12 */ +#define BSCIF_INT_AE (1 << 31) /* Bit 31 */ + +/* Power and Clocks Status Register */ + +#define BSCIF_PCLKSR_OSC32RDY (1 << 0) /* Bit 0 */ +#define BSCIF_PCLKSR_RC32KRDY (1 << 1) /* Bit 1 */ +#define BSCIF_PCLKSR_RC32KLOCK (1 << 2) /* Bit 2 */ +#define BSCIF_PCLKSR_RC32KREFE (1 << 3) /* Bit 3 */ +#define BSCIF_PCLKSR_RC32KSAT (1 << 4) /* Bit 4 */ +#define BSCIF_PCLKSR_BOD33DET (1 << 5) /* Bit 5 */ +#define BSCIF_PCLKSR_BOD18DET (1 << 6) /* Bit 6 */ +#define BSCIF_PCLKSR_BOD33SYNRDY (1 << 7) /* Bit 7 */ +#define BSCIF_PCLKSR_BOD18SYNRDY (1 << 8) /* Bit 8 */ +#define BSCIF_PCLKSR_SSWRDY (1 << 9) /* Bit 9: Buck voltage regulator has stopped switching */ +#define BSCIF_PCLKSR_VREGOK (1 << 10) /* Bit 10 */ +#define BSCIF_PCLKSR_RC1MRDY (1 << 11) /* Bit 11 */ +#define BSCIF_PCLKSR_LPBGRDY (1 << 12) /* Bit 12 */ + +/* Unlock Register */ + +#define BSCIF_UNLOCK_ADDR_SHIFT (0) /* Bits 0-9: Unlock Address */ +#define BSCIF_UNLOCK_ADDR_MASK (0x3ff << BSCIF_UNLOCK_ADDR_SHIFT) +# define BSCIF_UNLOCK_ADDR(n) ((n) << BSCIF_UNLOCK_ADDR_SHIFT) +#define BSCIF_UNLOCK_KEY_SHIFT (24) /* Bits 24-31: Unlock Key */ +#define BSCIF_UNLOCK_KEY_MASK (0xff << BSCIF_UNLOCK_KEY_SHIFT) +# define BSCIF_UNLOCK_KEY(n) ((n) << BSCIF_UNLOCK_KEY_SHIFT) + +/* Chip Specific Configuration Register */ + +/* Oscillator 32 Control Register */ + +#define BSCIF_OSCCTRL32_OSC32EN (1 << 0) /* Bit 0: 32 KHz Oscillator Enable */ +#define BSCIF_OSCCTRL32_EN32K (1 << 2) /* Bit 2: 32 KHz output Enable */ +#define BSCIF_OSCCTRL32_EN1K (1 << 3) /* Bit 3: 1 KHz output Enable */ +#define BSCIF_OSCCTRL32_MODE_SHIFT (8) /* Bits 8-10: Oscillator Mode */ +#define BSCIF_OSCCTRL32_MODE_MASK (7 << BSCIF_OSCCTRL32_MODE_SHIFT) +# define BSCIF_OSCCTRL32_MODE_EXTCLK (0 << BSCIF_OSCCTRL32_MODE_SHIFT) /* External clock */ +# define BSCIF_OSCCTRL32_MODE_XTAL (1 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal mode */ +# define BSCIF_OSCCTRL32_MODE_XTALAC (3 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + amplitude controlled mode */ +# define BSCIF_OSCCTRL32_MODE_XTALHC (4 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current mode */ +# define BSCIF_OSCCTRL32_MODE_XTALHCAC (5 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current + amplitude controlled mode */ +#define BSCIF_OSCCTRL32_SELCURR_SHIFT (12) /* Bits 12-15: Current Selection */ +#define BSCIF_OSCCTRL32_SELCURR_MASK (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_50 (0 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_75 (1 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_100 (2 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_125 (3 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_150 (4 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_175 (5 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_200 (6 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_225 (7 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_250 (8 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_275 (9 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_300 (10 << BSCIF_OSCCTRL32_SELCURR_SHIFT) /* (recommended value) */ +# define BSCIF_OSCCTRL32_SELCURR_325 (11 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_350 (12 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_375 (13 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_400 (14 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_425 (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +#define BSCIF_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Start-up Time */ +#define BSCIF_OSCCTRL32_STARTUP_MASK (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) +# define BSCIF_OSCCTRL32_STARTUP_0 (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) +# define BSCIF_OSCCTRL32_STARTUP_128 (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 128 1.1 ms */ +# define BSCIF_OSCCTRL32_STARTUP_8K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 8192 72.3 ms */ +# define BSCIF_OSCCTRL32_STARTUP_16K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 16384 143 ms */ +# define BSCIF_OSCCTRL32_STARTUP_64K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 65536 570 ms */ +# define BSCIF_OSCCTRL32_STARTUP_128K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 131072 1.1 s */ +# define BSCIF_OSCCTRL32_STARTUP_256K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 262144 2.3 s */ +# define BSCIF_OSCCTRL32_STARTUP_512K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 524288 4.6 s */ +#define BSCIF_OSCCTRL32_RESERVED (1 << 31) /* Bit 31: Reserved, must always be written as zero */ + +/* 32kHz RC Oscillator Control Register */ + +#define BSCIF_RC32KCR_EN (1 << 0) /* Bit 0: Enable as Generic clock source */ +#define BSCIF_RC32KCR_TCEN (1 << 1) /* Bit 1: Temperature Compensation Enable */ +#define BSCIF_RC32KCR_EN32K (1 << 2) /* Bit 2: Enable 32 KHz output */ +#define BSCIF_RC32KCR_EN1K (1 << 3) /* Bit 3: Enable 1 kHz output */ +#define BSCIF_RC32KCR_MODE (1 << 4) /* Bit 4: Mode Selection */ +#define BSCIF_RC32KCR_REF (1 << 5) /* Bit 5: Reference select */ +#define BSCIF_RC32KCR_FCD (1 << 7) /* Bit 7: Flash calibration done */ + +/* 32kHz RC Oscillator Tuning Register */ + +#define BSCIF_RC32KTUNE_FINE_SHIFT (0) /* Bits 0-5: Fine Value */ +#define BSCIF_RC32KTUNE_FINE_MASK (0x3f << BSCIF_RC32KTUNE_FINE_SHIFT) +#define BSCIF_RC32KTUNE_COARSE_SHIFT (16) /* Bits 16-22: Coarse value */ +#define BSCIF_RC32KTUNE_COARSE_MASK (0x7f << BSCIF_RC32KTUNE_COARSE_SHIFT) + +/* BOD33 Control Register */ +/* BOD18 Control Register */ + +#define BSCIF_BODCTRL_EN (1 << 0) /* Bit 0: Enable */ +#define BSCIF_BODCTRL_HYST (1 << 1) /* Bit 1: BOD Hysteresis */ +#define BSCIF_BODCTRL_ACTION_SHIFT (8) /* Bits 8-9: Action */ +# define BSCIF_BODCTRL_ACTION_RESET (1 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates a reset */ +# define BSCIF_BODCTRL_ACTION_INTR (2 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates an interrupt */ +#define BSCIF_BODCTRL_MODE (1 << 0) /* Bit 0: Operation modes */ +#define BSCIF_BODCTRL_FCD (1 << 0) /* Bit 0: BOD Fuse Calibration Done */ +#define BSCIF_BODCTRL_SFV (1 << 0) /* Bit 0: BOD Control Register Store Final Value */ + +/* BOD33 Level Register */ +/* BOD18 Level Register */ + +#define BSCIF_BODLEVEL_CEN (1 << 0) /* Bit 0: Clock Enable */ +#define BSCIF_BODLEVEL_CSSEL (1 << 1) /* Bit 1: Clock Source Select */ +#define BSCIF_BODLEVEL_PSEL_SHIFT (8) /* Bits 8-11: Prescaler Select */ +#define BSCIF_BODLEVEL_PSEL_MASK (15 << BSCIF_BODLEVEL_PSEL_SHIFT) + +/* BOD33 Sampling Control Register */ +/* BOD18 Sampling Control Register */ + +#define BSCIF_BODSAMPLING_VAL_SHIFT (0) /* Bits 0-5: BOD Value */ +#define BSCIF_BODSAMPLING_VAL_MASK (0x3f << BSCIF_BODSAMPLING_VAL_SHIFT) +#define BSCIF_BODSAMPLING_RANGE (1 << 31) /* Bit 31: BOD Threshold Range (available for BOD18 only */ + +/* Voltage Regulator Configuration Register */ + +#define BSCIF_VREGCR_DIS (1 << 0) /* Bit 0: Voltage Regulator disable */ +#define BSCIF_VREGCR_SSG (1 << 8) /* Bit 8: Spread Spectrum Generator Enable */ +#define BSCIF_VREGCR_SSW (1 << 9) /* Bit 9: Stop Switching */ +#define BSCIF_VREGCR_SSWEVT (1 << 10) /* Bit 10: Stop Switching On Event Enable */ +#define BSCIF_VREGCR_SFV (1 << 31) /* Bit 31: Store Final Value */ + +/* 1MHz RC Clock Configuration Register */ + +#define BSCIF_RC1MCR_FCD (1 << 0) /* Bit 0: Flash Calibration Done */ +#define BSCIF_RC1MCR_CLKOEN (1 << 7) /* Bit 7: 1MHz RC Osc Clock Output Enable */ +#define BSCIF_RC1MCR_CLKCAL_SHIFT (8) /* Bits 8-12: 1MHz RC Osc Calibration */ +#define BSCIF_RC1MCR_CLKCAL_MASK (31 << BSCIF_RC1MCR_CLKCAL_SHIFT) + +/* Bandgap Control Register */ + +#define BSCIF_BGCTRL_ADCISEL_SHIFT (0) /* Bits 0-1: ADC Input Selection */ +#define BSCIF_BGCTRL_ADCISEL_MASK (3 << BSCIF_BGCTRL_ADCISEL_SHIFT) +#define BSCIF_BGCTRL_TSEN (1 << 8) + +/* Bandgap Status Register */ + +#define BSCIF_BGS_BGBUFRDY_SHIFT (0) /* Bits 0-7: Bandgap Buffer Ready */ +#define BSCIF_BGS_BGBUFRDY_MASK (0xff << BSCIF_BGS_BGBUFRDY_SHIFT) +#define BSCIF_BGS_BGRDY (1 << 16) /* Bit 16: Bandgap Voltage Reference Ready */ +#define BSCIF_BGS_LPBGRDY (1 << 17) /* Bit 17: Low Power Bandgap Voltage Reference Ready */ +#define BSCIF_BGS_VREF_SHIFT (18) /* Bits 18-19: Voltage Reference Used by the System */ +#define BSCIF_BGS_VREF_MASK (3 << BSCIF_BGS_VREF_SHIFT) + +/* 0x0078-0x0084 Backup register n=0..3 (32-bit data) */ + +/* Backup Register Interface Version Register */ +/* BGREFIF Version Register */ +/* Voltage Regulator Version Register */ +/* BOD Version Register */ +/* 32kHz RC Oscillator Version Register */ +/* 32 kHz Oscillator Version Register */ +/* BSCIF Version Register */ + +#define BSCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ +#define BSCIF_VERSION_MASK (0xfff << BSCIF_VERSION_VERSION_SHIFT) +#define BSCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ +#define BSCIF_VARIANT_MASK (15 << BSCIF_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h b/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h index d2503aa18d..6902578d77 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h @@ -80,7 +80,7 @@ #define SAM_FLASHCALW_FCMD (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FCMD_OFFSET) #define SAM_FLASHCALW_FSR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FSR_OFFSET) #define SAM_FLASHCALW_FPR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FPR_OFFSET) -#define SAM_FLASHCALW_FSR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FSR_OFFSET) +#define SAM_FLASHCALW_FVR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FVR_OFFSET) #define SAM_FLASHCALW_FGPFRHI (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FGPFRHI_OFFSET) #define SAM_FLASHCALW_FGPFRLO (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FGPFRLO_OFFSET) @@ -131,6 +131,7 @@ #define FLASHCALW_FCMD_PAGEN_MASK (0xffff << FLASHCALW_FCMD_PAGEN_SHIFT) #define FLASHCALW_FCMD_KEY_SHIFT (14) /* Bits 24-31: Write protection key */ #define FLASHCALW_FCMD_KEY_MASK (0xff << FLASHCALW_FCMD_KEY_SHIFT) +# define FLASHCALW_FCMD_KEY (0xa5 << FLASHCALW_FCMD_KEY_SHIFT) /* Flash Status Register */ @@ -161,7 +162,6 @@ #define FLASHCALW_FSR_LOCK15 (1 << 31) /* Bit 31: Lock Region 15 Lock Status */ /* Flash Parameter Register */ -#define FLASHCALW_FPR_ #define FLASHCALW_FPR_FSZ_SHIFT (0) /* Bits 0-3: Flash Size */ #define FLASHCALW_FPR_FSZ_MASK (15 << FLASHCALW_FPR_FSZ_SHIFT) @@ -333,6 +333,36 @@ #define FLASH_CMD_HSEN 16 /* High Speed Mode Enable */ #define FLASH_CMD_HSDIS 17 /* High Speed Mode Disable */ +/* Maximum CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes + * (Table 42-30 in the big data sheet). + * + * ------- ------------------- ---------- ---------- + * Power Flash Read Mode Flash Maximum + * Sclaing Wait Operating + * Mode HSEN HSDIS FASTWKUP States Frequency + * ------- ---- ----- -------- ---------- ---------- + * PS0 X X 1 12MHz + * " " X 0 18MHz + * " " X 1 36MHz + * PS1 X X 1 12MHz + * " " X 0 8MHz + * " " X 1 12MHz + * PS2 X 0 24Mhz + * " " X 1 48MHz + * ------- ---- ----- -------- ---------- ---------- + */ + +#define FLASH_MAXFREQ_PS0_HSDIS_FASTWKUP_FWS1 (12000000ul) +#define FLASH_MAXFREQ_PS0_HSDIS_FWS0 (18000000ul) +#define FLASH_MAXFREQ_PS0_HSDIS_FWS1 (36000000ul) + +#define FLASH_MAXFREQ_PS1_HSDIS_FASTWKUP_FWS1 (12000000ul) +#define FLASH_MAXFREQ_PS1_HSDIS_FWS0 (8000000ul) +#define FLASH_MAXFREQ_PS1_HSDIS_FWS1 (12000000ul) + +#define FLASH_MAXFREQ_PS2_HSEN_FWS0 (24000000ul) +#define FLASH_MAXFREQ_PS2_HSEN_FWS1 (48000000ul) + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_picouart.h b/nuttx/arch/arm/src/sam34/chip/sam4l_picouart.h new file mode 100644 index 0000000000..ea7c428644 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_picouart.h @@ -0,0 +1,121 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_picouart.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PICOUART_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PICOUART_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PICOUART register offsets ************************************************************/ + +#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_PICOUART_CFG_OFFSET 0x0004 /* Configuration Register */ +#define SAM_PICOUART_SR_OFFSET 0x0008 /* Status Register */ +#define SAM_PICOUART_RHR_OFFSET 0x000c /* Receive Holding Register */ +#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */ + +/* PICOUART register adresses ***********************************************************/ + +#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_PICOUART_CFG_OFFSET 0x0004 /* Configuration Register */ +#define SAM_PICOUART_CFG_OFFSET 0x0004 /* Configuration Register */ +#define SAM_PICOUART_SR_OFFSET 0x0008 /* Status Register */ +#define SAM_PICOUART_SR_OFFSET 0x0008 /* Status Register */ +#define SAM_PICOUART_RHR_OFFSET 0x000c /* Receive Holding Register */ +#define SAM_PICOUART_RHR_OFFSET 0x000c /* Receive Holding Register */ +#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */ +#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */ + +/* PICOUART register bit definitions ****************************************************/ + +/* Control Register */ + +#define PICOUART_CR_EN (1 << 0) /* Bit 0: Enable */ +#define PICOUART_CR_DIS (1 << 1) /* Bit 1: Disable */ + +/* Configuration Register */ + +#define PICOUART_CFG_SOURCE_SHIFT (0) /* Bit 0-1: Source Enable Mode */ +#define PICOUART_CFG_SOURCE_MASK (3 << PICOUART_CFG_SOURCE_SHIFT) +# define PICOUART_CFG_SOURCE_WE (0 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up and event disable */ +# define PICOUART_CFG_SOURCE_WESB (1 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on start bit detection */ +# define PICOUART_CFG_SOURCE_WEFF (2 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on full frame reception */ +# define PICOUART_CFG_SOURCE_WECH (3 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on character recognition */ +#define PICOUART_CFG_ACTION (1 << 0) /* Bit 0: Action to perform */ +#define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */ +#define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */ +#define PICOUART_CFG_MATCH_MASK (0xff << PICOUART_CFG_MATCH_SHIFT) + +/* Status Register */ + +#define PICOUART_SR_EN (1 << 0) /* Bit 0: Enable Status */ +#define PICOUART_SR_DRDY (1 << 1) /* Bit 1: Data Ready */ + +/* Receive Holding Register */ + +#define PICOUART_RHR_MASK 0xff + +/* Version Register */ + +#define PICOUART_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number */ +#define PICOUART_VERSION_MASK (0xfff << PICOUART_VERSION_SHIFT) +#define PICOUART_VARIANT_SHIFT (16) /* Bits 16-18: Reserved */ +#define PICOUART_VARIANT_MASK (7 << PICOUART_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PICOUART_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h index c4babee650..68f4b2074d 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h @@ -48,7 +48,7 @@ /************************************************************************************ * Definitions ************************************************************************************/ -/* Alternate Pin Functions. +/* Alternate Pin Functions. * * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. * Drivers, however, will use the pin selection without the numeric suffix. diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h b/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h index ba78b3a957..86a55af8dc 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h @@ -145,7 +145,7 @@ /* CPU Mask Register Bit-field Definitions */ -#define PM_CPUMASK_OCD (1 << 0) /* Bit 0: OCD */ +#define PM_CPUMASK_OCD (1 << 0) /* Bit 0: On-Chip Debug */ /* HSB Mask Register Bit-field Definitions */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_scif.h b/nuttx/arch/arm/src/sam34/chip/sam4l_scif.h new file mode 100644 index 0000000000..d6f6661e6b --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_scif.h @@ -0,0 +1,432 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_scif.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_SCIF_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_SCIF_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SCIF register offsets ****************************************************************/ + +#define SAM_SCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */ +#define SAM_SCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */ +#define SAM_SCIF_IMR_OFFSET 0x0008 /* Interrupt Mask Register */ +#define SAM_SCIF_ISR_OFFSET 0x000c /* Interrupt Status Register */ +#define SAM_SCIF_ICR_OFFSET 0x0010 /* Interrupt Clear Register */ +#define SAM_SCIF_PCLKSR_OFFSET 0x0014 /* Power and Clocks Status Register */ +#define SAM_SCIF_UNLOCK_OFFSET 0x0018 /* Unlock Register */ +#define SAM_SCIF_CSCR_OFFSET 0x001c /* Chip Specific Configuration Register */ +#define SAM_SCIF_OSCCTRL0_OFFSET 0x0020 /* Oscillator Control Register */ +#define SAM_SCIF_PLL0_OFFSET 0x0024 /* PLL0 Control Register */ +#define SAM_SCIF_DFLL0CONF_OFFSET 0x0028 /* DFLL0 Config Register */ +#define SAM_SCIF_DFLL0VAL_OFFSET 0x002c /* DFLL Value Register */ +#define SAM_SCIF_DFLL0MUL_OFFSET 0x0030 /* DFLL0 Multiplier Register */ +#define SAM_SCIF_DFLL0STEP_OFFSET 0x0034 /* DFLL0 Step Register */ +#define SAM_SCIF_DFLL0SSG_OFFSET 0x0038 /* DFLL0 Spread Spectrum Generator Control Register */ +#define SAM_SCIF_DFLL0RATIO_OFFSET 0x003c /* DFLL0 Ratio Register */ +#define SAM_SCIF_DFLL0SYNC_OFFSET 0x0040 /* DFLL0 Synchronization Register */ +#define SAM_SCIF_RCCR_OFFSET 0x0044 /* System RC Oscillator Calibration Register */ +#define SAM_SCIF_RCFASTCFG_OFFSET 0x0048 /* 4/8/12MHz RC Oscillator Configuration Register */ +#define SAM_SCIF_RCFASTSR_OFFSET 0x004c /* 4/8/12MHz RC Oscillator Status Register */ +#define SAM_SCIF_RC80MCR_OFFSET 0x0050 /* 80MHz RC Oscillator Register */ +#define SAM_SCIF_HRPCR_OFFSET 0x0064 /* High Resolution Prescaler Control Register */ +#define SAM_SCIF_FPCR_OFFSET 0x0068 /* Fractional Prescaler Control Register */ +#define SAM_SCIF_FPMUL_OFFSET 0x006c /* Fractional Prescaler Multiplier Register */ +#define SAM_SCIF_FPDIV_OFFSET 0x0070 /* Fractional Prescaler DIVIDER Register */ +#define SAM_SCIF_GCCTRL0_OFFSET 0x0074 /* Generic Clock Control0 */ +#define SAM_SCIF_GCCTRL1_OFFSET 0x0078 /* Generic Clock Control1 */ +#define SAM_SCIF_GCCTRL2_OFFSET 0x007c /* Generic Clock Control2 */ +#define SAM_SCIF_GCCTRL3_OFFSET 0x0080 /* Generic Clock Control3 */ +#define SAM_SCIF_GCCTRL4_OFFSET 0x0084 /* Generic Clock Control4 */ +#define SAM_SCIF_GCCTRL5_OFFSET 0x0088 /* Generic Clock Control5 */ +#define SAM_SCIF_GCCTRL6_OFFSET 0x008c /* Generic Clock Control6 */ +#define SAM_SCIF_GCCTRL7_OFFSET 0x0090 /* Generic Clock Control7 */ +#define SAM_SCIF_GCCTRL8_OFFSET 0x0094 /* Generic Clock Control8 */ +#define SAM_SCIF_GCCTRL9_OFFSET 0x0098 /* Generic Clock Control9 */ +#define SAM_SCIF_GCCTRL10_OFFSET 0x009c /* Generic Clock Control10 */ +#define SAM_SCIF_GCCTRL11_OFFSET 0x00a0 /* Generic Clock Control11 */ +#define SAM_SCIF_RCFASTVERSION_OFFSET 0x03d8 /* 4/8/12MHz RC Oscillator Version Register */ +#define SAM_SCIF_GCLKPRESCVERSION_OFFSET 0x03dc /* Generic Clock Prescaler Version Register */ +#define SAM_SCIF_PLLIFAVERSION_OFFSET 0x03e0 /* PLL Version Register */ +#define SAM_SCIF_OSCIFAVERSION_OFFSET 0x03e4 /* Oscillator0 Version Register */ +#define SAM_SCIF_DFLLIFBVERSION_OFFSET 0x03e8 /* DFLL Version Register */ +#define SAM_SCIF_RCOSCIFAVERSION_OFFSET 0x03ec /* System RC Oscillator Version Register */ +#define SAM_SCIF_RC80MVERSION_OFFSET 0x03f4 /* 80MHz RC Oscillator Version Register */ +#define SAM_SCIF_GCLKVERSION_OFFSET 0x03f8 /* Generic Clock Version Register */ +#define SAM_SCIF_VERSION_OFFSET 0x03fc /* SCIF Version Register */ + +/* SCIF register adresses ***************************************************************/ + +#define SAM_SCIF_IER (SAM_SCIF_BASE+SAM_SCIF_IER_OFFSET) +#define SAM_SCIF_IDR (SAM_SCIF_BASE+SAM_SCIF_IDR_OFFSET) +#define SAM_SCIF_IMR (SAM_SCIF_BASE+SAM_SCIF_IMR_OFFSET) +#define SAM_SCIF_ISR (SAM_SCIF_BASE+SAM_SCIF_ISR_OFFSET) +#define SAM_SCIF_ICR (SAM_SCIF_BASE+SAM_SCIF_ICR_OFFSET) +#define SAM_SCIF_PCLKSR (SAM_SCIF_BASE+SAM_SCIF_PCLKSR_OFFSET) +#define SAM_SCIF_UNLOCK (SAM_SCIF_BASE+SAM_SCIF_UNLOCK_OFFSET) +#define SAM_SCIF_CSCR (SAM_SCIF_BASE+SAM_SCIF_CSCR_OFFSET) +#define SAM_SCIF_OSCCTRL0 (SAM_SCIF_BASE+SAM_SCIF_OSCCTRL0_OFFSET) +#define SAM_SCIF_PLL0 (SAM_SCIF_BASE+SAM_SCIF_PLL0_OFFSET) +#define SAM_SCIF_DFLL0CONF (SAM_SCIF_BASE+SAM_SCIF_DFLL0CONF_OFFSET) +#define SAM_SCIF_DFLL0VAL (SAM_SCIF_BASE+SAM_SCIF_DFLL0VAL_OFFSET) +#define SAM_SCIF_DFLL0MUL (SAM_SCIF_BASE+SAM_SCIF_DFLL0MUL_OFFSET) +#define SAM_SCIF_DFLL0STEP (SAM_SCIF_BASE+SAM_SCIF_DFLL0STEP_OFFSET) +#define SAM_SCIF_DFLL0SSG (SAM_SCIF_BASE+SAM_SCIF_DFLL0SSG_OFFSET) +#define SAM_SCIF_DFLL0RATIO (SAM_SCIF_BASE+SAM_SCIF_DFLL0RATIO_OFFSET) +#define SAM_SCIF_DFLL0SYNC (SAM_SCIF_BASE+SAM_SCIF_DFLL0SYNC_OFFSET) +#define SAM_SCIF_RCCR (SAM_SCIF_BASE+SAM_SCIF_RCCR_OFFSET) +#define SAM_SCIF_RCFASTCFG (SAM_SCIF_BASE+SAM_SCIF_RCFASTCFG_OFFSET) +#define SAM_SCIF_RCFASTSR (SAM_SCIF_BASE+SAM_SCIF_RCFASTSR_OFFSET) +#define SAM_SCIF_RC80MCR (SAM_SCIF_BASE+SAM_SCIF_RC80MCR_OFFSET) +#define SAM_SCIF_HRPCR (SAM_SCIF_BASE+SAM_SCIF_HRPCR_OFFSET) +#define SAM_SCIF_FPCR (SAM_SCIF_BASE+SAM_SCIF_FPCR_OFFSET) +#define SAM_SCIF_FPMUL (SAM_SCIF_BASE+SAM_SCIF_FPMUL_OFFSET) +#define SAM_SCIF_FPDIV (SAM_SCIF_BASE+SAM_SCIF_FPDIV_OFFSET) +#define SAM_SCIF_GCCTRL0 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL0_OFFSET) +#define SAM_SCIF_GCCTRL1 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL1_OFFSET) +#define SAM_SCIF_GCCTRL2 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL2_OFFSET) +#define SAM_SCIF_GCCTRL3 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL3_OFFSET) +#define SAM_SCIF_GCCTRL4 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL4_OFFSET) +#define SAM_SCIF_GCCTRL5 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL5_OFFSET) +#define SAM_SCIF_GCCTRL6 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL6_OFFSET) +#define SAM_SCIF_GCCTRL7 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL7_OFFSET) +#define SAM_SCIF_GCCTRL8 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL8_OFFSET) +#define SAM_SCIF_GCCTRL9 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL9_OFFSET) +#define SAM_SCIF_GCCTRL10 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL10_OFFSET) +#define SAM_SCIF_GCCTRL11 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL11_OFFSET) +#define SAM_SCIF_RCFASTVERSION (SAM_SCIF_BASE+SAM_SCIF_RCFASTVERSION_OFFSET) +#define SAM_SCIF_GCLKPRESCVERSION (SAM_SCIF_BASE+SAM_SCIF_GCLKPRESCVERSION_OFFSET) +#define SAM_SCIF_PLLIFAVERSION (SAM_SCIF_BASE+SAM_SCIF_PLLIFAVERSION_OFFSET) +#define SAM_SCIF_OSCIFAVERSION (SAM_SCIF_BASE+SAM_SCIF_OSCIFAVERSION_OFFSET) +#define SAM_SCIF_DFLLIFBVERSION (SAM_SCIF_BASE+SAM_SCIF_DFLLIFBVERSION_OFFSET) +#define SAM_SCIF_RCOSCIFAVERSION (SAM_SCIF_BASE+SAM_SCIF_RCOSCIFAVERSION_OFFSET) +#define SAM_SCIF_RC80MVERSION (SAM_SCIF_BASE+SAM_SCIF_RC80MVERSION_OFFSET) +#define SAM_SCIF_GCLKVERSION (SAM_SCIF_BASE+SAM_SCIF_GCLKVERSION_OFFSET) +#define SAM_SCIF_VERSION (SAM_SCIF_BASE+SAM_SCIF_VERSION_OFFSET) + +/* SCIF register bit definitions ********************************************************/ + +/* Interrupt Enable Register */ +/* Interrupt Disable Register */ +/* Interrupt Mask Register */ +/* Interrupt Status Register */ +/* Interrupt Clear Register */ +/* Power and Clocks Status Register */ + +#define SCIF_INT_OSC0RDY (1 << 0) /* Bit 0: OSC0 Ready */ +#define SCIF_INT_DFLL0LOCKC (1 << 1) /* Bit 1: DFLL0 Locked on Coarse Value */ +#define SCIF_INT_DFLL0LOCKF (1 << 2) /* Bit 2: DFLL0 Locked on Fine Value */ +#define SCIF_INT_DFLL0RDY (1 << 3) /* Bit 3: DFLL0 Synchronization Ready */ +#define SCIF_INT_DFLL0RCS (1 << 4) /* Bit 4: DFLL0 Reference Clock Stopped */ +#define SCIF_INT_PLL0LOCK (1 << 6) /* Bit 6: PLL0 Locked on Accurate value */ +#define SCIF_INT_PLL0LOCKLOST (1 << 7) /* Bit 7: PLL0 lock lost value */ +#define SCIF_INT_RCFASTLOCK (1 << 13) /* Bit 13: RCFAST Locked on Accurate value */ +#define SCIF_INT_RCFASTLOCKLOST (1 << 14) /* Bit 14: RCFAST lock lost value */ + +/* Unlock Register */ + +#define SCIF_UNLOCK_ADDR_SHIFT (0) /* Bits 0-9: Unlock Address */ +#define SCIF_UNLOCK_ADDR_MASK (0x3ff << SCIF_UNLOCK_ADDR_SHIFT) +# define SCIF_UNLOCK_ADDR(n) ((n) << SCIF_UNLOCK_ADDR_SHIFT) +#define SCIF_UNLOCK_KEY_SHIFT (24) /* Bits 24-31: Unlock Key */ +#define SCIF_UNLOCK_KEY_MASK (0xff << SCIF_UNLOCK_KEY_SHIFT) +# define SCIF_UNLOCK_KEY(n) ((n) << SCIF_UNLOCK_KEY_SHIFT) + +/* Chip Specific Configuration Register */ + +/* Oscillator Control Register */ + +#define SCIF_OSCCTRL0_MODE (1 << 0) /* Bit 0: Oscillator Mode */ +#define SCIF_OSCCTRL0_GAIN_SHIFT (1) /* Bits 1-2: Gain */ +#define SCIF_OSCCTRL0_GAIN_MASK (3 << SCIF_OSCCTRL0_GAIN_SHIFT) +# define SCIF_OSCCTRL0_GAIN(n) ((n) << SCIF_OSCCTRL0_GAIN_SHIFT) +#define SCIF_OSCCTRL0_AGC (1 << 3) /* Bit 3: Automatic Gain Control */ +#define SCIF_OSCCTRL0_STARTUP_SHIFT (9) /* Bits 8-11: Oscillator Start-up Time */ +#define SCIF_OSCCTRL0_STARTUP_MASK (15 << SCIF_OSCCTRL0_STARTUP_SHIFT) +# define SCIF_OSCCTRL0_STARTUP_0 (0 << SCIF_OSCCTRL0_STARTUP_SHIFT) +# define SCIF_OSCCTRL0_STARTUP_64 (1 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 64 557 us */ +# define SCIF_OSCCTRL0_STARTUP_128 (2 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 128 1.1 ms */ +# define SCIF_OSCCTRL0_STARTUP_2K (3 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 2048 18 ms */ +# define SCIF_OSCCTRL0_STARTUP_4K (4 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 4096 36 ms */ +# define SCIF_OSCCTRL0_STARTUP_8K (5 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 8192 71 ms */ +# define SCIF_OSCCTRL0_STARTUP_16K (6 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 16384 143 ms */ +# define SCIF_OSCCTRL0_STARTUP_32K (7 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 32768 285 ms */ +# define SCIF_OSCCTRL0_STARTUP_4 (8 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 4 35 us */ +# define SCIF_OSCCTRL0_STARTUP_8 (9 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 8 70 us */ +# define SCIF_OSCCTRL0_STARTUP_16 (10 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 16 139 us */ +# define SCIF_OSCCTRL0_STARTUP_32 (11 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 32 278 us */ +# define SCIF_OSCCTRL0_STARTUP_256 (12 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 256 2.2 ms */ +# define SCIF_OSCCTRL0_STARTUP_512 (13 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 512 4.5 ms */ +# define SCIF_OSCCTRL0_STARTUP_1K (14 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 1024 8.9 ms */ +# define SCIF_OSCCTRL0_STARTUP_32K2 (15 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 2768 285 ms */ +#define SCIF_OSCCTRL0_OSCEN (1 << 16) /* Bit 16: Oscillator Enable */ + +/* PLL0 Control Register */ + +#define SCIF_PLL0_PLLEN (1 << 0) /* Bit 0: PLL Enable */ +#define SCIF_PLL0_PLLOSC_SHIFT (1) /* Bits 1-2: PLL Oscillator Select */ +#define SCIF_PLL0_PLLOSC_MASK (3 << SCIF_PLL0_PLLOSC_SHIFT) +# define SCIF_PLL0_PLLOSC_OSC0 (0 << SCIF_PLL0_PLLOSC_SHIFT) /* Output clock from Oscillator0 */ +# define SCIF_PLL0_PLLOSC_GCLK9 (1 << SCIF_PLL0_PLLOSC_SHIFT) /* Generic clock 9 */ +#define SCIF_PLL0_PLLOPT_SHIFT (3) /* Bits 3-5: PLL Option */ +#define SCIF_PLL0_PLLOPT_MASK (7 << SCIF_PLL0_PLLOPT_SHIFT) +# define SCIF_PLL0_PLLOPT_FVO (1 << SCIF_PLL0_PLLOPT_SHIFT) /* Selects the VCO frequency range (fvco) */ +# define SCIF_PLL0_PLLOPT_DIV2 (2 << SCIF_PLL0_PLLOPT_SHIFT) /* Divides the output frequency by 2 */ +# define SCIF_PLL0_PLLOPT_WBM (4 << SCIF_PLL0_PLLOPT_SHIFT) /* Wide-Bandwidth mode */ +#define SCIF_PLL0_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */ +#define SCIF_PLL0_PLLDIV_MASK (15 << SCIF_PLL0_PLLDIV_SHIFT) +#define SCIF_PLL0_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */ +#define SCIF_PLL0_PLLMUL_MASK (15 << SCIF_PLL0_PLLMUL_SHIFT) +#define SCIF_PLL0_PLLCOUNT_SHIFT (24) /* Bits 24-24: PLL Count */ +#define SCIF_PLL0_PLLCOUNT_MASK (63 << SCIF_PLL0_PLLCOUNT_SHIFT) +# define SCIF_PLL0_PLLCOUNT_MAX (63 << SCIF_PLL0_PLLCOUNT_SHIFT) + +/* PLL0 operates in two frequency ranges as determined by SCIF_PLL0_PLLOPT_FVO: + * + * 0: 80MHz < fvco < 180MHz + * 1: 160MHz < fvco < 240MHz + * + * These ranges and recommend threshold value are defined below: + */ + +#define SCIF_PLL0_VCO_RANGE1_MINFREQ 160000000 +#define SCIF_PLL0_VCO_RANGE1_MAXFREQ 240000000 +#define SCIF_PLL0_VCO_RANGE0_MINFREQ 80000000 +#define SCIF_PLL0_VCO_RANGE0_MAXFREQ 180000000 + +#define SAM_PLL0_VCO_RANGE_THRESHOLD \ + ((SCIF_PLL0_VCO_RANGE1_MINFREQ + SCIF_PLL0_VCO_RANGE0_MAXFREQ) >> 1) + +/* DFLL0 Config Register */ + +#define SCIF_DFLL0CONF_EN (1 << 0) /* Bit 0: Enable */ +#define SCIF_DFLL0CONF_MODE (1 << 1) /* Bit 1: Mode Selection */ +#define SCIF_DFLL0CONF_STABLE (1 << 2) /* Bit 2: Stable DFLL Frequency */ +#define SCIF_DFLL0CONF_LLAW (1 << 3) /* Bit 3: Lose Lock After Wake */ +#define SCIF_DFLL0CONF_CCDIS (1 << 5) /* Bit 5: Chill Cycle Disable */ +#define SCIF_DFLL0CONF_QLDIS (1 << 6) /* Bit 6: Quick Lock Disable */ +#define SCIF_DFLL0CONF_RANGE_SHIFT (16) /* Bits 16-17: Range Value */ +#define SCIF_DFLL0CONF_RANGE_MASK (3 << SCIF_DFLL0CONF_RANGE_SHIFT) +# define SCIF_DFLL0CONF_RANGE(n) ((n) << SCIF_DFLL0CONF_RANGE_SHIFT) +# define SCIF_DFLL0CONF_RANGE0 (0 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 96-150MHz */ +# define SCIF_DFLL0CONF_RANGE1 (1 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 50-110MHz */ +# define SCIF_DFLL0CONF_RANGE2 (2 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 25-55MHz */ +# define SCIF_DFLL0CONF_RANGE3 (3 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 20-30MHz */ +#define SCIF_DFLL0CONF_FCD (1 << 23) /* Bit 23: Fuse Calibration Done */ +#define SCIF_DFLL0CONF_CALIB_SHIFT (24) /* Bits 24-27: Calibration Value */ +#define SCIF_DFLL0CONF_CALIB_MASK (15 << SCIF_DFLL0CONF_CALIB_SHIFT) + +/* Min/max frequencies for each DFLL0 range */ + +#define SCIF_DFLL0CONF_MAX_RANGE0 (150000000) +#define SCIF_DFLL0CONF_MIN_RANGE0 (96000000) +#define SCIF_DFLL0CONF_MAX_RANGE1 (110000000) +#define SCIF_DFLL0CONF_MIN_RANGE1 (50000000) +#define SCIF_DFLL0CONF_MAX_RANGE2 (55000000) +#define SCIF_DFLL0CONF_MIN_RANGE2 (25000000) +#define SCIF_DFLL0CONF_MAX_RANGE3 (30000000) +#define SCIF_DFLL0CONF_MIN_RANGE3 (20000000) + +/* DFLL Value Register */ + +#define SCIF_DFLL0VAL_FINE_SHIFT (0) /* Bits 0-7: Fine Value */ +#define SCIF_DFLL0VAL_FINE_MASK (0xff << SCIF_DFLL0VAL_FINE_SHIFT) +#define SCIF_DFLL0VAL_COARSE_SHIFT (16) /* Bits 16-20: Coarse value */ +#define SCIF_DFLL0VAL_COARSE_MASK (31 << SCIF_DFLL0VAL_COARSE_SHIFT) + +/* DFLL0 Multiplier Register */ + +#define SCIF_DFLL0MUL_MASK 0xffff + +/* DFLL0 Step Register */ + +#define SCIF_DFLL0STEP_FSTEP_SHIFT (0) /* Bits 0-7: Fine Maximum Step */ +#define SCIF_DFLL0STEP_FSTEP_MASK (0xff << SCIF_DFLL0STEP_FSTEP_SHIFT) +# define SCIF_DFLL0STEP_FSTEP(n) ((n) << SCIF_DFLL0STEP_FSTEP_SHIFT) +#define SCIF_DFLL0STEP_CSTEP_SHIFT (16) /* Bits 16-20: Coarse Maximum Step */ +#define SCIF_DFLL0STEP_CSTEP_MASK (31 << SCIF_DFLL0STEP_CSTEP_SHIFT) +# define SCIF_DFLL0STEP_CSTEP(n) ((n) << SCIF_DFLL0STEP_CSTEP_SHIFT) + +/* DFLL0 Spread Spectrum Generator Control Register */ + +#define SCIF_DFLL0SSG_EN (1 << 0) /* Bit 0: Enable */ +#define SCIF_DFLL0SSG_PRBS (1 << 1) /* Bit 1: Pseudo Random Bit Sequence */ +#define SCIF_DFLL0SSG_AMPLITUDE_SHIFT (8) /* Bits 8-12: SSG Amplitude */ +#define SCIF_DFLL0SSG_AMPLITUDE_MASK (31 << SCIF_DFLL0SSG_AMPLITUDE_SHIFT) +#define SCIF_DFLL0SSG_STEPSIZE_SHIFT (16) /* Bits 16-20: SSG Step Size */ +#define SCIF_DFLL0SSG_STEPSIZE_MASK (31 << SCIF_DFLL0SSG_STEPSIZE_SHIFT) + +/* DFLL0 Ratio Register */ + +#define SCIF_DFLL0RATIO_MASK 0xffff + +/* DFLL0 Synchronization Register */ + +#define SCIF_DFLL0SYNC_SYNC (1 << 0) /* Bit 0: Synchronization */ + +/* System RC Oscillator Calibration Register */ + +#define SCIF_RCCR_CALIB_SHIFT (0) /* Bits 0-9: Calibration Value */ +#define SCIF_RCCR_CALIB_MASK (0x3ff << SCIF_RCCR_CALIB_SHIFT) +#define SCIF_RCCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */ + +/* 4/8/12MHz RC Oscillator Configuration Register */ + +#define SCIF_RCFASTCFG_EN (1 << 0) /* Bit 0: Oscillator Enable */ +#define SCIF_RCFASTCFG_TUNEEN (1 << 1) /* Bit 1: Tuner Enable */ +#define SCIF_RCFASTCFG_JITMODE (1 << 2) /* Bit 2: Jitter Mode */ +#define SCIF_RCFASTCFG_NBPERIODS_SHIFT (4) /* Bits 4-6: Number of 32kHz Periods */ +#define SCIF_RCFASTCFG_NBPERIODS_MASK (7 << SCIF_RCFASTCFG_NBPERIODS_SHIFT) +#define SCIF_RCFASTCFG_FCD (1 << 7) /* Bit 7: RCFAST Fuse Calibration Done */ +#define SCIF_RCFASTCFG_FRANGE_SHIFT (8) /* Bits 8-9: Frequency Range */ +#define SCIF_RCFASTCFG_FRANGE_MASK (3 << SCIF_RCFASTCFG_FRANGE_SHIFT) +# define SCIF_RCFASTCFG_FRANGE_4MHZ (0 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 4MHz range selected */ +# define SCIF_RCFASTCFG_FRANGE_8MHZ (1 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 8MHz range selected */ +# define SCIF_RCFASTCFG_FRANGE_12MHZ (2 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 12MHz range selected */ +#define SCIF_RCFASTCFG_LOCKMARGIN_SHIFT (12) /* Bits 12-15: Accepted Count Error for Lock */ +#define SCIF_RCFASTCFG_LOCKMARGIN_MASK (15 << SCIF_RCFASTCFG_LOCKMARGIN_SHIFT) +#define SCIF_RCFASTCFG_CALIB_SHIFT (16) /* Bits 16-22: Oscillator Calibration Value */ +#define SCIF_RCFASTCFG_CALIB_MASK (0x7f << SCIF_RCFASTCFG_CALIB_SHIFT) + +/* 4/8/12MHz RC Oscillator Status Register */ + +#define SCIF_RCFASTSR_CURTRIM_SHIFT (0) /* Bits 0-6: Current Trim Value */ +#define SCIF_RCFASTSR_CURTRIM_MASK (0x7f << SCIF_RCFASTSR_CURTRIM_SHIFT) +#define SCIF_RCFASTSR_CNTERR_SHIFT (16) /* Bits 16-20: Current Count Error */ +#define SCIF_RCFASTSR_CNTERR_MASK (31 << SCIF_RCFASTSR_CNTERR_SHIFT) +#define SCIF_RCFASTSR_SIGN (1 << 21) /* Bit 21: Sign of Current Count Error */ +#define SCIF_RCFASTSR_LOCK (1 << 24) /* Bit 24: Lock */ +#define SCIF_RCFASTSR_LOCKLOST (1 << 25) /* Bit 25: Lock Lost */ +#define SCIF_RCFASTSR_UPDATED (1 << 31) /* Bit 31: Current Trim Value Updated */ + +/* 80MHz RC Oscillator Register */ + +#define SCIF_RC80MCR_EN (1 << 0) /* Bit 0: Enable */ +#define SCIF_RC80MCR_FCD (1 << 7) /* Bit 7: Flash Calibration Done */ +#define SCIF_RC80MCR_CALIB_SHIFT (16) /* Bits 16-17: Calibration Value */ +#define SCIF_RC80MCR_CALIB_MASK (3 << SCIF_RC80MCR_CALIB_SHIFT) + +/* High Resolution Prescaler Control Register */ + +#define SCIF_HRPCR_HRPEN (1 << 0) /* Bit 0: High Resolution Prescaler Enable */ +#define SCIF_HRPCR_CKSEL_SHIFT (1) /* Bits 1-3: Clock input selection */ +#define SCIF_HRPCR_CKSEL_MASK (7 << SCIF_HRPCR_CKSEL_SHIFT) +#define SCIF_HRPCR_HRCOUNT_SHIFT (8) /* Bits 8-31: High Resolution Counter */ +#define SCIF_HRPCR_HRCOUNT_MASK (0xffffff << SCIF_HRPCR_HRCOUNT_SHIFT) + +/* Fractional Prescaler Control Register */ + +#define SCIF_FPCR_FPEN (1 << 0) /* Bit 0: High Resolution Prescaler Enable */ +#define SCIF_FPCR_CKSEL_SHIFT (1) /* Bits 1-3: Clock input selection */ +#define SCIF_FPCR_CKSEL_MASK (7 << SCIF_FPCR_CKSEL_SHIFT) + +/* Fractional Prescaler Multiplier Register */ + +#define SCIF_FPMUL_MASK 0xffff + +/* Fractional Prescaler DIVIDER Register */ + +#define SCIF_FPDIV_MASK 0xffff + +/* Generic Clock Control0-11 */ + +#define SCIF_GCCTRL_CEN (1 << 0) /* Bit 0: Clock Enable */ +#define SCIF_GCCTRL_DIVEN (1 << 1) /* Bit 1: Divide Enable */ +#define SCIF_GCCTRL_OSCSEL_SHIFT (8) /* Bits 8-12: Oscillator Select */ +#define SCIF_GCCTRL_OSCSEL_MASK (31 << SCIF_GCCTRL_OSCSEL_SHIFT) +# define SCIF_GCCTRL_OSCSEL_RCSYS (0 << SCIF_GCCTRL_OSCSEL_SHIFT) /* System RC oscillator */ +# define SCIF_GCCTRL_OSCSEL_OSC32K (1 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from OSC32K */ +# define SCIF_GCCTRL_OSCSEL_DFLL0 (2 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from DFLL0 */ +# define SCIF_GCCTRL_OSCSEL_OSC0 (3 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from Oscillator0 */ +# define SCIF_GCCTRL_OSCSEL_RC80M (4 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 80MHz RCOSC */ +# define SCIF_GCCTRL_OSCSEL_RCFAST (5 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 4,8,12MHz RCFAST */ +# define SCIF_GCCTRL_OSCSEL_RC1M (6 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 1MHz RC1M */ +# define SCIF_GCCTRL_OSCSEL_CPUCLK (7 << SCIF_GCCTRL_OSCSEL_SHIFT) /* The CPU clock */ +# define SCIF_GCCTRL_OSCSEL_HSBCLK (8 << SCIF_GCCTRL_OSCSEL_SHIFT) /* High Speed Bus clock */ +# define SCIF_GCCTRL_OSCSEL_PBACLK (9 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus A clock */ +# define SCIF_GCCTRL_OSCSEL_PBBCLK (10 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus B clock */ +# define SCIF_GCCTRL_OSCSEL_PBCCLK (11 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus C clock */ +# define SCIF_GCCTRL_OSCSEL_PBDCLK (12 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus D clock */ +# define SCIF_GCCTRL_OSCSEL_RC32K (13 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 32kHz RCOSC */ +# define SCIF_GCCTRL_OSCSEL_1K (15 << SCIF_GCCTRL_OSCSEL_SHIFT) /* 1 kHz output from OSC32K */ +# define SCIF_GCCTRL_OSCSEL_PLL0 (16 << SCIF_GCCTRL_OSCSEL_SHIFT) /* PLL0 */ +# define SCIF_GCCTRL_OSCSEL_HRPCLK (17 << SCIF_GCCTRL_OSCSEL_SHIFT) /* High resolution prescaler */ +# define SCIF_GCCTRL_OSCSEL_FPCLK (18 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Fractional prescaler */ +# define SCIF_GCCTRL_OSCSEL_GCLKIN0 (19 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN0 */ +# define SCIF_GCCTRL_OSCSEL_GCLKIN1 (20 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN1 */ +# define SCIF_GCCTRL_OSCSEL_GCLK11 (21 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLK11 */ +#define SCIF_GCCTRL_DIV_SHIFT (16) /* Bits 16-31: Division Factor */ +#define SCIF_GCCTRL_DIV_MASK (0xffff << SCIF_GCCTRL_DIV_SHIFT) +# define SCIF_GCCTRL_DIV(n) ((n) << SCIF_GCCTRL_DIV_SHIFT) + +/* 4/8/12MHz RC Oscillator Version Register */ +/* Generic Clock Prescaler Version Register */ +/* PLL Version Register */ +/* Oscillator0 Version Register */ +/* DFLL Version Register */ +/* System RC Oscillator Version Register */ +/* 80MHz RC Oscillator Version Register */ +/* Generic Clock Version Register */ +/* SCIF Version Register */ + +#define SCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ +#define SCIF_VERSION_MASK (0xfff << SCIF_VERSION_VERSION_SHIFT) +#define SCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ +#define SCIF_VARIANT_MASK (15 << SCIF_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_SCIF_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_usart.h b/nuttx/arch/arm/src/sam34/chip/sam4l_usart.h new file mode 100644 index 0000000000..feaf4b48c5 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_usart.h @@ -0,0 +1,447 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam4l_uart.h + * Universal Synchronous Asynchronous Receiver Transmitter (USART) definitions for the SAM4L + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_UART_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_UART_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* USART register offsets ***********************************************************************/ + +#define SAM_UART_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register */ +#define SAM_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register */ +#define SAM_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register */ +#define SAM_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register */ +#define SAM_UART_SR_OFFSET 0x0014 /* Channel Status Register */ +#define SAM_UART_RHR_OFFSET 0x0018 /* Receive Holding Register */ +#define SAM_UART_THR_OFFSET 0x001c /* Transmit Holding Register */ +#define SAM_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register */ +#define SAM_UART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register */ +#define SAM_UART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register */ + /* 0x002c-0x003c: Reserved */ +#define SAM_UART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register */ +#define SAM_UART_NER_OFFSET 0x0044 /* Number of Errors Register */ + /* 0x0048: Reserved */ +#define SAM_UART_IFR_OFFSET 0x004c /* IrDA Filter Register */ +#define SAM_UART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register */ +#define SAM_UART_LINMR_OFFSET 0x0054 /* LIN Mode Register */ +#define SAM_UART_LINIR_OFFSET 0x0058 /* LIN Identifier Register */ +#define SAM_UART_LINBR_OFFSET 0x005c /* LIN Baud Rate Register */ + /* 0x0060-0x00e0: Reserved */ +#define SAM_UART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM_UART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + /* 0x005c-0xf008: Reserved */ +#define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register */ + /* 0x0100-0x0124: PDC Area */ + +/* USART register adresses **********************************************************************/ + +#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET) +#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET) +#define SAM_USART_IER(n) (SAM_USARTN_BASE(n)+SAM_UART_IER_OFFSET) +#define SAM_USART_IDR(n) (SAM_USARTN_BASE(n)+SAM_UART_IDR_OFFSET) +#define SAM_USART_IMR(n) (SAM_USARTN_BASE(n)+SAM_UART_IMR_OFFSET) +#define SAM_USART_SR(n) (SAM_USARTN_BASE(n)+SAM_UART_SR_OFFSET) +#define SAM_USART_RHR(n) (SAM_USARTN_BASE(n)+SAM_UART_RHR_OFFSET) +#define SAM_USART_THR(n) (SAM_USARTN_BASE(n)+SAM_UART_THR_OFFSET) +#define SAM_USART_BRGR(n) (SAM_USARTN_BASE(n)+SAM_UART_BRGR_OFFSET) +#define SAM_USART_RTOR(n) (SAM_USARTN_BASE(n)+SAM_UART_RTOR_OFFSET) +#define SAM_USART_TTGR(n) (SAM_USARTN_BASE(n)+SAM_UART_TTGR_OFFSET) +#define SAM_USART_FIDI(n) (SAM_USARTN_BASE(n)+SAM_UART_FIDI_OFFSET) +#define SAM_USART_NER(n) (SAM_USARTN_BASE(n)+SAM_UART_NER_OFFSET) +#define SAM_USART_IFR(n) (SAM_USARTN_BASE(n)+SAM_UART_IFR_OFFSET) +#define SAM_USART_MAN(n) (SAM_USARTN_BASE(n)+SAM_UART_MAN_OFFSET) +#define SAM_USART_LINMR(n) (SAM_USARTN_BASE(n)+SAM_UART_LINMR_OFFSET) +#define SAM_USART_LINIR(n) (SAM_USARTN_BASE(n)+SAM_UART_LINIR_OFFSET) +#define SAM_USART_LINBR(n) (SAM_USARTN_BASE(n)+UART_LINBR_OFFSET) +#define SAM_USART_WPMR(n) (SAM_USARTN_BASE(n)+SAM_UART_WPMR_OFFSET) +#define SAM_USART_WPSR(n) (SAM_USARTN_BASE(n)+SAM_UART_WPSR_OFFSET) +#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_UART_VERSION_OFFSET) + +#define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART0_MR (SAM_USART0_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART0_SR (SAM_USART0_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART0_RHR (SAM_USART0_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART0_THR (SAM_USART0_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART0_BRGR (SAM_USART0_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART0_RTOR (SAM_USART0_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART0_TTGR (SAM_USART0_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART0_FIDI (SAM_USART0_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART0_NER (SAM_USART0_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART0_IFR (SAM_USART0_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART0_MAN (SAM_USART0_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART0_LINMR (SAM_USART0_BASE+SAM_UART_LINMR_OFFSET) +#define SAM_USART0_LINIR (SAM_USART0_BASE+SAM_UART_LINIR_OFFSET) +#define SAM_USART0_LINBR (SAM_USART0_BASE+UART_LINBR_OFFSET) +#define SAM_USART0_WPMR (SAM_USART0_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART0_WPSR (SAM_USART0_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART1_MR (SAM_USART1_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART1_SR (SAM_USART1_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART1_RHR (SAM_USART1_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART1_THR (SAM_USART1_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART1_BRGR (SAM_USART1_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART1_RTOR (SAM_USART1_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART1_TTGR (SAM_USART1_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART1_FIDI (SAM_USART1_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART1_NER (SAM_USART1_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART1_IFR (SAM_USART1_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART1_MAN (SAM_USART1_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART1_LINMR (SAM_USART1_BASE+SAM_UART_LINMR_OFFSET) +#define SAM_USART1_LINIR (SAM_USART1_BASE+SAM_UART_LINIR_OFFSET) +#define SAM_USART1_LINBR (SAM_USART1_BASE+UART_LINBR_OFFSET) +#define SAM_USART1_WPMR (SAM_USART1_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART1_WPSR (SAM_USART1_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART2_MR (SAM_USART2_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART2_SR (SAM_USART2_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART2_RHR (SAM_USART2_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART2_THR (SAM_USART2_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART2_BRGR (SAM_USART2_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART2_RTOR (SAM_USART2_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART2_TTGR (SAM_USART2_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART2_FIDI (SAM_USART2_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART2_NER (SAM_USART2_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART2_IFR (SAM_USART2_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART2_MAN (SAM_USART2_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART2_LINMR (SAM_USART2_BASE+SAM_UART_LINMR_OFFSET) +#define SAM_USART2_LINIR (SAM_USART2_BASE+SAM_UART_LINIR_OFFSET) +#define SAM_USART2_LINBR (SAM_USART2_BASE+UART_LINBR_OFFSET) +#define SAM_USART2_WPMR (SAM_USART2_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART2_WPSR (SAM_USART2_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART3_MR (SAM_USART3_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART3_SR (SAM_USART3_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART3_RHR (SAM_USART3_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART3_THR (SAM_USART3_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART3_BRGR (SAM_USART3_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART3_RTOR (SAM_USART3_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART3_TTGR (SAM_USART3_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART3_FIDI (SAM_USART3_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART3_NER (SAM_USART3_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART3_IFR (SAM_USART3_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART3_MAN (SAM_USART3_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART3_LINMR (SAM_USART3_BASE+SAM_UART_LINMR_OFFSET) +#define SAM_USART3_LINIR (SAM_USART3_BASE+SAM_UART_LINIR_OFFSET) +#define SAM_USART3_LINBR (SAM_USART3_BASE+UART_LINBR_OFFSET) +#define SAM_USART3_WPMR (SAM_USART3_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_UART_VERSION_OFFSET) + +/* USART register bit definitions ***************************************************************/ + +/* USART Control Register */ + +#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver */ +#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter */ +#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable */ +#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable */ +#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable */ +#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable */ +#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits */ +#define UART_CR_STTBRK (1 << 9) /* Bit 9: Start Break */ +#define UART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break */ +#define UART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out */ +#define UART_CR_SENDA (1 << 12) /* Bit 12: Send Address */ +#define UART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations */ +#define UART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge */ +#define UART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out */ +#define UART_CR_DTREN (1 << 16) /* Bit 16: Data Terminal Ready Enable */ +#define UART_CR_DTRDIS (1 << 17) /* Bit 17: Data Terminal Ready Disable */ +#define UART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable */ +#define UART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select */ +#define UART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable */ +#define UART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select */ +#define UART_CR_LINABT (1 << 20) /* Bit 20: Abort LIN Transmission */ +#define UART_CR_LINWKUP (1 << 21) /* Bit 21: Send LIN Wakeup Signal */ + +/* USART Mode Register */ + +#define UART_MR_MODE_SHIFT (0) /* Bits 0-3: */ +#define UART_MR_MODE_MASK (15 << UART_MR_MODE_SHIFT) +# define UART_MR_MODE_NORMAL (0 << UART_MR_MODE_SHIFT) /* Normal */ +# define UART_MR_MODE_RS485 (1 << UART_MR_MODE_SHIFT) /* RS485 */ +# define UART_MR_MODE_HWHS (2 << UART_MR_MODE_SHIFT) /* Hardware Handshaking */ +# define UART_MR_MODE_ISO7816_0 (4 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ +# define UART_MR_MODE_ISO7816_1 (6 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ +# define UART_MR_MODE_IRDA (8 << UART_MR_MODE_SHIFT) /* IrDA */ +# define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master */ +# define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave */ +#define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection */ +#define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT) +# define UART_MR_USCLKS_USART (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART */ +# define UART_MR_USCLKS_USARTDIV (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART/DIV(1) */ +# define UART_MR_USCLKS_CLK (0 << UART_MR_USCLKS_SHIFT) /* CLK */ +#define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length */ +#define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT) +# define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */ +# define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits */ +# define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */ +# define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */ +#define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select */ +#define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase */ +#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type */ +#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) +# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity */ +# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity */ +# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 */ +# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 */ +# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity */ +# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode */ +#define UART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits */ +#define UART_MR_NBSTOP_MASK (3 << UART_MR_NBSTOP_SHIFT) +# define UART_MR_NBSTOP_1 (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ +# define UART_MR_NBSTOP_1p5 (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ +# define UART_MR_NBSTOP_2 (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ +#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode */ +#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) +# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ +# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ +# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ +# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ +#define UART_MR_MSBF (1 << 16) /* Bit 16: Most Significant Bit first */ +#define UART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity */ +#define UART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length */ +#define UART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select */ +#define UART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode */ +#define UART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge */ +#define UART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK */ +#define UART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define UART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data */ +#define UART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 */ +#define UART_MR_MAXITER_MASK (7 << UART_MR_MAXITER_SHIFT) +#define UART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter */ +#define UART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable */ +#define UART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode */ +#define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector */ + +/* USART Interrupt Enable Register, USART Interrupt Disable Register, USART Interrupt Mask + * Register, and USART Status Register common bit field definitions. + * + * - Bits that provide interrupts with UART_INT_ + * - Bits unique to the USART status register begin with UART_SR_ + */ + +#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt */ +#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt */ +#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */ +#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt */ +#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt */ +#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt */ +#define UART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt */ +#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt */ +#define UART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt */ +#define UART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt */ +#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt */ +#define UART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt */ +#define UART_INT_LINBK (1 << 13) /* Bit 13: LIN Break */ +#define UART_INT_LINID (1 << 14) /* Bit 14: LIN Identifier */ +#define UART_INT_LINTC (1 << 15) /* Bit 15: LIN Transfer Completed */ +#define UART_INT_RIIC (1 << 16) /* Bit 16: Ring Indicator Input Change Flag */ +#define UART_INT_DSRIC (1 << 17) /* Bit 17: DSR Input Change Flag */ +#define UART_INT_DCDIC (1 << 18) /* Bit 18: DCD Input Change Flag */ +#define UART_INT_CTSIC (1 << 19) /* Bit 19: CTS Input Change Interrupt */ +#define UART_SR_RI (1 << 20) /* Bit 20: Image of RI Input (Status only) */ +#define UART_SR_DSR (1 << 21) /* Bit 21: Image of DSR Input (Status only) */ +#define UART_SR_DCD (1 << 22) /* Bit 22: Image of DCD Input (Status only) */ +#define UART_SR_CTS (1 << 23) /* Bit 23: Image of CTS Input (Status only) */ +#define UART_SR_LINBLS (1 << 23) /* Bit 23: ILIN Bus Line Status (Status only) */ +#define UART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt */ +#define UART_INT_LINBE (1 << 25) /* Bit 25: LIN Bit Error */ +#define UART_INT_LINISFE (1 << 26) /* Bit 26: LIN Inconsistent Sync Field Error */ +#define UART_INT_LINIPE (1 << 27) /* Bit 27: LIN Identifier Parity Error */ +#define UART_INT_LINCE (1 << 28) /* Bit 28: LIN Checksum Error */ +#define UART_INT_LINSNRE (1 << 29) /* Bit 29: LIN Slave Not Responding Error */ +#define UART_INT_LINSTE (1 << 30) /* Bit 30: LIN Sync Tolerance Error */ +#define UART_INT_LINHTE (1 << 31) /* Bit 31: LIN Header Time-out Error */ + +/* USART Receiver Holding Register */ + +#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character */ +#define UART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT) +#define UART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync */ + +/* USART Transmit Holding Register */ + +#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted */ +#define UART_THR_TXCHR_MASK (0x1ff << UART_THR_TXCHR_SHIFT) +#define UART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran */ + +/* USART Baud Rate Generator Register */ + +#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor */ +#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT) +#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part */ +#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT) + +/* USART Receiver Time-out Register */ + +#define UART_RTOR_TO_SHIFT (0) /* Bits 0-16: Time-out Value */ +#define UART_RTOR_TO_MASK (0x1ffff << UART_RTOR_TO_SHIFT) + +/* USART Transmitter Timeguard Register */ + +#define UART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value */ +#define UART_TTGR_TG_MASK (0xff << UART_TTGR_TG_SHIFT) + +/* USART FI DI RATIO Register */ + +#define UART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value */ +#define UART_FIDI_RATIO_MASK (0x7ff << UART_FIDI_RATIO_SHIFT) + +/* USART Number of Errors Register */ + +#define UART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors */ +#define UART_NER_NBERRORS_MASK (0xff << UART_NER_NBERRORS_SHIFT) + +/* USART IrDA FILTER Register */ + +#define UART_IFR_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter */ +#define UART_IFR_IRDAFILTER_MASK (0xff << UART_IFR_IRDAFILTER_SHIFT) + +/* USART Manchester Configuration Register */ + +#define UART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length */ +#define UART_MAN_TXPL_MASK (15 << UART_MAN_TXPL_SHIFT) +#define UART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern */ +#define UART_MAN_TXPP_MASK (3 << UART_MAN_TXPP_SHIFT) +# define UART_MAN_TXPP_ALLONE (0 << UART_MAN_TXPP_SHIFT) /* ALL_ONE */ +# define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */ +# define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */ +# define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */ +#define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity */ +#define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length */ +#define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT) +#define UART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected */ +#define UART_MAN_RXPP_MASK (3 << UART_MAN_RXPP_SHIFT) +# define UART_MAN_RXPP_ALLONE (0 << UART_MAN_RXPP_SHIFT) /* ALL_ONE */ +# define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */ +# define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */ +# define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */ +#define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity */ +#define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation */ + +/* USART LIN Mode Register */ + +#define UART_LINMR_NACT_SHIFT (0) /* Bits 0-1: LIN Node Action */ +#define UART_LINMR_NACT_MASK (3 << UART_LINMR_NACT_SHIFT) +# define UART_LINMR_NACT_PUBLISH (0 << UART_LINMR_NACT_SHIFT) /* USART transmits response */ +# define UART_LINMR_NACT_SUBSCRIBE (1 << UART_LINMR_NACT_SHIFT) /* USART receives response */ +# define UART_LINMR_NACT_IGNORE (2 << UART_LINMR_NACT_SHIFT) /* USART does neither */ +#define UART_LINMR_PARDIS (1 << 2) /* Bit 0: Parity Disable */ +#define UART_LINMR_CHKDIS (1 << 3) /* Bit 0: Checksum Disable */ +#define UART_LINMR_CHKTYP (1 << 4) /* Bit 0: Checksum Type */ +#define UART_LINMR_DLM (1 << 5) /* Bit 0: Data Length Mode */ +#define UART_LINMR_FSDIS (1 << 6) /* Bit 0: Frame Slot Mode Disable */ +#define UART_LINMR_WKUPTYP (1 << 7) /* Bit 0: Wakeup Signal Type */ +#define UART_LINMR_DLC_SHIFT (8) /* Bits 8-15: Data Length Control */ +#define UART_LINMR_DLC_MASK (0xff << UART_LINMR_DLC_SHIFT) +#define UART_LINMR_PDCM (1 << 16) /* Bit 16: Peripheral DMA Controller Mode */ +#define UART_LINMR_SYNCDIS (1 << 17) /* Bit 17: Synchronization Disable */ + +/* USART LIN Identifier Register */ + +#define UART_LINIR_MASK 0xff /* Bits 0-7: Identifer character */ + +/* USART LIN Baud Rate Register */ + +#define UART_LINBR_LINCD_SHIFT (0) /* Bit 0-15:LIN Clock Divider after Synchronization */ +#define UART_LINBR_LINCD_MASK (0xffff << UART_LINBR_LINCD_SHIFT) +#define UART_LINBR_LINFP_SHIFT (16) /* Bits 16-18: LIN Fractional Part after Synchronization */ +#define UART_LINBR_LINFP_MASK (7 << UART_LINBR_LINFP_SHIFT) + +/* USART Write Protect Mode Register */ + +#define UART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define UART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define UART_WPMR_WPKEY_MASK (0x00ffffff << UART_WPMR_WPKEY_SHIFT) + +/* USART Write Protect Status Register */ + +#define UART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define UART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define UART_WPSR_WPVSRC_MASK (0xffff << UART_WPSR_WPVSRC_SHIFT) + +/* USART Version Register */ + +#define UART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number */ +#define UART_VERSION_VERSION_MASK (0xfff << UART_VERSION_VERSION_SHIFT) +#define UART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved */ +#define UART_VERSION_MFN_MASK (7 << UART_VERSION_MFN_SHIFT) + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_UART_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h b/nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h new file mode 100644 index 0000000000..6383706141 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h @@ -0,0 +1,137 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_wdt.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* WDT register offsets ****************************************************************/ + +#define SAM_WDT_CTRL_OFFSET 0x0000 /* Control Register */ +#define SAM_WDT_CLR_OFFSET 0x0004 /* Clear Register */ +#define SAM_WDT_SR_OFFSET 0x0008 /* Status Register */ +#define SAM_WDT_IER_OFFSET 0x000c /* Interrupt Enable Register */ +#define SAM_WDT_IDR_OFFSET 0x0010 /* Interrupt Disable Register */ +#define SAM_WDT_IMR_OFFSET 0x0014 /* Interrupt Mask Register */ +#define SAM_WDT_ISR_OFFSET 0x0018 /* Interrupt Status Register */ +#define SAM_WDT_ICR_OFFSET 0x001c /* Interrupt Clear Register */ +#define SAM_WDT_VERSION_OFFSET 0x03fc /* Version Register */ + +/* WDT register adresses ***************************************************************/ + +#define SAM_WDT_CTRL (SAM_WDT_BASE+SAM_WDT_CTRL_OFFSET) +#define SAM_WDT_CLR (SAM_WDT_BASE+SAM_WDT_CLR_OFFSET) +#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) +#define SAM_WDT_IER (SAM_WDT_BASE+SAM_WDT_IER_OFFSET) +#define SAM_WDT_IDR (SAM_WDT_BASE+SAM_WDT_IDR_OFFSET) +#define SAM_WDT_IMR (SAM_WDT_BASE+SAM_WDT_IMR_OFFSET) +#define SAM_WDT_ISR (SAM_WDT_BASE+SAM_WDT_ISR_OFFSET) +#define SAM_WDT_ICR (SAM_WDT_BASE+SAM_WDT_ICR_OFFSET) +#define SAM_WDT_VERSION (SAM_WDT_BASE+SAM_WDT_VERSION_OFFSET) + +/* WDT register bit definitions ********************************************************/ + +/* Control Register */ + +#define WDT_CTRL_EN (1 << 0) /* Bit 0: WDT Enable */ +#define WDT_CTRL_DAR (1 << 1) /* Bit 1: WDT Disable After Reset */ +#define WDT_CTRL_MODE (1 << 2) /* Bit 2: WDT Mode */ +#define WDT_CTRL_SFV (1 << 3) /* Bit 3: WDT Control Register Store Final Value */ +#define WDT_CTRL_IM (1 << 4) /* Bit 4: Interrupt Mode */ +#define WDT_CTRL_FCD (1 << 7) /* Bit 7: Flash Calibration Done */ +#define WDT_CTRL_PSEL_SHIFT (8) /* Bits 8-12: Time Out Prescale Select */ +#define WDT_CTRL_PSEL_MASK (31 << WDT_CTRL_PSEL_SHIFT) +#define WDT_CTRL_CEN (1 << 16) /* Bit 16: Clock Enable */ +#define WDT_CTRL_CSSEL (1 << 17) /* Bit 17: Clock Source Select */ +#define WDT_CTRL_TBAN_SHIFT (18) /* Bits 18-22: Time Ban Prescale Select */ +#define WDT_CTRL_TBAN_MASK (31 << WDT_CTRL_TBAN_SHIFT) +#define WDT_CTRL_KEY_SHIFT (24) /* Bits 24-31: Key */ +#define WDT_CTRL_KEY_MASK (0xff << WDT_CTRL_KEY_SHIFT) +# define WDT_CTRL_KEY_FIRST (0x55 << WDT_CTRL_KEY_SHIFT) +# define WDT_CTRL_KEY_SECOND (0xaa << WDT_CTRL_KEY_SHIFT) + +/* Clear Register */ + +#define WDT_CLR_WDTCLR (1 << 0) /* Bit 0: Watchdog Clear */ +#define WDT_CLR_KEY_SHIFT (24) /* Bits 24-31: Key */ +#define WDT_CLR_KEY_MASK (0xff << WDT_CLR_KEY_SHIFT) +# define WDT_CLR_KEY_FIRST (0x55 << WDT_CLR_KEY_SHIFT) +# define WDT_CLR_KEY_SECOND (0xaa << WDT_CLR_KEY_SHIFT) + +/* Status Register */ + +#define WDT_SR_WINDOW (1 << 0) /* Bit 0: Within Window */ +#define WDT_SR_CLEARED (1 << 1) /* Bit 1: WDT Counter Cleared */ + +/* Interrupt Enable Register */ +/* Interrupt Disable Register */ +/* Interrupt Mask Register */ +/* Interrupt Status Register */ +/* Interrupt Clear Register */ + +#define WDT_WINT (1 << 2) /* Bit 2: WINT */ + +/* Version Register */ + +#define WDT_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ +#define WDT_VERSION_MASK (0xfff << WDT_VERSION_VERSION_SHIFT) +#define WDT_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ +#define WDT_VARIANT_MASK (15 << WDT_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam4s_memorymap.h new file mode 100644 index 0000000000..406b01dd90 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_memorymap.h @@ -0,0 +1,153 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam4s_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "chip.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Address regions */ + +#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */ +#define SAM_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */ +#define SAM_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */ +#define SAM_EXTRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External RAM */ +#define SAM_EXTDEV_BASE 0xa0000000 /* 0xa0000000-0xdfffffff: External device */ +#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */ + +/* Code memory region */ + +#define SAM_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x003fffff: Boot Memory */ +#define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */ +#define SAM_INTROM_BASE 0x00800000 /* 0x00180000-0x00bfffff: Internal ROM */ + /* 0x00c00000-0x1fffffff: Reserved */ +/* Internal SRAM memory region */ + +#define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */ +#define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */ + /* 0x24000000-0x3fffffff: Undefined */ +/* Peripherals address region */ + +#define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ +#define SAM_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */ +#define SAM_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ + /* 0x4000c000-0x4000ffff: Reserved */ +#define SAM_TC_BASE 0x40010000 /* 0x40010000-0x40017fff: Timer Counters */ +# define SAM_TC0_BASE 0x40080000 /* 0x40010000-0x4001003f: Timer Counter 0 */ +# define SAM_TC1_BASE 0x40080040 /* 0x40010040-0x4001007f: Timer Counter 1 */ +# define SAM_TC2_BASE 0x40080080 /* 0x40010080-0x400100bf: Timer Counter 2 */ + /* 0x400100c0-0x40013fff Reserved */ +# define SAM_TC3_BASE 0x40080000 /* 0x40014000-0x4001403f: Timer Counter 3 */ +# define SAM_TC4_BASE 0x40080040 /* 0x40014040-0x4001407f: Timer Counter 4 */ +# define SAM_TC5_BASE 0x40080080 /* 0x40014080-0x400140bf: Timer Counter 5 */ +#define SAM_TWI_BASE 0x40018000 /* 0x40018000-0x4001ffff: Two-Wire Interface */ +# define SAM_TWI0_BASE 0x40018000 /* 0x40018000-0x4001bfff: Two-Wire Interface 0 */ +# define SAM_TWI1_BASE 0x4001c000 /* 0x4001c000-0x4001ffff: Two-Wire Interface 1 */ +#define SAM_PWM_BASE 0x40020000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */ +#define SAM_USART_BASE 0x40024000 /* 0x40024000-0x4002bfff: USART */ +# define SAM_USART0_BASE 0x40024000 /* 0x40024000-0x40023fff: USART0 */ +# define SAM_USART1_BASE 0x40028000 /* 0x40028000-0x4002bfff: USART1 */ + /* 0x4002C000-0x4002ffff: Reserved */ + /* 0x40030000-0x40033fff: Reserved */ +#define SAM_UDP_BASE 0x40034000 /* 0x40034000-0x40037fff: USB 2.0 Device */ +#define SAM_ADC_BASE 0x40038000 /* 0x40038000-0x4003bfff: Analog To Digital Converter */ +#define SAM_DACCBASE 0x400cC000 /* 0x4003c000-0x4003ffff: Digital To Analog Converter */ +#define SAM_ACC_BASE 0x40040000 /* 0x40040000-0x40043fff: Analog Comparator */ +#define SAM_CRCCU_BASE 0x40044000 /* 0x40040000-0x40047fff: CRC Calculation Unit */ + /* 0x40048000-0x400dffff: Reserved */ +#define SAM_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System Controller */ + /* 0x400e2600-0x400fffff: Reserved */ + /* 0x40100000-0x4002ffff: Reserved */ +#define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32MB bit-band region */ + /* 0x44000000-0x5fffffff: Reserved */ +/* System Controller Register Blocks: 0x400e0000-0x4007ffff */ + +#define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ +#define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ +#define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ +#define SAM_UART0_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART 0 */ +#define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ +#define SAM_UART1_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: UART 1 */ +#define SAM_EEFC_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controllers*/ +# define SAM_EEFC0_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 0 */ +# define SAM_EEFC1_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Enhanced Embedded Flash Controller 1 */ +#define SAM_PIO_BASE 0x400e0e00 /* 0x400e0e00-0x400e13ff: Parallel I/O Controllers */ +# define SAM_PION_BASE(n) (0x400e0e00 + ((n) << 9)) +# define SAM_PIOA_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller A */ +# define SAM_PIOB_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller B */ +# define SAM_PIOC_BASE 0x400e1200 /* 0x400e1200-0x400e13ff: Parallel I/O Controller C */ +#define SAM_RSTC_BASE 0x400e1400 /* 0x400e1400-0x400e140f: Reset Controller */ +#define SAM_SUPC_BASE 0x400e1410 /* 0x400e1410-0x400e142f: Supply Controller */ +#define SAM_RTT_BASE 0x400e1430 /* 0x400e1430-0x400e144f: Real Time Timer */ +#define SAM_WDT_BASE 0x400e1450 /* 0x400e1250-0x400e145f: Watchdog Timer */ +#define SAM_RTC_BASE 0x400e1460 /* 0x400e1460-0x400e148f: Real Time Clock */ +#define SAM_GPBR_BASE 0x400e1490 /* 0x400e1490-0x400e15ff: GPBR */ + /* 0x400e1600-0x4007ffff: Reserved */ +/* External RAM memory region */ + +#define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ +# define SAM_EXTCSN_BASE(n) (0x60000000*((n)<<24)) +# define SAM_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */ +# define SAM_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */ +# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */ +# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */ + /* 0x64000000-0x9fffffff: Reserved */ +/* System memory region */ + +#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */ +#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h new file mode 100644 index 0000000000..cb6d7eb182 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h @@ -0,0 +1,314 @@ +/************************************************************************************ + * arch/arm/src/sam34/chip/sam4s_pinmap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "sam_gpio.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* GPIO pin definitions *************************************************************/ +/* Alternate Pin Functions. + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if we + * wanted the programmable clock output PCK0 on PA6, then the following definition + * should appear in the board.h header file for that board: + * + * #define GPIO_PCK0 GPIO_PCK0_1 + * + * The driver will then automatically configre PA6 as the PCK0 pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +/* 12-bit Analog-to-Digital Conververt (ADC) */ + +#define GPIO_ADC0_AD0 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_ADC0_AD1 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_ADC0_AD2 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_ADC0_AD3 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_ADC0_AD4 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0) +#define GPIO_ADC0_AD5 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) +#define GPIO_ADC0_AD6 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_ADC0_AD7 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) +#define GPIO_ADC0_AD8 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_ADC0_AD9 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_ADC0_AD10 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_ADC0_AD11 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_ADC0_AD12 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_ADC0_AD13 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_ADC0_AD14 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_ADC0_ADTRG (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) + +/* Digital-to-Analog Convert (DAC) */ + +#define GPIO_DAC0 (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_DAC1 (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_DAC_DATRG (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) + +/* High-Speed Multimedia Card Interface (HSMCI) */ + +#define GPIO_MCI_CK (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_MCI_DA (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_MCI_DAT0 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_MCI_DAT1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_MCI_DAT2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_MCI_DAT3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) + +/* Programmable Clock Output */ + +#define GPIO_PCK0_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_PCK0_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_PCK1_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_PCK1_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_PCK2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_PCK2_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_PCK2_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) + +/* Pulse Width Modulation (PWM) */ + +#define GPIO_PWM0_FI (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_PWM0_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_PWM0_H_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0) +#define GPIO_PWM0_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_PWM0_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_PWM0_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_PWM0_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_PWM0_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) +#define GPIO_PWM0_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_PWM0_L_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_PWM1_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_PWM1_H_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) +#define GPIO_PWM1_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_PWM1_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_PWM1_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_PWM1_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_PWM1_L_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) +#define GPIO_PWM1_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_PWM1_L_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_PWM2_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) +#define GPIO_PWM2_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_PWM2_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_PWM2_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) +#define GPIO_PWM2_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_PWM2_L_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_PWM2_L_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_PWM2_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_PWM2_L_4 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_PWM3_H_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) +#define GPIO_PWM3_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_PWM3_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_PWM3_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_PWM3_H_5 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_PWM3_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_PWM3_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_PWM3_L_3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) + +/* Static Memory Controller (SMC) */ + +#define GPIO_SMC_A0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_SMC_A1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_SMC_A2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_SMC_A3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_SMC_A4 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_SMC_A5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_SMC_A6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_SMC_A7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_SMC_A8 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_SMC_A9 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_SMC_A10 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_SMC_A11 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_SMC_A12 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_SMC_A13 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_SMC_A14 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_SMC_A15 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_SMC_A16 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_SMC_A17 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_SMC_A18 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_SMC_A19 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_SMC_A20 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_SMC_A21 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_SMC_A22 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_SMC_A23 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_SMC_D0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_SMC_D1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_SMC_D2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_SMC_D3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_SMC_D4 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_SMC_D5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) +#define GPIO_SMC_D6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) +#define GPIO_SMC_D7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_SMC_NANDALE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_SMC_NANDCLE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_SMC_NANDOE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_SMC_NANDWE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_SMC_NCS0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_SMC_NCS1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_SMC_NCS2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_SMC_NCS3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_SMC_NRD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) +#define GPIO_SMC_NWAIT (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_SMC_NWE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) + +/* Serial Peripheral Interface (SPI) */ + +#define GPIO_SPI0_MISO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_SPI0_MOSI (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_SPI0_NPCS0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_SPI0_NPCS1_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_SPI0_NPCS1_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_SPI0_NPCS1_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_SPI0_NPCS1_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_SPI0_NPCS2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_SPI0_NPCS2_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_SPI0_NPCS2_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_SPI0_NPCS3_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_SPI0_NPCS3_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN3) +#define GPIO_SPI0_NPCS3_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_SPI0_SPCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) + +/* Synchronous Serial Controller (SSC) */ + +#define GPIO_SSC_RD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_SSC_RF (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_SSC_RK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_SSC_TD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_SSC_TF (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_SSC_TK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) + +/* Timer/Counters (TC) */ + +#define GPIO_TC0_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_TC0_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_TC0_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_TC1_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_TC1_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_TC1_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_TC2_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_TC2_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_TC2_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_TC3_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_TC3_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_TC3_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_TC4_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_TC4_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_TC4_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_TC5_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_TC5_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_TC5_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) + +/* Two Wire Interface (TWI) */ + +#define GPIO_TWI0_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_TWI0_D (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN3) +#define GPIO_TWI1_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) +#define GPIO_TWI1_D (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) + +/* Universal Asynchronous Receiver Transceiver (UART) */ + +#define GPIO_UART0_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_UART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_UART1_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_UART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) + +/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ + +#define GPIO_USART0_CTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) +#define GPIO_USART0_RTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_USART0_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_USART0_SCK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) +#define GPIO_USART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) + +#define GPIO_USART1_CTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_USART1_DCD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_USART1_DSR (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_USART1_DTR (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_USART1_RI (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) + +#define GPIO_USART1_RTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_USART1_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h b/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h index c65d5dcbef..93111dddbb 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam4s_pio.h + * Parallel Input/Output (PIO) Controller definitions for the SAM4S * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -57,7 +58,7 @@ /* 0x000c: Reserved */ #define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */ #define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */ -#define SAM_PIO_OSR_OFFSET 0x0018 /* utput Status Register */ +#define SAM_PIO_OSR_OFFSET 0x0018 /* Output Status Register */ /* 0x001c: Reserved */ #define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */ #define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */ @@ -82,13 +83,13 @@ #define SAM_PIO_ABCDSR1_OFFSET 0x0070 /* Peripheral Select Register 1 */ #define SAM_PIO_ABCDSR2_OFFSET 0x0074 /* Peripheral Select Register 2 */ /* 0x0078-0x007c: Reserved */ -#define SAM_PIO_IFSCDR_OFFSET 0x0080 /* SInput Filter Slow Clock Disable Register */ +#define SAM_PIO_IFSCDR_OFFSET 0x0080 /* Input Filter Slow Clock Disable Register */ #define SAM_PIO_IFSCER_OFFSET 0x0084 /* Input Filter Slow Clock Enable Register */ #define SAM_PIO_IFSCSR_OFFSET 0x0088 /* Input Filter Slow Clock Status Register */ #define SAM_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */ -#define SAM_PIO_PPDDR_OFFSET 0x0090 /* Pad Pull-down Enable Register */ -#define SAM_PIO_PPDER_OFFSET 0x0094 /* Pad Pull-down Status Register */ -#define SAM_PIO_PPDSR_OFFSET 0x0098 /* Input Filter Slow Clock Disable Register */ +#define SAM_PIO_PPDDR_OFFSET 0x0090 /* Pad Pull Down Disable Register */ +#define SAM_PIO_PPDER_OFFSET 0x0094 /* PIO Pad Pull Down Enable Register */ +#define SAM_PIO_PPDSR_OFFSET 0x0098 /* PIO Pad Pull Down Status Register */ /* 0x009c: Reserved */ #define SAM_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */ #define SAM_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h b/nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h new file mode 100644 index 0000000000..b2587cd121 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h @@ -0,0 +1,92 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam42_vectors.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ +/* This file is included by sam_vectors.S. It provides the macro VECTOR that + * supplies ach SAM3U vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h. + * sam_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 35 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 35 + +#else + VECTOR(sam_supc, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */ + VECTOR(sam_rstc, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */ + VECTOR(sam_rtc, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */ + VECTOR(sam_rtt, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */ + VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */ + VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */ + VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */ + VECTOR(sam_eefc1, SAM_IRQ_EEFC1) /* Vector 16+7: Enhanced Embedded Flash Controller 1 */ + VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter 0 */ + VECTOR(sam_uart1, SAM_IRQ_UART1) /* Vector 16+9: Universal Asynchronous Receiver Transmitter 1 */ + VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+10: Static Memory Controller */ + VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+11: Parallel I/O Controller A */ + VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+12: Parallel I/O Controller B */ + VECTOR(sam_pioc, SAM_IRQ_PIOC) /* Vector 16+13: Parallel I/O Controller C */ + VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+14: USART 0 */ + VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+15: USART 1 */ + UNUSED(SAM_IRQ_RESERVED_16) /* Vector 16+16: Reserved */ + UNUSED(SAM_IRQ_RESERVED_17) /* Vector 16+17: Reserved */ + VECTOR(sam_hsmci, SAM_IRQ_HSMCI) /* Vector 16+18: High Speed Multimedia Card Interface */ + VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+19: Two-Wire Interface 0 */ + VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+20: Two-Wire Interface 1 */ + VECTOR(sam_spi, SAM_PID_SPI) /* Vector 16+21: Serial Peripheral Interface */ + VECTOR(sam_ssc, SAM_IRQ_SSC) /* Vector 16+22: Synchronous Serial Controller */ + VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+23: Timer Counter 0 */ + VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+24: Timer Counter 1 */ + VECTOR(sam_tc2, SAM_IRQ_TC2) /* Vector 16+25: Timer Counter 2 */ + VECTOR(sam_tc3, SAM_IRQ_TC3) /* Vector 16+26: Timer Counter 3 */ + VECTOR(sam_tc4, SAM_IRQ_TC4) /* Vector 16+27: Timer Counter 4 */ + VECTOR(sam_tc5, SAM_IRQ_TC5) /* Vector 16+28: Timer Counter 5 */ + VECTOR(sam_adc, SAM_IRQ_ADC) /* Vector 16+29: Analog To Digital Converter */ + VECTOR(sam_dacc, SAM_IRQ_DACC) /* Vector 16+30: Digital To Analog Converter */ + VECTOR(sam_pwm, SAM_IRQ_PWM) /* Vector 16+31: Pulse Width Modulation */ + VECTOR(sam_crccu, SAM_IRQ_CRCCU) /* Vector 16+32: CRC Calculation Unit */ + VECTOR(sam_acc, SAM_IRQ_ACC) /* Vector 16+33: Analog Comparator */ + VECTOR(sam_udp, SAM_IRQ_UDP) /* Vector 16+34: USB Device Port */ +#endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_chipid.h b/nuttx/arch/arm/src/sam34/chip/sam_chipid.h index c98130efec..fd5fc977a3 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_chipid.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_chipid.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_chipid.h + * CHIPID Register Definitions for the SAM3U, SAM4S, and SAM4L * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -100,10 +101,11 @@ #define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) # define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */ # define CHIPID_CIDR_SRAMSIZ_1KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 1K bytes */ +# define CHIPID_CIDR_SRAMSIZ_192KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 192K bytes (SAM4S) */ # define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */ # define CHIPID_CIDR_SRAMSIZ_6KB (3 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 6K bytes */ # define CHIPID_CIDR_SRAMSIZ_112KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 112K bytes */ -# define CHIPID_CIDR_SRAMSIZ_24KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 24K bytes */ +# define CHIPID_CIDR_SRAMSIZ_24KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 24K bytes (SAM4S, SAM4L) */ # define CHIPID_CIDR_SRAMSIZ_4KB (5 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 4K bytes */ # define CHIPID_CIDR_SRAMSIZ_80KB (6 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 80K bytes */ # define CHIPID_CIDR_SRAMSIZ_160KB (7 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 160K bytes */ @@ -142,27 +144,32 @@ # define CHIPID_CIDR_ARCH_SAM3XXE (0x85 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxE Series (144-pin version) */ # define CHIPID_CIDR_ARCH_SAM3XXG (0x86 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxG Series (208/217-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxA Series (48-pin version) */ +# define CHIPID_CIDR_ARCH_SAM4SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4SxA Series (48-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM4SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM34xB Series (64-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM4SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM4SxC Series (100-pin version) */ # define CHIPID_CIDR_ARCH_AT91X92 (0x92 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x92 Series */ # define CHIPID_CIDR_ARCH_SAM3NXA (0x93 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxA Series (48-pin version) */ # define CHIPID_CIDR_ARCH_SAM3NXB (0x94 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxB Series (64-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3NxC (0x95 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxC Series (100-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3NXC (0x99 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxB SAM3SDxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3NXC (0x95 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3DXB (0x99 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxB SAM3SDxB Series (64-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SDXC (0x9a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxC Series (100-pin version) */ # define CHIPID_CIDR_ARCH_SAM5A (0xa5 << CHIPID_CIDR_ARCH_SHIFT) /* SAM5A */ -# define CHIPID_CIDR_ARCH_SAM4L (0xb0 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4Lxx Series */ +# define CHIPID_CIDR_ARCH_SAM4LA (0xb0 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxA Series */ +# define CHIPID_CIDR_ARCH_SAM4LB (0xb1 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxB Series */ +# define CHIPID_CIDR_ARCH_SAM4LC (0xb2 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxC Series */ # define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ #define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ #define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT) -# define CHIPID_CIDR_NVPTYP ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ -# define CHIPID_CIDR_NVPTYP FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */ -# define CHIPID_CIDR_NVPTYP SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ -# define CHIPID_CIDR_NVPTYP EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ -# define CHIPID_CIDR_NVPTYP REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ +# define CHIPID_CIDR_NVPTYP_ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ +# define CHIPID_CIDR_NVPTYP_FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */ +# define CHIPID_CIDR_NVPTYP_SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ +# define CHIPID_CIDR_NVPTYP_EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ +# define CHIPID_CIDR_NVPTYP_REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ #define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ -/* Chip ID Extension Register */ +/* Chip ID Extension Register (32-bit value for SAM3U and SAM4S) */ #ifdef CONFIG_ARCH_CHIP_SAM4L # define CHIPID_EXID_AES (1 << 0) /* Bit 0: AES Option */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h b/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h index dfee208c31..887d561ca1 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h @@ -70,13 +70,17 @@ #define SAM_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */ #define SAM_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */ #define SAM_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */ -#define SAM_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */ +#endif + #define SAM_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */ /* 0x0058-0x00e0: Reserved */ #define SAM_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */ #define SAM_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ /* 0x00ec-0x00fc: Reserved */ - /* 0x0100-0x0124: Reserved */ + /* 0x0100-0x0124: Reserved for PCD registers */ #define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */ /* HSMCI register adresses **************************************************************/ @@ -99,7 +103,11 @@ #define SAM_HSMCI_IER (SAM_MCI_BASE+SAM_HSMCI_IER_OFFSET) #define SAM_HSMCI_IDR (SAM_MCI_BASE+SAM_HSMCI_IDR_OFFSET) #define SAM_HSMCI_IMR (SAM_MCI_BASE+SAM_HSMCI_IMR_OFFSET) -#define SAM_HSMCI_DMA (SAM_MCI_BASE+SAM_HSMCI_DMA_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_HSMCI_DMA (SAM_MCI_BASE+SAM_HSMCI_DMA_OFFSET) +#endif + #define SAM_HSMCI_CFG (SAM_MCI_BASE+SAM_HSMCI_CFG_OFFSET) #define SAM_HSMCI_WPMR (SAM_MCI_BASE+SAM_HSMCI_WPMR_OFFSET) #define SAM_HSMCI_WPSR (SAM_MCI_BASE+SAM_HSMCI_WPSR_OFFSET) @@ -126,8 +134,15 @@ #define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */ #define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */ #define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */ -#define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ -#define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define HSMCI_MR_PDCMODE (1 << 15) /* Bit 15: PDC-oriented Mode */ +#endif + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ +# define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT) +#endif /* HSMCI Data Timeout Register */ @@ -157,6 +172,8 @@ # define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT) # define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT) +/* HSMCI Argument Register (32-bit value) */ + /* HSMCI Command Register */ #define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */ @@ -200,7 +217,7 @@ # define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */ # define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */ #define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */ -#define HSMCI_CMDR_BOOTACK (1 << 17) /* Bit 27: Boot Operation Acknowledge */ +#define HSMCI_CMDR_BOOTACK (1 << 27) /* Bit 27: Boot Operation Acknowledge */ /* HSMCI Block Register */ @@ -224,6 +241,10 @@ # define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT) # define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) +/* HSMCI Response Registers (32-bit data) */ +/* HSMCI Receive Data Registers (32-bit data) */ +/* HSMCI Transmit Data Registers (32-bit data) */ + /* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable * Register, and HSMCI Interrupt Mask Register common bit-field definitions */ @@ -234,9 +255,21 @@ #define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */ #define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */ #define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define HSMCI_INT_ENDRX (1 << 6) /* Bit 6: End of RX Buffer */ +# define HSMCI_INT_ENDTX (1 << 7) /* Bit 7: End of TX Buffer */ +#endif + #define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */ #define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */ #define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define HSMCI_INT_RXBUFF (1 << 14) /* Bit 14: RXBUFF: RX Buffer Full */ +# define HSMCI_INT_TXBUFE (1 << 15) /* Bit 15: TXBUFE: TX Buffer Empty */ +#endif + #define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */ #define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */ #define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */ @@ -245,8 +278,12 @@ #define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */ #define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */ #define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */ -#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */ -#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */ +# define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */ +#endif + #define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */ #define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */ #define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */ @@ -256,11 +293,13 @@ /* HSMCI DMA Configuration Register */ -#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */ -#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT) -#define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */ -#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ -#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */ +# define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT) +# define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */ +# define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ +# define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */ +#endif /* HSMCI Configuration Register */ @@ -274,13 +313,18 @@ #define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */ #define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */ #define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT) +# define HSMCI_WPMR_WP_KEY (0x004d4349 << HSMCI_WPMR_WP_KEY_SHIFT) /* HSMCI Write Protect Status Register */ -#define HSMCI_WPSR_WP_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VS_MASK (15 << HSMCI_WPSR_WP_VS_SHIFT) -#define HSMCI_WPSR_WP_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ -#define HSMCI_WPSR_WP_VSRC_MASK (0xffff << HSMCI_WPSR_WP_VSRC_SHIFT) +#define HSMCI_WPSR_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +#define HSMCI_WPSR_VS_MASK (15 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_NONE (0 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_WRITE (1 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_RESET (2 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_BOTH (3 << HSMCI_WPSR_VS_SHIFT) +#define HSMCI_WPSR_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ +#define HSMCI_WPSR_VSRC_MASK (0xffff << HSMCI_WPSR_VSRC_SHIFT) /**************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h index a1fe603823..05e53ec8ee 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h @@ -47,6 +47,8 @@ # include "chip/sam3u_memorymap.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_memorymap.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_memorymap.h" #else # error Unrecognized SAM architecture #endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h index 6adb547bf7..74538cdaf1 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h @@ -45,6 +45,10 @@ #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_pinmap.h" #else # error Unrecognized SAM architecture #endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pmc.h b/nuttx/arch/arm/src/sam34/chip/sam_pmc.h deleted file mode 100644 index f6a98e3eec..0000000000 --- a/nuttx/arch/arm/src/sam34/chip/sam_pmc.h +++ /dev/null @@ -1,315 +0,0 @@ -/**************************************************************************************** - * arch/arm/src/sam34/chip/sam_pmc.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "chip/sam_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* PMC register offsets *****************************************************************/ - -#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ -#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ -#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ - /* 0x000c: Reserved */ -#define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ -#define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ -#define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ -#define SAM_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ -#define SAM_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ -#define SAM_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ -#define SAM_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ - /* 0x002c: Reserved */ -#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ - /* 0x0034-0x003C Reserved */ -#define SAM_PMC_PCK_OFFSET(n) (0x0040+((n)<<2)) -#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ -#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ -#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ - /* 0x004c-0x005c: Reserved */ -#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ -#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ -#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */ -#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ -#define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ -#define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ -#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ - /* 0x007c-0x00fc: Reserved */ -#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ -#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ - -/* PMC register adresses ****************************************************************/ - -#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET) -#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET) -#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET) -#define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET) -#define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET) -#define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET) -#define SAM_CKGR_UCKR (SAM_PMC_BASE+SAM_CKGR_UCKR_OFFSET) -#define SAM_CKGR_MOR (SAM_PMC_BASE+SAM_CKGR_MOR_OFFSET) -#define SAM_CKGR_MCFR (SAM_PMC_BASE+SAM_CKGR_MCFR_OFFSET) -#define SAM_CKGR_PLLAR (SAM_PMC_BASE+SAM_CKGR_PLLAR_OFFSET) -#define SAM_PMC_MCKR (SAM_PMC_BASE+SAM_PMC_MCKR_OFFSET) -#define SAM_PMC_PCK(n) (SAM_PMC_BASE+SAM_PMC_PCK_OFFSET(n)) -#define SAM_PMC_PCK0 (SAM_PMC_BASE+SAM_PMC_PCK0_OFFSET) -#define SAM_PMC_PCK1 (SAM_PMC_BASE+SAM_PMC_PCK1_OFFSET) -#define SAM_PMC_PCK2 (SAM_PMC_BASE+SAM_PMC_PCK2_OFFSET) -#define SAM_PMC_IER (SAM_PMC_BASE+SAM_PMC_IER_OFFSET) -#define SAM_PMC_IDR (SAM_PMC_BASE+SAM_PMC_IDR_OFFSET) -#define SAM_PMC_SR (SAM_PMC_BASE+SAM_PMC_SR_OFFSET) -#define SAM_PMC_IMR (SAM_PMC_BASE+SAM_PMC_IMR_OFFSET) -#define SAM_PMC_FSMR (SAM_PMC_BASE+SAM_PMC_FSMR_OFFSET) -#define SAM_PMC_FSPR (SAM_PMC_BASE+SAM_PMC_FSPR_OFFSET) -#define SAM_PMC_FOCR (SAM_PMC_BASE+SAM_PMC_FOCR_OFFSET) -#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET) -#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET) - -/* PMC register bit definitions *********************************************************/ - -/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System - * Clock Status Register common bit-field definitions - */ - -#define PMC_PCK(n) (1 <<((n)+8) -#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */ -#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */ -#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */ - -/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC - * Peripheral Clock Status Register common bit-field definitions. - */ - -#define PMC_PID(n) (1<<(n)) -#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ -#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ -#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ -#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ -#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ -#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ -#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ -#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ -#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ -#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ -#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ -#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ -#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ -#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ -#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ -#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ -#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ -#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ -#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ -#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ -#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ -#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ -#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ -#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ -#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ -#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ -#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ -#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ -#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ -#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ - -/* PMC UTMI Clock Configuration Register */ - -#define CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ -#define CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ -#define CKGR_UCKR_UPLLCOUNT_MASK (15 << CKGR_UCKR_UPLLCOUNT_SHIFT) - -/* PMC Clock Generator Main Oscillator Register */ - -#define CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCRCF_MASK (7 << CKGR_MOR_MOSCRCF_SHIFT) -#define CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_MOSCXTST_MASK (0x1ff << CKGR_MOR_MOSCXTST_SHIFT) -#define CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ -#define CKGR_MOR_KEY_MASK (0xff << CKGR_MOR_KEY_SHIFT) -#define CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ - -/* PMC Clock Generator Main Clock Frequency Register */ - -#define CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ -#define CKGR_MCFR_MAINF_MASK (0xffff << CKGR_MCFR_MAINF_SHIFT) -#define CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ - -/* PMC Clock Generator PLLA Register */ - -#define CKGR_PLLAR_DIVA_SHIFT (0) /* Bits 0-7: Divider */ -#define CKGR_PLLAR_DIVA_MASK (0xff << CKGR_PLLAR_DIVA_SHIFT) -# define CKGR_PLLAR_DIVA_ZERO (0 << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is 0 */ -# define CKGR_PLLAR_DIVA_BYPASS (1 << CKGR_PLLAR_DIVA_SHIFT) /* Divider is bypassed (DIVA=1) */ -# define CKGR_PLLAR_DIVA(n) ((n) << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is DIVA=n, n=2..255 */ -#define CKGR_PLLAR_PLLACOUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ -#define CKGR_PLLAR_PLLACOUNT_MASK (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) -#define CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */ -#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT) -# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */ -# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */ -#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ -#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT) -#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ - -/* PMC Master Clock Register */ - -#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ -#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) -# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ -# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ -# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ -# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ -#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ -#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) -# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ -# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ -# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ -# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ -# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ -# define PMC_MCKR_PRES_DIV32K (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ -# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ -# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ -#define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */ - -/* PMC Programmable Clock Register (0,1,2) */ - -#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ -#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) -# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ -# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ -# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ -# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ -# define PMC_PCK_CSS_MASTER (4 << PMC_PCK_CSS_MASK) /* Master Clock */ -#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ -#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) -# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ -# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ -# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ -# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ -# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ -# define PMC_PCK_PRES_DIV32K (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ -# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ - -/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, - * and PMC Interrupt Mask Register common bit-field definitions - */ - -#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ -#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ -#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ -#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ -#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */ -#define PMC_INT_PCKRDY(n) (1 << ((n)+8) -#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ -#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ -#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ -#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ -#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ -#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ -#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ -#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ - -/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field - * definitions - */ - -#define PMC_FSTI(n) (1 << (n)) -#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */ -#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */ -#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */ -#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */ -#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */ -#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */ -#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */ -#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */ -#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */ -#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */ -#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */ -#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */ -#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */ -#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */ -#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */ -#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */ - -#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */ -#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */ -#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */ -#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */ - -/* PMC Fault Output Clear Register */ - -#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ - -/* PMC Write Protect Mode Register */ - -#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ -#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ -#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) - -/* PMC Write Protect Status Register */ - -#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ -#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pwm.h b/nuttx/arch/arm/src/sam34/chip/sam_pwm.h index fe3bf04a14..d18ca291cf 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_pwm.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_pwm.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_pwm.h + * Pulse Width Modulation Controller (PWM) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -83,6 +84,9 @@ #define SAM_PWM_EL0MR_OFFSET 0x07c /* PWM Event Line 0 Mode Register */ #define SAM_PWM_EL1MR_OFFSET 0x080 /* PWM Event Line 1 Mode Register */ /* 0x084-0x0ac: Reserved */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */ +#endif /* 0x0b4-0x0e0: Reserved */ #define SAM_PWM_WPCR_OFFSET 0x0e4 /* PWM Write Protect Control Register */ #define SAM_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */ @@ -215,6 +219,10 @@ #define SAM_PWM_FPE (SAM_PWM_BASE+SAM_PWM_FPE_OFFSET) #define SAM_PWM_EL0MR (SAM_PWM_BASE+SAM_PWM_EL0MR_OFFSET) #define SAM_PWM_EL1MR (SAM_PWM_BASE+SAM_PWM_EL1MR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */ +# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */ +#endif #define SAM_PWM_WPCR (SAM_PWM_BASE+SAM_PWM_WPCR_OFFSET) #define SAM_PWM_WPSR (SAM_PWM_BASE+SAM_PWM_WPSR_OFFSET) @@ -518,6 +526,12 @@ #define PWM_ELMR_CSEL6 (1 << 6) /* Bit 6: Comparison 6 Selection */ #define PWM_ELMR_CSEL7 (1 << 7) /* Bit 7: Comparison 7 Selection */ +/* PWM Stepper Motor Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# warning SAM4S not yet integrated +#endif + /* PWM Write Protect Control Register */ #define PWM_WPCR_WPCMD_SHIFT (0) /* Bits 0-1: Write Protect Command */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rstc.h b/nuttx/arch/arm/src/sam34/chip/sam_rstc.h index 3a620d7ef9..3b278d45fa 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_rstc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_rstc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_rstc.h + * Reset Controller (RSTC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -68,6 +69,7 @@ #define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */ #define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ #define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) +# define RSTC_CR_KEY (0xa5 << RSTC_CR_KEY_SHIFT) #define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */ #define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */ @@ -86,6 +88,7 @@ #define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT) #define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */ #define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) +# define RSTC_MR_KEY (0xa5 << RSTC_CR_KEY_SHIFT) /**************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rtc.h b/nuttx/arch/arm/src/sam34/chip/sam_rtc.h index 5c0a2e15e3..4fe94a459b 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_rtc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_rtc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_rtc.h + * Real-time Clock (RTC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -81,6 +82,8 @@ /* RTC register bit definitions *********************************************************/ +/* RTC Control Register */ + #define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */ #define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */ #define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */ @@ -95,8 +98,56 @@ # define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT) # define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT) +/* RTC Mode Register */ + #define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTC_MR_PERSIAN (1 << 1) /* Bit 1: PERSIAN Calendar */ +# define RTC_MR_NEGPPM (1 << 4) /* Bit 4: Negative PPM Correction */ +# define RTC_MR_CORRECTION_SHIFT (8) /* Bits 8-14: Slow Clock Correction */ +# define RTC_MR_CORRECTION_ +# define RTC_MR_HIGHPPM (1 << 15) /* Bit 15: HIGH PPM Correction */ +# define RTC_MR_OUT0_SHIFT (16) /* Bits 16-18: RTCOUT0 Output Source Selection */ +# define RTC_MR_OUT0_MASK (7 << RTC_MR_OUT0_SHIFT) +# define RTC_MR_OUT0_NOWAVE (0 << RTC_MR_OUT0_SHIFT) /* No waveform, stuck at 0 */ +# define RTC_MR_OUT0_FREQ1HZ (1 << RTC_MR_OUT0_SHIFT) /* 1Hz square wave */ +# define RTC_MR_OUT0_FREQ32HZ (2 << RTC_MR_OUT0_SHIFT) /* 32Hz square wave */ +# define RTC_MR_OUT0_FREQ64HZ (3 << RTC_MR_OUT0_SHIFT) /* 64Hz square wave */ +# define RTC_MR_OUT0_FREQ512HZ (4 << RTC_MR_OUT0_SHIFT) /* 512Hz square wave */ +# define RTC_MR_OUT0_ALARM_TOGGLE (5 << RTC_MR_OUT0_SHIFT) /* Output toggles when alarm flag rises */ +# define RTC_MR_OUT0_ALARM_FLAG (6 << RTC_MR_OUT0_SHIFT) /* Output is a copy of the alarm flag */ +# define RTC_MR_OUT0_PROG_PULSE (7 << RTC_MR_OUT0_SHIFT) /* Duty cycle programmable pulse */ +# define RTC_MR_OUT1_SHIFT (20) /* Bits 20-22: RTCOUT1 Output Source Selection */ +# define RTC_MR_OUT1_MASK (7 << RTC_MR_OUT1_SHIFT) +# define RTC_MR_OUT1_NOWAVE (0 << RTC_MR_OUT1_SHIFT) /* No waveform, stuck at 0 */ +# define RTC_MR_OUT1_FREQ1HZ (1 << RTC_MR_OUT1_SHIFT) /* 1Hz square wave */ +# define RTC_MR_OUT1_FREQ32HZ (2 << RTC_MR_OUT1_SHIFT) /* 32Hz square wave */ +# define RTC_MR_OUT1_FREQ64HZ (3 << RTC_MR_OUT1_SHIFT) /* 64Hz square wave */ +# define RTC_MR_OUT1_FREQ512HZ (4 << RTC_MR_OUT1_SHIFT) /* 512Hz square wave */ +# define RTC_MR_OUT1_ALARM_TOGGLE (5 << RTC_MR_OUT1_SHIFT) /* Output toggles when alarm flag rises */ +# define RTC_MR_OUT1_ALARM_FLAG (6 << RTC_MR_OUT1_SHIFT) /* Output is a copy of the alarm flag */ +# define RTC_MR_OUT1_PROG_PULSE (7 << RTC_MR_OUT1_SHIFT) /* Duty cycle programmable pulse */ +# define RTC_MR_THIGH_SHIFT (24) /* Bits 24-26: High Duration of the Output Pulse */ +# define RTC_MR_THIGH_MASK (7 << RTC_MR_THIGH_SHIFT) +# define RTC_MR_THIGH_ 31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */ +# define RTC_MR_THIGH_ 16MS (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */ +# define RTC_MR_THIGH_ 4MS (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */ +# define RTC_MR_THIGH_ 976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */ +# define RTC_MR_THIGH_ 488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */ +# define RTC_MR_THIGH_ 22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */ +# define RTC_MR_THIGH_ 0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */ +# define RTC_MR_THIGH_ 15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */ +# define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */ +# define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT) +# define RTC_MR_TPERIOD_ 1S (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */ +# define RTC_MR_TPERIOD_ 500MS (1 << RTC_MR_TPERIOD_SHIFT) /* 500 ms */ +# define RTC_MR_TPERIOD_ 250MS (2 << RTC_MR_TPERIOD_SHIFT) /* 250 ms */ +# define RTC_MR_TPERIOD_ 125MS (3 << RTC_MR_TPERIOD_SHIFT) /* 125 ms */ +#endif + +/* RTC Time Register */ + #define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */ #define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT) #define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */ @@ -105,6 +156,8 @@ #define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT) #define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */ +/* RTC Calendar Register */ + #define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */ #define RTC_CALR_CENT_MASK (0x7f << RTC_TIMR_HOUR_SHIFT) #define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */ @@ -116,6 +169,8 @@ #define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */ #define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT) +/* RTC Time Alarm Register */ + #define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */ #define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT) #define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */ @@ -127,43 +182,73 @@ #define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */ #define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */ +/* RTC Calendar Alarm Register */ + #define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */ #define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT) #define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */ #define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */ -#define RTC_CALALR_DATE_MASK (0x3c << RTC_CALALR_DATE_SHIFT) +#define RTC_CALALR_DATE_MASK (0x3f << RTC_CALALR_DATE_SHIFT) #define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */ +/* RTC Status Register */ + #define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */ #define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */ #define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */ #define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */ #define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTC_SR_TDERR (1 << 5) /* Bit 5: Time and/or Date Free Running Error */ +#endif + +/* RTC Status Clear Command Register */ + #define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */ #define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */ #define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */ #define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */ #define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTC_SR_TDERRCLR (1 << 5) /* Bit 5: Time and/or Date Free Running Error Clear */ +#endif + +/* RTC Interrupt Enable Register */ + #define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */ #define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */ #define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */ #define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */ #define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTC_SR_TDERREN (1 << 5) /* Bit 5: Time and/or Date Error Interrupt Enable */ +#endif + +/* RTC Interrupt Disable Register */ + #define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */ #define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */ #define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */ #define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */ #define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTC_SR_TDERRDIS (1 << 5) /* Bit 5: Time and/or Date Error Interrupt Disable */ +#endif + +/* RTC Interrupt Mask Register */ + #define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */ #define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */ #define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */ #define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */ #define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */ +/* RTC Valid Entry Register */ + #define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */ #define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */ #define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rtt.h b/nuttx/arch/arm/src/sam34/chip/sam_rtt.h index 75b0d361e6..bd34ca814c 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_rtt.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_rtt.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_rtt.h + * Real-time Timer (RTT) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -65,12 +66,24 @@ /* RTT register bit definitions ********************************************************/ +/* Real-time Timer Mode Register */ + #define RTT_MR_RTPRES_SHIFT (0) /* Bits 0-15: Real-time Timer Prescaler Value */ #define RTT_MR_RTPRES__MASK (0xffff << RTT_MR_RTPRES_SHIFT) #define RTT_MR_ALMIEN (1 << 16) /* Bit 16: Alarm Interrupt Enable */ #define RTT_MR_RTTINCIEN (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */ #define RTT_MR_RTTRST (1 << 18) /* Bit 18: Real-time Timer Restart */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTT_MR_RTTDIS (1 << 20) /* Bit 20: Real-time Timer Disable */ +# define RTT_MR_RTC1HZ (1 << 24) /* Bit 24: Real-Time Clock 1Hz Clock Selection */ +#endif + +/* Real-time Timer Alarm Register (32-bit alarm value) */ +/* Real-time Timer Value Register (32-bit timer value) */ + +/* Real-time Timer Status Register */ + #define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */ #define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_smc.h b/nuttx/arch/arm/src/sam34/chip/sam_smc.h index ba67d66088..e729c1519e 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_smc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_smc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_smc.h + * Static Memory Controller (SMC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -51,369 +52,437 @@ /* SMC register offsets *****************************************************************/ -#define SAM_SMC_CFG_OFFSET 0x000 /* SMC NFC Configuration Register */ -#define SAM_SMC_CTRL_OFFSET 0x004 /* SMC NFC Control Register */ -#define SAM_SMC_SR_OFFSET 0x008 /* SMC NFC Status Register */ -#define SAM_SMC_IER_OFFSET 0x00c /* SMC NFC Interrupt Enable Register */ -#define SAM_SMC_IDR_OFFSET 0x010 /* SMC NFC Interrupt Disable Register */ -#define SAM_SMC_IMR_OFFSET 0x014 /* SMC NFC Interrupt Mask Register */ -#define SAM_SMC_ADDR_OFFSET 0x018 /* SMC NFC Address Cycle Zero Register */ -#define SAM_SMC_BANK_OFFSET 0x01c /* SMC Bank Address Register */ -#define SAM_SMC_ECCCTRL_OFFSET 0x020 /* SMC ECC Control Register */ -#define SAM_SMC_ECCMD_OFFSET 0x024 /* SMC ECC Mode Register */ -#define SAM_SMC_ECCSR1_OFFSET 0x028 /* SMC ECC Status 1 Register */ -#define SAM_SMC_ECCPR0_OFFSET 0x02c /* SMC ECC parity 0 Register */ -#define SAM_SMC_ECCPR1_OFFSET 0x030 /* SMC ECC parity 1 Register */ -#define SAM_SMC_ECCSR2_OFFSET 0x034 /* SMC ECC status 2 Register */ -#define SAM_SMC_ECCPR2_OFFSET 0x038 /* SMC ECC parity 2 Register */ -#define SAM_SMC_ECCPR3_OFFSET 0x03c /* SMC ECC parity 3 Register */ -#define SAM_SMC_ECCPR4_OFFSET 0x040 /* SMC ECC parity 4 Register */ -#define SAM_SMC_ECCPR5_OFFSET 0x044 /* SMC ECC parity 5 Register */ -#define SAM_SMC_ECCPR6_OFFSET 0x048 /* SMC ECC parity 6 Register */ -#define SAM_SMC_ECCPR7_OFFSET 0x04c /* SMC ECC parity 7 Register */ -#define SAM_SMC_ECCPR8_OFFSET 0x050 /* SMC ECC parity 8 Register */ -#define SAM_SMC_ECCPR9_OFFSET 0x054 /* SMC ECC parity 9 Register */ -#define SAM_SMC_ECCPR10_OFFSET 0x058 /* SMC ECC parity 10 Register */ -#define SAM_SMC_ECCPR11_OFFSET 0x05c /* SMC ECC parity 11 Register */ -#define SAM_SMC_ECCPR12_OFFSET 0x060 /* SMC ECC parity 12 Register */ -#define SAM_SMC_ECCPR13_OFFSET 0x064 /* SMC ECC parity 13 Register */ -#define SAM_SMC_ECCPR14_OFFSET 0x068 /* SMC ECC parity 14 Register */ -#define SAM_SMC_ECCPR15_OFFSET 0x06c /* SMC ECC parity 15 Register */ - -#define SAM_SMCCS_OFFSET(n) (0x070+((n)*0x014)) -#define SAM_SMCCS_SETUP_OFFSET 0x000 /* SMC SETUP Register */ -#define SAM_SMCCS_PULSE_OFFSET 0x004 /* SMC PULSE Register */ -#define SAM_SMCCS_CYCLE_OFFSET 0x008 /* SMC CYCLE Register */ -#define SAM_SMCCS_TIMINGS_OFFSET 0x00c /* SMC TIMINGS Register */ -#define SAM_SMCCS_MODE_OFFSET 0x010 /* SMC MODE Register */ - -#define SAM_SMC_OCMS_OFFSET 0x110 /* SMC OCMS MODE Register */ -#define SAM_SMC_KEY1_OFFSET 0x114 /* SMC KEY1 Register */ -#define SAM_SMC_KEY2_OFFSET 0x118 /* SMC KEY2 Register */ -#define SAM_SMC_WPCR_OFFSET 0x1e4 /* Write Protection Control Register */ -#define SAM_SMC_WPSR_OFFSET 0x1e8 /* Write Protection Status Register */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMC_CFG_OFFSET 0x0000 /* SMC NFC Configuration Register */ +# define SAM_SMC_CTRL_OFFSET 0x0004 /* SMC NFC Control Register */ +# define SAM_SMC_SR_OFFSET 0x0008 /* SMC NFC Status Register */ +# define SAM_SMC_IER_OFFSET 0x000c /* SMC NFC Interrupt Enable Register */ +# define SAM_SMC_IDR_OFFSET 0x0010 /* SMC NFC Interrupt Disable Register */ +# define SAM_SMC_IMR_OFFSET 0x0014 /* SMC NFC Interrupt Mask Register */ +# define SAM_SMC_ADDR_OFFSET 0x0018 /* SMC NFC Address Cycle Zero Register */ +# define SAM_SMC_BANK_OFFSET 0x001c /* SMC Bank Address Register */ +# define SAM_SMC_ECCCTRL_OFFSET 0x0020 /* SMC ECC Control Register */ +# define SAM_SMC_ECCMD_OFFSET 0x0024 /* SMC ECC Mode Register */ +# define SAM_SMC_ECCSR1_OFFSET 0x0028 /* SMC ECC Status 1 Register */ +# define SAM_SMC_ECCPR0_OFFSET 0x002c /* SMC ECC parity 0 Register */ +# define SAM_SMC_ECCPR1_OFFSET 0x0030 /* SMC ECC parity 1 Register */ +# define SAM_SMC_ECCSR2_OFFSET 0x0034 /* SMC ECC status 2 Register */ +# define SAM_SMC_ECCPR2_OFFSET 0x0038 /* SMC ECC parity 2 Register */ +# define SAM_SMC_ECCPR3_OFFSET 0x003c /* SMC ECC parity 3 Register */ +# define SAM_SMC_ECCPR4_OFFSET 0x0040 /* SMC ECC parity 4 Register */ +# define SAM_SMC_ECCPR5_OFFSET 0x0044 /* SMC ECC parity 5 Register */ +# define SAM_SMC_ECCPR6_OFFSET 0x0048 /* SMC ECC parity 6 Register */ +# define SAM_SMC_ECCPR7_OFFSET 0x004c /* SMC ECC parity 7 Register */ +# define SAM_SMC_ECCPR8_OFFSET 0x0050 /* SMC ECC parity 8 Register */ +# define SAM_SMC_ECCPR9_OFFSET 0x0054 /* SMC ECC parity 9 Register */ +# define SAM_SMC_ECCPR10_OFFSET 0x0058 /* SMC ECC parity 10 Register */ +# define SAM_SMC_ECCPR11_OFFSET 0x005c /* SMC ECC parity 11 Register */ +# define SAM_SMC_ECCPR12_OFFSET 0x0060 /* SMC ECC parity 12 Register */ +# define SAM_SMC_ECCPR13_OFFSET 0x0064 /* SMC ECC parity 13 Register */ +# define SAM_SMC_ECCPR14_OFFSET 0x0068 /* SMC ECC parity 14 Register */ +# define SAM_SMC_ECCPR15_OFFSET 0x006c /* SMC ECC parity 15 Register */ + +# define SAM_SMCCS_OFFSET(n) (0x0070+((n)*0x014)) +# define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup register */ +# define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */ +# define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */ +# define SAM_SMCCS_TIMINGS_OFFSET 0x000c /* SMC Timings Register */ +# define SAM_SMCCS_MODE_OFFSET 0x0010 /* SMC Mode Register */ + +# define SAM_SMC_OCMS_OFFSET 0x0110 /* SMC OCMS Mode Register */ +# define SAM_SMC_KEY1_OFFSET 0x0114 /* SMC KEY1 Register */ +# define SAM_SMC_KEY2_OFFSET 0x0118 /* SMC KEY2 Register */ +# define SAM_SMC_WPCR_OFFSET 0x01e4 /* Write Protection Control Register */ +# define SAM_SMC_WPSR_OFFSET 0x01e8 /* Write Protection Status Register */ + +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_SMCCS_OFFSET(n) ((n) << 4) +# define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup Register */ +# define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */ +# define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */ +# define SAM_SMCCS_MODE_OFFSET 0x000c /* SMC Mode Register */ + +# define SAM_SMC_OCMS_OFFSET 0x0080 /* SMC OCMS Mode Register */ +# define SAM_SMC_KEY1_OFFSET 0x0084 /* SMC KEY1 Register */ +# define SAM_SMC_KEY2_OFFSET 0x0088 /* SMC KEY2 Register */ +# define SAM_SMC_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */ +# define SAM_SMC_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ + +#else +# error Unrecognized SAM architecture +#endif /* SMC register adresses ****************************************************************/ -#define SAM_SMC_CFG (SAM_SMC_BASE+SAM_SMC_CFG_OFFSET) -#define SAM_SMC_CTRL (SAM_SMC_BASE+SAM_SMC_CTRL_OFFSET) -#define SAM_SMC_SR (SAM_SMC_BASE+SAM_SMC_SR_OFFSET) -#define SAM_SMC_IER (SAM_SMC_BASE+SAM_SMC_IER_OFFSET) -#define SAM_SMC_IDR (SAM_SMC_BASE+SAM_SMC_IDR_OFFSET) -#define SAM_SMC_IMR (SAM_SMC_BASE+SAM_SMC_IMR_OFFSET) -#define SAM_SMC_ADDR (SAM_SMC_BASE+SAM_SMC_ADDR_OFFSET) -#define SAM_SMC_BANK (SAM_SMC_BASE+SAM_SMC_BANK_OFFSET) -#define SAM_SMC_ECCCTRL (SAM_SMC_BASE+SAM_SMC_ECCCTRL_OFFSET) -#define SAM_SMC_ECCMD (SAM_SMC_BASE+SAM_SMC_ECCMD_OFFSET) -#define SAM_SMC_ECCSR1 (SAM_SMC_BASE+SAM_SMC_ECCSR1_OFFSET) -#define SAM_SMC_ECCPR0 (SAM_SMC_BASE+SAM_SMC_ECCPR0_OFFSET) -#define SAM_SMC_ECCPR1 (SAM_SMC_BASE+SAM_SMC_ECCPR1_OFFSET) -#define SAM_SMC_ECCSR2 (SAM_SMC_BASE+SAM_SMC_ECCSR2_OFFSET) -#define SAM_SMC_ECCPR2 (SAM_SMC_BASE+SAM_SMC_ECCPR2_OFFSET) -#define SAM_SMC_ECCPR3 (SAM_SMC_BASE+SAM_SMC_ECCPR3_OFFSET) -#define SAM_SMC_ECCPR4 (SAM_SMC_BASE+SAM_SMC_ECCPR4_OFFSET) -#define SAM_SMC_ECCPR5 (SAM_SMC_BASE+SAM_SMC_ECCPR5_OFFSET) -#define SAM_SMC_ECCPR6 (SAM_SMC_BASE+SAM_SMC_ECCPR6_OFFSET) -#define SAM_SMC_ECCPR7 (SAM_SMC_BASE+SAM_SMC_ECCPR7_OFFSET) -#define SAM_SMC_ECCPR8 (SAM_SMC_BASE+SAM_SMC_ECCPR8_OFFSET) -#define SAM_SMC_ECCPR9 (SAM_SMC_BASE+SAM_SMC_ECCPR9_OFFSET) -#define SAM_SMC_ECCPR10 (SAM_SMC_BASE+SAM_SMC_ECCPR10_OFFSET) -#define SAM_SMC_ECCPR11 (SAM_SMC_BASE+SAM_SMC_ECCPR11_OFFSET) -#define SAM_SMC_ECCPR12 (SAM_SMC_BASE+SAM_SMC_ECCPR12_OFFSET) -#define SAM_SMC_ECCPR13 (SAM_SMC_BASE+SAM_SMC_ECCPR13_OFFSET) -#define SAM_SMC_ECCPR14 (SAM_SMC_BASE+SAM_SMC_ECCPR14_OFFSET) -#define SAM_SMC_ECCPR15 (SAM_SMC_BASE+SAM_SMC_ECCPR15_OFFSET) - -#define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n)) -# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(0)) -# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(1)) -# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(2)) -# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(3)) -#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET) -#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET) -#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET) -#define SAM_SMCCS_TIMINGS(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_TIMINGS_OFFSET) -#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET) - -#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET) -#define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET) -#define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET) -#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET) -#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMC_CFG (SAM_SMC_BASE+SAM_SMC_CFG_OFFSET) +# define SAM_SMC_CTRL (SAM_SMC_BASE+SAM_SMC_CTRL_OFFSET) +# define SAM_SMC_SR (SAM_SMC_BASE+SAM_SMC_SR_OFFSET) +# define SAM_SMC_IER (SAM_SMC_BASE+SAM_SMC_IER_OFFSET) +# define SAM_SMC_IDR (SAM_SMC_BASE+SAM_SMC_IDR_OFFSET) +# define SAM_SMC_IMR (SAM_SMC_BASE+SAM_SMC_IMR_OFFSET) +# define SAM_SMC_ADDR (SAM_SMC_BASE+SAM_SMC_ADDR_OFFSET) +# define SAM_SMC_BANK (SAM_SMC_BASE+SAM_SMC_BANK_OFFSET) +# define SAM_SMC_ECCCTRL (SAM_SMC_BASE+SAM_SMC_ECCCTRL_OFFSET) +# define SAM_SMC_ECCMD (SAM_SMC_BASE+SAM_SMC_ECCMD_OFFSET) +# define SAM_SMC_ECCSR1 (SAM_SMC_BASE+SAM_SMC_ECCSR1_OFFSET) +# define SAM_SMC_ECCPR0 (SAM_SMC_BASE+SAM_SMC_ECCPR0_OFFSET) +# define SAM_SMC_ECCPR1 (SAM_SMC_BASE+SAM_SMC_ECCPR1_OFFSET) +# define SAM_SMC_ECCSR2 (SAM_SMC_BASE+SAM_SMC_ECCSR2_OFFSET) +# define SAM_SMC_ECCPR2 (SAM_SMC_BASE+SAM_SMC_ECCPR2_OFFSET) +# define SAM_SMC_ECCPR3 (SAM_SMC_BASE+SAM_SMC_ECCPR3_OFFSET) +# define SAM_SMC_ECCPR4 (SAM_SMC_BASE+SAM_SMC_ECCPR4_OFFSET) +# define SAM_SMC_ECCPR5 (SAM_SMC_BASE+SAM_SMC_ECCPR5_OFFSET) +# define SAM_SMC_ECCPR6 (SAM_SMC_BASE+SAM_SMC_ECCPR6_OFFSET) +# define SAM_SMC_ECCPR7 (SAM_SMC_BASE+SAM_SMC_ECCPR7_OFFSET) +# define SAM_SMC_ECCPR8 (SAM_SMC_BASE+SAM_SMC_ECCPR8_OFFSET) +# define SAM_SMC_ECCPR9 (SAM_SMC_BASE+SAM_SMC_ECCPR9_OFFSET) +# define SAM_SMC_ECCPR10 (SAM_SMC_BASE+SAM_SMC_ECCPR10_OFFSET) +# define SAM_SMC_ECCPR11 (SAM_SMC_BASE+SAM_SMC_ECCPR11_OFFSET) +# define SAM_SMC_ECCPR12 (SAM_SMC_BASE+SAM_SMC_ECCPR12_OFFSET) +# define SAM_SMC_ECCPR13 (SAM_SMC_BASE+SAM_SMC_ECCPR13_OFFSET) +# define SAM_SMC_ECCPR14 (SAM_SMC_BASE+SAM_SMC_ECCPR14_OFFSET) +# define SAM_SMC_ECCPR15 (SAM_SMC_BASE+SAM_SMC_ECCPR15_OFFSET) +#endif + +#define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n)) +# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(0)) +# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(1)) +# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(2)) +# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(3)) +#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET) +#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET) +#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMCCS_TIMINGS(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_TIMINGS_OFFSET) +#endif +#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET) + +#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET) +#define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET) +#define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET) +#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET) +#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET) /* SMC register bit definitions *********************************************************/ /* SMC NFC Configuration Register */ -#define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */ -#define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT) -# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */ -# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */ -# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */ -# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */ -#define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */ -#define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */ -#define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */ -#define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */ -#define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */ -#define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT) -#define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */ -#define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */ +# define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT) +# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */ +# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */ +# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */ +# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */ +# define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */ +# define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */ +# define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */ +# define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */ +# define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */ +# define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT) +# define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */ +# define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT) +#endif /* SMC NFC Control Register */ -#define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */ -#define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */ +# define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */ +#endif /* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt * Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions */ -#define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */ -#define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */ -#define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */ -#define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */ -#define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */ -#define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */ -#define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */ -#define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */ -#define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */ -#define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */ -#define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */ -#define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */ -#define SMC_INT_RBEDGE(n) (1<<((n)+24)) -#define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */ -#define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */ -#define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */ -#define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */ -#define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */ -#define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */ -#define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */ -#define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */ +# define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */ +# define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */ +# define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */ +# define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */ +# define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */ +# define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */ +# define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */ +# define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */ +# define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */ +# define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */ +# define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */ +# define SMC_INT_RBEDGE(n) (1<<((n)+24)) +# define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */ +# define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */ +# define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */ +# define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */ +# define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */ +# define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */ +# define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */ +# define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */ +#endif /* SMC NFC Address Cycle Zero Register */ -#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ -#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ +# define SMC_ADDR_CYCLE0_MASK (0xff << SMC_ADDR_CYCLE0_SHIFT) +#endif /* SMC NFC Bank Register */ -#define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */ -#define SMC_BANK_MASK (7 << SMC_BANK_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */ +# define SMC_BANK_MASK (7 << SMC_BANK_SHIFT) +#endif /* SMC ECC Control Register */ -#define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */ -#define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */ +# define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */ +#endif /* SMC ECC MODE Register */ -#define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */ -#define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -#define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */ -#define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT) -# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */ -# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */ -# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */ +# define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */ +# define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT) +# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */ +# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */ +# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */ +#endif /* SMC ECC Status Register 1 */ -#define _RECERR (0) /* Recoverable Error */ -#define _ECCERR (1) /* ECC Error */ -#define _MULERR (2) /* Multiple Error */ - -#define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR)) -#define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR)) -#define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR)) - -#define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0) -#define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0) -#define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0) -#define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1) -#define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1) -#define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1) -#define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2) -#define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2) -#define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2) -#define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3) -#define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3) -#define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3) -#define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4) -#define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4) -#define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4) -#define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5) -#define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5) -#define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5) -#define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6) -#define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6) -#define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6) -#define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7) -#define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7) -#define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define _RECERR (0) /* Recoverable Error */ +# define _ECCERR (1) /* ECC Error */ +# define _MULERR (2) /* Multiple Error */ + +# define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR)) +# define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR)) +# define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR)) + +# define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0) +# define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0) +# define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0) +# define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1) +# define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1) +# define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1) +# define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2) +# define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2) +# define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2) +# define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3) +# define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3) +# define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3) +# define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4) +# define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4) +# define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4) +# define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5) +# define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5) +# define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5) +# define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6) +# define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6) +# define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6) +# define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7) +# define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7) +# define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7) +#endif /* SMC ECC Status Register 2 */ -#define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR)) -#define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR)) -#define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR)) - -#define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8) -#define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8) -#define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8) -#define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9) -#define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9) -#define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9) -#define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10) -#define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10) -#define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10) -#define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11) -#define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11) -#define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11) -#define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12) -#define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12) -#define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12) -#define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13) -#define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13) -#define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13) -#define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14) -#define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14) -#define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14) -#define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15) -#define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15) -#define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR)) +# define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR)) +# define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR)) + +# define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8) +# define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8) +# define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8) +# define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9) +# define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9) +# define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9) +# define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10) +# define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10) +# define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10) +# define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11) +# define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11) +# define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11) +# define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12) +# define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12) +# define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12) +# define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13) +# define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13) +# define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13) +# define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14) +# define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14) +# define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14) +# define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15) +# define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15) +# define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15) +#endif /* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */ /* SMC_ECC_PR0 */ -#define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ -#define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT) -#define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ -#define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ +# define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT) +# define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ +# define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT) -#define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */ -#define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT) +# define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */ +# define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT) +#endif /* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */ -#define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ -#define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT) -#define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ -#define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT) -#define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */ -#define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ +# define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT) +# define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ +# define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT) +# define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */ +# define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT) +#endif /* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */ -#define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */ -#define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT) -#define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */ -#define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT) -#define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */ -#define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */ +# define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT) +# define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */ +# define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT) +# define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */ +# define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT) +#endif /* SMC Setup Register */ -#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */ -#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT) -#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */ -#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT) -#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */ -#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT) -#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */ -#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT) +#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */ +#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT) +#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */ +#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT) +#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */ +#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT) +#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */ +#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT) /* SMC Pulse Register */ -#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */ -#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT) -#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */ -#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT) -#define SMCCS_PULSE_RDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */ -#define SMCCS_PULSE_RDPULSE_MASK (63 << SMCCS_PULSE_RDPULSE_SHIFT) -#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */ -#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT) +#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */ +#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT) +#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */ +#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT) +#define SMCCS_PULSE_NRDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */ +#define SMCCS_PULSE_NRDPULSE_MASK (63 << SMCCS_PULSE_NRDPULSE_SHIFT) +#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */ +#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT) /* SMC Cycle Register */ -#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */ -#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT) -#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */ -#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT) +#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */ +#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT) +#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */ +#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT) /* SMC Timings Register */ -#define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */ -#define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT) -#define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */ -#define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT) -#define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */ -#define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT) -#define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */ -#define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */ -#define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT) -#define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */ -#define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT) -#define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */ -#define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT) -#define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */ +# define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT) +# define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */ +# define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT) +# define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */ +# define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT) +# define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */ +# define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */ +# define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT) +# define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */ +# define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT) +# define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */ +# define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT) +# define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */ +#endif /* SMC Mode Register */ -#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */ -#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */ -#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */ -#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT) -# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT) -# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT) -# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT) -#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */ -#define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */ -#define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT) -# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */ -# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */ -# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */ -#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */ -#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT) -#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */ -#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */ -#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ -#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT) -# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */ -# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */ -# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */ -# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */ - -/* SMC OCMS Register */ - -#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */ - -/* SMC Write Protection Control */ - -#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */ -#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */ -#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT) +#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */ +#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */ +#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */ +#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */ +# define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */ +# define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT) +# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */ +# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */ +# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */ +#endif + +#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */ +#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT) +#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */ +#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */ +#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ +#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT) +# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */ +# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */ +# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */ +# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */ + +/* SMC OCMS Mode Register */ + +#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SMC_OCMS_CSSE(n) (1 << ((n)+16)) /* Chip Select (n=0-3) Scrambling Enable */ +# define SMC_OCMS_CS0SE (1 << 16) /* Bit 16: Chip Select 0 Scrambling Enable */ +# define SMC_OCMS_CS1SE (1 << 17) /* Bit 17: Chip Select 1 Scrambling Enable */ +# define SMC_OCMS_CS2SE (1 << 18) /* Bit 18: Chip Select 2 Scrambling Enable */ +# define SMC_OCMS_CS3SE (1 << 19) /* Bit 19: Chip Select 3 Scrambling Enable */ +#endif + +/* SMC KEY1/2 Registers (32-bit data) */ + +/* SMC Write Protect Mode Register */ + +#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */ +#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */ +#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT) +# define SMC_WPCR_WPKEY (0x00534d43 << SMC_WPCR_WPKEY_SHIFT) /* SMC Write Protection Status */ -#define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ -#define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT) -# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */ -# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */ -# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */ -# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +# define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT) +# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */ +# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */ +# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */ +# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define SMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Source */ +#endif + #define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ #define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT) diff --git a/nuttx/arch/arm/src/sam34/chip/sam_spi.h b/nuttx/arch/arm/src/sam34/chip/sam_spi.h index 91720647fd..887b7f656d 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_spi.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_spi.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_spi.h + * Serial Peripheral Interface (SPI) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -67,7 +68,8 @@ /* 0x40-0xe0: Reserved */ #define SAM_SPI_WPCR_OFFSET 0xe4 /* Write Protection Control Register */ #define SAM_SPI_WPSR_OFFSET 0xe8 /* Write Protection Status Register */ - /* 0xec-0xf8: Reserved*/ + /* 0xec-0xfc: Reserved */ + /* 0x100-0x124 Reserved for PDC Registers */ /* SPI register adresses ****************************************************************/ @@ -105,6 +107,10 @@ #define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */ #define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ #define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT) +# define SPI_MR_PCS0 (0 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */ +# define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ #define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */ #define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT) @@ -114,6 +120,10 @@ #define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT) #define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ #define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT) +# define SPI_RDR_PCS0 (0 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_RDR_PCS1 (1 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */ +# define SPI_RDR_PCS2 (3 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_RDR_PCS3 (7 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ /* SPI Transmit Data Register */ @@ -121,6 +131,10 @@ #define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT) #define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ #define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT) +# define SPI_TDR_PCS0 (0 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */ +# define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ #define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */ /* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register, @@ -131,6 +145,14 @@ #define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */ #define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */ #define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SPI_INT_ENDRX (1 << 4) /* Bit 4: End of RX buffer */ +# define SPI_INT_ENDTX (1 << 5) /* Bit 5: End of TX buffer */ +# define SPI_INT_RXBUFF (1 << 6) /* Bit 6: RX Buffer Full */ +# define SPI_INT_TXBUFE (1 << 7) /* Bit 7: TX Buffer Empty */ +#endif + #define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */ #define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */ #define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */ @@ -163,16 +185,17 @@ /* SPI Write Protection Control Register */ -#define SPI_WPCR_SPIWPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */ -#define SPI_WPCR_SPIWPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */ -#define SPI_WPCR_SPIWPKEY_MASK (0x00ffffff << SPI_WPCR_SPIWPKEY_SHIFT) +#define SPI_WPCR_WPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */ +#define SPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */ +#define SPI_WPCR_WPKEY_MASK (0x00ffffff << SPI_WPCR_WPKEY_SHIFT) +# define SPI_WPCR_WPKEY (0x00535049 << SPI_WPCR_WPKEY_SHIFT) /* SPI Write Protection Status Register */ -#define SPI_WPSR_SPIWPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVS_MASK (7 << SPI_WPSR_SPIWPVS_SHIFT) -#define SPI_WPSR_SPIWPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */ -#define SPI_WPSR_SPIWPVSRC_MASK (0xff << SPI_WPSR_SPIWPVSRC_SHIFT) +#define SPI_WPSR_WPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */ +#define SPI_WPSR_WPVS_MASK (7 << SPI_WPSR_WPVS_SHIFT) +#define SPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */ +#define SPI_WPSR_WPVSRC_MASK (0xff << SPI_WPSR_WPVSRC_SHIFT) /**************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/src/sam34/chip/sam_ssc.h b/nuttx/arch/arm/src/sam34/chip/sam_ssc.h index 5526592602..2b3755a1c2 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_ssc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_ssc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_ssc.h + * Synchronous Serial Controller (SSC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -74,7 +75,7 @@ #define SAM_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */ #define SAM_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */ /* 0x050-0x0fc: Reserved */ - /* 0x100-0x124: Reserved */ + /* 0x100-0x124: Reserved for PDC registers */ /* SSC register adresses ****************************************************************/ @@ -121,7 +122,7 @@ # define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */ #define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */ #define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT) -# define SSC_RCMR_CKO_ NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */ +# define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */ # define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */ # define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */ #define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */ @@ -142,12 +143,11 @@ # define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */ # define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */ #define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */ -#define SSC_RCMR_STTDLY_SHIFT (15) /* Bits 16-23: Receive Start Delay */ +#define SSC_RCMR_STTDLY_SHIFT (16) /* Bits 16-23: Receive Start Delay */ #define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT) #define SSC_RCMR_PERIOD_SHIFT (24) /* Bits 24-31: Receive Period Divider Selection */ #define SSC_RCMR_PERIOD_MASK (0xff << SSC_RCMR_PERIOD_SHIFT) - /* SSC Receive Frame Mode Register */ #define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */ @@ -162,7 +162,7 @@ #define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT) # define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None */ # define SSC_RFMR_FSOS_NEG (1 << SSC_RFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ -# define SSC_RFMR_FSOS_POW (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ +# define SSC_RFMR_FSOS_POS (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ # define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ # define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ # define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ @@ -175,11 +175,11 @@ #define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */ #define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT) # define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */ -# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Clock signal */ -# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK pin */ +# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK Clock signal */ +# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Pin */ #define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ #define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) -# define SSC_TCMR_CKO_ NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */ +# define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */ # define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */ # define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */ #define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */ @@ -217,7 +217,7 @@ #define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT) # define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None */ # define SSC_TFMR_FSOS_NEG (1 << SSC_TFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ -# define SSC_TFMR_FSOS_POW (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ +# define SSC_TFMR_FSOS_POS (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ # define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ # define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ # define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ @@ -226,6 +226,8 @@ #define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ #define SSC_TFMR_FSLENEXT_MASK (15 << SSC_TFMR_FSLENEXT_SHIFT) +/* SSC Receive/Transmit Holding Registers (32-bit data) */ + /* SSC Receive Synchronization Holding Register */ #define SSC_RSHR_RSDAT_SHIFT (0) /* Bits 0-15: Receive Synchronization Data */ @@ -270,6 +272,7 @@ #define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ #define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ #define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT) +# define SSC_WPMR_WPKEY (0x00535343 << SSC_WPMR_WPKEY_SHIFT) /* SSC Write Protect Status Register */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_tc.h b/nuttx/arch/arm/src/sam34/chip/sam_tc.h index de20468520..779a5a2afb 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_tc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_tc.h @@ -1,5 +1,6 @@ /************************************************************************************************ * arch/arm/src/sam34/chip/sam_tc.h + * Timer Counter (TC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -56,7 +57,10 @@ #define SAM_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */ #define SAM_TCN_CCR_OFFSET 0x00 /* Channel Control Register */ #define SAM_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */ - /* 0x08 Reserved */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +#define SAM_TCN_SMMR_OFFSET 0x08 /* Stepper Motor Mode Register */ +#endif /* 0x0c Reserved */ #define SAM_TCN_CV_OFFSET 0x10 /* Counter Value */ #define SAM_TCN_RA_OFFSET 0x14 /* Register A */ @@ -75,8 +79,11 @@ #define SAM_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */ #define SAM_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */ #define SAM_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */ - /* 0xd8 Reserved */ - /* 0xe4 Reserved */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TCN_FMR_OFFSET 0xd8 /* Fault Mode Register */ +# define SAM_TCN_WPMR_OFFSET 0xe4 /* Write Protect Mode Register */ +#endif /* TC register adresses *************************************************************************/ @@ -84,6 +91,9 @@ #define SAM_TC_CCR(n) (SAM_TCN_BASE(n)+SAM_TCN_CCR_OFFSET) #define SAM_TC_CMR(n) (SAM_TCN_BASE(n)+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TCN_SMMR(n) (SAM_TCN_BASE(n)+SAM_TCN_SMMR_OFFSET) +#endif #define SAM_TC_CV(n) (SAM_TCN_BASE(n)+SAM_TCN_CV_OFFSET) #define SAM_TC_RA(n) (SAM_TCN_BASE(n)+SAM_TCN_RA_OFFSET) #define SAM_TC_RB(n) (SAM_TCN_BASE(n)+SAM_TCN_RB_OFFSET) @@ -92,9 +102,16 @@ #define SAM_TC_IER(n) (SAM_TCN_BASE(n)+SAM_TCN_IER_OFFSET) #define SAM_TC_IDR(n) (SAM_TCN_BASE(n)+SAM_TCN_IDR_OFFSET) #define SAM_TC_IMR(n) (SAM_TCN_BASE(n)+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TCN_FMR(n) (SAM_TCN_BASE(n)+SAM_TCN_FMR_OFFSET) +# define SAM_TCN_WPMR(n) (SAM_TCN_BASE(n)+SAM_TCN_WPMR_OFFSET) +#endif #define SAM_TC0_CCR (SAM_TC0_BASE+SAM_TCN_CCR_OFFSET) #define SAM_TC0_CMR (SAM_TC0_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC0_SMMR (SAM_TC0_BASE+SAM_TCN_SMMR_OFFSET) +#endif #define SAM_TC0_CV (SAM_TC0_BASE+SAM_TCN_CV_OFFSET) #define SAM_TC0_RA (SAM_TC0_BASE+SAM_TCN_RA_OFFSET) #define SAM_TC0_RB (SAM_TC0_BASE+SAM_TCN_RB_OFFSET) @@ -103,9 +120,16 @@ #define SAM_TC0_IER (SAM_TC0_BASE+SAM_TCN_IER_OFFSET) #define SAM_TC0_IDR (SAM_TC0_BASE+SAM_TCN_IDR_OFFSET) #define SAM_TC0_IMR (SAM_TC0_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC0_FMR (SAM_TC0_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC0_WPMR (SAM_TC0_BASE+SAM_TCN_WPMR_OFFSET) +#endif #define SAM_TC1_CCR (SAM_TC1_BASE+SAM_TCN_CCR_OFFSET) #define SAM_TC1_CMR (SAM_TC1_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC1_SMMR (SAM_TC1_BASE+SAM_TCN_SMMR_OFFSET) +#endif #define SAM_TC1_CV (SAM_TC1_BASE+SAM_TCN_CV_OFFSET) #define SAM_TC1_RA (SAM_TC1_BASE+SAM_TCN_RA_OFFSET) #define SAM_TC1_RB (SAM_TC1_BASE+SAM_TCN_RB_OFFSET) @@ -114,9 +138,16 @@ #define SAM_TC1_IER (SAM_TC1_BASE+SAM_TCN_IER_OFFSET) #define SAM_TC1_IDR (SAM_TC1_BASE+SAM_TCN_IDR_OFFSET) #define SAM_TC1_IMR (SAM_TC1_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC1_FMR (SAM_TC1_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC1_WPMR (SAM_TC1_BASE+SAM_TCN_WPMR_OFFSET) +#endif #define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TCN_CCR_OFFSET) #define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC2_SMMR (SAM_TC2_BASE+SAM_TCN_SMMR_OFFSET) +#endif #define SAM_TC2_CV (SAM_TC2_BASE+SAM_TCN_CV_OFFSET) #define SAM_TC2_RA (SAM_TC2_BASE+SAM_TCN_RA_OFFSET) #define SAM_TC2_RB (SAM_TC2_BASE+SAM_TCN_RB_OFFSET) @@ -125,6 +156,64 @@ #define SAM_TC2_IER (SAM_TC2_BASE+SAM_TCN_IER_OFFSET) #define SAM_TC2_IDR (SAM_TC2_BASE+SAM_TCN_IDR_OFFSET) #define SAM_TC2_IMR (SAM_TC2_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC2_FMR (SAM_TC2_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC2_WPMR (SAM_TC2_BASE+SAM_TCN_WPMR_OFFSET) +#endif + +#define SAM_TC3_CCR (SAM_TC3_BASE+SAM_TCN_CCR_OFFSET) +#define SAM_TC3_CMR (SAM_TC3_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC3_SMMR (SAM_TC3_BASE+SAM_TCN_SMMR_OFFSET) +#endif +#define SAM_TC3_CV (SAM_TC3_BASE+SAM_TCN_CV_OFFSET) +#define SAM_TC3_RA (SAM_TC3_BASE+SAM_TCN_RA_OFFSET) +#define SAM_TC3_RB (SAM_TC3_BASE+SAM_TCN_RB_OFFSET) +#define SAM_TC3_RC (SAM_TC3_BASE+SAM_TCN_RC_OFFSET) +#define SAM_TC3_SR (SAM_TC3_BASE+SAM_TCN_SR_OFFSET) +#define SAM_TC3_IER (SAM_TC3_BASE+SAM_TCN_IER_OFFSET) +#define SAM_TC3_IDR (SAM_TC3_BASE+SAM_TCN_IDR_OFFSET) +#define SAM_TC3_IMR (SAM_TC3_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC3_FMR (SAM_TC3_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC3_WPMR (SAM_TC3_BASE+SAM_TCN_WPMR_OFFSET) +#endif + +#define SAM_TC4_CCR (SAM_TC4_BASE+SAM_TCN_CCR_OFFSET) +#define SAM_TC4_CMR (SAM_TC4_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC4_SMMR (SAM_TC4_BASE+SAM_TCN_SMMR_OFFSET) +#endif +#define SAM_TC4_CV (SAM_TC4_BASE+SAM_TCN_CV_OFFSET) +#define SAM_TC4_RA (SAM_TC4_BASE+SAM_TCN_RA_OFFSET) +#define SAM_TC4_RB (SAM_TC4_BASE+SAM_TCN_RB_OFFSET) +#define SAM_TC4_RC (SAM_TC4_BASE+SAM_TCN_RC_OFFSET) +#define SAM_TC4_SR (SAM_TC4_BASE+SAM_TCN_SR_OFFSET) +#define SAM_TC4_IER (SAM_TC4_BASE+SAM_TCN_IER_OFFSET) +#define SAM_TC4_IDR (SAM_TC4_BASE+SAM_TCN_IDR_OFFSET) +#define SAM_TC4_IMR (SAM_TC4_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC4_FMR (SAM_TC4_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC4_WPMR (SAM_TC4_BASE+SAM_TCN_WPMR_OFFSET) +#endif + +#define SAM_TC5_CCR (SAM_TC5_BASE+SAM_TCN_CCR_OFFSET) +#define SAM_TC5_CMR (SAM_TC5_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC5_SMMR (SAM_TC5_BASE+SAM_TCN_SMMR_OFFSET) +#endif +#define SAM_TC5_CV (SAM_TC5_BASE+SAM_TCN_CV_OFFSET) +#define SAM_TC5_RA (SAM_TC5_BASE+SAM_TCN_RA_OFFSET) +#define SAM_TC5_RB (SAM_TC5_BASE+SAM_TCN_RB_OFFSET) +#define SAM_TC5_RC (SAM_TC5_BASE+SAM_TCN_RC_OFFSET) +#define SAM_TC5_SR (SAM_TC5_BASE+SAM_TCN_SR_OFFSET) +#define SAM_TC5_IER (SAM_TC5_BASE+SAM_TCN_IER_OFFSET) +#define SAM_TC5_IDR (SAM_TC5_BASE+SAM_TCN_IDR_OFFSET) +#define SAM_TC5_IMR (SAM_TC5_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC5_FMR (SAM_TC5_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC5_WPMR (SAM_TC5_BASE+SAM_TCN_WPMR_OFFSET) +#endif /* Timer common registers */ @@ -308,6 +397,12 @@ # define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT) # define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT) +/* Stepper Motor Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# warning SAM4S not yet integrated +#endif + /* TC Counter Value Register */ #define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */ @@ -332,6 +427,18 @@ #define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */ #define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/ +/* Fault Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# warning SAM4S not yet integrated +#endif + +/* Write Protect Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# warning SAM4S not yet integrated +#endif + /************************************************************************************************ * Public Types ************************************************************************************************/ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_twi.h b/nuttx/arch/arm/src/sam34/chip/sam_twi.h index 056f1062eb..091e98f34a 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_twi.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_twi.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_twi.h + * Two-wire Interface (TWI) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -125,13 +126,13 @@ # define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */ # define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */ #define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */ -#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */ -#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT) +#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */ +#define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT) /* TWI Slave Mode Register */ -#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */ -#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT) +#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-22: Slave Address */ +#define TWI_SMR_SADR_MASK (0x7f << TWI_SMR_SADR_SHIFT) /* TWI Internal Address Register */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_uart.h b/nuttx/arch/arm/src/sam34/chip/sam_uart.h deleted file mode 100644 index 4825435fdb..0000000000 --- a/nuttx/arch/arm/src/sam34/chip/sam_uart.h +++ /dev/null @@ -1,391 +0,0 @@ -/************************************************************************************************ - * arch/arm/src/sam34/chip/sam_uart.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H - -/************************************************************************************************ - * Included Files - ************************************************************************************************/ - -#include - -#include "chip.h" -#include "chip/sam_memorymap.h" - -/************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************/ - -/* UART register offsets ************************************************************************/ - -#define SAM_UART_CR_OFFSET 0x0000 /* Control Register (Common) */ -#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */ -#define SAM_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */ -#define SAM_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */ -#define SAM_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */ -#define SAM_UART_SR_OFFSET 0x0014 /* Status Register (Common) */ -#define SAM_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */ -#define SAM_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */ -#define SAM_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */ - /* 0x0024-0x003c: Reserved (UART) */ -#define SAM_USART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */ -#define SAM_USART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */ - /* 0x002c-0x003c: Reserved (UART) */ -#define SAM_USART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */ -#define SAM_USART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */ - /* 0x0048: Reserved (USART) */ -#define SAM_USART_IF_OFFSET 0x004c /* IrDA Filter Register (USART only) */ -#define SAM_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */ -#define SAM_USART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */ -#define SAM_USART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */ - /* 0x005c-0xf008: Reserved (USART) */ -#define SAM_USART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */ - /* 0x0100-0x0124: PDC Area (Common) */ - -/* UART register adresses ***********************************************************************/ - -#define SAM_UART_CR (SAM_UART_BASE+SAM_UART_CR_OFFSET) -#define SAM_UART_MR (SAM_UART_BASE+SAM_UART_MR_OFFSET) -#define SAM_UART_IER (SAM_UART_BASE+SAM_UART_IER_OFFSET) -#define SAM_UART_IDR (SAM_UART_BASE+SAM_UART_IDR_OFFSET) -#define SAM_UART_IMR (SAM_UART_BASE+SAM_UART_IMR_OFFSET) -#define SAM_UART_SR (SAM_UART_BASE+SAM_UART_SR_OFFSET) -#define SAM_UART_RHR (SAM_UART_BASE+SAM_UART_RHR_OFFSET) -#define SAM_UART_THR (SAM_UART_BASE+SAM_UART_THR_OFFSET) -#define SAM_UART_BRGR (SAM_UART_BASE+SAM_UART_BRGR_OFFSET) - -#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET) -#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET) -#define SAM_USART_IER(n) (SAM_USARTN_BASE(n)+SAM_UART_IER_OFFSET) -#define SAM_USART_IDR(n) (SAM_USARTN_BASE(n)+SAM_UART_IDR_OFFSET) -#define SAM_USART_IMR(n) (SAM_USARTN_BASE(n)+SAM_UART_IMR_OFFSET) -#define SAM_USART_SR(n) (SAM_USARTN_BASE(n)+SAM_UART_SR_OFFSET) -#define SAM_USART_RHR(n) (SAM_USARTN_BASE(n)+SAM_UART_RHR_OFFSET) -#define SAM_USART_THR(n) (SAM_USARTN_BASE(n)+SAM_UART_THR_OFFSET) -#define SAM_USART_BRGR(n) (SAM_USARTN_BASE(n)+SAM_UART_BRGR_OFFSET) -#define SAM_USART_RTOR(n) (SAM_USARTN_BASE(n)+SAM_USART_RTOR_OFFSET) -#define SAM_USART_TTGR(n) (SAM_USARTN_BASE(n)+SAM_USART_TTGR_OFFSET) -#define SAM_USART_FIDI(n) (SAM_USARTN_BASE(n)+SAM_USART_FIDI_OFFSET) -#define SAM_USART_NER(n) (SAM_USARTN_BASE(n)+SAM_USART_NER_OFFSET) -#define SAM_USART_IF(n) (SAM_USARTN_BASE(n)+SAM_USART_IF_OFFSET) -#define SAM_USART_MAN(n) (SAM_USARTN_BASE(n)+SAM_USART_MAN_OFFSET) -#define SAM_USART_WPMR(n) (SAM_USARTN_BASE(n)+SAM_USART_WPMR_OFFSET) -#define SAM_USART_WPSR(n) (SAM_USARTN_BASE(n)+SAM_USART_WPSR_OFFSET) -#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_USART_VERSION_OFFSET) - -#define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART0_MR_ (SAM_USART0_BASE+SAM_UART_MR_OFFSET) -#define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET) -#define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET) -#define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET) -#define SAM_USART0_SR (SAM_USART0_BASE+SAM_UART_SR_OFFSET) -#define SAM_USART0_RHR (SAM_USART0_BASE+SAM_UART_RHR_OFFSET) -#define SAM_USART0_THR (SAM_USART0_BASE+SAM_UART_THR_OFFSET) -#define SAM_USART0_BRGR (SAM_USART0_BASE+SAM_UART_BRGR_OFFSET) -#define SAM_USART0_RTOR (SAM_USART0_BASE+SAM_USART_RTOR_OFFSET) -#define SAM_USART0_TTGR (SAM_USART0_BASE+SAM_USART_TTGR_OFFSET) -#define SAM_USART0_FIDI (SAM_USART0_BASE+SAM_USART_FIDI_OFFSET) -#define SAM_USART0_NER (SAM_USART0_BASE+SAM_USART_NER_OFFSET) -#define SAM_USART0_IF (SAM_USART0_BASE+SAM_USART_IF_OFFSET) -#define SAM_USART0_MAN (SAM_USART0_BASE+SAM_USART_MAN_OFFSET) -#define SAM_USART0_WPMR (SAM_USART0_BASE+SAM_USART_WPMR_OFFSET) -#define SAM_USART0_WPSR (SAM_USART0_BASE+SAM_USART_WPSR_OFFSET) -#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_USART_VERSION_OFFSET) - -#define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART1_MR_ (SAM_USART1_BASE+SAM_UART_MR_OFFSET) -#define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET) -#define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET) -#define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET) -#define SAM_USART1_SR (SAM_USART1_BASE+SAM_UART_SR_OFFSET) -#define SAM_USART1_RHR (SAM_USART1_BASE+SAM_UART_RHR_OFFSET) -#define SAM_USART1_THR (SAM_USART1_BASE+SAM_UART_THR_OFFSET) -#define SAM_USART1_BRGR (SAM_USART1_BASE+SAM_UART_BRGR_OFFSET) -#define SAM_USART1_RTOR (SAM_USART1_BASE+SAM_USART_RTOR_OFFSET) -#define SAM_USART1_TTGR (SAM_USART1_BASE+SAM_USART_TTGR_OFFSET) -#define SAM_USART1_FIDI (SAM_USART1_BASE+SAM_USART_FIDI_OFFSET) -#define SAM_USART1_NER (SAM_USART1_BASE+SAM_USART_NER_OFFSET) -#define SAM_USART1_IF (SAM_USART1_BASE+SAM_USART_IF_OFFSET) -#define SAM_USART1_MAN (SAM_USART1_BASE+SAM_USART_MAN_OFFSET) -#define SAM_USART1_WPMR (SAM_USART1_BASE+SAM_USART_WPMR_OFFSET) -#define SAM_USART1_WPSR (SAM_USART1_BASE+SAM_USART_WPSR_OFFSET) -#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_USART_VERSION_OFFSET) - -#define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART2_MR_ (SAM_USART2_BASE+SAM_UART_MR_OFFSET) -#define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET) -#define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET) -#define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET) -#define SAM_USART2_SR (SAM_USART2_BASE+SAM_UART_SR_OFFSET) -#define SAM_USART2_RHR (SAM_USART2_BASE+SAM_UART_RHR_OFFSET) -#define SAM_USART2_THR (SAM_USART2_BASE+SAM_UART_THR_OFFSET) -#define SAM_USART2_BRGR (SAM_USART2_BASE+SAM_UART_BRGR_OFFSET) -#define SAM_USART2_RTOR (SAM_USART2_BASE+SAM_USART_RTOR_OFFSET) -#define SAM_USART2_TTGR (SAM_USART2_BASE+SAM_USART_TTGR_OFFSET) -#define SAM_USART2_FIDI (SAM_USART2_BASE+SAM_USART_FIDI_OFFSET) -#define SAM_USART2_NER (SAM_USART2_BASE+SAM_USART_NER_OFFSET) -#define SAM_USART2_IF (SAM_USART2_BASE+SAM_USART_IF_OFFSET) -#define SAM_USART2_MAN (SAM_USART2_BASE+SAM_USART_MAN_OFFSET) -#define SAM_USART2_WPMR (SAM_USART2_BASE+SAM_USART_WPMR_OFFSET) -#define SAM_USART2_WPSR (SAM_USART2_BASE+SAM_USART_WPSR_OFFSET) -#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_USART_VERSION_OFFSET) - -#define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART3_MR_ (SAM_USART3_BASE+SAM_UART_MR_OFFSET) -#define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET) -#define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET) -#define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET) -#define SAM_USART3_SR (SAM_USART3_BASE+SAM_UART_SR_OFFSET) -#define SAM_USART3_RHR (SAM_USART3_BASE+SAM_UART_RHR_OFFSET) -#define SAM_USART3_THR (SAM_USART3_BASE+SAM_UART_THR_OFFSET) -#define SAM_USART3_BRGR (SAM_USART3_BASE+SAM_UART_BRGR_OFFSET) -#define SAM_USART3_RTOR (SAM_USART3_BASE+SAM_USART_RTOR_OFFSET) -#define SAM_USART3_TTGR (SAM_USART3_BASE+SAM_USART_TTGR_OFFSET) -#define SAM_USART3_FIDI (SAM_USART3_BASE+SAM_USART_FIDI_OFFSET) -#define SAM_USART3_NER (SAM_USART3_BASE+SAM_USART_NER_OFFSET) -#define SAM_USART3_IF (SAM_USART3_BASE+SAM_USART_IF_OFFSET) -#define SAM_USART3_MAN (SAM_USART3_BASE+SAM_USART_MAN_OFFSET) -#define SAM_USART3_WPMR (SAM_USART3_BASE+SAM_USART_WPMR_OFFSET) -#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_USART_WPSR_OFFSET) -#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_USART_VERSION_OFFSET) - -/* UART register bit definitions ****************************************************************/ - -/* UART Control Register */ - -#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver (Common) */ -#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter (Common) */ -#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable (Common) */ -#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable (Common) */ -#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable (Common) */ -#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable (Common) */ -#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */ -#define USART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART only) */ -#define USART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART only) */ -#define USART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART only) */ -#define USART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART only) */ -#define USART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART only) */ -#define USART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */ -#define USART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */ -#define USART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */ -#define USART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART only) */ -#define USART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */ -#define USART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART only) */ - -/* UART Mode Register */ - -#define USART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */ -#define USART_MR_MODE_MASK (15 << USART_MR_MODE_SHIFT) -# define USART_MR_MODE_NORMAL (0 << USART_MR_MODE_SHIFT) /* Normal */ -# define USART_MR_MODE_RS485 (1 << USART_MR_MODE_SHIFT) /* RS485 */ -# define USART_MR_MODE_HWHS (2 << USART_MR_MODE_SHIFT) /* Hardware Handshaking */ -# define USART_MR_MODE_ISO7816_0 (4 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ -# define USART_MR_MODE_ISO7816_1 (6 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ -# define USART_MR_MODE_IRDA (8 << USART_MR_MODE_SHIFT) /* IrDA */ -# define USART_MR_MODE_SPIMSTR (14 << USART_MR_MODE_SHIFT) /* SPI Master */ -# define USART_MR_MODE_SPISLV (15 << USART_MR_MODE_SHIFT) /* SPI Slave */ -#define USART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */ -#define USART_MR_USCLKS_MASK (3 << USART_MR_USCLKS_SHIFT) -# define USART_MR_USCLKS_MCK (0 << USART_MR_USCLKS_SHIFT) /* MCK */ -# define USART_MR_USCLKS_MCKDIV (1 << USART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ -# define USART_MR_USCLKS_SCK (3 << USART_MR_USCLKS_SHIFT) /* SCK */ -#define USART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */ -#define USART_MR_CHRL_MASK (3 << USART_MR_CHRL_SHIFT) -# define USART_MR_CHRL_5BITS (0 << USART_MR_CHRL_SHIFT) /* 5 bits */ -# define USART_MR_CHRL_6BITS (1 << USART_MR_CHRL_SHIFT) /* 6 bits */ -# define USART_MR_CHRL_7BITS (2 << USART_MR_CHRL_SHIFT) /* 7 bits */ -# define USART_MR_CHRL_8BITS (3 << USART_MR_CHRL_SHIFT) /* 8 bits */ -#define USART_MR_YNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */ -#define USART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART only) */ -#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */ -#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) -# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */ -# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity (Common) */ -# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (Common) */ -# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */ -# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */ -# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */ -#define USART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */ -#define USART_MR_NBSTOP_MASK (3 << USART_MR_NBSTOP_SHIFT) -# define USART_MR_NBSTOP_1 (0 << USART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ -# define USART_MR_NBSTOP_1p5 (1 << USART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ -# define USART_MR_NBSTOP_2 (2 << USART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ -#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */ -#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) -# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ -# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ -# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ -# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ -#define USART_MR_MSBF (1 << 16) /* Bit 16: Bit Order or SPI Clock Polarity (USART only) */ -#define USART_MR_CPOL (1 << 16) -#define USART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */ -#define USART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */ -#define USART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */ -#define USART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */ -#define USART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */ -#define USART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */ -#define USART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */ -#define USART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */ -#define USART_MR_MAXITER_MASK (7 << USART_MR_MAXITER_SHIFT) -#define USART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */ -#define USART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */ -#define USART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */ -#define USART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */ - -/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask - * Register, and UART Status Register common bit field definitions - */ - -#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */ -#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt (Common) */ -#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */ -#define UART_INT_ENDRX (1 << 3) /* Bit 3: End of Receive Transfer Interrupt (Common) */ -#define UART_INT_ENDTX (1 << 4) /* Bit 4: End of Transmit Interrupt (Common) */ -#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt (Common) */ -#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt (Common) */ -#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt (Common) */ -#define USART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */ -#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */ -#define USART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */ -#define USART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART only) */ -#define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */ -#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */ -#define USART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */ -#define USART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */ -#define USART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */ - -/* UART Receiver Holding Register */ - -#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-7: Received Character (UART only) */ -#define UART_RHR_RXCHR_MASK (0xff << UART_RHR_RXCHR_SHIFT) -#define USART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character (USART only) */ -#define USART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT) -#define USART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync (USART only) */ - -/* UART Transmit Holding Register */ - -#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-7: Character to be Transmitted (UART only) */ -#define UART_THR_TXCHR_MASK (0xff << UART_THR_TXCHR_SHIFT) -#define USART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted (USART only) */ -#define USART_THR_TXCHR_MASK (0x1ff << USART_THR_TXCHR_SHIFT) -#define USART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */ - -/* UART Baud Rate Generator Register */ - -#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor (Common) */ -#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT) -#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part (USART only) */ -#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT) - -/* USART Receiver Time-out Register (USART only) */ - -#define USART_RTOR_TO_SHIFT (0) /* Bits 0-15: Time-out Value (USART only) */ -#define USART_RTOR_TO_MASK (0xffff << USART_RTOR_TO_SHIFT) - -/* USART Transmitter Timeguard Register (USART only) */ - -#define USART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value (USART only) */ -#define USART_TTGR_TG_MASK (0xff << USART_TTGR_TG_SHIFT) - -/* USART FI DI RATIO Register (USART only) */ - -#define USART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value (USART only) */ -#define USART_FIDI_RATIO_MASK (0x7ff << USART_FIDI_RATIO_SHIFT) - -/* USART Number of Errors Register (USART only) */ - -#define USART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors (USART only) */ -#define USART_NER_NBERRORS_MASK (0xff << USART_NER_NBERRORS_SHIFT) - -/* USART IrDA FILTER Register (USART only) */ - -#define USART_IF_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter (USART only) */ -#define USART_IF_IRDAFILTER_MASK (0xff << USART_IF_IRDAFILTER_SHIFT) - -/* USART Manchester Configuration Register (USART only) */ - -#define USART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length (USART only) */ -#define USART_MAN_TXPL_MASK (15 << USART_MAN_TXPL_SHIFT) -#define USART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern (USART only) */ -#define USART_MAN_TXPP_MASK (3 << USART_MAN_TXPP_SHIFT) -# define USART_MAN_TXPP_ALLONE (0 << USART_MAN_TXPP_SHIFT) /* ALL_ONE */ -# define USART_MAN_TXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */ -# define USART_MAN_TXPP_ZEROONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */ -# define USART_MAN_TXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */ -#define USART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ -#define USART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ -#define USART_MAN_RXPL_MASK (15 << USART_MAN_RXPL_SHIFT) -#define USART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */ -#define USART_MAN_RXPP_MASK (3 << USART_MAN_RXPP_SHIFT) -# define USART_MAN_RXPP_ALLONE (0 << USART_MAN_RXPP_SHIFT) /* ALL_ONE */ -# define USART_MAN_RXPP_ALLZERO (1 << USART_MAN_RXPP_SHIFT) /* ALL_ZERO */ -# define USART_MAN_RXPP_ZEROONE (2 << USART_MAN_RXPP_SHIFT) /* ZERO_ONE */ -# define USART_MAN_RXPP_ONEZERO (3 << USART_MAN_RXPP_SHIFT) /* ONE_ZERO */ -#define USART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ -#define USART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ - -/* USART Write Protect Mode Register (USART only) */ - -#define USART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */ -#define USART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */ -#define USART_WPMR_WPKEY_MASK (0x00ffffff << USART_WPMR_WPKEY_SHIFT) - -/* USART Write Protect Status Register (USART only) */ - -#define USART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */ -#define USART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */ -#define USART_WPSR_WPVSRC_MASK (0xffff << USART_WPSR_WPVSRC_SHIFT) - -/* USART Version Register */ - -#define USART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number (USART only) */ -#define USART_VERSION_VERSION_MASK (0xfff << USART_VERSION_VERSION_SHIFT) -#define USART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */ -#define USART_VERSION_MFN_MASK (7 << USART_VERSION_MFN_SHIFT) - -/************************************************************************************************ - * Public Types - ************************************************************************************************/ - -/************************************************************************************************ - * Public Data - ************************************************************************************************/ - -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H */ diff --git a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c index 374e4868a7..71d918b8c2 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c +++ b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c @@ -49,11 +49,11 @@ #include "up_internal.h" #include "sam_clockconfig.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam3u_eefc.h" -#include "chip/sam_wdt.h" +#include "chip/sam3u_wdt.h" #include "chip/sam3u_supc.h" -#include "chip/sam_matrix.h" +#include "chip/sam3u_matrix.h" /**************************************************************************** * Pre-processor Definitions @@ -63,21 +63,22 @@ * in board.h */ -#define CKGR_MOR_KEY (0x37 << CKGR_MOR_KEY_SHIFT) -#define SUPR_CR_KEY (0xa5 << SUPC_CR_KEY_SHIFT) +#define BOARD_CKGR_MOR (PMC_CKGR_MOR_KEY | BOARD_CKGR_MOR_MOSCXTST | \ + PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN) -#define BOARD_CKGR_MOR (CKGR_MOR_KEY|BOARD_CKGR_MOR_MOSCXTST|\ - CKGR_MOR_MOSCRCEN|CKGR_MOR_MOSCXTEN) - -#define BOARD_CKGR_PLLAR (CKGR_PLLAR_ONE|BOARD_CKGR_PLLAR_MULA|\ - BOARD_CKGR_PLLAR_STMODE|BOARD_CKGR_PLLAR_PLLACOUNT|\ - BOARD_CKGR_PLLAR_DIVA) - -#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES|PMC_MCKR_CSS_MAIN) -#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES|BOARD_PMC_MCKR_CSS) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ + BOARD_CKGR_PLLAR_STMODE | BOARD_CKGR_PLLAR_COUNT | \ + BOARD_CKGR_PLLAR_DIV) +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ + BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV) +#endif -#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT|CKGR_UCKR_UPLLEN) +#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES | PMC_MCKR_CSS_MAIN) +#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES | BOARD_PMC_MCKR_CSS) +#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN) /**************************************************************************** * Public Data @@ -101,8 +102,8 @@ static inline void sam_efcsetup(void) { - putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM_EEFC0_FMR); - putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM_EEFC1_FMR); + putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC0_FMR); + putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC1_FMR); } /**************************************************************************** @@ -170,7 +171,7 @@ static inline void sam_pmcsetup(void) /* Enable main oscillator (if it has not already been selected) */ - if ((getreg32(SAM_CKGR_MOR) & CKGR_MOR_MOSCSEL) == 0) + if ((getreg32(SAM_PMC_CKGR_MOR) & PMC_CKGR_MOR_MOSCSEL) == 0) { /* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to * enable the main oscillator, the MOSCXTS bit in the Power Management @@ -180,7 +181,7 @@ static inline void sam_pmcsetup(void) * indicating that the main clock is valid." */ - putreg32(BOARD_CKGR_MOR, SAM_CKGR_MOR); + putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR); sam_pmcwait(PMC_INT_MOSCXTS); } @@ -196,7 +197,7 @@ static inline void sam_pmcsetup(void) * 1 = Selection is in progress */ - putreg32((BOARD_CKGR_MOR|CKGR_MOR_MOSCSEL), SAM_CKGR_MOR); + putreg32((BOARD_CKGR_MOR | PMC_CKGR_MOR_MOSCSEL), SAM_PMC_CKGR_MOR); sam_pmcwait(PMC_INT_MOSCSELS); /* "Select the master clock. "The Master Clock selection is made by writing @@ -214,17 +215,17 @@ static inline void sam_pmcsetup(void) putreg32(regval, SAM_PMC_MCKR); sam_pmcwait(PMC_INT_MCKRDY); - /* Settup PLLA and wait for LOCKA */ + /* Setup PLLA and wait for LOCKA */ - putreg32(BOARD_CKGR_PLLAR, SAM_CKGR_PLLAR); + putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR); sam_pmcwait(PMC_INT_LOCKA); /* Setup UTMI for USB and wait for LOCKU */ #ifdef CONFIG_USBDEV - regval = getreg32(SAM_CKGR_UCKR); + regval = getreg32(SAM_PMC_CKGR_UCKR); regval |= BOARD_CKGR_UCKR; - putreg32(regval, SAM_CKGR_UCKR); + putreg32(regval, SAM_PMC_CKGR_UCKR); sam_pmcwait(PMC_INT_LOCKU); #endif diff --git a/nuttx/arch/arm/src/sam34/sam3u_gpio.c b/nuttx/arch/arm/src/sam34/sam3u_gpio.c index 271bb2f9b1..a59878a3d1 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_gpio.c +++ b/nuttx/arch/arm/src/sam34/sam3u_gpio.c @@ -1,5 +1,6 @@ /**************************************************************************** * arch/arm/src/sam34/sam3u_gpio.c + * General Purpose Input/Output (GPIO) logic for the SAM3U and SAM4S * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -52,7 +53,14 @@ #include "chip.h" #include "sam_gpio.h" -#include "chip/sam_pio.h" + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "chip/sam3u_pio.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_pio.h" +#else +# error Unrecognized SAM architecture +#endif /**************************************************************************** * Definitions @@ -111,6 +119,10 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset) static inline int sam_configinput(uintptr_t base, uint32_t pin, gpio_pinset_t cfgset) { +#ifdef GPIO_HAVE_SCHMITT + uint32_t regval; +#endif + /* Disable interrupts on the pin */ putreg32(pin, base + SAM_PIO_IDR_OFFSET); @@ -126,6 +138,19 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin, putreg32(pin, base + SAM_PIO_PUDR_OFFSET); } +#ifdef GPIO_HAVE_PULLDOWN + /* Enable/disable the pull-down as requested */ + + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + putreg32(pin, base + SAM_PIO_PPDER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); + } +#endif + /* Check if filtering should be enabled */ if ((cfgset & GPIO_CFG_DEGLITCH) != 0) @@ -137,14 +162,29 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin, putreg32(pin, base + SAM_PIO_IFDR_OFFSET); } +#ifdef GPIO_HAVE_SCHMITT + /* Enable/disable the Schmitt trigger */ + + regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET); + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + regval |= pin; + } + else + { + regval &= ~pin; + } + putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET); +#endif + /* Configure the pin as an input and enable the GPIO function */ putreg32(pin, base + SAM_PIO_ODR_OFFSET); putreg32(pin, base + SAM_PIO_PER_OFFSET); /* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and - * registers. This would probably best be done with another, new - * API... perhaps sam_configfilter() + * IFDGSR registers. This would probably best be done with + * another, new API... perhaps sam_configfilter() */ return OK; @@ -176,6 +216,19 @@ static inline int sam_configoutput(uintptr_t base, uint32_t pin, putreg32(pin, base + SAM_PIO_PUDR_OFFSET); } +#ifdef GPIO_HAVE_PULLDOWN + /* Enable/disable the pull-down as requested */ + + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + putreg32(pin, base + SAM_PIO_PPDER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); + } +#endif + /* Enable the open drain driver if requrested */ if ((cfgset & GPIO_CFG_OPENDRAIN) != 0) @@ -234,7 +287,58 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, putreg32(pin, base + SAM_PIO_PUDR_OFFSET); } - /* Configure pin, depending upon the peripheral A or B*/ +#ifdef GPIO_HAVE_PULLDOWN + /* Enable/disable the pull-down as requested */ + + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + putreg32(pin, base + SAM_PIO_PPDER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); + } +#endif + +#ifdef GPIO_HAVE_PERIPHCD + /* Configure pin, depending upon the peripheral A, B, C or D + * + * PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0 + * PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0 + * PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1 + * PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1 + */ + + regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET); + if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA || + (cfgset & GPIO_MODE_MASK) == GPIO_PERIPHC) + { + regval &= ~pin; + } + else + { + regval |= pin; + } + putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET); + + regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET); + if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA || + (cfgset & GPIO_MODE_MASK) == GPIO_PERIPHB) + { + regval &= ~pin; + } + else + { + regval |= pin; + } + putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET); + +#else + /* Configure pin, depending upon the peripheral A or B: + * + * PERIPHA: ABSR[n] = 0 + * PERIPHB: ABSR[n] = 1 + */ regval = getreg32(base + SAM_PIO_ABSR_OFFSET); if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA) @@ -246,6 +350,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, regval |= pin; } putreg32(regval, base + SAM_PIO_ABSR_OFFSET); +#endif /* Disable PIO functionality */ @@ -375,11 +480,17 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n", getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET), getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET)); - lldbg(" PUSR: %08x ABSR: %08x SCIFSR: %08x DIFSR: %08x\n", - getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_ABSR_OFFSET), - getreg32(base + SAM_PIO_SCIFSR_OFFSET), getreg32(base + SAM_PIO_DIFSR_OFFSET)); - lldbg(" IFDGSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n", - getreg32(base + SAM_PIO_IFDGSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), +#if defined(CONFIG_ARCH_CHIP_ATSAM3U) + lldbg(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n", + getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET), + getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET)); +#elif defined(CONFIG_ARCH_CHIP_ATSAM4S) + lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n", + getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET), + getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIOC_PPDSR)); +#endif + lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n", + getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET)); lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n", getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET), @@ -387,6 +498,13 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n", getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET), getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET)); +#if defined(CONFIG_ARCH_CHIP_ATSAM4S) + lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n", + getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET), + getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET)); + lldbg("SCHMITT: %08x\n", + getreg32(base + SAM_PIO_SCHMITT_OFFSET)); +#endif irqrestore(flags); return OK; } diff --git a/nuttx/arch/arm/src/sam34/sam3u_gpio.h b/nuttx/arch/arm/src/sam34/sam3u_gpio.h index 7a9fea1ca1..84f5430567 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_gpio.h +++ b/nuttx/arch/arm/src/sam34/sam3u_gpio.h @@ -1,5 +1,6 @@ /************************************************************************************ * arch/arm/src/sam34/sam3u_gpio.h + * General Purpose Input/Output (GPIO) definitions for the SAM3U * * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -45,16 +46,22 @@ /************************************************************************************ * Definitions ************************************************************************************/ +/* Configuration ********************************************************************/ + +#undef GPIO_HAVE_PULLDOWN +#undef GPIO_HAVE_PERIPHCD +#undef GPIO_HAVE_SCHMITT /* Bit-encoded input to sam_configgpio() ********************************************/ /* 16-bit Encoding: - * MMCC CII. VPPB BBBB + * + * MMCC CII. VPPB BBBB */ /* Input/Output mode: * - * MM.. .... .... .... + * MM.. .... .... .... */ #define GPIO_MODE_SHIFT (14) /* Bits 14-15: GPIO mode */ @@ -65,7 +72,8 @@ # define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */ /* These bits set the configuration of the pin: - * ..CC C... .... .... + * + * ..CC C... .... .... */ #define GPIO_CFG_SHIFT (11) /* Bits 11-13: GPIO configuration bits */ @@ -76,10 +84,11 @@ # define GPIO_CFG_OPENDRAIN (4 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */ /* Additional interrupt modes: - * .... .II. .... .... + * + * .... .II. .... .... */ -#define GPIO_INT_SHIFT (9) /* Bits 9-10: GPIO configuration bits */ +#define GPIO_INT_SHIFT (9) /* Bits 9-10: GPIO interrupt bits */ #define GPIO_INT_MASK (3 << GPIO_INT_SHIFT) # define GPIO_INT_LEVEL (1 << 10) /* Bit 10: Level detection interrupt */ # define GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */ @@ -89,14 +98,16 @@ # define GPIO_INT_FALLING (0) /* (vs. Falling edge detection interrupt) */ /* If the pin is an GPIO output, then this identifies the initial output value: - * .... .... V... .... + * + * .... .... V... .... */ #define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */ #define GPIO_OUTPUT_CLEAR (0) /* This identifies the GPIO port: - * .... .... .PP. .... + * + * .... .... .PP. .... */ #define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */ @@ -106,10 +117,11 @@ # define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT) /* This identifies the bit in the port: - * .... .... ...B BBBB + * + * .... .... ...B BBBB */ -#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ #define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) #define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) #define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) diff --git a/nuttx/arch/arm/src/sam34/sam3u_periphclks.h b/nuttx/arch/arm/src/sam34/sam3u_periphclks.h new file mode 100644 index 0000000000..09c1abb4d2 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam3u_periphclks.h @@ -0,0 +1,149 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam3u_periphclks.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H +#define __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include +#include "chip/sam3u_pmc.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helper macros */ + +#define sam_enableperipheral(s) putreg32((1 << (s)), SAM_PMC_PCER) +#define sam_disableperipheral(s) putreg32((1 << (s)), SAM_PMC_PDER) + +#define sam_supc_enableclk() sam_enableperipheral(SAM_PID_SUPC) +#define sam_rstc_enableclk() sam_enableperipheral(SAM_PID_RSTC) +#define sam_rtc_enableclk() sam_enableperipheral(SAM_PID_RTC) +#define sam_rtt_enableclk() sam_enableperipheral(SAM_PID_RTT) +#define sam_wdt_enableclk() sam_enableperipheral(SAM_PID_WDT) +#define sam_pmc_enableclk() sam_enableperipheral(SAM_PID_PMC) +#define sam_eefc0_enableclk() sam_enableperipheral(SAM_PID_EEFC0) +#define sam_eefc1_enableclk() sam_enableperipheral(SAM_PID_EEFC1) +#define sam_uart0_enableclk() sam_enableperipheral(SAM_PID_UART0) +#define sam_smc_enableclk() sam_enableperipheral(SAM_PID_SMC) +#define sam_pioa_enableclk() sam_enableperipheral(SAM_PID_PIOA) +#define sam_piob_enableclk() sam_enableperipheral(SAM_PID_PIOB) +#define sam_pioc_enableclk() sam_enableperipheral(SAM_PID_PIOC) +#define sam_usart0_enableclk() sam_enableperipheral(SAM_PID_USART0) +#define sam_usart1_enableclk() sam_enableperipheral(SAM_PID_USART1) +#define sam_usart2_enableclk() sam_enableperipheral(SAM_PID_USART2) +#define sam_usart3_enableclk() sam_enableperipheral(SAM_PID_USART3) +#define sam_hsmci_enableclk() sam_enableperipheral(SAM_PID_HSMCI) +#define sam_twi0_enableclk() sam_enableperipheral(SAM_PID_TWI0) +#define sam_twi1_enableclk() sam_enableperipheral(SAM_PID_TWI1) +#define sam_spi_enableclk() sam_enableperipheral(SAM_PID_SPI) +#define sam_ssc_enableclk() sam_enableperipheral(SAM_PID_SSC) +#define sam_tc0_enableclk() sam_enableperipheral(SAM_PID_TC0) +#define sam_tc1_enableclk() sam_enableperipheral(SAM_PID_TC1) +#define sam_tc2_enableclk() sam_enableperipheral(SAM_PID_TC2) +#define sam_pwm_enableclk() sam_enableperipheral(SAM_PID_PWM) +#define sam_adc12b_enableclk() sam_enableperipheral(SAM_PID_ADC12B) +#define sam_dmac_enableclk() sam_enableperipheral(SAM_PID_DMAC) +#define sam_udphs_enableclk() sam_enableperipheral(SAM_PID_UDPHS) + +#define sam_supc_disableclk() sam_disableperipheral(SAM_PID_SUPC) +#define sam_rstc_disableclk() sam_disableperipheral(SAM_PID_RSTC) +#define sam_rtc_disableclk() sam_disableperipheral(SAM_PID_RTC) +#define sam_rtt_disableclk() sam_disableperipheral(SAM_PID_RTT) +#define sam_wdt_disableclk() sam_disableperipheral(SAM_PID_WDT) +#define sam_pmc_disableclk() sam_disableperipheral(SAM_PID_PMC) +#define sam_eefc0_disableclk() sam_disableperipheral(SAM_PID_EEFC0) +#define sam_eefc1_disableclk() sam_disableperipheral(SAM_PID_EEFC1) +#define sam_uart0_disableclk() sam_disableperipheral(SAM_PID_UART0) +#define sam_smc_disableclk() sam_disableperipheral(SAM_PID_SMC) +#define sam_pioa_disableclk() sam_disableperipheral(SAM_PID_PIOA) +#define sam_piob_disableclk() sam_disableperipheral(SAM_PID_PIOB) +#define sam_pioc_disableclk() sam_disableperipheral(SAM_PID_PIOC) +#define sam_usart0_disableclk() sam_disableperipheral(SAM_PID_USART0) +#define sam_usart1_disableclk() sam_disableperipheral(SAM_PID_USART1) +#define sam_usart2_disableclk() sam_disableperipheral(SAM_PID_USART2) +#define sam_usart3_disableclk() sam_disableperipheral(SAM_PID_USART3) +#define sam_hsmci_disableclk() sam_disableperipheral(SAM_PID_HSMCI) +#define sam_twi0_disableclk() sam_disableperipheral(SAM_PID_TWI0) +#define sam_twi1_disableclk() sam_disableperipheral(SAM_PID_TWI1) +#define sam_spi_disableclk() sam_disableperipheral(SAM_PID_SPI) +#define sam_ssc_disableclk() sam_disableperipheral(SAM_PID_SSC) +#define sam_tc0_disableclk() sam_disableperipheral(SAM_PID_TC0) +#define sam_tc1_disableclk() sam_disableperipheral(SAM_PID_TC1) +#define sam_tc2_disableclk() sam_disableperipheral(SAM_PID_TC2) +#define sam_pwm_disableclk() sam_disableperipheral(SAM_PID_PWM) +#define sam_adc12b_disableclk() sam_disableperipheral(SAM_PID_ADC12B) +#define sam_dmac_disableclk() sam_disableperipheral(SAM_PID_DMAC) +#define sam_udphs_disableclk() sam_disableperipheral(SAM_PID_UDPHS) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H */ diff --git a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c index 2857c7fb10..59bd62bf09 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c +++ b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c @@ -41,6 +41,9 @@ #include +#include +#include + #include #include @@ -48,24 +51,390 @@ #include "up_internal.h" #include "chip/sam4l_pm.h" +#include "chip/sam4l_scif.h" +#include "chip/sam4l_bpm.h" +#include "chip/sam4l_bscif.h" #include "chip/sam4l_flashcalw.h" +#include "sam4l_periphclks.h" #include "sam_clockconfig.h" /**************************************************************************** - * Private Definitions + * Pre-processor Definitions ****************************************************************************/ +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_RAMFUNCS +# error "CONFIG_ARCH_RAMFUNCS must be defined" +#endif + +/* Board/Clock Setup *******************************************************/ +/* Verify dividers */ + +#if ((BOARD_CPU_SHIFT > BOARD_PBA_SHIFT) || (BOARD_CPU_SHIFT > BOARD_PBB_SHIFT) || \ + (BOARD_CPU_SHIFT > BOARD_PBC_SHIFT) || (BOARD_CPU_SHIFT > BOARD_PBD_SHIFT)) +# error BOARD_PBx_SHIFT must be greater than or equal to BOARD_CPU_SHIFT +#endif + +/* Nominal frequencies in on-chip RC oscillators. These may frequencies + * may vary with temperature changes. + */ + +#define SAM_RCSYS_FREQUENCY 115000 /* Nominal frequency of RCSYS (Hz) */ +#define SAM_RC32K_FREQUENCY 32768 /* Nominal frequency of RC32K (Hz) */ +#define SAM_RC80M_FREQUENCY 80000000 /* Nominal frequency of RC80M (Hz) */ +#define SAM_RCFAST4M_FREQUENCY 4000000 /* Nominal frequency of RCFAST4M (Hz) */ +#define SAM_RCFAST8M_FREQUENCY 8000000 /* Nominal frequency of RCFAST8M (Hz) */ +#define SAM_RCFAST12M_FREQUENCY 12000000 /* Nominal frequency of RCFAST12M (Hz) */ +#define SAM_RC1M_FREQUENCY 1000000 /* Nominal frequency of RC1M (Hz) */ + +/* Oscillator 0. This might be the system clock or the source clock for + * either PLL0 or DFPLL. It might also be needed if OSC0 is the source + * clock for GCLK9. + * + * By selecting CONFIG_SAM34_OSC0, you can also force the clock to be enabled + * at boot time. + */ + +#if defined(CONFIG_SAM34_OSC0) || defined(BOARD_SYSCLK_SOURCE_OSC0) || \ + defined(BOARD_DFLL0_SOURCE_OSC0) || defined(BOARD_PLL0_SOURCE_OSC0) || \ + defined(BOARD_GLCK9_SOURCE_OSC0) +# define NEED_OSC0 1 +#endif + +#ifdef NEED_OSC0 +# if !defined(BOARD_OSC0_STARTUP_US) +# error BOARD_OSC0_STARTUP_US is not defined +# elif BOARD_OSC0_STARTUP_US == 0 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_0 +# define SAM_OSC0_STARTUP_TIMEOUT 8 +# elif BOARD_OSC0_STARTUP_US <= 557 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_64 +# define SAM_OSC0_STARTUP_TIMEOUT 80 +# elif BOARD_OSC0_STARTUP_US <= 1100 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_128 +# define SAM_OSC0_STARTUP_TIMEOUT 160 +# elif BOARD_OSC0_STARTUP_US <= 18000 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_2K +# define SAM_OSC0_STARTUP_TIMEOUT 2560 +# elif BOARD_OSC0_STARTUP_US <= 36000 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_4K +# define SAM_OSC0_STARTUP_TIMEOUT 5120 +# elif BOARD_OSC0_STARTUP_US <= 71000 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_8K +# define SAM_OSC0_STARTUP_TIMEOUT 10240 +# elif BOARD_OSC0_STARTUP_US <= 143000 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_16K +# define SAM_OSC0_STARTUP_TIMEOUT 20480 +# elif BOARD_OSC0_STARTUP_US <= 285000 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_32K +# define SAM_OSC0_STARTUP_TIMEOUT 40960 +# else +# error BOARD_OSC0_STARTUP_US is out of range +# endif + +# ifdef BOARD_OSC0_ISXTAL +# define SAM_OSC0_MODE_VALUE SCIF_OSCCTRL0_MODE +# if BOARD_OSC0_FREQUENCY < 2000000 +# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(0) +# elif BOARD_OSC0_FREQUENCY < 4000000 +# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(1) +# elif BOARD_OSC0_FREQUENCY < 8000000 +# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(2) +# elif BOARD_OSC0_FREQUENCY < 16000000 +# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(3) +# else +# define SAM_OSC0_GAIN_VALUE ((0x1u << 4) | SCIF_OSCCTRL0_GAIN(0)) +# endif +# else +# define SAM_OSC0_MODE_VALUE 0 +# define SAM_OSC0_GAIN_VALUE 0 +# endif +#endif + +/* OSC32. The 32K oscillator may be the source clock for DFPLL0 or + * the source clock for GLK9 that might be used to driver PLL0. + * + * By selecting CONFIG_SAM34_OSC32K, you can also force the clock to be + * enabled at boot time. OSC32 may needed by other devices as well + * (AST, WDT, PICUART, RTC). + */ + +#if defined(CONFIG_SAM34_OSC32K) || defined(BOARD_DFLL0_SOURCE_OSC32K) || \ + defined(BOARD_GLCK9_SOURCE_OSC32K) +# define NEED_OSC32K 1 +#endif -#if defined(SAM_CLOCK_OSC0) || \ - (defined (SAM_CLOCK_PLL0) && defined(SAM_CLOCK_PLL0_OSC0)) || \ - (defined (SAM_CLOCK_PLL1) && defined(SAM_CLOCK_PLL1_OSC0)) -# define NEED_OSC0 +#ifdef NEED_OSC32K +# if !defined(BOARD_OSC32_STARTUP_US) +# error BOARD_OSC32_STARTUP_US is not defined +# elif BOARD_OSC32_STARTUP_US == 0 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_0 +# elif BOARD_OSC32_STARTUP_US <= 1100 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_128 +# elif BOARD_OSC32_STARTUP_US <= 72300 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_8K +# elif BOARD_OSC32_STARTUP_US <= 143000 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_16K +# elif BOARD_OSC32_STARTUP_US <= 570000 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_64K +# elif BOARD_OSC32_STARTUP_US <= 1100000 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_128K +# elif BOARD_OSC32_STARTUP_US <= 2300000 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_256K +# elif BOARD_OSC32_STARTUP_US <= 4600000 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_512K +# else +# error BOARD_OSC32_STARTUP_US is out of range +# endif + +# ifdef BOARD_OSC32_ISXTAL +# define SAM_OSC32_MODE_VALUE BSCIF_OSCCTRL32_MODE_XTAL +# else +# define SAM_OSC32_MODE_VALUE BSCIF_OSCCTRL32_MODE_EXTCLK +# endif + +# ifndef BOARD_OSC32_SELCURR +# define BOARD_OSC32_SELCURR BSCIF_OSCCTRL32_SELCURR_300 +# endif #endif -#if defined(SAM_CLOCK_OSC1) || \ - (defined (SAM_CLOCK_PLL0) && defined(SAM_CLOCK_PLL0_OSC1)) || \ - (defined (SAM_CLOCK_PLL1) && defined(SAM_CLOCK_PLL1_OSC1)) -# define NEED_OSC1 +/* RC80M. This might be the system clock or the source clock for the DFPLL + * or it could be the source for GCLK9 that drives PLL0. + * + * By selecting CONFIG_SAM34_RC80M, you can also force the clock to be enabled + * at boot time. + */ + +#if defined(CONFIG_SAM34_RC80M) || defined(BOARD_SYSCLK_SOURCE_RC80M) || \ + defined(BOARD_DFLL0_SOURCE_RC80M) || BOARD_GLCK9_SOURCE_RC80M +# define NEED_RC80M 1 +#endif + +/* RCFAST. The 12/8/4 fast RC oscillator may be used as the system clock + * or as the source for GLCK9 that drives PLL0. + * If not then, it may be enabled by setting the CONFIG_SAM34_RCFASTxM + * configuration variable. + */ + +#if defined(CONFIG_SAM34_RCFAST12M) +# undef CONFIG_SAM34_RCFAST8M +# undef CONFIG_SAM34_RCFAST4M +#elif defined(CONFIG_SAM34_RCFAST8M) +# undef CONFIG_SAM34_RCFAST4M +#endif + +#if defined(BOARD_SYSCLK_SOURCE_FCFAST12M) +# if defined(CONFIG_SAM34_RCFAST8M) || defined(CONFIG_SAM34_RCFAST4M) +# error BOARD_SYSCLK_SOURCE_FCFAST12M inconsistent with CONFIG_SAM34_RCFAST8/4M +# endif +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_12MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST12M_FREQUENCY +#elif defined(BOARD_SYSCLK_SOURCE_FCFAST8M) +# if defined(CONFIG_SAM34_RCFAST12M) || defined(CONFIG_SAM34_RCFAST4M) +# error BOARD_SYSCLK_SOURCE_FCFAST8M inconsistent with CONFIG_SAM34_RCFAST12/4M +# endif +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_8MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST8M_FREQUENCY +#elif defined(BOARD_SYSCLK_SOURCE_FCFAST4M) +# if defined(CONFIG_SAM34_RCFAST12M) || defined(CONFIG_SAM34_RCFAST8M) +# error BOARD_SYSCLK_SOURCE_FCFAST4M inconsistent with CONFIG_SAM34_RCFAST12/8M +# endif +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_4MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST4M_FREQUENCY +#elif defined(CONFIG_SAM34_RCFAST12M) +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_12MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST12M_FREQUENCY +#elif defined(CONFIG_SAM34_RCFAST8M) +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_8MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST8M_FREQUENCY +#elif defined(CONFIG_SAM34_RCFAST4M) +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_4MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST4M_FREQUENCY +#endif + +/* RC1M. The 1M RC oscillator may be used as the system block or + * may be the source clock for GLCK9 that drives PLL0 + * + * By selecting CONFIG_SAM34_RC1M, you can also force the clock to be + * enabled at boot time. + */ + +#if defined(CONFIG_SAM34_RC1M) || defined(BOARD_SYSCLK_SOURCE_RC1M) || \ + defined(BOARD_GLCK9_SOURCE_RC1M) +# define NEED_RC1M 1 +#endif + +/* RC32K. The 32KHz RC oscillator may be used as the input to DFLL0 + * or as the input to GCLK9 that drives PLL0. + * + * By selecting CONFIG_SAM34_RC32K, you can also force the clock to be + * enabled at boot time. + */ + +#if defined(CONFIG_SAM34_RC32K) || defined(BOARD_DFLL0_SOURCE_RC32K) || \ + defined(BOARD_GLCK9_SOURCE_RC32K) +# define NEED_RC32K 1 +#endif + +/* GCLK9. May used as a source clock for PLL0 */ + +#ifdef BOARD_PLL0_SOURCE_GCLK9 +# define NEED_GLCK9 1 +#endif + +#ifdef NEED_GLCK9 +# if defined(BOARD_GLCK9_SOURCE_RCSYS) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RCSYS +# define SAM_GCLK9_FREQUENCY SAM_RCSYS_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_OSC32K) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_OSC32K +# define SAM_GCLK9_FREQUENCY BOARD_OSC32_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_DFLL0) +# error BOARD_GLCK9_SOURCE_DFLL0 is not supported +# elif defined(BOARD_GLCK9_SOURCE_OSC0) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_OSC0 +# define SAM_GCLK9_FREQUENCY BOARD_OSC0_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_RC80M) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RC80M +# define SAM_GCLK9_FREQUENCY SAM_RC80M_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_RCFAST) +# error BOARD_GLCK9_SOURCE_RCFAST is not supported (needs RCFAST configuration) +# elif defined(BOARD_GLCK9_SOURCE_RC1M) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RC1M +# define SAM_GCLK9_FREQUENCY SAM_RCFAST_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_CPUCLK) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_CPUCLK +# define SAM_GCLK9_FREQUENCY BOARD_CPU_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_HSBCLK) +# error BOARD_GLCK9_SOURCE_HSBCLK is not supported (REVISIT) +# elif defined(BOARD_GLCK9_SOURCE_PBACLK) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBACLK +# define SAM_GCLK9_FREQUENCY BOARD_PBA_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_PBBCLK) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBBCLK +# define SAM_GCLK9_FREQUENCY BOARD_PBB_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_PBCCLK) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBCCLK +# define SAM_GCLK9_FREQUENCY BOARD_PBC_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_PBDCLK) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBDCLK +# define SAM_GCLK9_FREQUENCY BOARD_PBD_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_RC32K) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RC32K +# define SAM_GCLK9_FREQUENCY SAM_RC32K_FREQUENCY +# else +# error Missing GCLK9 source +# endif +#endif + +/* PLL0 */ + +#ifdef BOARD_SYSCLK_SOURCE_PLL0 +/* PLL0 source */ + +# if defined(BOARD_PLL0_SOURCE_OSC0) +# define SAM_PLL0_SOURCE SCIF_PLL0_PLLOSC_OSC0 +# define SAM_PLL0_SOURCE_FREQUENCY BOARD_OSC0_FREQUENCY +# elif defined(BOARD_PLL0_SOURCE_GCLK9) +# define SAM_PLL0_SOURCE SCIF_PLL0_PLLOSC_GCLK9 +# define SAM_PLL0_SOURCE_FREQUENCY SAM_GCLK9_FREQUENCY +# else +# error Missing PLL0 source +# endif + +/* PLL0 Multipler and Divider */ + +# if !defined(BOARD_PLL0_MUL) +# error BOARD_PLL0_MUL is not defined +# elif BOARD_PLL0_MUL <= 2 || BOARD_PLL0_MUL > 16 +# error BOARD_PLL0_MUL is out of range +# endif + +# if !defined(BOARD_PLL0_DIV) +# error BOARD_PLL0_DIV is not defined +# elif BOARD_PLL0_DIV < 1 || BOARD_PLL0_DIV > 15 +# error BOARD_PLL0_DIV is out of range +# endif + +/* PLL0 frequency ranges */ + +# define SAM_PLL0_MIN_FREQUENCY 40000000 +# define SAM_PLL0_MAX_FREQUENCY 240000000 + +/* PLL0 VCO frequency */ + +# define SAM_PLL0_VCO_DIV1_FREQUENCY \ + (SAM_PLL0_SOURCE_FREQUENCY * BOARD_PLL0_MUL / BOARD_PLL0_DIV) + +# if (SAM_PLL0_VCO_DIV1_FREQUENCY < SAM_PLL0_MIN_FREQUENCY) || \ + (SAM_PLL0_VCO_DIV1_FREQUENCY > SAM_PLL0_MAX_FREQUENCY) +# error PLL0 VCO frequency is out of range +# endif + +/* PLL0 Options: + * + * PLL0 supports an option to divide the frequency output by 2. We + * will do this division to bring the internal VCO frequency up to the + * minimum value + * + * PLL0 operates in two frequency ranges as determined by + * SCIF_PLL0_PLLOPT_FVO: + * + * 0: 80MHz < fvco < 180MHz + * 1: 160MHz < fvco < 240MHz + * + * Select the correct frequncy range using the recommended threshold + * value. + */ + +# if SAM_PLL0_VCO_DIV1_FREQUENCY < (2*SAM_PLL0_MIN_FREQUENCY) && BOARD_PLL0_MUL <= 8 +# define SAM_PLL0_VCO_FREQUENCY (2 * SAM_PLL0_VCO_DIV1_FREQUENCY) +# define SAM_PLL0_MUL (2 * BOARD_PLL0_MUL) + +# if SAM_PLL0_VCO_FREQUENCY > (SAM_PLL0_VCO_RANGE_THRESHOLD / 2) +# define SAM_PLL0_OPTIONS (SCIF_PLL0_PLLOPT_DIV2 | SCIF_PLL0_PLLOPT_FVO) +# else +# define SAM_PLL0_OPTIONS SCIF_PLL0_PLLOPT_DIV2 +# endif + +# else +# define SAM_PLL0_VCO_FREQUENCY SAM_PLL0_VCO_DIV1_FREQUENCY +# define SAM_PLL0_MUL BOARD_PLL0_MUL + +# if SAM_PLL0_VCO_FREQUENCY > SAM_PLL0_VCO_RANGE_THRESHOLD +# define SAM_PLL0_OPTIONS SCIF_PLL0_PLLOPT_FVO +# else +# define SAM_PLL0_OPTIONS 0 +# endif +# endif +#endif + +/* DFLL0 */ + +#ifdef BOARD_SYSCLK_SOURCE_DFLL0 +/* DFLL0 reference clock */ + +# if defined(BOARD_DFLL0_SOURCE_RCSYS) +# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RCSYS +# elif defined(BOARD_DFLL0_SOURCE_OSC32K) +# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_OSC32K +# elif define(BOARD_DFLL0_SOURCE_OSC0) +# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_OSC0 +# elif define(BOARD_DFLL0_SOURCE_RC80M) +# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RC80M +# elif define(BOARD_DFLL0_SOURCE_RC32K) +# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RC32K +# else +# error No DFLL0 source for reference clock defined +# endif + #endif /**************************************************************************** @@ -96,7 +465,7 @@ * ****************************************************************************/ -#ifdef CONFIG_SAM_PICOCACHE +#ifdef CONFIG_SAM34_PICOCACHE static inline void sam_picocache(void) { /* Enable clocking to the PICOCACHE */ @@ -113,231 +482,370 @@ static inline void sam_picocache(void) # define sam_picocache() #endif +/**************************************************************************** + * Name: sam_enableosc0 + * + * Description: + * Initialiaze OSC0 settings per the definitions in the board.h file. + * + ****************************************************************************/ + +#ifdef NEED_OSC0 +static inline void sam_enableosc0(void) +{ + uint32_t regval; + + /* Enable and configure OSC0 */ + + regval = SAM_OSC0_STARTUP_VALUE | SAM_OSC0_GAIN_VALUE | SAM_OSC0_MODE_VALUE | + SCIF_OSCCTRL0_OSCEN; + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_OSCCTRL0_OFFSET), + SAM_SCIF_UNLOCK); + putreg32(regval, SAM_SCIF_OSCCTRL0); + + /* Wait for OSC0 to be ready */ + + while (getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_OSC0RDY) == 0); +} +#endif + /**************************************************************************** * Name: sam_enableosc32 * * Description: - * Initialiaze the 32KHz oscillator. This oscillator is used by the RTC - * logic to provide the sysem timer. + * Initialiaze the 32KHz oscillator per settings in the board.h header + * file. * ****************************************************************************/ -#ifdef SAM_CLOCK_OSC32 +#ifdef NEED_OSC32K static inline void sam_enableosc32(void) { uint32_t regval; - /* Select the 32KHz oscillator crystal */ + /* Set up the OSCCTRL32 register using settings from the board.h file. + * Also enable the oscillator and provide bother the 32KHz and 1KHz output. + */ - regval = getreg32(SAM_PM_OSCCTRL32); - regval &= ~PM_OSCCTRL32_MODE_MASK; - regval |= PM_OSCCTRL32_MODE_XTAL; - putreg32(regval, SAM_PM_OSCCTRL32); + regval = SAM_OSC32_STARTUP_VALUE | BOARD_OSC32_SELCURR | SAM_OSC32_MODE_VALUE | + BSCIF_OSCCTRL32_EN1K | BSCIF_OSCCTRL32_EN32K | + BSCIF_OSCCTRL32_OSC32EN; - /* Enable the 32-kHz clock */ + putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_OSCCTRL32_OFFSET), + SAM_BSCIF_UNLOCK); + putreg32(regval, SAM_BSCIF_OSCCTRL32); - regval = getreg32(SAM_PM_OSCCTRL32); - regval &= ~PM_OSCCTRL32_STARTUP_MASK; - regval |= PM_OSCCTRL32_EN|(SAM_OSC32STARTUP << PM_OSCCTRL32_STARTUP_SHIFT); - putreg32(regval, SAM_PM_OSCCTRL32); + /* Wait for OSC32 to be ready */ + + while ((getreg32(SAM_BSCIF_PCLKSR) & BSCIF_INT_OSC32RDY) == 0); } #endif /**************************************************************************** - * Name: sam_enableosc0 + * Name: sam_enablerc80m * * Description: - * Initialiaze OSC0 settings per the definitions in the board.h file. + * Initialiaze the 80 MHz RC oscillator per settings in the board.h header + * file. * ****************************************************************************/ -#ifdef NEED_OSC0 -static inline void sam_enableosc0(void) +#ifdef NEED_RC80M +static inline void sam_enablerc80m(void) { uint32_t regval; - /* Enable OSC0 in the correct crystal mode by setting the mode value in OSCCTRL0 */ + /* Configure and enable RC80M */ - regval = getreg32(SAM_PM_OSCCTRL0); - regval &= ~PM_OSCCTRL_MODE_MASK; -#if SAM_FOSC0 < 900000 - regval |= PM_OSCCTRL_MODE_XTALp9; /* Crystal XIN 0.4-0.9MHz */ -#elif SAM_FOSC0 < 3000000 - regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */ -#elif SAM_FOSC0 < 8000000 - regval |= PM_OSCCTRL_MODE_XTAL8; /* Crystal XIN 3.0-8.0MHz */ -#else - regval |= PM_OSCCTRL_MODE_XTALHI; /* Crystal XIN above 8.0MHz */ + regval = getreg32(SAM_SCIF_RC80MCR); + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_RC80MCR_OFFSET), + SAM_SCIF_UNLOCK); + putreg32(regval | SCIF_RC80MCR_EN, SAM_SCIF_RC80MCR); + + /* Wait for OSC32 to be ready */ + + while (getreg32(SAM_SCIF_RC80MCR) & SCIF_RC80MCR_EN) == 0); +} #endif - putreg32(regval, SAM_PM_OSCCTRL0); - /* Enable OSC0 using the startup time provided in board.h. This startup time - * is critical and depends on the characteristics of the crystal. - */ +/**************************************************************************** + * Name: sam_enablerc80m + * + * Description: + * Initialiaze the 12/8/4 RC fast oscillator per settings in the board.h + * header file. + * + ****************************************************************************/ - regval = getreg32(SAM_PM_OSCCTRL0); - regval &= ~PM_OSCCTRL_STARTUP_MASK; - regval |= (SAM_OSC0STARTUP << PM_OSCCTRL_STARTUP_SHIFT); - putreg32(regval, SAM_PM_OSCCTRL0); +#ifdef NEED_RCFAST +static inline void sam_enablercfast(void) +{ + uint32_t regval; - /* Enable OSC0 */ + /* Configure and enable RCFAST */ - regval = getreg32(SAM_PM_MCCTRL); - regval |= PM_MCCTRL_OSC0EN; - putreg32(regval, SAM_PM_MCCTRL); + regval = getreg32(SAM_SCIF_RCFASTCFG); + regval &= ~SCIF_RCFASTCFG_FRANGE_MASK; + regval |= (SAM_RCFAST_RANGE | SCIF_RCFASTCFG_EN); - /* Wait for OSC0 to be ready */ + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_RCFASTCFG_OFFSET), + SAM_SCIF_UNLOCK); + putreg32(regval, SAM_SCIF_RCFASTCFG); + + /* Wait for RCFAST to be ready */ - while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_OSC0RDY) == 0); + while (getreg32(SAM_SCIF_RCFASTCFG) & SCIF_RCFASTCFG_EN) == 0); } #endif /**************************************************************************** - * Name: sam_enableosc1 + * Name: sam_enablerc1m * * Description: - * Initialiaze OSC0 settings per the definitions in the board.h file. + * Initialiaze the 1M RC oscillator per settings in the board.h header + * file. * ****************************************************************************/ -#ifdef NEED_OSC1 -static inline void sam_enableosc1(void) +#ifdef NEED_RC1M +static inline void sam_enablerc1m(void) { uint32_t regval; - /* Enable OSC1 in the correct crystal mode by setting the mode value in OSCCTRL1 */ + /* Configure and enable RC1M */ - regval = getreg32(SAM_PM_OSCCTRL1); - regval &= ~PM_OSCCTRL_MODE_MASK; -#if SAM_FOSC1 < 900000 - regval |= PM_OSCCTRL_MODE_XTALp9; /* Crystal XIN 0.4-0.9MHz */ -#elif SAM_FOSC1 < 3000000 - regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */ -#elif SAM_FOSC1 < 8000000 - regval |= PM_OSCCTRL_MODE_XTAL8; /* Crystal XIN 3.0-8.0MHz */ -#else - regval |= PM_OSCCTRL_MODE_XTALHI; /* Crystal XIN above 8.0MHz */ + regval = getreg32(SAM_BSCIF_RC1MCR); + regval &= ~BSCIF_RCFASTCFG_FRANGE_MASK; + regval |= (SAM_RCFAST_RANGE | BSCIF_RCFASTCFG_EN); + + putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC1MCR_OFFSET), + SAM_BSCIF_UNLOCK); + putreg32(regval | BSCIF_RC1MCR_CLKOEN, SAM_BSCIF_RC1MCR); + + /* Wait for RCFAST to be ready */ + + while (getreg32(SAM_BSCIF_RC1MCR) & BSCIF_RC1MCR_CLKOEN) == 0); +} #endif - putreg32(regval, SAM_PM_OSCCTRL1); - /* Enable OSC1 using the startup time provided in board.h. This startup time - * is critical and depends on the characteristics of the crystal. - */ +/**************************************************************************** + * Name: sam_enablerc32k + * + * Description: + * Initialiaze the 23KHz RC oscillator per settings in the board.h header + * file. + * + ****************************************************************************/ - regval = getreg32(SAM_PM_OSCCTRL1); - regval &= ~PM_OSCCTRL_STARTUP_MASK; - regval |= (SAM_OSC1STARTUP << PM_OSCCTRL_STARTUP_SHIFT); - putreg32(regval, SAM_PM_OSCCTRL1); +#ifdef NEED_RC32K +static inline void sam_enablerc32k(void) +{ + uint32_t regval; - /* Enable OSC1 */ + /* Configure and enable RC32K */ - regval = getreg32(SAM_PM_MCCTRL); - regval |= PM_MCCTRL_OSC1EN; - putreg32(regval, SAM_PM_MCCTRL); + regval = getreg32(SAM_BSCIF_RC32KCR); + putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC32KCR_OFFSET), + SAM_BSCIF_UNLOCK); + putreg32(regval | BSCIF_RC32KCR_EN32K | BSCIF_RC32KCR_EN, SAM_BSCIF_RC32KCR); - /* Wait for OSC1 to be ready */ + /* Wait for RCFAST to be ready */ - while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_OSC1RDY) == 0); + while (getreg32(SAM_BSCIF_RC32KCR) & BSCIF_RC32KCR_EN) == 0); } #endif /**************************************************************************** - * Name: sam_enablepll0 + * Name: sam_enableglck9 + * + * Description: + * Enable GLCK9. + * + ****************************************************************************/ + +#ifdef NEED_GLCK9 +static inline void sam_enableglck9(void) +{ + /* Enable the generic clock using the source specified in the board.h + * file. No division is used so that the GCLK9 frequency is the same + * as the source frequency. + */ + + putreg32(SAM_GCLK9_SOURCE_VALUE | SCIF_GCCTRL_CEN, SAM_SCIF_GCCTRL9); +} +#endif + +/**************************************************************************** + * Name: sam_enablepll0 (and its helper sam_pll0putreg()) * * Description: * Initialiaze PLL0 settings per the definitions in the board.h file. * ****************************************************************************/ -#ifdef SAM_CLOCK_PLL0 +#ifdef BOARD_SYSCLK_SOURCE_PLL0 +static inline void sam_pll0putreg(uint32_t regval, uint32_t regaddr, + uint32_t regoffset) +{ + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(regoffset), + SAM_SCIF_UNLOCK); + putreg32(regval, regaddr); +} + static inline void sam_enablepll0(void) { - /* Setup PLL0 */ + uint32_t regval; - regval = (SAM_PLL0_DIV << PM_PLL_PLLDIV_SHIFT) | (SAM_PLL0_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT) + /* Clear the PLL0 control register */ - /* Select PLL0/1 oscillator */ + sam_pll0putreg(0, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET); -#if SAM_CLOCK_PLL_OSC1 - regval |= PM_PLL_PLLOSC; -#endif + /* Write the selected options */ - putreg32(regval, SAM_PM_PLL0); + regval = getreg32(SAM_SCIF_PLL0); + regval &= SCIF_PLL0_PLLOPT_MASK; + regval |= SAM_PLL0_OPTIONS; + sam_pll0putreg(regval, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET); - /* Set PLL0 options */ + /* Set up the multiers and dividers */ - regval = getreg32(SAM_PM_PLL0); - regval &= ~PM_PLL_PLLOPT_MASK -#if SAM_PLL0_FREQ < 160000000 - regval |= PM_PLL_PLLOPT_VCO; -#endif -#if SAM_PLL0_DIV2 != 0 - regval |= PM_PLL_PLLOPT_XTRADIV; -#endif -#if SAM_PLL0_WBWM != 0 - regval |= PM_PLL_PLLOPT_WBWDIS; -#endif - putreg32(regval, SAM_PM_PLL0) + regval = getreg32(SAM_SCIF_PLL0); + regval &= ~(SCIF_PLL0_PLLOSC_MASK | SCIF_PLL0_PLLDIV_MASK | SCIF_PLL0_PLLMUL_MASK); + regval |= ((SAM_PLL0_MUL - 1) << SCIF_PLL0_PLLMUL_SHIFT) | + (BOARD_DFLL0_DIV << SCIF_PLL0_PLLDIV_SHIFT) | + SCIF_PLL0_PLLCOUNT_MAX | SAM_PLL0_SOURCE; + sam_pll0putreg(regval, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET); - /* Enable PLL0 */ + /* And, finally, enable PLL0 */ - regval = getreg32(SAM_PM_PLL0); - regval |= PM_PLL_PLLEN; - putreg32(regval, SAM_PM_PLL0) + regval = getreg32(SAM_SCIF_PLL0); + regval |= SCIF_PLL_PLLEN; + sam_pll0putreg(regval, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET); - /* Wait for PLL0 locked. */ + /* Wait for PLL0 to become locked */ - while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_LOCK0) == 0); + while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_PLL0LOCK) == 0); } #endif /**************************************************************************** - * Name: sam_enablepll1 + * Name: sam_enabledfll0 (and its helper sam_dfll0_putreg32()) * * Description: - * Initialiaze PLL1 settings per the definitions in the board.h file. + * Initialiaze DFLL0 settings per the definitions in the board.h file. * ****************************************************************************/ -#ifdef SAM_CLOCK_PLL1 -static inline void sam_enablepll1(void) +#ifdef BOARD_SYSCLK_SOURCE_DFLL0 +static inline void sam_dfll0_putreg32(uint32_t regval, uint32_t regaddr, + uint32_t regoffset) { - /* Setup PLL1 */ + /* Wait until DFLL0 is completes the last setting */ - regval = (SAM_PLL1_DIV << PM_PLL_PLLDIV_SHIFT) | (SAM_PLL1_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT) + while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0); - /* Select PLL0/1 oscillator */ + /* Then unlock the register and write the next value */ -#if SAM_CLOCK_PLL_OSC1 - regval |= PM_PLL_PLLOSC; -#endif + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(regoffset), + SAM_SCIF_UNLOCK); + putreg32(regval, regaddr); +} - putreg32(regval, SAM_PM_PLL1); +static inline void sam_enabledfll0(void) +{ + uint32_t regval; + uint32_t conf; - /* Set PLL1 options */ + /* Set up generic clock source with specified reference clock + * and divider. + */ - regval = getreg32(SAM_PM_PLL1); - regval &= ~PM_PLL_PLLOPT_MASK -#if SAM_PLL1_FREQ < 160000000 - regval |= PM_PLL_PLLOPT_VCO; -#endif -#if SAM_PLL1_DIV2 != 0 - regval |= PM_PLL_PLLOPT_XTRADIV; + putreg32(0, SAM_SCIF_GCCTRL0); + + /* Set the generic clock 0 source */ + + regval = getreg32(SAM_SCIF_GCCTRL0); + regval &= ~SCIF_GCCTRL_OSCSEL_MASK; + regval |= SAM_DFLLO_REFCLK; + putreg32(regval, SAM_SCIF_GCCTRL0); + + /* Get the generic clock 0 divider */ + + regval = getreg32(SAM_SCIF_GCCTRL0); + regval &= ~(SCIF_GCCTRL_DIVEN | SCIF_GCCTRL_DIV_MASK); + +#if BOARD_DFLL0_DIV > 1 + regval |= SCIF_GCCTRL_DIVEN; + regval |= SCIF_GCCTRL_DIV(((BOARD_DFLL0_DIV + 1) / 2) - 1); #endif -#if SAM_PLL1_WBWM != 0 - regval |= PM_PLL_PLLOPT_WBWDIS; + + putreg32(regval, SAM_SCIF_GCCTRL0); + + /* Sync before reading a dfll conf register */ + + putreg32(SCIF_DFLL0SYNC_SYNC, SAM_SCIF_DFLL0SYNC); + while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0); + + /* Select Closed Loop Mode */ + + conf = getreg32(SAM_SCIF_DFLL0CONF); + conf &= ~SCIF_DFLL0CONF_RANGE_MASK; + conf |= SCIF_DFLL0CONF_MODE; + + /* Select the DFLL0 Frequency Range */ + +#if BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE3 + conf |= SCIF_DFLL0CONF_RANGE3; +#elif BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE2 + conf |= SCIF_DFLL0CONF_RANGE2; +#elif BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE1 + conf |= SCIF_DFLL0CONF_RANGE1; +#else + conf |= SCIF_DFLL0CONF_RANGE0; #endif - putreg32(regval, SAM_PM_PLL1) - /* Enable PLL1 */ + /* Enable the reference generic clock 0 */ + + regval = getreg32(SAM_SCIF_GCCTRL0); + regval |= SCIF_GCCTRL_CEN; + putreg32(regval, SAM_SCIF_GCCTRL0); + + /* Enable DFLL0. Here we assume DFLL0RDY because the DFLL was disabled + * before this function was called. + */ + + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_DFLL0CONF_OFFSET), + SAM_SCIF_UNLOCK); + putreg32(SCIF_DFLL0CONF_EN, SAM_SCIF_DFLL0CONF); + + /* Configure DFLL0. Note that now we do have to wait for DFLL0RDY before + * every write. + * + * Set the initial coarse and fine step lengths to 4. If this is set + * too high, DFLL0 may fail to lock. + */ + + sam_dfll0_putreg32(SCIF_DFLL0STEP_CSTEP(4) | SCIF_DFLL0STEP_FSTEP(4), + SAM_SCIF_DFLL0STEP, + SAM_SCIF_DFLL0STEP_OFFSET); + + /* Set the DFLL0 multipler register */ - regval = getreg32(SAM_PM_PLL1); - regval |= PM_PLL_PLLEN; - putreg32(regval, SAM_PM_PLL1) + sam_dfll0_putreg32(BOARD_DFLL0_MUL, SAM_SCIF_DFLL0MUL, + SAM_SCIF_DFLL0MUL_OFFSET); - /* Wait for PLL1 locked. */ + /* Set the multipler and spread spectrum generator control registers */ - while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_LOCK1) == 0); + sam_dfll0_putreg32(0, SAM_SCIF_DFLL0SSG, SAM_SCIF_DFLL0SSG_OFFSET); + + /* Finally, set the DFLL0 configuration */ + + sam_dfll0_putreg32(conf | SCIF_DFLL0CONF_EN, + SAM_SCIF_DFLL0CONF, SAM_SCIF_DFLL0CONF_OFFSET); + + /* Wait until we are locked on the fine value */ + + while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0LOCKF) == 0); } #endif @@ -349,49 +857,47 @@ static inline void sam_enablepll1(void) * ****************************************************************************/ -static inline void sam_setdividers(uint32_t cpudiv, uint32_t pbadiv, - uint32_t pbbdiv, uint32_t pbcdiv, - uint32_t pbddiv) +static inline void sam_setdividers(void) { - irqstate_t flags; - uint32_t cpusel = 0; - uint32_t pbasel = 0; - uint32_t pbbsel = 0; - uint32_t pbcsel = 0; - uint32_t pbdsel = 0; + uint32_t cpusel; + uint32_t pbasel; + uint32_t pbbsel; + uint32_t pbcsel; + uint32_t pbdsel; /* Get the register setting for each divider value */ - if (cpudiv > 0) - { - cpusel = (PM_CPUSEL(cpudiv - 1)) | PM_CPUSEL_DIV; - } - - if (pbadiv > 0) - { - pbasel = (PM_PBSEL(pbadiv - 1)) | PM_PBSEL_DIV; - } +#if BOARD_CPU_SHIFT > 0 + cpusel = (PM_CPUSEL(BOARD_CPU_SHIFT - 1)) | PM_CPUSEL_DIV; +#else + cpusel = 0; +#endif - if (pbbdiv > 0) - { - pbbsel = (PM_PBSEL(pbbdiv - 1)) | PM_PBSEL_DIV; - } +#if BOARD_PBA_SHIFT > 0 + pbasel = (PM_PBSEL(BOARD_PBA_SHIFT - 1)) | PM_PBSEL_DIV; +#else + pbasel = 0; +#endif - if (pbcdiv > 0) - { - pbcsel = (PM_PBSEL(pbcdiv - 1)) | PM_PBSEL_DIV; - } +#if BOARD_PBB_SHIFT >0 + pbbsel = (PM_PBSEL(BOARD_PBB_SHIFT - 1)) | PM_PBSEL_DIV; +#else + pbbsel = 0; +#endif - if (pbddiv > 0) - { - pbdsel = (PM_PBSEL(pbddiv - 1)) | PM_PBSEL_DIV; - } +#if BOARD_PBC_SHIFT > 0 + pbcsel = (PM_PBSEL(BOARD_PBC_SHIFT - 1)) | PM_PBSEL_DIV; +#else + pbcsel = 0; +#endif - /* Then set the divider values. The following operations need to be atomic - * for the unlock-write sequeuences. - */ +#if BOARD_PBD_SHIFT > 0 + pbdsel = (PM_PBSEL(BOARD_PBD_SHIFT - 1)) | PM_PBSEL_DIV; +#else + pbdsel = 0; +#endif - flags = irqsave(); + /* Then set the divider values. */ putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUSEL_OFFSET), SAM_PM_UNLOCK); putreg32(cpusel, SAM_PM_CPUSEL); @@ -407,24 +913,46 @@ static inline void sam_setdividers(uint32_t cpudiv, uint32_t pbadiv, putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDSEL_OFFSET), SAM_PM_UNLOCK); putreg32(pbdsel, SAM_PM_PBDSEL); +} + +/**************************************************************************** + * Name: sam_enable_fastwakeup + * + * Description: + * Enable FLASH fast wakeup mode. + * + ****************************************************************************/ + +static inline void sam_enable_fastwakeup(void) +{ + uint32_t regval; - irqrestore(flags); + regval = getreg32(SAM_BPM_PMCON); + regval |= BPM_PMCON_FASTWKUP; + putreg32(BPM_UNLOCK_KEY(0xaa) | BPM_UNLOCK_ADDR(SAM_BPM_PMCON_OFFSET), + SAM_BPM_UNLOCK); + putreg32(regval, SAM_BPM_PMCON); } /**************************************************************************** - * Name: sam_fws + * Name: set_flash_waitstate * * Description: - * Setup FLASH wait states. + * Setup one or two FLASH wait states. * ****************************************************************************/ -static void sam_fws(uint32_t cpuclock) +static inline void set_flash_waitstate(bool waitstate) { uint32_t regval; + /* Set or clear the FLASH wait state (FWS) bit in the FLASH control + * register (FCR). + */ + regval = getreg32(SAM_FLASHCALW_FCR); - if (cpuclock > SAM_FLASHCALW_FWS0_MAXFREQ) + + if (waitstate) { regval |= FLASHCALW_FCR_FWS; } @@ -436,6 +964,157 @@ static void sam_fws(uint32_t cpuclock) putreg32(regval, SAM_FLASHCALW_FCR); } +/**************************************************************************** + * Name: sam_flash_readmode + * + * Description: + * Send a FLASH command to enable to disable high speed FLASH read mode. + * + ****************************************************************************/ + +static inline void sam_flash_readmode(uint32_t command) +{ + uint32_t regval; + + /* Make sure that any previous FLASH operation is completed */ + + while ((getreg32(SAM_FLASHCALW_FSR) & FLASHCALW_FSR_FRDY) == 0); + + /* Write the specified FLASH command to the FCMD register */ + + regval = getreg32(SAM_FLASHCALW_FCMD); + regval &= ~FLASHCALW_FCMD_CMD_MASK; + regval |= (FLASHCALW_FCMD_KEY | command); + putreg32(regval, SAM_FLASHCALW_FCMD); + + /* Wait for this FLASH operation to complete */ + + while ((getreg32(SAM_FLASHCALW_FSR) & FLASHCALW_FSR_FRDY) == 0); +} + +/**************************************************************************** + * Name: sam_flash_config + * + * Description: + * Configure FLASH read mode and wait states. + * + * Maximum CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes + * (Table 42-30 in the big data sheet). + * + * ------- ------------------- ---------- ---------- + * Power Flash Read Mode Flash Maximum + * Sclaing Wait Operating + * Mode HSEN HSDIS FASTWKUP States Frequency + * ------- ---- ----- -------- ---------- ---------- + * PS0 X X 1 12MHz + * " " X 0 18MHz + * " " X 1 36MHz + * PS1 X X 1 12MHz + * " " X 0 8MHz + * " " X 1 12MHz + * PS2 X 0 24Mhz + * " " X 1 48MHz + * ------- ---- ----- -------- ---------- ---------- + * + ****************************************************************************/ + +static inline void sam_flash_config(uint32_t cpuclock, uint32_t psm, bool fastwkup) +{ + bool waitstate; + uint32_t command; + +#ifdef CONFIG_SAM34_FLASH_HSEN + /* High speed flash read mode (with power scaling mode == 2). Set one + * wait state if the CPU clock frequency exceeds the threshold value + * and enable high speed read mode. + */ + + waitstate = (cpuclock > FLASH_MAXFREQ_PS2_HSEN_FWS0); + command = FLASHCALW_FCMD_CMD_HSEN; +#else + /* Assume that we will select no wait states and that we will disable high- + * speed read mode. + */ + + waitstate = false; + command = FLASHCALW_FCMD_CMD_HSDIS; + + /* Handle power scaling mode == 0 FLASH configuration */ + + if (psm == 0) + { + /* Power scaling mode 0. We need to set wait state the CPU clock if + * the CPU frequency exceeds a threshold. + */ + + if (cpuclock > FLASH_MAXFREQ_PS0_HSDIS_FWS0) + { + /* Set one wait state */ + + waitstate = true; + + /* Enable high speed read mode if the frequency exceed the maximum + * for the low speed configuration. This mode is not documented + * in the data sheet, but I see that they do this in some Atmel + * code examples. + */ + + if (cpuclock > FLASH_MAXFREQ_PS0_HSDIS_FWS1) + { + /* Enable high speed read mode. */ + + command = FLASHCALW_FCMD_CMD_HSEN; + } + } + + /* The is below the threshold that requires one wait state. But we + * have to check a few more things. + */ + + else + { + /* If FLASH wake-up mode is selected and the we are in the lower + * operating frequency for this mode, then set 1 waitate and + * disable high speed read mode. + */ + + if ((fastwkup == true) && + (cpuclock <= FLASH_MAXFREQ_PS1_HSDIS_FASTWKUP_FWS1)) + { + /* Set one wait state */ + + waitstate = true; + } + } + } + + /* Otherwise, this is power scaling mode 1 */ + + else /* if (psm == 1) */ + { + /* If we are in the lower operating frequency range, then select + * zero wait states. Otherwise, select one wait state. + */ + + if (cpuclock > FLASH_MAXFREQ_PS1_HSDIS_FWS0) + { + /* Set one wait state */ + + waitstate = true; + } + } + +#endif + + /* Set 0 or 1 waitstates */ + + set_flash_waitstate(waitstate); + + /* Enable/disable the high-speed read mode. */ + + sam_flash_readmode(command); +} + /**************************************************************************** * Name: sam_mainclk * @@ -451,9 +1130,50 @@ static inline void sam_mainclk(uint32_t mcsel) regval = getreg32(SAM_PM_MCCTRL); regval &= ~PM_MCCTRL_MCSEL_MASK; regval |= mcsel; + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_MCCTRL_OFFSET), + SAM_PM_UNLOCK); putreg32(regval, SAM_PM_MCCTRL); } +/**************************************************************************** + * Name: sam_setpsm (and its helper, sam_instantiatepsm()) + * + * Description: + * Switch to the selected power scaling mode. + * + ****************************************************************************/ + +static __ramfunc__ void sam_instantiatepsm(uint32_t regval) +{ + /* Set the BMP PCOM register (containing the new power scaling mode) */ + + putreg32(BPM_UNLOCK_KEY(0xaa) | BPM_UNLOCK_ADDR(SAM_BPM_PMCON_OFFSET), + SAM_BPM_UNLOCK); + putreg32(regval, SAM_BPM_PMCON); + + /* Wait for new power scaling mode to become active. There should be + * timeout on this wait. + */ + + while ((getreg32(SAM_BPM_SR) & BPM_INT_PSOK) == 0); +} + +static inline void sam_setpsm(uint32_t psm) +{ + uint32_t regval; + + /* Setup the PMCON register content fo the new power scaling mode */ + + regval = getreg32(SAM_BPM_PMCON); + regval &= ~BPM_PMCON_PS_MASK; + regval |= (psm | BPM_PMCON_PSCM | BPM_PMCON_PSCREQ); + + /* Then call the RAMFUNC sam_setpsm() to set the new power scaling mode */ + + sam_instantiatepsm(regval); +} + /**************************************************************************** * Name: sam_usbclock * @@ -505,67 +1225,210 @@ static inline void sam_usbclock(void) void sam_clockconfig(void) { + uint32_t psm; + bool fastwkup; + /* Enable clocking to the PICOCACHE */ sam_picocache(); - /* Configure dividers derived clocks. These divider definitions must be - * provided in the board.h header file. + /* Configure dividers for derived clocks. These divider definitions must + * be provided in the board.h header file. */ - sam_setdividers(BOARD_SYSCLK_CPU_DIV, BOARD_SYSCLK_PBA_DIV, - BOARD_SYSCLK_PBB_DIV, BOARD_SYSCLK_PBC_DIV, - BOARD_SYSCLK_PBD_DIV); + sam_setdividers(); + + /* Select a power scaling mode and possible fast wakeup so that we get the + * best possible flash performance. The following table shows the maximum + * CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes + * (Table 42-30 in the big data sheet). + * + * ------- ------------------- ---------- ---------- + * Power Flash Read Mode Flash Maximum + * Sclaing Wait Operating + * Mode HSEN HSDIS FASTWKUP States Frequency + * ------- ---- ----- -------- ---------- ---------- + * PS0 X X 1 12MHz + * " " X 0 18MHz + * " " X 1 36MHz + * PS1 X X 1 12MHz + * " " X 0 8MHz + * " " X 1 12MHz + * PS2 X 0 24Mhz + * " " X 1 48MHz + * ------- ---- ----- -------- ---------- ---------- + */ -#ifdef SAM_CLOCK_OSC32 - /* Enable the 32KHz oscillator (need by the RTC module) */ +#ifdef CONFIG_SAM34_FLASH_HSEN + /* The high speed FLASH mode has been enabled. Select power scaling + * mode 2, no fast wakeup. + */ - sam_enableosc32(); + psm = BPM_PMCON_PS2; + fastwkup = false; + +#elif BOARD_CPU_FREQUENCY <= FLASH_MAXFREQ_PS1_HSDIS_FWS1 + /* Not high speed mode and frequency is below the thrshold. We can go to + * power scaling mode 1. + */ + + psm = BPM_PMCON_PS1; + +# if BOARD_CPU_FREQUENCY > FLASH_MAXFREQ_PS1_HSDIS_FWS0 + /* We need to enable fast wakeup */ + + sam_enable_fastwakeup() + fastwkup = true; +# endif +#else + /* Power scaling mode 0, disable high speed mode, no fast wakeup */ + + psm = BPM_PMCON_PS0; + fastwkup = false; #endif -#ifdef NEED_OSC0 + /* Enable clock sources: + * + * OSC0: Might by the system clock or the source clock for PLL0 or DFLL0 + * OSC32: Might be source clock for DFLL0 + */ + +#if NEED_OSC0 /* Enable OSC0 using the settings in board.h */ sam_enableosc0(); +#endif - /* Set up FLASH wait states */ +#ifdef NEED_OSC32K + /* Enable the 32KHz oscillator using the settings in board.h */ - sam_fws(SAM_FOSC0); + sam_enableosc32(); +#endif - /* Then switch the main clock to OSC0 */ +#ifdef NEED_RC80M + /* Enable the 32KHz oscillator using the settings in board.h */ - sam_mainclk(PM_MCCTRL_MCSEL_OSC0); + sam_enablerc80m(); +#endif + +#ifdef NEED_RCFAST + /* Enable the 12/8/4MHz RC fast oscillator using the settings in board.h */ + + sam_enablercrcfast(); +#endif + +#ifdef NEED_RC1M + /* Enable the 1MHz RC oscillator using the settings in board.h */ + + sam_enablerc1m(); +#endif + +#ifdef NEED_RC32K + /* Enable the 32KHz RC oscillator using the settings in board.h */ + + sam_enablerc32k(); #endif -#ifdef NEED_OSC1 - /* Enable OSC1 using the settings in board.h */ +#ifdef NEED_GLCK9 + /* Enable the GLCK9 */ - sam_enableosc1(); + sam_enableglck9(); #endif -#ifdef SAM_CLOCK_PLL0 + /* Switch to the system clock selected by the settings in the board.h + * header file. + */ + +#if defined(BOARD_SYSCLK_SOURCE_RCSYS) + /* Since this function only executes at power up, we know that we are + * already running from RCSYS. + */ + + // sam_mainclk(PM_MCCTRL_MCSEL_RCSYS); +#elif defined(BOARD_SYSCLK_SOURCE_OSC0) + + /* Configure FLASH read mode and wait states */ + + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); + + /* Then switch the main clock to OSC0 */ + + sam_mainclk(PM_MCCTRL_MCSEL_OSC0); + +#elif defined(BOARD_SYSCLK_SOURCE_PLL0) + /* Enable PLL0 using the settings in board.h */ sam_enablepll0(); - /* Set up FLASH wait states */ + /* Configure FLASH read mode and wait states */ - sam_fws(SAM_CPU_CLOCK); + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); /* Then switch the main clock to PLL0 */ - sam_mainclk(PM_MCCTRL_MCSEL_PLL0); -#endif + sam_mainclk(PM_MCCTRL_MCSEL_PLL); + +#elif defined(BOARD_SYSCLK_SOURCE_DFLL0) + + /* Enable PLL0 using the settings in board.h */ + + sam_enabledfll0(); + + /* Configure FLASH read mode and wait states */ + + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); -#ifdef SAM_CLOCK_PLL1 - /* Enable PLL1 using the settings in board.h */ + /* Then switch the main clock to DFLL0 */ - sam_enablepll1(); + sam_mainclk(PM_MCCTRL_MCSEL_DFLL); + +#elif defined(BOARD_SYSCLK_SOURCE_RC80M) + + /* Configure FLASH read mode and wait states */ + + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); + + /* Then switch the main clock to RCM80 */ + + sam_mainclk(PM_MCCTRL_MCSEL_RC80M); + +#elif defined(BOARD_SYSCLK_SOURCE_FCFAST12M) || defined(BOARD_SYSCLK_SOURCE_FCFAST8M) || \ + defined(BOARD_SYSCLK_SOURCE_FCFAST4M) + + /* Configure FLASH read mode and wait states */ + + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); + + /* Then switch the main clock to RCFAST */ + + sam_mainclk(PM_MCCTRL_MCSEL_RCFAST); + +#elif defined(BOARD_SYSCLK_SOURCE_RC1M) + + /* Configure FLASH read mode and wait states */ + + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); + + /* Then switch the main clock to RC1M */ + + sam_mainclk(PM_MCCTRL_MCSEL_RC1M); + +#else +# error "No SYSCLK source provided" #endif - /* Set up the USBB GCLK */ + /* Switch to the selected power scaling mode */ + + sam_setpsm(psm); + + /* Enable all selected peripheral cloks */ + + sam_init_periphclks(); + + /* Configure clocking to the USB controller */ #ifdef CONFIG_USBDEV - void sam_usbclock(); + sam_usbc_enableclk(); #endif } diff --git a/nuttx/arch/arm/src/sam34/sam4l_periphclks.c b/nuttx/arch/arm/src/sam34/sam4l_periphclks.c index abd766695a..2c55ab6b01 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_periphclks.c +++ b/nuttx/arch/arm/src/sam34/sam4l_periphclks.c @@ -52,8 +52,23 @@ #include "sam4l_periphclks.h" /**************************************************************************** - * Private Definitions + * Pre-processor Definitions ****************************************************************************/ +/* USBC source clock selection */ + +#ifdef CONFIG_SAM34_USBC +# if defined(BOARD_USBC_SRC_OSC0) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_OSC0 +# elif defined(BOARD_USBC_SRC_PLL0) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_PLL0 +# elif defined(BOARD_USBC_SRC_DFLL) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_DFLL0 +# elif defined(BOARD_USBC_SRC_GCLKIN0) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_GCLKIN0 +# else +# error No USBC GCLK7 source clock defined +# endif +#endif /**************************************************************************** * Private Types @@ -75,10 +90,328 @@ * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: sam_init_cpumask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * CPU mask register. + * + ****************************************************************************/ + +static inline void sam_init_cpumask(void) +{ + uint32_t mask = 0; + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_OCD + mask |= PM_CPUMASK_OCD; /* On-Chip Debug */ +#endif +#endif + + /* Save the new CPU mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_CPUMASK); +} + +/**************************************************************************** + * Name: sam_init_hsbmask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * HSB mask register. + * + ****************************************************************************/ + +static inline void sam_init_hsbmask(void) +{ + /* Select the non-optional peripherals */ + + uint32_t mask = (PM_HSBMASK_FLASHCALW | PM_HSBMASK_APBB | + PM_HSBMASK_APBC | PM_HSBMASK_APBD); + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_PDCA + mask |= PM_HSBMASK_PDCA; /* PDCA */ +#endif +#ifdef CONFIG_SAM34_HRAMC1 + mask |= PM_HSBMASK_HRAMC1; /* HRAMC1 (picoCache RAM) */ +#endif +#ifdef CONFIG_SAM34_USBC + mask |= PM_HSBMASK_USBC; /* USBC */ +#endif +#ifdef CONFIG_SAM34_CRCCU + mask |= PM_HSBMASK_CRCCU; /* CRCCU */ +#endif +#ifdef CONFIG_SAM34_APBA + mask |= PM_HSBMASK_APBA; /* APBA bridge */ +#endif +#ifdef CONFIG_SAM34_AESA + mask |= PM_HSBMASK_AESA; /* AESA */ +#endif +#endif + + /* Save the new HSB mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_HSBMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_HSBMASK); +} + +/**************************************************************************** + * Name: sam_init_pbamask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * PBA mask register. + * + ****************************************************************************/ + +static inline void sam_init_pbamask(void) +{ + /* Select the non-optional peripherals */ + + uint32_t mask = 0; + uint32_t divmask = 0; + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_IISC + mask |= PM_PBAMASK_IISC; /* IISC */ +#endif +#ifdef CONFIG_SAM34_SPI + mask |= PM_PBAMASK_SPI; /* SPI */ +#endif +#ifdef CONFIG_SAM34_TC0 + mask |= PM_PBAMASK_TC0; /* TC0 */ + divmask |= PM_PBADIVMASK_TIMER_CLOCKS; +#endif +#ifdef CONFIG_SAM34_TC1 + mask |= PM_PBAMASK_TC1; /* TC1 */ + divmask |= PM_PBADIVMASK_TIMER_CLOCKS; +#endif +#ifdef CONFIG_SAM34_TWIM0 + mask |= PM_PBAMASK_TWIM0; /* TWIM0 */ +#endif +#ifdef CONFIG_SAM34_TWIS0 + mask |= PM_PBAMASK_TWIS0; /* TWIS0 */ +#endif +#ifdef CONFIG_SAM34_TWIM1 + mask |= PM_PBAMASK_TWIM1; /* TWIM1 */ +#endif +#ifdef CONFIG_SAM34_TWIS1 + mask |= PM_PBAMASK_TWIS1; /* TWIS1 */ +#endif +#ifdef CONFIG_SAM34_USART0 + mask |= PM_PBAMASK_USART0; /* USART0 */ + divmask |= PM_PBADIVMASK_CLK_USART; +#endif +#ifdef CONFIG_SAM34_USART1 + mask |= PM_PBAMASK_USART1; /* USART1 */ + divmask |= PM_PBADIVMASK_CLK_USART; +#endif +#ifdef CONFIG_SAM34_USART2 + mask |= PM_PBAMASK_USART2; /* USART2 */ + divmask |= PM_PBADIVMASK_CLK_USART; +#endif +#ifdef CONFIG_SAM34_USART3 + mask |= PM_PBAMASK_USART3; /* USART3 */ + divmask |= PM_PBADIVMASK_CLK_USART; +#endif +#ifdef CONFIG_SAM34_ADCIFE + mask |= PM_PBAMASK_ADCIFE; /* ADCIFE */ +#endif +#ifdef CONFIG_SAM34_DACC + mask |= PM_PBAMASK_DACC; /* DACC */ +#endif +#ifdef CONFIG_SAM34_ACIFC + mask |= PM_PBAMASK_ACIFC; /* ACIFC */ +#endif +#ifdef CONFIG_SAM34_GLOC + mask |= PM_PBAMASK_GLOC; /* GLOC */ +#endif +#ifdef CONFIG_SAM34_ABDACB + mask |= PM_PBAMASK_ABDACB; /* ABDACB */ +#endif +#ifdef CONFIG_SAM34_TRNG + mask |= PM_PBAMASK_TRNG; /* TRNG */ +#endif +#ifdef CONFIG_SAM34_PARC + mask |= PM_PBAMASK_PARC; /* PARC */ +#endif +#ifdef CONFIG_SAM34_CATB + mask |= PM_PBAMASK_CATB; /* CATB */ +#endif +#ifdef CONFIG_SAM34_TWIM2 + mask |= PM_PBAMASK_TWIM2; /* TWIM2 */ +#endif +#ifdef CONFIG_SAM34_TWIM3 + mask |= PM_PBAMASK_TWIM3; /* TWIM3 */ +#endif +#ifdef CONFIG_SAM34_LCDCA + mask |= PM_PBAMASK_LCDCA; /* LCDCA*/ +#endif +#endif + + /* Save the new PBA mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBAMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_PBAMASK); + + /* Set the peripheral divider mask as necessary */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(divmask, SAM_PM_PBADIVMASK); +} + +/**************************************************************************** + * Name: sam_init_pbbmask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * PBB mask register. + * + ****************************************************************************/ + +static inline void sam_init_pbbmask(void) +{ + /* Select the non-optional peripherals */ + + uint32_t mask = PM_PBBMASK_FLASHCALW; + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_HRAMC1 + mask |= PM_PBBMASK_HRAMC1; /* HRAMC1 */ +#endif +#ifdef CONFIG_SAM34_HMATRIX + mask |= PM_PBBMASK_HMATRIX; /* HMATRIX */ +#endif +#ifdef CONFIG_SAM34_PDCA + mask |= PM_PBBMASK_PDCA; /* PDCA */ +#endif +#ifdef CONFIG_SAM34_CRCCU + mask |= PM_PBBMASK_CRCCU; /* CRCCU */ +#endif +#ifdef CONFIG_SAM34_USBC + mask |= PM_PBBMASK_USBC; /* USBC */ +#endif +#ifdef CONFIG_SAM34_PEVC + mask |= PM_PBBMASK_PEVC; /* PEVC */ +#endif +#endif + + /* Save the new PBB mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_PBBMASK); +} + +/**************************************************************************** + * Name: sam_init_pbcmask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * PBC mask register. + * + ****************************************************************************/ + +static inline void sam_init_pbcmask(void) +{ + /* Select the non-optional peripherals */ + + uint32_t mask = (PM_PBCMASK_PM | PM_PBCMASK_SCIF | PM_PBCMASK_GPIO); + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_CHIPID + mask |= PM_PBCMASK_CHIPID; /* CHIPID */ +#endif +#ifdef CONFIG_SAM34_FREQM + mask |= PM_PBCMASK_FREQM; /* FREQM */ +#endif +#endif + + /* Save the new PBC mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_PBCMASK); +} + +/**************************************************************************** + * Name: sam_init_pbdmask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * PBD mask register. + * + ****************************************************************************/ + +static inline void sam_init_pbdmask(void) +{ + /* Select the non-optional peripherals */ + + uint32_t mask = (PM_PBDMASK_BPM | PM_PBDMASK_BSCIF); + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_AST + mask |= PM_PBDMASK_AST; /* AST */ +#endif +#ifdef CONFIG_SAM34_WDT + mask |= PM_PBDMASK_WDT; /* WDT */ +#endif +#ifdef CONFIG_SAM34_EIC + mask |= PM_PBDMASK_EIC; /* EIC */ +#endif +#ifdef CONFIG_SAM34_PICOUART + mask |= PM_PBDMASK_PICOUART; /* PICOUART */ +#endif +#endif + + /* Save the new PBD mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_PBDMASK); +} + /**************************************************************************** * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: sam_init_periphclks + * + * Description: + * Called during boot to enable clocking on all selected peripherals. + * + ****************************************************************************/ + +void sam_init_periphclks(void) +{ + sam_init_cpumask(); + sam_init_hsbmask(); + sam_init_pbamask(); + sam_init_pbbmask(); + sam_init_pbcmask(); + sam_init_pbdmask(); +} + /**************************************************************************** * Name: sam_modifyperipheral * @@ -88,7 +421,8 @@ * ****************************************************************************/ -void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits) +void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, + uint32_t setbits) { irqstate_t flags; uint32_t regval; @@ -102,7 +436,8 @@ void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits) regval = getreg32(regaddr); regval &= ~clrbits; regval |= setbits; - putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE), SAM_PM_UNLOCK); + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE), + SAM_PM_UNLOCK); putreg32(regval, regaddr); irqrestore(flags); @@ -131,7 +466,8 @@ void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits) regval = getreg32(SAM_PM_PBADIVMASK); regval &= ~clrbits; regval |= setbits; - putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET), SAM_PM_UNLOCK); + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET), + SAM_PM_UNLOCK); putreg32(regval, SAM_PM_PBADIVMASK); irqrestore(flags); @@ -270,3 +606,86 @@ void sam_pbb_disableperipheral(uint32_t bitset) irqrestore(flags); } + +/**************************************************************************** + * Name: sam_usbc_enableclk + * + * Description: + * Enable clocking for the USBC using settings from the board.h header files. + * + * "The USBC has two bus clocks connected: One High Speed Bus clock + * (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks + * are generated by the Power Manager. Both clocks are enabled at reset + * and can be disabled by the Power Manager. It is recommended to disable + * the USBC before disabling the clocks, to avoid freezing the USBC in + * an undefined state. + * + * "To follow the usb data rate at 12Mbit/s in full-speed mode, the + * CLK_USBC_AHB clock should be at minimum 12MHz. + * + * "The 48MHz USB clock is generated by a dedicated generic clock from + * the SCIF module. Before using the USB, the user must ensure that the + * USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module." + * + ****************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_enableclk(void) +{ + irqstate_t flags; + uint32_t regval; + + /* Enable USBC clocking (possibly along with the PBB peripheral bridge) */ + + flags = irqsave(); + sam_hsb_enableperipheral(PM_HSBMASK_USBC); + sam_pbb_enableperipheral(PM_PBBMASK_USBC); + + /* Reset generic clock 7 */ + + putreg32(0, SAM_SCIF_GCCTRL7); + + /* Set the generic clock source */ + + regval = getreg32(SAM_SCIF_GCCTRL7); + regval &= ~SCIF_GCCTRL_OSCSEL_MASK; + regval |= SAM_USBC_GCLK_SOURCE; + putreg32(regval, SAM_SCIF_GCCTRL7); + + /* Set the generic clock divider */ + + regval = getreg32(SAM_SCIF_GCCTRL7); + regval &= ~(SCIF_GCCTRL_DIVEN | SCIF_GCCTRL_DIV_MASK); + +#if BOARD_USBC_GCLK_DIV > 1 + regval |= SCIF_GCCTRL_DIVEN; + regval |= SCIF_GCCTRL_DIV(((divider + 1) / 2) - 1); +#endif + + putreg32(regval, SAM_SCIF_GCCTRL7); + + /* Enable the generic clock */ + + regval = getreg32(SAM_SCIF_GCCTRL7); + regval |= SCIF_GCCTRL_CEN; + putreg32(regval, SAM_SCIF_GCCTRL7); + irqrestore(flags); +} +#endif /* CONFIG_SAM34_USBC */ + +/**************************************************************************** + * Name: sam_usbc_disableclk + * + * Description: + * Disable clocking to the USBC. + * + ****************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_disableclk(void) +{ + putreg32(0, SAM_SCIF_GCCTRL7); + sam_pbb_enableperipheral(PM_PBBMASK_USBC); + sam_hsb_enableperipheral(PM_HSBMASK_USBC); +} +#endif /* CONFIG_SAM34_USBC */ diff --git a/nuttx/arch/arm/src/sam34/sam4l_periphclks.h b/nuttx/arch/arm/src/sam34/sam4l_periphclks.h index 895556e5de..f7509e278c 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_periphclks.h +++ b/nuttx/arch/arm/src/sam34/sam4l_periphclks.h @@ -42,6 +42,10 @@ #include +#include "chip/sam4l_pm.h" + +#ifdef CONFIG_ARCH_CHIP_SAM4L + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -90,13 +94,13 @@ #define sam_usart0_enableclk() \ do { \ sam_pba_enableperipheral(PM_PBAMASK_USART0); \ - sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \ + sam_pba_enabledivmask(PM_PBADIVMASK_CLK_USART); \ } while (0) #define sam_usart1_enableclk() \ do { \ sam_pba_enableperipheral(PM_PBAMASK_USART1); \ - sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \ + sam_pba_enabledivmask(PM_PBADIVMASK_CLK_USART); \ } while (0) #define sam_usart2_enableclk() \ @@ -149,12 +153,6 @@ sam_pbb_enableperipheral(PM_PBBMASK_CRCCU); \ } while (0) -#define sam_usbc_enableclk() \ - do { \ - sam_hsb_enableperipheral(PM_HSBMASK_USBC); \ - sam_pbb_enableperipheral(PM_PBBMASK_USBC); \ - } while (0) - #define sam_pevc_enableclk() sam_pbb_enableperipheral(PM_PBBMASK_PEVC) #define sam_pm_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_PM) #define sam_chipid_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_CHIPID) @@ -216,12 +214,6 @@ sam_pbb_disableperipheral(PM_PBBMASK_CRCCU); \ } while (0) -#define sam_usbc_disableclk() \ - do { \ - sam_hsb_disableperipheral(PM_HSBMASK_USBC); \ - sam_pbb_disableperipheral(PM_PBBMASK_USBC); \ - } while (0) - #define sam_pevc_disableclk() sam_pbb_disableperipheral(PM_PBBMASK_PEVC) #define sam_pm_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_PM) #define sam_chipid_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_CHIPID) @@ -262,82 +254,114 @@ extern "C" * Public Function Prototypes ************************************************************************************/ -/**************************************************************************** +/************************************************************************************ + * Name: sam_init_periphclks + * + * Description: + * Called during boot to enable clocking on all selected peripherals. + * + ************************************************************************************/ + +void sam_init_periphclks(void); + +/************************************************************************************ * Name: sam_modifyperipheral * * Description: - * This is a convenience function that is intended to be used to enable - * or disable module clocking. + * This is a convenience function that is intended to be used to enable or disable + * module clocking. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits); -#endif -/**************************************************************************** +/************************************************************************************ * Name: sam_pba_modifydivmask * * Description: - * This is a convenience function that is intended to be used to modify - * bits in the PBA divided clock (DIVMASK) register. + * This is a convenience function that is intended to be used to modify bits in + * the PBA divided clock (DIVMASK) register. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits); -#endif -/**************************************************************************** +/************************************************************************************ * Name: sam_pba_enableperipheral * * Description: - * This is a convenience function to enable a peripheral on the APBA - * bridge. + * This is a convenience function to enable a peripheral on the APBA bridge. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_pba_enableperipheral(uint32_t bitset); -#endif -/**************************************************************************** +/************************************************************************************ * Name: sam_pba_disableperipheral * * Description: - * This is a convenience function to disable a peripheral on the APBA - * bridge. + * This is a convenience function to disable a peripheral on the APBA bridge. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_pba_disableperipheral(uint32_t bitset); -#endif -/**************************************************************************** +/************************************************************************************ * Name: sam_pbb_enableperipheral * * Description: - * This is a convenience function to enable a peripheral on the APBB - * bridge. + * This is a convenience function to enable a peripheral on the APBB bridge. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_pbb_enableperipheral(uint32_t bitset); -#endif -/**************************************************************************** +/************************************************************************************ * Name: sam_pbb_disableperipheral * * Description: - * This is a convenience function to disable a peripheral on the APBA - * bridge. + * This is a convenience function to disable a peripheral on the APBA bridge. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_pbb_disableperipheral(uint32_t bitset); + +/************************************************************************************ + * Name: sam_usbc_enableclk + * + * Description: + * Enable clocking for the USBC using settings from the board.h header files. + * + * "The USBC has two bus clocks connected: One High Speed Bus clock + * (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks + * are generated by the Power Manager. Both clocks are enabled at reset + * and can be disabled by the Power Manager. It is recommended to disable + * the USBC before disabling the clocks, to avoid freezing the USBC in + * an undefined state. + * + * "To follow the usb data rate at 12Mbit/s in full-speed mode, the + * CLK_USBC_AHB clock should be at minimum 12MHz. + * + * "The 48MHz USB clock is generated by a dedicated generic clock from + * the SCIF module. Before using the USB, the user must ensure that the + * USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module." + * + ************************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_enableclk(void); +#endif + +/************************************************************************************ + * Name: sam_usbc_disableclk + * + * Description: + * Disable clocking to the USBC. + * + ************************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_disableclk(void); #endif #undef EXTERN @@ -346,4 +370,5 @@ void sam_pbb_disableperipheral(uint32_t bitset); #endif #endif /* __ASSEMBLY__ */ +#endif /* CONFIG_ARCH_CHIP_SAM4L */ #endif /* __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H */ diff --git a/nuttx/arch/arm/src/sam34/sam4s_gpio.h b/nuttx/arch/arm/src/sam34/sam4s_gpio.h new file mode 100644 index 0000000000..2d9fd8bb56 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam4s_gpio.h @@ -0,0 +1,201 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam4s_gpio.h + * General Purpose Input/Output (GPIO) definitions for the SAM4S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H +#define __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +#define GPIO_HAVE_PULLDOWN 1 +#define GPIO_HAVE_PERIPHCD 1 +#define GPIO_HAVE_SCHMITT 1 + +/* Bit-encoded input to sam_configgpio() ********************************************/ + +/* 32-bit Encoding: + * + * MMMC CCCC II.. VPPB BBBB + */ + +/* Input/Output mode: + * + * MMM. .... .... .... .... + */ + +#define GPIO_MODE_SHIFT (17) /* Bits 17-23: GPIO mode */ +#define GPIO_MODE_MASK (7 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */ +# define GPIO_PERIPHA (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */ +# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */ +# define GPIO_PERIPHC (4 << GPIO_MODE_SHIFT) /* Controlled by periph C signal */ +# define GPIO_PERIPHD (5 << GPIO_MODE_SHIFT) /* Controlled by periph D signal */ + +/* These bits set the configuration of the pin: + * NOTE: No definitions for parallel capture mode + * + * ...C CCCC .... .... .... + */ + +#define GPIO_CFG_SHIFT (12) /* Bits 12-16: GPIO configuration bits */ +#define GPIO_CFG_MASK (31 << GPIO_CFG_SHIFT) +# define GPIO_CFG_DEFAULT (0 << GPIO_CFG_SHIFT) /* Default, no attribute */ +# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */ +# define GPIO_CFG_PULLDOWN (2 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-down */ +# define GPIO_CFG_DEGLITCH (4 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */ +# define GPIO_CFG_OPENDRAIN (8 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */ +# define GPIO_CFG_SCHMITT (16 << GPIO_CFG_SHIFT) /* Bit 13: Schmitt trigger */ + +/* Additional interrupt modes: + * + * .... .... II.. .... .... + */ + +#define GPIO_INT_SHIFT (10) /* Bits 10-11: GPIO interrupt bits */ +#define GPIO_INT_MASK (3 << GPIO_INT_SHIFT) +# define GPIO_INT_LEVEL (1 << 10) /* Bit 10: Level detection interrupt */ +# define GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */ +# define GPIO_INT_HIGHLEVEL (1 << 9) /* Bit 9: High level detection interrupt */ +# define GPIO_INT_LOWLEVEL (0) /* (vs. Low level detection interrupt) */ +# define GPIO_INT_RISING (1 << 9) /* Bit 9: Rising edge detection interrupt */ +# define GPIO_INT_FALLING (0) /* (vs. Falling edge detection interrupt) */ + +/* If the pin is an GPIO output, then this identifies the initial output value: + * + * .... .... .... V... .... + */ + +#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */ +#define GPIO_OUTPUT_CLEAR (0) + +/* This identifies the GPIO port: + * + * .... .... .... .PP. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */ +#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT_PIOA (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT_PIOB (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT) + +/* This identifies the bit in the port: + * + * .... .... .... ...B BBBB + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/* Must be big enough to hold the 32-bit encoding */ + +typedef uint32_t gpio_pinset_t; + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H */ diff --git a/nuttx/arch/arm/src/sam34/sam4s_periphclks.h b/nuttx/arch/arm/src/sam34/sam4s_periphclks.h new file mode 100644 index 0000000000..071d475ebf --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam4s_periphclks.h @@ -0,0 +1,157 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam4s_periphclks.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H +#define __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include +#include "chip/sam3u_pmc.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helper macros */ + +#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) +#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1) +#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0) +#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1) + +#define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC) +#define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC) +#define sam_rtc_enableclk() sam_enableperiph0(SAM_PID_RTC) +#define sam_rtt_enableclk() sam_enableperiph0(SAM_PID_RTT) +#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT) +#define sam_pmc_enableclk() sam_enableperiph0(SAM_PID_PMC) +#define sam_eefc0_enableclk() sam_enableperiph0(SAM_PID_EEFC0) +#define sam_eefc1_enableclk() sam_enableperiph0(SAM_PID_EEFC1) +#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0) +#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1) +#define sam_smc_enableclk() sam_enableperiph0(SAM_PID_SMC) +#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA) +#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB) +#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC) +#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0) +#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1) +#define sam_hsmci_enableclk() sam_enableperiph0(SAM_PID_HSMCI) +#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0) +#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1) +#define sam_ssc_enableclk() sam_enableperiph0(SAM_PID_SSC) +#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0) +#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1) +#define sam_tc2_enableclk() sam_enableperiph0(SAM_PID_TC2) +#define sam_tc3_enableclk() sam_enableperiph0(SAM_PID_TC3) +#define sam_tc4_enableclk() sam_enableperiph0(SAM_PID_TC4) +#define sam_tc5_enableclk() sam_enableperiph0(SAM_PID_TC5) +#define sam_adc12b_enableclk() sam_enableperiph0(SAM_PID_ADC12B) +#define sam_dacc_enableclk() sam_enableperiph0(SAM_PID_DACC) +#define sam_pwm_enableclk() sam_enableperiph0(SAM_PID_PWM) +#define sam_crccu_enableclk() sam_enableperiph1(SAM_PID_CRCCU) +#define sam_acc_enableclk() sam_enableperiph1(SAM_PID_ACC) +#define sam_udp_enableclk() sam_enableperiph1(SAM_PID_UDP) + +#define sam_supc_disableclk() sam_disableperiph0(SAM_PID_SUPC) +#define sam_rstc_disableclk() sam_disableperiph0(SAM_PID_RSTC) +#define sam_rtc_disableclk() sam_disableperiph0(SAM_PID_RTC) +#define sam_rtt_disableclk() sam_disableperiph0(SAM_PID_RTT) +#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT) +#define sam_pmc_disableclk() sam_disableperiph0(SAM_PID_PMC) +#define sam_eefc0_disableclk() sam_disableperiph0(SAM_PID_EEFC0) +#define sam_eefc1_disableclk() sam_disableperiph0(SAM_PID_EEFC1) +#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0) +#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1) +#define sam_smc_disableclk() sam_disableperiph0(SAM_PID_SMC) +#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA) +#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB) +#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC) +#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0) +#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1) +#define sam_hsmci_disableclk() sam_disableperiph0(SAM_PID_HSMCI) +#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0) +#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1) +#define sam_ssc_disableclk() sam_disableperiph0(SAM_PID_SSC) +#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0) +#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1) +#define sam_tc2_disableclk() sam_disableperiph0(SAM_PID_TC2) +#define sam_tc3_disableclk() sam_disableperiph0(SAM_PID_TC3) +#define sam_tc4_disableclk() sam_disableperiph0(SAM_PID_TC4) +#define sam_tc5_disableclk() sam_disableperiph0(SAM_PID_TC5) +#define sam_adc12b_disableclk() sam_disableperiph0(SAM_PID_ADC) +#define sam_dacc_disableclk() sam_disableperiph0(SAM_PID_DACC) +#define sam_pwm_disableclk() sam_disableperiph0(SAM_PID_PWM) +#define sam_crccu_disableclk() sam_disableperiph1(SAM_PID_CRCCU) +#define sam_acc_disableclk() sam_disableperiph1(SAM_PID_ACC) +#define sam_udp_disableclk() sam_disableperiph1(SAM_PID_UDP) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H */ diff --git a/nuttx/arch/arm/src/sam34/sam_allocateheap.c b/nuttx/arch/arm/src/sam34/sam_allocateheap.c index 390234b710..edacfc6172 100644 --- a/nuttx/arch/arm/src/sam34/sam_allocateheap.c +++ b/nuttx/arch/arm/src/sam34/sam_allocateheap.c @@ -57,7 +57,7 @@ * Private Definitions ****************************************************************************/ -#if CONFIG_MM_REGIONS < 2 +#if CONFIG_MM_REGIONS < 2 && SAM34_SRAM1_SIZE > 0 # warning "CONFIG_MM_REGIONS < 2: SRAM1 not included in HEAP" #endif @@ -66,16 +66,16 @@ #endif #if CONFIG_MM_REGIONS > 2 && defined(CONFIG_SAM34_NAND) -# error "CONFIG_MM_REGIONS > 3 but cannot used NFC SRAM" +# error "CONFIG_MM_REGIONS > 2 but cannot use NFC SRAM" # undef CONFIG_MM_REGIONS # define CONFIG_MM_REGIONS 2 #endif -#if CONFIG_DRAM_END > (SAM_INTSRAM0_BASE+CONFIG_SAM34_SRAM0_SIZE) +#if CONFIG_DRAM_END > (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE) # error "CONFIG_DRAM_END is beyond the end of SRAM0" # undef CONFIG_DRAM_END -# define CONFIG_DRAM_END (SAM_INTSRAM0_BASE+CONFIG_SAM34_SRAM0_SIZE) -#elif CONFIG_DRAM_END < (SAM_INTSRAM0_BASE+CONFIG_SAM34_SRAM0_SIZE) +# define CONFIG_DRAM_END (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE) +#elif CONFIG_DRAM_END < (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE) # warning "CONFIG_DRAM_END is before end of SRAM0... not all of SRAM0 used" #endif @@ -224,25 +224,25 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void up_addregion(void) { -#if CONFIG_SAM34_SRAM1_SIZE > 0 +#if SAM34_SRAM1_SIZE > 0 /* Allow user access to the heap memory */ - sam_mpu_uheap(SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE); + sam_mpu_uheap(SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE); /* Add the region */ - kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE); + kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE); -#if CONFIG_MM_REGIONS > 2 && CONFIG_SAM34_NFCSRAM_SIZE > 0 +#if CONFIG_MM_REGIONS > 2 && SAM34_NFCSRAM_SIZE > 0 /* Allow user access to the heap memory */ - sam_mpu_uheap(SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE); + sam_mpu_uheap(SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); /* Add the region */ - kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE); + kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); -#endif /* CONFIG_MM_REGIONS > 2 && CONFIG_SAM34_NFCSRAM_SIZE > 0 */ -#endif /* CONFIG_SAM34_SRAM1_SIZE > 0 */ +#endif /* CONFIG_MM_REGIONS > 2 && SAM34_NFCSRAM_SIZE > 0 */ +#endif /* SAM34_SRAM1_SIZE > 0 */ } #endif /* CONFIG_MM_REGIONS > 1 */ diff --git a/nuttx/arch/arm/src/sam34/sam_dmac.c b/nuttx/arch/arm/src/sam34/sam_dmac.c index b11199fb17..4f6ede437e 100644 --- a/nuttx/arch/arm/src/sam34/sam_dmac.c +++ b/nuttx/arch/arm/src/sam34/sam_dmac.c @@ -56,7 +56,7 @@ #include "chip.h" #include "sam_dmac.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam_dmac.h" /**************************************************************************** @@ -1160,7 +1160,7 @@ void weak_function up_dmainitialize(void) { /* Enable peripheral clock */ - putreg32((1 << SAM_PID_DMAC), SAM_PMC_PCER); + sam_dmac_enableclk(); /* Disable all DMA interrupts */ diff --git a/nuttx/arch/arm/src/sam34/sam_gpio.h b/nuttx/arch/arm/src/sam34/sam_gpio.h index 53f36c8fb3..fd4e88fd1b 100644 --- a/nuttx/arch/arm/src/sam34/sam_gpio.h +++ b/nuttx/arch/arm/src/sam34/sam_gpio.h @@ -51,6 +51,8 @@ # include "sam3u_gpio.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "sam4l_gpio.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "sam4s_gpio.h" #else # error Unrecognized SAM architecture #endif diff --git a/nuttx/arch/arm/src/sam34/sam_gpioirq.c b/nuttx/arch/arm/src/sam34/sam_gpioirq.c index e5f0364cd9..b7c7ead278 100644 --- a/nuttx/arch/arm/src/sam34/sam_gpioirq.c +++ b/nuttx/arch/arm/src/sam34/sam_gpioirq.c @@ -54,8 +54,9 @@ #include "up_internal.h" #include "sam_gpio.h" -#include "chip/sam_pio.h" -#include "chip/sam_pmc.h" +#include "sam_periphclks.h" +#include "chip/sam3u_pio.h" +#include "chip/sam3u_pmc.h" #ifdef CONFIG_GPIO_IRQ @@ -209,15 +210,12 @@ static int up_gpiocinterrupt(int irq, void *context) void sam_gpioirqinitialize(void) { - uint32_t pcer; - /* Configure GPIOA interrupts */ #ifdef CONFIG_GPIOA_IRQ /* Enable GPIOA clocking */ - pcer |= (1 << SAM_PID_PIOA); - putreg32(pcer, SAM_PMC_PCER); + sam_pioa_enableclk(); /* Clear and disable all GPIOA interrupts */ @@ -235,8 +233,7 @@ void sam_gpioirqinitialize(void) #ifdef CONFIG_GPIOB_IRQ /* Enable GPIOB clocking */ - pcer |= (1 << SAM_PID_PIOB); - putreg32(pcer, SAM_PMC_PCER); + sam_piob_enableclk(); /* Clear and disable all GPIOB interrupts */ @@ -254,8 +251,7 @@ void sam_gpioirqinitialize(void) #ifdef CONFIG_GPIOC_IRQ /* Enable GPIOC clocking */ - pcer |= (1 << SAM_PID_PIOC); - putreg32(pcer, SAM_PMC_PCER); + sam_pioc_enableclk(); /* Clear and disable all GPIOC interrupts */ diff --git a/nuttx/arch/arm/src/sam34/sam_hsmci.c b/nuttx/arch/arm/src/sam34/sam_hsmci.c index f9ee665a80..f44d9fbbac 100644 --- a/nuttx/arch/arm/src/sam34/sam_hsmci.c +++ b/nuttx/arch/arm/src/sam34/sam_hsmci.c @@ -64,7 +64,7 @@ #include "sam_dmac.h" #include "sam_hsmci.h" #include "chip/sam_dmac.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam_hsmci.h" #include "chip/sam_pinmap.h" @@ -644,7 +644,7 @@ static inline void sam_disable(void) { /* Disable the MCI peripheral clock */ - putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCDR); + sam_hsmci_disableclk(); /* Disable the MCI */ @@ -667,7 +667,7 @@ static inline void sam_enable(void) { /* Enable the MCI peripheral clock */ - putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCER); + sam_hsmci_enableclk(); /* Enable the MCI and the Power Saving */ @@ -1223,8 +1223,7 @@ static void sam_reset(FAR struct sdio_dev_s *dev) /* Enable the MCI clock */ flags = irqsave(); - putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCER); - fdbg("PCSR: %08x\n", getreg32(SAM_PMC_PCSR)); + sam_hsmci_enableclk(); /* Reset the MCI */ diff --git a/nuttx/arch/arm/src/sam34/sam_irq.c b/nuttx/arch/arm/src/sam34/sam_irq.c index f212742114..00c88a7c1c 100644 --- a/nuttx/arch/arm/src/sam34/sam_irq.c +++ b/nuttx/arch/arm/src/sam34/sam_irq.c @@ -221,18 +221,51 @@ static inline void sam_prioritize_syscall(int priority) static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) { + unsigned int extint = irq - SAM_IRQ_EXTINT; + DEBUGASSERT(irq >= SAM_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ if (irq >= SAM_IRQ_EXTINT) { - if (irq < SAM_IRQ_NIRQS) +#if SAM_IRQ_NEXTINT <= 32 + if (extint < SAM_IRQ_NEXTINT) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << extint; + } + else +#elif SAM_IRQ_NEXTINT <= 64 + if (extint < 32) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << extint; + } + else if (extint < SAM_IRQ_NEXTINT) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (extint - 32); + } + else +#elif SAM_IRQ_NEXTINT <= 96 + if (extint < 32) { *regaddr = NVIC_IRQ0_31_ENABLE; - *bit = 1 << (irq - SAM_IRQ_EXTINT); + *bit = 1 << extint; + } + else if (extint < 64) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (extint - 32); + } + else if (extint < SAM_IRQ_NEXTINT) + { + *regaddr = NVIC_IRQ64_95_ENABLE; + *bit = 1 << (extint - 64); } else +#endif { return ERROR; /* Invalid interrupt */ } @@ -279,9 +312,35 @@ static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) void up_irqinitialize(void) { - /* Disable all interrupts */ + uintptr_t regaddr; +#if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) + uint32_t regval; +#endif + int nintlines; + int i; - putreg32(0, NVIC_IRQ0_31_ENABLE); + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } /* Set up the vector table address. * @@ -291,24 +350,26 @@ void up_irqinitialize(void) #if defined(CONFIG_ARCH_RAMVECTORS) up_ramvec_initialize(); -#elif defined(CONFIG_STM32_DFU) +#elif defined(CONFIG_SAM_BOOTLOADER) putreg32((uint32_t)sam_vectors, NVIC_VECTAB); #endif - /* Set all interrrupts (and exceptions) to the default priority */ + /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ + + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } /* currents_regs is non-NULL only while processing an interrupt */ @@ -357,8 +418,18 @@ void up_irqinitialize(void) sam_dumpnvic("initial", SAM_IRQ_NIRQS); -#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* If a debugger is connected, try to prevent it from catching hardfaults. + * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal + * operation. + */ + +#if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) + regval = getreg32(NVIC_DEMCR); + regval &= ~NVIC_DEMCR_VCHARDERR; + putreg32(regval, NVIC_DEMCR); +#endif +#ifndef CONFIG_SUPPRESS_INTERRUPTS /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ diff --git a/nuttx/arch/arm/src/sam34/sam_lowputc.c b/nuttx/arch/arm/src/sam34/sam_lowputc.c index 00a3d3a895..55ab7555b6 100644 --- a/nuttx/arch/arm/src/sam34/sam_lowputc.c +++ b/nuttx/arch/arm/src/sam34/sam_lowputc.c @@ -48,9 +48,19 @@ #include "up_arch.h" #include "sam_gpio.h" +#include "sam_periphclks.h" #include "sam_lowputc.h" -#include "chip/sam_pmc.h" -#include "chip/sam_uart.h" + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "chip/sam3u_uart.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_usart.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam3u_uart.h" +#else +# error Unknown UART +#endif + #include "chip/sam_pinmap.h" /************************************************************************** @@ -76,40 +86,54 @@ # undef CONFIG_SAM34_USART3 #endif -/* Is there a serial console? It could be on the UART, or USARTn */ +/* Is there a serial console? It could be on UART0-1 or USART0-3 */ -#if defined(CONFIG_UART_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART0) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART1) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART2) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART3) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #else -# undef CONFIG_USART_SERIAL_CONSOLE +# warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -117,14 +141,37 @@ # undef HAVE_CONSOLE #endif +/* Select MCU-specific settings + * + * For the SAM3U, the USARTs are driven by the main clock. + * For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is + * selected by the PBADIVMASK register. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ +# define SAM_USART_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# define SAM_MR_USCLKS UART_MR_USCLKS_USART /* Source = USART_CLK (undefined) */ +# define SAM_USART_CLOCK BOARD_PBA_FREQUENCY /* PBA frequency is undivided */ +#else +# error Unrecognized SAM architecture +#endif + /* Select USART parameters for the selected console */ -#if defined(CONFIG_UART_SERIAL_CONSOLE) -# define SAM_CONSOLE_BASE SAM_UART_BASE -# define SAM_CONSOLE_BAUD CONFIG_UART_BAUD -# define SAM_CONSOLE_BITS CONFIG_UART_BITS -# define SAM_CONSOLE_PARITY CONFIG_UART_PARITY -# define SAM_CONSOLE_2STOP CONFIG_UART_2STOP +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define SAM_CONSOLE_BASE SAM_UART0_BASE +# define SAM_CONSOLE_BAUD CONFIG_UART0_BAUD +# define SAM_CONSOLE_BITS CONFIG_UART0_BITS +# define SAM_CONSOLE_PARITY CONFIG_UART0_PARITY +# define SAM_CONSOLE_2STOP CONFIG_UART0_2STOP +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define SAM_CONSOLE_BASE SAM_UART1_BASE +# define SAM_CONSOLE_BAUD CONFIG_UART1_BAUD +# define SAM_CONSOLE_BITS CONFIG_UART1_BITS +# define SAM_CONSOLE_PARITY CONFIG_UART1_PARITY +# define SAM_CONSOLE_2STOP CONFIG_UART1_2STOP #elif defined(CONFIG_USART0_SERIAL_CONSOLE) # define SAM_CONSOLE_BASE SAM_USART0_BASE # define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD @@ -156,15 +203,16 @@ /* Select the settings for the mode register */ #if SAM_CONSOLE_BITS == 5 -# define MR_CHRL_VALUE USART_MR_CHRL_5BITS /* 5 bits */ +# define MR_CHRL_VALUE UART_MR_CHRL_5BITS /* 5 bits */ #elif SAM_CONSOLE_BITS == 6 -# define MR_CHRL_VALUE USART_MR_CHRL_6BITS /* 6 bits */ +# define MR_CHRL_VALUE UART_MR_CHRL_6BITS /* 6 bits */ #elif SAM_CONSOLE_BITS == 7 -# define MR_CHRL_VALUE USART_MR_CHRL_7BITS /* 7 bits */ +# define MR_CHRL_VALUE UART_MR_CHRL_7BITS /* 7 bits */ #elif SAM_CONSOLE_BITS == 8 -# define MR_CHRL_VALUE USART_MR_CHRL_8BITS /* 8 bits */ -#elif SAM_CONSOLE_BITS == 9 && !defined(CONFIG_UART_SERIAL_CONSOLE) -# define MR_CHRL_VALUE USART_MR_MODE9 +# define MR_CHRL_VALUE UART_MR_CHRL_8BITS /* 8 bits */ +#elif SAM_CONSOLE_BITS == 9 && !defined(CONFIG_UART0_SERIAL_CONSOLE) && \ + !defined(CONFIG_UART1_SERIAL_CONSOLE) +# define MR_CHRL_VALUE UART_MR_MODE9 #else # error "Invlaid number of bits" #endif @@ -178,12 +226,12 @@ #endif #if SAM_CONSOLE_2STOP != 0 -# define MR_NBSTOP_VALUE USART_MR_NBSTOP_2 +# define MR_NBSTOP_VALUE UART_MR_NBSTOP_2 #else -# define MR_NBSTOP_VALUE USART_MR_NBSTOP_1 +# define MR_NBSTOP_VALUE UART_MR_NBSTOP_1 #endif -#define MR_VALUE (USART_MR_MODE_NORMAL | USART_MR_USCLKS_MCK | \ +#define MR_VALUE (UART_MR_MODE_NORMAL | SAM_MR_USCLKS | \ MR_CHRL_VALUE | MR_PAR_VALUE | MR_NBSTOP_VALUE) /************************************************************************** @@ -241,69 +289,81 @@ void up_lowputc(char ch) void sam_lowsetup(void) { - uint32_t regval; - /* Enable clocking for all selected UART/USARTs */ - regval = 0; -#ifdef CONFIG_SAM34_UART - regval |= (1 << SAM_PID_UART); +#ifdef CONFIG_SAM34_UART0 + sam_uart0_enableclk(); +#endif +#ifdef CONFIG_SAM34_UART1 + sam_uart1_enableclk(); #endif #ifdef CONFIG_SAM34_USART0 - regval |= (1 << SAM_PID_USART0); + sam_usart0_enableclk(); #endif #ifdef CONFIG_SAM34_USART1 - regval |= (1 << SAM_PID_USART1); + sam_usart1_enableclk(); #endif #ifdef CONFIG_SAM34_USART2 - regval |= (1 << SAM_PID_USART2); + sam_usart2_enableclk(); #endif #ifdef CONFIG_SAM34_USART3 - regval |= (1 << SAM_PID_USART3); + sam_usart3_enableclk(); #endif - putreg32(regval, SAM_PMC_PCER); /* Configure UART pins for all selected UART/USARTs */ -#ifdef CONFIG_SAM34_UART - (void)sam_configgpio(GPIO_UART_RXD); - (void)sam_configgpio(GPIO_UART_TXD); +#ifdef CONFIG_SAM34_UART0 + (void)sam_configgpio(GPIO_UART0_RXD); + (void)sam_configgpio(GPIO_UART0_TXD); #endif + +#ifdef CONFIG_SAM34_UART1 + (void)sam_configgpio(GPIO_UART1_RXD); + (void)sam_configgpio(GPIO_UART1_TXD); +#endif + #ifdef CONFIG_SAM34_USART0 (void)sam_configgpio(GPIO_USART0_RXD); (void)sam_configgpio(GPIO_USART0_TXD); +#ifdef CONFIG_USART0_OFLOWCONTROL (void)sam_configgpio(GPIO_USART0_CTS); +#endif +#ifdef CONFIG_USART0_IFLOWCONTROL (void)sam_configgpio(GPIO_USART0_RTS); #endif +#endif + #ifdef CONFIG_SAM34_USART1 (void)sam_configgpio(GPIO_USART1_RXD); (void)sam_configgpio(GPIO_USART1_TXD); +#ifdef CONFIG_USART1_OFLOWCONTROL (void)sam_configgpio(GPIO_USART1_CTS); +#endif +#ifdef CONFIG_USART1_IFLOWCONTROL (void)sam_configgpio(GPIO_USART1_RTS); #endif +#endif + #ifdef CONFIG_SAM34_USART2 (void)sam_configgpio(GPIO_USART2_RXD); (void)sam_configgpio(GPIO_USART2_TXD); +#ifdef CONFIG_USART2_OFLOWCONTROL (void)sam_configgpio(GPIO_USART2_CTS); +#endif +#ifdef CONFIG_USART2_IFLOWCONTROL (void)sam_configgpio(GPIO_USART2_RTS); #endif +#endif + #ifdef CONFIG_SAM34_USART3 (void)sam_configgpio(GPIO_USART3_RXD); (void)sam_configgpio(GPIO_USART3_TXD); +#ifdef CONFIG_USART3_OFLOWCONTROL (void)sam_configgpio(GPIO_USART3_CTS); - (void)sam_configgpio(GPIO_USART3_RTS); #endif - -#ifdef GPIO_CONSOLE_RXD -#endif -#ifdef GPIO_CONSOLE_TXD - (void)sam_configgpio(GPIO_CONSOLE_TXD); -#endif -#ifdef GPIO_CONSOLE_CTS - (void)sam_configgpio(GPIO_CONSOLE_CTS); +#ifdef CONFIG_USART3_IFLOWCONTROL + (void)sam_configgpio(GPIO_USART3_RTS); #endif -#ifdef GPIO_CONSOLE_RTS - (void)sam_configgpio(GPIO_CONSOLE_RTS); #endif /* Configure the console (only) */ @@ -321,9 +381,11 @@ void sam_lowsetup(void) putreg32(MR_VALUE, SAM_CONSOLE_BASE + SAM_UART_MR_OFFSET); - /* Configure the console baud */ + /* Configure the console baud. NOTE: Oversampling by 8 is not supported. + * This may limit BAUD rates for lower USART clocks. + */ - putreg32(((SAM_MCK_FREQUENCY + (SAM_CONSOLE_BAUD << 3))/(SAM_CONSOLE_BAUD << 4)), + putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)), SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET); /* Enable receiver & transmitter */ diff --git a/nuttx/arch/arm/src/sam34/sam_periphclks.h b/nuttx/arch/arm/src/sam34/sam_periphclks.h new file mode 100644 index 0000000000..43fb6dc899 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam_periphclks.h @@ -0,0 +1,92 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam_periphclks.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM_PERIPHCLKS_H +#define __ARCH_ARM_SRC_SAM34_SAM_PERIPHCLKS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "sam3u_periphclks.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "sam4l_periphclks.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "sam4s_periphclks.h" +#else +# error Unknown SAM chip +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM_PERIPHCLKS_H */ diff --git a/nuttx/arch/arm/src/sam34/sam_serial.c b/nuttx/arch/arm/src/sam34/sam_serial.c index fb7d69cba0..2afc302e54 100644 --- a/nuttx/arch/arm/src/sam34/sam_serial.c +++ b/nuttx/arch/arm/src/sam34/sam_serial.c @@ -60,7 +60,13 @@ #include "os_internal.h" #include "chip.h" -#include "chip/sam_uart.h" +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam3u_uart.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_usart.h" +#else +# error Unknown UART +#endif /**************************************************************************** * Definitions @@ -87,9 +93,9 @@ /* Is there a USART/USART enabled? */ -#if !defined(CONFIG_SAM34_UART) && !defined(CONFIG_SAM34_USART0) && \ - !defined(CONFIG_SAM34_USART1) && !defined(CONFIG_SAM34_USART2) && \ - !defined(CONFIG_SAM34_USART3) +#if !defined(CONFIG_SAM34_UART0) && !defined(CONFIG_SAM34_UART1) && \ + !defined(CONFIG_SAM34_USART0) && !defined(CONFIG_SAM34_USART1) && \ + !defined(CONFIG_SAM34_USART2) && !defined(CONFIG_SAM34_USART3) # error "No USARTs enabled" #endif @@ -98,41 +104,54 @@ # define HAVE_USART #endif -/* Is there a serial console? */ +/* Is there a serial console? It could be on UART0-1 or USART0-3 */ -#if defined(CONFIG_UART_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART0) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART1) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART2) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART3) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #else # warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting" -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -146,405 +165,165 @@ #ifdef USE_SERIALDRIVER -/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? tty4? */ - -#if defined(CONFIG_UART_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uartport /* UART=console */ -# define TTYS0_DEV g_uartport /* UART=ttyS0 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* UART=ttyS0;USART0=ttyS1 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* UART=ttyS0;USART0=ttyS1;USART1=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* UART=ttyS0;USART0=ttyS1;USART2=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART2=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* UART=ttyS0;USART0=ttyS1;USART2=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* UART=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* UART=ttyS0;USART1=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* UART=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* UART=ttyS0;USART1=ttyS1;USART2=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* UART=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* UART=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* UART=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* UART=ttyS0;USART2=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* UART=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* UART=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* UART=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* UART=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? tty4? tty5? */ + +/* First pick the console and ttys0. This could be any of UART0-1, USART0-3 */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart0port /* USART0=console */ -# define TTYS0_DEV g_usart0port /* USART0=ttyS0 */ -# ifdef CONFIG_SAM34_UART -# define TTYS1_DEV g_uartport /* USART0=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2;USART2=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2;USART2=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2;USART2=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;UART=ttyS1;USART1=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART0=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART2=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART0=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* USART0=ttyS0;USART1=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART0=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART0=ttyS0;USART1=ttyS1;USART2=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART0=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART0=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* USART0=ttyS0;USART2=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART0=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* USART0=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART0=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +# define CONSOLE_DEV g_usart0port /* USART0 is console */ +# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ +# define USART0_ASSIGNED 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart1port /* USART1=console */ -# define TTYS0_DEV g_usart1port /* USART1=ttyS0 */ -# ifdef CONFIG_SAM34_UART -# define TTYS1_DEV g_uartport /* USART1=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS2_DEV g_usart0port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2;USART2=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2;USART2=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2;USART2=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;UART=ttyS1;USART0=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART1=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART2=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART1=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* USART1=ttyS0;USART0=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART1=ttyS0;USART0=ttyS1;USART2=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART1=ttyS0;USART0=ttyS1;USART2=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;USART0=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART1=ttyS0;USART0=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART1=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* USART1=ttyS0;USART2=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART1=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* USART1=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART1=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +# define CONSOLE_DEV g_usart1port /* USART1 is console */ +# define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */ +# define USART1_ASSIGNED 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart2port /* USART2=console */ -# define TTYS0_DEV g_usart2port /* USART2=ttyS0 */ -# ifdef CONFIG_SAM34_UART -# define TTYS1_DEV g_uartport /* USART2=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS2_DEV g_usart0port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS3_DEV g_usart1port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART2=ttyS0;UART=ttyS1;USART0=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART2=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART1=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART2=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART2=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* USART2=ttyS0;USART0=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART2=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART2=ttyS0;USART0=ttyS1;USART1=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART2=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART2=ttyS0;USART0=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART2=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* USART2=ttyS0;USART1=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART2=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART2=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* USART2=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART2=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +# define CONSOLE_DEV g_usart2port /* USART2 is console */ +# define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */ +# define USART2_ASSIGNED 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart3port /* USART3=console */ -# define TTYS0_DEV g_usart3port /* USART3=ttyS0 */ -# ifdef CONFIG_SAM34_UART -# define TTYS1_DEV g_uartport /* USART3=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS2_DEV g_usart0port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS3_DEV g_usart1port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS4_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;USART2=ttyS4 */ -# else -# undef TTYS4_DEV /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS;USART2=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART3=ttyS0;UART=ttyS1;USART0=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART3=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART1=ttys2;USART2=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART3=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART3=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* USART3=ttyS0;USART0=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART3=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART3=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART3=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART3=ttyS0;USART0=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART3=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* USART3=ttyS0;USART1=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_EEEEport /* USART3=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART3=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* USART3=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART3=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ +# define CONSOLE_DEV g_usart3port /* USART3 is console */ +# define TTYS5_DEV g_usart3port /* USART3 is ttyS0 */ +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_SAM34_UART0) +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_SAM34_UART1) +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART0) +# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ +# define USART0_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART1) +# define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */ +# define USART1_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART2) +# define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */ +# define USART2_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART3) +# define TTYS0_DEV g_usart3port /* USART3 is ttyS0 */ +# define USART3_ASSIGNED 1 # endif #endif +/* Pick ttys1. This could be any of UART0-1, USART0-3 excluding the console UART. */ + +#if defined(CONFIG_SAM34_UART0) && !defined(UART0_ASSIGNED) +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_UART1) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED) +# define TTYS1_DEV g_usart0port /* USART0 is ttyS1 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS1_DEV g_usart1port /* USART1 is ttyS1 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS1_DEV g_usart2port /* USART2 is ttyS1 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS1_DEV g_usart3port /* USART3 is ttyS1 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys2. This could be one of UART1 or USART0-3. It can't be UART0 + * because that was either assigned as ttyS0 or ttys1. One of these + * could also be the console. + */ + +#if defined(CONFIG_SAM34_UART1) && !defined(UART1_ASSIGNED) +# define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED) +# define TTYS2_DEV g_usart0port /* USART0 is ttyS2 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS2_DEV g_usart1port /* USART1 is ttyS2 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS2_DEV g_usart2port /* USART2 is ttyS2 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS2_DEV g_usart3port /* USART3 is ttyS2 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys3. This could be one of USART0-3. It can't be UART0-1 because + * those have already been assigned to ttsyS0, 1, or 2. One of + * USART0-3 could also be the console. + */ + +#if defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED) +# define TTYS3_DEV g_usart0port /* USART0 is ttyS3 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS3_DEV g_usart1port /* USART1 is ttyS3 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS3_DEV g_usart2port /* USART2 is ttyS3 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS3_DEV g_usart3port /* USART3 is ttyS3 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys4. This could be one of USART1-3. It can't be UART0-1 or USART0 + * because those have already been assigned to ttsyS0, 1, 2 or 3. One of + * USART1-3 could also be the console. + */ + +#if defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS4_DEV g_usart1port /* USART1 is ttyS4 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS4_DEV g_usart2port /* USART2 is ttyS4 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS4_DEV g_usart3port /* USART3 is ttyS4 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys5. This could be one of USART2-3. It can't be UART0-1 or + * USART0-1 because those have already been assigned to ttsyS0, 1, 2, + * 3 or 4. One of USART2-3 could also be the console. + */ + +#if defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS5_DEV g_usart2port /* USART2 is ttyS5 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS5_DEV g_usart3port /* USART3 is ttyS5 */ +# define USART3_ASSIGNED 1 +#endif + +/* Select MCU-specific settings + * + * For the SAM3U, the USARTs are driven by the main clock. + * For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is + * selected by the PBADIVMASK register. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ +# define SAM_USART_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# define SAM_MR_USCLKS UART_MR_USCLKS_USART /* Source = USART_CLK (undefined) */ +# define SAM_USART_CLOCK BOARD_PBA_FREQUENCY /* PBA frequency is undivided */ +#else +# error Unrecognized SAM architecture +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -601,9 +380,13 @@ static const struct uart_ops_s g_uart_ops = /* I/O buffers */ -#ifdef CONFIG_SAM34_UART -static char g_uartrxbuffer[CONFIG_UART_RXBUFSIZE]; -static char g_uarttxbuffer[CONFIG_UART_TXBUFSIZE]; +#ifdef CONFIG_SAM34_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_SAM34_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; #endif #ifdef CONFIG_SAM34_USART0 static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE]; @@ -622,33 +405,63 @@ static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; #endif -/* This describes the state of the UART port. */ +/* This describes the state of the UART0 port. */ -#ifdef CONFIG_SAM34_UART -static struct up_dev_s g_uartpriv = +#ifdef CONFIG_SAM34_UART0 +static struct up_dev_s g_uart0priv = { - .usartbase = SAM_UART_BASE, - .baud = CONFIG_UART_BAUD, - .irq = SAM_IRQ_UART, - .parity = CONFIG_UART_PARITY, - .bits = CONFIG_UART_BITS, - .stopbits2 = CONFIG_UART_2STOP, + .usartbase = SAM_UART0_BASE, + .baud = CONFIG_UART0_BAUD, + .irq = SAM_IRQ_UART0, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, }; -static uart_dev_t g_uartport = +static uart_dev_t g_uart0port = { .recv = { - .size = CONFIG_UART_RXBUFSIZE, - .buffer = g_uartrxbuffer, + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, }, .xmit = { - .size = CONFIG_UART_TXBUFSIZE, - .buffer = g_uarttxbuffer, + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, }, .ops = &g_uart_ops, - .priv = &g_uartpriv, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the UART1 port. */ + +#ifdef CONFIG_SAM34_UART1 +static struct up_dev_s g_uart1priv = +{ + .usartbase = SAM_UART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irq = SAM_IRQ_UART1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, }; #endif @@ -873,37 +686,38 @@ static int up_setup(struct uart_dev_s *dev) * as the timing source */ - regval = (USART_MR_MODE_NORMAL|USART_MR_USCLKS_MCK); + regval = (UART_MR_MODE_NORMAL | SAM_MR_USCLKS); /* OR in settings for the selected number of bits */ if (priv->bits == 5) { - regval |= USART_MR_CHRL_5BITS; /* 5 bits */ + regval |= UART_MR_CHRL_5BITS; /* 5 bits */ } else if (priv->bits == 6) { - regval |= USART_MR_CHRL_6BITS; /* 6 bits */ + regval |= UART_MR_CHRL_6BITS; /* 6 bits */ } else if (priv->bits == 7) { - regval |= USART_MR_CHRL_7BITS; /* 7 bits */ + regval |= UART_MR_CHRL_7BITS; /* 7 bits */ } #ifdef HAVE_USART -#ifdef CONFIG_SAM34_UART - /* UART does not support 9bit mode */ - - else if (priv->bits == 9 && priv->usartbase != SAM_UART_BASE) -#else - else if (priv->bits == 9) /* Only USARTS */ + else if (priv->bits == 9 +#if defined(CONFIG_SAM34_UART0) + && priv->usartbase != SAM_UART0_BASE #endif +#if defined(CONFIG_SAM34_UART1) + && priv->usartbase != SAM_UART1_BASE +#endif + ) { - regval |= USART_MR_MODE9; /* 9 bits */ + regval |= UART_MR_MODE9; /* 9 bits */ } #endif else /* if (priv->bits == 8) */ { - regval |= USART_MR_CHRL_8BITS; /* 8 bits (default) */ + regval |= UART_MR_CHRL_8BITS; /* 8 bits (default) */ } /* OR in settings for the selected parity */ @@ -925,20 +739,22 @@ static int up_setup(struct uart_dev_s *dev) if (priv->stopbits2) { - regval |= USART_MR_NBSTOP_2; + regval |= UART_MR_NBSTOP_2; } else { - regval |= USART_MR_NBSTOP_1; + regval |= UART_MR_NBSTOP_1; } /* And save the new mode register value */ up_serialout(priv, SAM_UART_MR_OFFSET, regval); - /* Configure the console baud */ + /* Configure the console baud. NOTE: Oversampling by 8 is not supported. + * This may limit BAUD rates for lower USART clocks. + */ - regval = (SAM_MCK_FREQUENCY + (priv->baud << 3))/(priv->baud << 4); + regval = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4); up_serialout(priv, SAM_UART_BRGR_OFFSET, regval); /* Enable receiver & transmitter */ @@ -1042,10 +858,17 @@ static int up_interrupt(int irq, void *context) int passes; bool handled; -#ifdef CONFIG_SAM34_UART - if (g_uartpriv.irq == irq) +#ifdef CONFIG_SAM34_UART0 + if (g_uart0priv.irq == irq) { - dev = &g_uartport; + dev = &g_uart0port; + } + else +#endif +#ifdef CONFIG_SAM34_UART1 + if (g_uart1priv.irq == irq) + { + dev = &g_uart1port; } else #endif @@ -1094,7 +917,7 @@ static int up_interrupt(int irq, void *context) /* Get the UART/USART status (we are only interested in the unmasked interrupts). */ priv->sr = up_serialin(priv, SAM_UART_SR_OFFSET); /* Save for error reporting */ - pending = priv->sr & priv->imr; /* Mask out disabled interrupt sources */ + pending = priv->sr & priv->imr; /* Mask out disabled interrupt sources */ /* Handle an incoming, receive byte. RXRDY: At least one complete character * has been received and US_RHR has not yet been read. @@ -1285,6 +1108,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) priv->imr &= ~UART_INT_TXRDY; up_disableint(priv); } + irqrestore(flags); } diff --git a/nuttx/arch/arm/src/sam34/sam_spi.c b/nuttx/arch/arm/src/sam34/sam_spi.c index 10395ec90f..2143a5c15c 100644 --- a/nuttx/arch/arm/src/sam34/sam_spi.c +++ b/nuttx/arch/arm/src/sam34/sam_spi.c @@ -57,7 +57,8 @@ #include "chip.h" #include "sam_gpio.h" #include "sam_spi.h" -#include "chip/sam_pmc.h" +#include "sam_periphclks.h" +#include "chip/sam3u_pmc.h" #include "chip/sam_spi.h" #include "chip/sam_pinmap.h" @@ -66,6 +67,19 @@ /**************************************************************************** * Definitions ****************************************************************************/ +/* Select MCU-specific settings + * + * For the SAM3U, SPI is driven by the main clock. + * For the SAM4L, SPI driven by CLK_SPI which is the PBB clock. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SPI_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# define SAM_SPI_CLOCK BOARD_PBB_FREQUENCY /* PBB frequency */ +#else +# error Unrecognized SAM architecture +#endif /* Check if SPI debut is enabled (non-standard.. no support in * include/debug.h @@ -461,7 +475,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * SPCK frequency = MCK / SCBR, or SCBR = MCK / frequency */ - scbr = SAM_MCK_FREQUENCY / frequency; + scbr = SAM_SPI_CLOCK / frequency; if (scbr < 8) { @@ -493,7 +507,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * DLYBS = MCK * 0.000002 = MCK / 500000 */ - dlybs = SAM_MCK_FREQUENCY / 500000; + dlybs = SAM_SPI_CLOCK / 500000; regval |= dlybs << SPI_CSR_DLYBS_SHIFT; /* DLYBCT: Delay Between Consecutive Transfers. This field defines the delay @@ -508,13 +522,13 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * DLYBCT = MCK * 0.000005 / 32 = MCK / 200000 / 32 */ - dlybct = SAM_MCK_FREQUENCY / 200000 / 32; + dlybct = SAM_SPI_CLOCK / 200000 / 32; regval |= dlybct << SPI_CSR_DLYBCT_SHIFT; putreg32(regval, regaddr); /* Calculate the new actual frequency */ - actual = SAM_MCK_FREQUENCY / scbr; + actual = SAM_SPI_CLOCK / scbr; spivdbg("csr[%08x]=%08x actual=%d\n", regaddr, regval, actual); /* Save the frequency setting */ @@ -886,7 +900,6 @@ FAR struct spi_dev_s *up_spiinitialize(int port) { FAR struct sam_spidev_s *priv = &g_spidev; irqstate_t flags; - uint32_t regval; /* The SAM3U has only a single SPI port */ @@ -897,15 +910,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port) priv->cs = 0xff; - /* Apply power to the SPI block */ + /* Enable clocking to the SPI block */ - flags = irqsave(); - regval = getreg32(SAM_PMC_PCER); - regval |= (1 << SAM_PID_SPI); -#ifdef CONFIG_SAM34_SPIINTERRUPT - regval |= (1 << SAM_IRQ_SPI); -#endif - putreg32(regval, SAM_PMC_PCER); + sam_spi_enableclk(); /* Configure multiplexed pins as connected on the board. Chip select pins * must be configured by board-specific logic. diff --git a/nuttx/arch/arm/src/sam34/sam_start.c b/nuttx/arch/arm/src/sam34/sam_start.c index a3fc49fa29..6324617f3f 100644 --- a/nuttx/arch/arm/src/sam34/sam_start.c +++ b/nuttx/arch/arm/src/sam34/sam_start.c @@ -54,8 +54,11 @@ #include "sam_userspace.h" /**************************************************************************** - * Private Definitions + * Pre-processor Definitions ****************************************************************************/ +#if defined(CONFIG_WDT_ENABLED_ON_RESET) && defined(CONFIG_WDT_DISABLE_ON_RESET) +# define NEED_WDT_DISABLE +#endif /**************************************************************************** * Private Data @@ -100,12 +103,6 @@ void __start(void) const uint32_t *src; uint32_t *dest; - /* Configure the uart so that we can get debug output as soon as possible */ - - sam_clockconfig(); - sam_lowsetup(); - showprogress('A'); - /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. */ @@ -114,7 +111,6 @@ void __start(void) { *dest++ = 0; } - showprogress('B'); /* Move the intialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is @@ -126,14 +122,38 @@ void __start(void) { *dest++ = *src++; } - showprogress('C'); + +#ifdef NEED_WDT_DISABLE + /* Disable the watchdog timer */ +# warning Missing logic +#endif + + /* Copy any necessary code sections from FLASH to RAM. The correct + * destination in SRAM is geive by _sramfuncs and _eramfuncs. The + * temporary location is in flash after the data initalization code + * at _framfuncs. This must be done before sam_clockconfig() can be + * called (at least for the SAM4L family). + */ + +#ifdef CONFIG_ARCH_RAMFUNCS + for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; ) + { + *dest++ = *src++; + } +#endif + + /* Configure the uart so that we can get debug output as soon as possible */ + + sam_clockconfig(); + sam_lowsetup(); + showprogress('A'); /* Perform early serial initialization */ #ifdef USE_EARLYSERIALINIT up_earlyserialinit(); #endif - showprogress('D'); + showprogress('B'); /* For the case of the separate user-/kernel-space build, perform whatever * platform specific initialization of the user memory is required. @@ -143,13 +163,13 @@ void __start(void) #ifdef CONFIG_NUTTX_KERNEL sam_userspace(); - showprogress('E'); + showprogress('C'); #endif /* Initialize onboard resources */ sam_boardinitialize(); - showprogress('F'); + showprogress('D'); /* Then start NuttX */ diff --git a/nuttx/arch/arm/src/sam34/sam_timerisr.c b/nuttx/arch/arm/src/sam34/sam_timerisr.c index e1879d5cc1..572b046267 100644 --- a/nuttx/arch/arm/src/sam34/sam_timerisr.c +++ b/nuttx/arch/arm/src/sam34/sam_timerisr.c @@ -55,6 +55,20 @@ /**************************************************************************** * Definitions ****************************************************************************/ +/* Select MCU-specific settings + * + * For the SAM3U, Systick is driven by the main clock. + * For the SAM4L, Systick is driven by the CPU clock which is just the main + * clock divided down. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SYSTICK_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) || defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* CPU frequency */ +#else +# error Unrecognized SAM architecture +#endif /* The desired timer interrupt frequency is provided by the definition * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of @@ -69,9 +83,9 @@ #undef CONFIG_SAM34_SYSTICK_HCLKd8 /* Power up default is MCK, not MCK/8 */ #if CONFIG_SAM34_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((SAM_MCK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((SAM_MCK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value diff --git a/nuttx/arch/arm/src/sam34/sam_vectors.S b/nuttx/arch/arm/src/sam34/sam_vectors.S index 007367857c..c6a11b31e1 100644 --- a/nuttx/arch/arm/src/sam34/sam_vectors.S +++ b/nuttx/arch/arm/src/sam34/sam_vectors.S @@ -61,19 +61,23 @@ * 0x2000:bfff - End of SRAM and end of heap */ -#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE) +#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) #define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE) /************************************************************************************************ * Global Symbols ************************************************************************************************/ - .globl __start - .syntax unified .thumb .file "sam_vectors.S" +/* Check if common ARMv7 interrupt vectoring is used (see arch/arm/src/armv7-m/up_vectors.S) */ + +#ifndef CONFIG_ARMV7M_CMNVECTOR + + .globl __start + /************************************************************************************************ * Macros ************************************************************************************************/ @@ -128,14 +132,16 @@ sam_vectors: #define VECTOR(l,i) .word l #undef UNUSED -#define UNUSED(i) .word stm32_reserved +#define UNUSED(i) .word sam_reserved #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_vectors.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_vectors.h" #else -# Unrecognized SAM architecture +# error Unrecognized SAM architecture #endif .size sam_vectors, .-sam_vectors @@ -169,8 +175,10 @@ handlers: # include "chip/sam3u_vectors.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_vectors.h" #else -# Unrecognized SAM architecture +# error Unrecognized SAM architecture #endif /* Common IRQ handling logic. On entry here, the return stack is on either @@ -293,8 +301,8 @@ sam_common: #endif /* We are returning with a pending context switch. This case is different - * because in this case, the register save structure does not lie on the - * stack but, rather, are within a TCB structure. We'll have to copy some + * because in this case, the register save structure does not lie in the + * stack but, rather, within a TCB structure. We'll have to copy some * values to the stack. */ @@ -401,6 +409,7 @@ up_interruptstack: g_intstackbase: .size up_interruptstack, .-up_interruptstack #endif +#endif /* CONFIG_ARMV7M_CMNVECTOR */ /************************************************************************************************ * .rodata diff --git a/nuttx/arch/arm/src/stm32/stm32_otgfshost.c b/nuttx/arch/arm/src/stm32/stm32_otgfshost.c index 80a9392dc9..4b9eeb6c2d 100644 --- a/nuttx/arch/arm/src/stm32/stm32_otgfshost.c +++ b/nuttx/arch/arm/src/stm32/stm32_otgfshost.c @@ -1,7 +1,7 @@ /******************************************************************************* * arch/arm/src/stm32/stm32_otgfshost.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -2176,7 +2176,7 @@ static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv) { /* Were we previously connected? */ - if (!priv->connected) + if (priv->connected) { /* Yes.. then we no longer connected */ diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c index b172a224f6..52a77e2558 100644 --- a/nuttx/arch/arm/src/stm32/stm32_serial.c +++ b/nuttx/arch/arm/src/stm32/stm32_serial.c @@ -257,15 +257,23 @@ struct up_dev_s uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (7 or 8) */ bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL bool oflow; /* output flow control (CTS) enabled */ +#endif uint32_t baud; /* Configured baud */ #else const uint8_t parity; /* 0=none, 1=odd, 2=even */ const uint8_t bits; /* Number of bits (7 or 8) */ const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL const bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL const bool oflow; /* output flow control (CTS) enabled */ +#endif const uint32_t baud; /* Configured baud */ #endif @@ -274,8 +282,12 @@ struct up_dev_s const uint32_t usartbase; /* Base address of USART registers */ const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ +#endif #ifdef SERIAL_HAVE_DMA const unsigned int rxdma_channel; /* DMA channel assigned */ @@ -496,17 +508,21 @@ static struct up_dev_s g_usart1priv = .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_USART1_BAUD, .apbclock = STM32_PCLK2_FREQUENCY, .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, -#ifdef GPIO_USART1_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART1_OFLOWCONTROL) .cts_gpio = GPIO_USART1_CTS, #endif -#ifdef GPIO_USART1_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART1_IFLOWCONTROL) .rts_gpio = GPIO_USART1_RTS, #endif #ifdef CONFIG_USART1_RXDMA @@ -558,17 +574,21 @@ static struct up_dev_s g_usart2priv = .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_USART2_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, -#ifdef GPIO_USART2_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART2_OFLOWCONTROL) .cts_gpio = GPIO_USART2_CTS, #endif -#ifdef GPIO_USART2_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART2_IFLOWCONTROL) .rts_gpio = GPIO_USART2_RTS, #endif #ifdef CONFIG_USART2_RXDMA @@ -620,17 +640,21 @@ static struct up_dev_s g_usart3priv = .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_USART3_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, -#ifdef GPIO_USART3_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART3_OFLOWCONTROL) .cts_gpio = GPIO_USART3_CTS, #endif -#ifdef GPIO_USART3_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART3_IFLOWCONTROL) .rts_gpio = GPIO_USART3_RTS, #endif #ifdef CONFIG_USART3_RXDMA @@ -682,15 +706,23 @@ static struct up_dev_s g_uart4priv = .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_UART4_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, - .cts_gpio = 0, /* flow control not supported on this port */ - .rts_gpio = 0, /* flow control not supported on this port */ +#ifdef CONFIG_SERIAL_OFLOWCONROL + .cts_gpio = 0, +#endif +#ifdef CONFIG_SERIAL_IFLOWCONROL + .rts_gpio = 0, +#endif #ifdef CONFIG_UART4_RXDMA .rxdma_channel = DMAMAP_UART4_RX, .rxfifo = g_uart4rxfifo, @@ -740,15 +772,23 @@ static struct up_dev_s g_uart5priv = .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_UART5_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, - .cts_gpio = 0, /* flow control not supported on this port */ - .rts_gpio = 0, /* flow control not supported on this port */ +#ifdef CONFIG_SERIAL_OFLOWCONROL + .cts_gpio = 0, +#endif +#ifdef CONFIG_SERIAL_IFLOWCONROL + .rts_gpio = 0, +#endif #ifdef CONFIG_UART5_RXDMA .rxdma_channel = DMAMAP_UART5_RX, .rxfifo = g_uart5rxfifo, @@ -798,17 +838,21 @@ static struct up_dev_s g_usart6priv = .parity = CONFIG_USART6_PARITY, .bits = CONFIG_USART6_BITS, .stopbits2 = CONFIG_USART6_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_USART6_BAUD, .apbclock = STM32_PCLK2_FREQUENCY, .usartbase = STM32_USART6_BASE, .tx_gpio = GPIO_USART6_TX, .rx_gpio = GPIO_USART6_RX, -#ifdef GPIO_USART6_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART6_OFLOWCONTROL) .cts_gpio = GPIO_USART6_CTS, #endif -#ifdef GPIO_USART6_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART6_IFLOWCONTROL) .rts_gpio = GPIO_USART6_RTS, #endif #ifdef CONFIG_USART6_RXDMA @@ -865,10 +909,10 @@ static struct up_dev_s g_uart7priv = .usartbase = STM32_UART7_BASE, .tx_gpio = GPIO_UART7_TX, .rx_gpio = GPIO_UART7_RX, -#ifdef GPIO_UART7_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART7_OFLOWCONTROL) .cts_gpio = GPIO_UART7_CTS, #endif -#ifdef GPIO_UART7_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART7_IFLOWCONTROL) .rts_gpio = GPIO_UART7_RTS, #endif #ifdef CONFIG_UART7_RXDMA @@ -925,10 +969,10 @@ static struct up_dev_s g_uart8priv = .usartbase = STM32_UART8_BASE, .tx_gpio = GPIO_UART8_TX, .rx_gpio = GPIO_UART8_RX, -#ifdef GPIO_UART8_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART8_OFLOWCONTROL) .cts_gpio = GPIO_UART8_CTS, #endif -#ifdef GPIO_UART8_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART8_IFLOWCONTROL) .rts_gpio = GPIO_UART8_RTS, #endif #ifdef CONFIG_UART8_RXDMA @@ -1109,13 +1153,14 @@ static int up_dma_nextrx(struct up_dev_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void up_set_format(struct uart_dev_s *dev) { -#ifdef CONFIG_STM32_STM32F30XX + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32_t regval; +#ifdef CONFIG_STM32_STM32F30XX /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. */ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; uint32_t usartdiv8; uint32_t cr1; uint32_t brr; @@ -1171,12 +1216,10 @@ static void up_set_format(struct uart_dev_s *dev) * dividers. */ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; uint32_t usartdiv32; uint32_t mantissa; uint32_t fraction; uint32_t brr; - uint32_t regval; /* Configure the USART Baud Rate. The baud rate for the receiver and * transmitter (Rx and Tx) are both set to the same value as programmed @@ -1206,6 +1249,7 @@ static void up_set_format(struct uart_dev_s *dev) fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; brr |= fraction << USART_BRR_FRAC_SHIFT; up_serialout(priv, STM32_USART_BRR_OFFSET, brr); +#endif /* Configure parity mode */ @@ -1232,6 +1276,7 @@ static void up_set_format(struct uart_dev_s *dev) { regval |= USART_CR2_STOP2; } + up_serialout(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ @@ -1239,14 +1284,19 @@ static void up_set_format(struct uart_dev_s *dev) regval = up_serialin(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE|USART_CR3_RTSE); +#ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow && (priv->rts_gpio != 0)) - { + { regval |= USART_CR3_RTSE; } +#endif + +#ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->oflow && (priv->cts_gpio != 0)) - { + { regval |= USART_CR3_CTSE; } +#endif up_serialout(priv, STM32_USART_CR3_OFFSET, regval); @@ -1279,15 +1329,19 @@ static int up_setup(struct uart_dev_s *dev) stm32_configgpio(priv->tx_gpio); stm32_configgpio(priv->rx_gpio); +#ifdef CONFIG_SERIAL_OFLOWCONROL if (priv->cts_gpio != 0) { stm32_configgpio(priv->cts_gpio); } +#endif +#ifdef CONFIG_SERIAL_IFLOWCONROL if (priv->rts_gpio != 0) { stm32_configgpio(priv->rts_gpio); } +#endif #if HAVE_RS485 if (priv->rs485_dir_gpio != 0) @@ -1298,10 +1352,10 @@ static int up_setup(struct uart_dev_s *dev) #endif /* Configure CR2 */ - /* Clear CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ + /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ regval = up_serialin(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_CLKEN|USART_CR2_CPOL| + regval &= ~(USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL| USART_CR2_CPHA|USART_CR2_LBCL|USART_CR2_LBDIE); /* Configure STOP bits */ @@ -1317,8 +1371,7 @@ static int up_setup(struct uart_dev_s *dev) /* Clear M, TE, REm and all interrupt enable bits */ regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_M|USART_CR1_TE| - USART_CR1_RE|USART_CR1_ALLINTS); + regval &= ~(USART_CR1_M|USART_CR1_TE|USART_CR1_RE|USART_CR1_ALLINTS); /* Configure word length */ @@ -1347,8 +1400,6 @@ static int up_setup(struct uart_dev_s *dev) regval |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE); up_serialout(priv, STM32_USART_CR1_OFFSET, regval); -#endif - /* Set up the cached interrupt enables value */ priv->ie = 0; @@ -1374,7 +1425,7 @@ static int up_dma_setup(struct uart_dev_s *dev) /* Do the basic UART setup first, unless we are the console */ if (!dev->isconsole) - { + { result = up_setup(dev); if (result != OK) { @@ -1706,7 +1757,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) up_serialout(priv, STM32_USART_CR3_OFFSET, cr); } - break; + break; #endif #ifdef CONFIG_SERIAL_TERMIOS @@ -1726,12 +1777,16 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * there is no way to report 9-bit mode, we always claim 8. */ - termiosp->c_cflag = + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | ((priv->parity == 1) ? PARODD : 0) | ((priv->stopbits2) ? CSTOPB : 0) | +#ifdef CONFIG_SERIAL_OFLOWCONTROL ((priv->oflow) ? CCTS_OFLOW : 0) | +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL ((priv->iflow) ? CRTS_IFLOW : 0) | +#endif CS8; /* TODO: CCTS_IFLOW, CCTS_OFLOW */ @@ -1750,26 +1805,35 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) /* Perform some sanity checks before accepting any changes */ - if (((termiosp->c_cflag & CSIZE) != CS8) || - ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) || - ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0))) - { + if (((termiosp->c_cflag & CSIZE) != CS8) +#ifdef CONFIG_SERIAL_IFLOWCONROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { ret = -EINVAL; break; } if (termiosp->c_cflag & PARENB) - { + { priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; } else - { + { priv->parity = 0; } priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; +#ifdef CONFIG_SERIAL_OFLOWCONTROL priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif /* Note that since there is no way to request 9-bit mode * and no way to support 5/6/7-bit modes, we ignore them diff --git a/nuttx/arch/avr/src/at32uc3/at32uc3_clkinit.c b/nuttx/arch/avr/src/at32uc3/at32uc3_clkinit.c index 1a39aad783..baaecbce37 100644 --- a/nuttx/arch/avr/src/at32uc3/at32uc3_clkinit.c +++ b/nuttx/arch/avr/src/at32uc3/at32uc3_clkinit.c @@ -98,7 +98,7 @@ static inline void up_enableosc32(void) { uint32_t regval; - + /* Select the 32KHz oscillator crystal */ regval = getreg32(AVR32_PM_OSCCTRL32); @@ -225,7 +225,7 @@ static inline void up_enableosc1(void) static inline void up_enablepll0(void) { /* Setup PLL0 */ - + regval = (AVR32_PLL0_DIV << PM_PLL_PLLDIV_SHIFT) | (AVR32_PLL0_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT) /* Select PLL0/1 oscillator */ @@ -256,7 +256,7 @@ static inline void up_enablepll0(void) regval = getreg32(AVR32_PM_PLL0); regval |= PM_PLL_PLLEN; putreg32(regval, AVR32_PM_PLL0) - + /* Wait for PLL0 locked. */ while ((getreg32(AVR32_PM_POSCSR) & PM_POSCSR_LOCK0) == 0); @@ -275,11 +275,11 @@ static inline void up_enablepll0(void) static inline void up_enablepll1(void) { /* Setup PLL1 */ - + regval = (AVR32_PLL1_DIV << PM_PLL_PLLDIV_SHIFT) | (AVR32_PLL1_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT) /* Select PLL0/1 oscillator */ - + #if AVR32_CLOCK_PLL_OSC1 regval |= PM_PLL_PLLOSC; #endif @@ -363,7 +363,7 @@ static inline void up_clksel(void) static void up_fws(uint32_t cpuclock) { uint32_t regval; - + regval = getreg32(AVR32_FLASHC_FCR); if (cpuclock > AVR32_FLASHC_FWS0_MAXFREQ) { @@ -387,7 +387,7 @@ static void up_fws(uint32_t cpuclock) static inline void up_mainclk(uint32_t mcsel) { uint32_t regval; - + regval = getreg32(AVR32_PM_MCCTRL); regval &= ~PM_MCCTRL_MCSEL_MASK; regval |= mcsel; @@ -422,7 +422,7 @@ static inline void up_usbclock(void) putreg32(regval, AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB)) /* Enable USB GCLK */ - + regval = getreg32(AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB)) regval |= PM_GCCTRL_CEN; putreg32(regval, AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB)) @@ -441,7 +441,7 @@ static inline void up_usbclock(void) * file. * **************************************************************************/ - + void up_clkinitialize(void) { #ifdef AVR32_CLOCK_OSC32 @@ -458,7 +458,7 @@ void up_clkinitialize(void) /* Set up FLASH wait states */ up_fws(AVR32_FOSC0); - + /* Then switch the main clock to OSC0 */ up_mainclk(PM_MCCTRL_MCSEL_OSC0); @@ -474,11 +474,11 @@ void up_clkinitialize(void) /* Enable PLL0 using the settings in board.h */ up_enablepll0(); - + /* Set up FLASH wait states */ up_fws(AVR32_CPU_CLOCK); - + /* Then switch the main clock to PLL0 */ up_mainclk(PM_MCCTRL_MCSEL_PLL0); diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig index dcfa1c3eb9..6bbfe96e27 100644 --- a/nuttx/configs/Kconfig +++ b/nuttx/configs/Kconfig @@ -482,6 +482,15 @@ config ARCH_BOARD_SAM4L_XPLAINED ---help--- The port of NuttX to the Atmel SAM4L-Xplained Pro development board. +config ARCH_BOARD_SAM4S_XPLAINED + bool "Atmel SAM4S-Xplained development board" + depends on ARCH_CHIP_ATSAM4S16C + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + The port of NuttX to the Atmel SAM4S-Xplained development board. + config ARCH_BOARD_SHENZHOU bool "Shenzhou STM32F107 board" depends on ARCH_CHIP_STM32F107VC @@ -796,6 +805,7 @@ config ARCH_BOARD default "rgmp" if ARCH_BOARD_RGMP default "sam3u-ek" if ARCH_BOARD_SAM3UEK default "sam4l-xplained" if ARCH_BOARD_SAM4L_XPLAINED + default "sam4s-xplained" if ARCH_BOARD_SAM4S_XPLAINED default "shenzhou" if ARCH_BOARD_SHENZHOU default "skp16c26" if ARCH_BOARD_SKP16C26 default "stm32_tiny" if ARCH_BOARD_STM32_TINY @@ -1021,6 +1031,9 @@ endif if ARCH_BOARD_SAM4L_XPLAINED source "configs/sam4l-xplained/Kconfig" endif +if ARCH_BOARD_SAM4S_XPLAINED +source "configs/sam4s-xplained/Kconfig" +endif if ARCH_BOARD_SHENZHOU source "configs/shenzhou/Kconfig" endif diff --git a/nuttx/configs/cloudctrl/src/up_usbmsc.c b/nuttx/configs/cloudctrl/src/up_usbmsc.c index 04f35efea4..454cfccf56 100644 --- a/nuttx/configs/cloudctrl/src/up_usbmsc.c +++ b/nuttx/configs/cloudctrl/src/up_usbmsc.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/cloudctrl/src/up_usbmsc.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * Darcy Gong * @@ -96,7 +96,7 @@ int usbmsc_archinitialize(void) * this case, there is nothing further to be done here. */ -#ifndef CONFIG_EXAMPLES_USBMSC_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS return stm32_sdinitialize(CONFIG_EXAMPLES_USBMSC_DEVMINOR1); #else return OK; diff --git a/nuttx/configs/compal_e99/nsh_highram/defconfig b/nuttx/configs/compal_e99/nsh_highram/defconfig index bc3cbd6494..56fe639cba 100644 --- a/nuttx/configs/compal_e99/nsh_highram/defconfig +++ b/nuttx/configs/compal_e99/nsh_highram/defconfig @@ -262,9 +262,6 @@ CONFIG_NSH_BUILTIN_APPS=y # Settings for examples/hello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y -CONFIG_EXAMPLES_NXTEXT_BUILTIN=y -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=2 CONFIG_EXAMPLES_NXLINES_LINEWIDTH=4 diff --git a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig index 9331512b8c..c5b0889670 100644 --- a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig +++ b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig @@ -429,7 +429,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/ez80f910200kitg/ostest/defconfig b/nuttx/configs/ez80f910200kitg/ostest/defconfig index 1abc3fb587..b32a9ed754 100644 --- a/nuttx/configs/ez80f910200kitg/ostest/defconfig +++ b/nuttx/configs/ez80f910200kitg/ostest/defconfig @@ -368,7 +368,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/ez80f910200zco/ostest/defconfig b/nuttx/configs/ez80f910200zco/ostest/defconfig index e67f93da6c..6df0efdb7b 100644 --- a/nuttx/configs/ez80f910200zco/ostest/defconfig +++ b/nuttx/configs/ez80f910200zco/ostest/defconfig @@ -376,7 +376,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/fire-stm32v2/nsh/defconfig b/nuttx/configs/fire-stm32v2/nsh/defconfig index e9df03b99c..f1a89316be 100644 --- a/nuttx/configs/fire-stm32v2/nsh/defconfig +++ b/nuttx/configs/fire-stm32v2/nsh/defconfig @@ -773,7 +773,6 @@ CONFIG_EXAMPLES_NSH=y # USB Mass Storage Class Example # CONFIG_EXAMPLES_USBMSC=y -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" @@ -996,7 +995,6 @@ CONFIG_NSH_NOMAC=y # I2C tool # CONFIG_SYSTEM_I2CTOOL=y -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=2 CONFIG_I2CTOOL_MINADDR=0x03 diff --git a/nuttx/configs/fire-stm32v2/src/up_usbmsc.c b/nuttx/configs/fire-stm32v2/src/up_usbmsc.c index 98c06336f3..3a1ebe0e08 100644 --- a/nuttx/configs/fire-stm32v2/src/up_usbmsc.c +++ b/nuttx/configs/fire-stm32v2/src/up_usbmsc.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/fire-stm32v2/src/up_usbmsc.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Configure and register the STM32 SPI-based MMC/SD block driver. @@ -95,7 +95,7 @@ int usbmsc_archinitialize(void) * this case, there is nothing further to be done here. */ -#ifndef CONFIG_EXAMPLES_USBMSC_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS return stm32_sdinitialize(CONFIG_EXAMPLES_USBMSC_DEVMINOR1); #else return OK; diff --git a/nuttx/configs/freedom-kl25z/ostest/defconfig b/nuttx/configs/freedom-kl25z/ostest/defconfig index 442487f3e6..89cad14c6c 100644 --- a/nuttx/configs/freedom-kl25z/ostest/defconfig +++ b/nuttx/configs/freedom-kl25z/ostest/defconfig @@ -449,7 +449,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=1536 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/hymini-stm32v/README.txt b/nuttx/configs/hymini-stm32v/README.txt index 3765dbf356..02ab521133 100644 --- a/nuttx/configs/hymini-stm32v/README.txt +++ b/nuttx/configs/hymini-stm32v/README.txt @@ -627,7 +627,7 @@ Where is one of the following: long file names in the FAT file system. Please refer to the details in the top-level COPYING file. Please do not use FAT long file name unless you are familiar with these patent issues. - (4) When built as an NSH add-on command (CONFIG_EXAMPLES_USBMSC_BUILTIN=y), + (4) When built as an NSH add-on command (CONFIG_NSH_BUILTIN_APPS=y), Caution should be used to assure that the SD drive is not in use when the USB storage device is configured. Specifically, the SD driver should be unmounted like: diff --git a/nuttx/configs/hymini-stm32v/nsh2/defconfig b/nuttx/configs/hymini-stm32v/nsh2/defconfig index 62793df979..0c3897eff3 100644 --- a/nuttx/configs/hymini-stm32v/nsh2/defconfig +++ b/nuttx/configs/hymini-stm32v/nsh2/defconfig @@ -691,7 +691,6 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_DEFAULT_COLORS=y @@ -719,14 +718,12 @@ CONFIG_EXAMPLES_NXIMAGE=y # CONFIG_EXAMPLES_THTTPD is not set # CONFIG_EXAMPLES_TIFF is not set CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" # CONFIG_EXAMPLES_UDP is not set # CONFIG_EXAMPLES_UIP is not set # CONFIG_EXAMPLES_USBSERIAL is not set CONFIG_EXAMPLES_USBMSC=y -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/hymini-stm32v/ostest/defconfig b/nuttx/configs/hymini-stm32v/ostest/defconfig index 6f515839bd..209b5634b1 100644 --- a/nuttx/configs/hymini-stm32v/ostest/defconfig +++ b/nuttx/configs/hymini-stm32v/ostest/defconfig @@ -516,7 +516,6 @@ CONFIG_SCHED_WORKSTACKSIZE=1024 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8 diff --git a/nuttx/configs/hymini-stm32v/src/up_usbmsc.c b/nuttx/configs/hymini-stm32v/src/up_usbmsc.c index c5abaa9110..e7fc419079 100644 --- a/nuttx/configs/hymini-stm32v/src/up_usbmsc.c +++ b/nuttx/configs/hymini-stm32v/src/up_usbmsc.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/hymini-stm32v/src/up_usbmsc.c * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Configure and register the STM32 MMC/SD SDIO block driver. @@ -114,7 +114,7 @@ int usbmsc_archinitialize(void) * this case, there is nothing further to be done here. */ -#ifndef CONFIG_EXAMPLES_USBMSC_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS FAR struct sdio_dev_s *sdio; int ret; @@ -156,7 +156,7 @@ int usbmsc_archinitialize(void) sdio_mediachange(sdio, true); -#endif /* CONFIG_EXAMPLES_USBMSC_BUILTIN */ +#endif /* CONFIG_NSH_BUILTIN_APPS */ return OK; } diff --git a/nuttx/configs/hymini-stm32v/usbserial/defconfig b/nuttx/configs/hymini-stm32v/usbserial/defconfig index ca793bae7d..25382b32b5 100755 --- a/nuttx/configs/hymini-stm32v/usbserial/defconfig +++ b/nuttx/configs/hymini-stm32v/usbserial/defconfig @@ -477,7 +477,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/usbterm # -CONFIG_EXAMPLES_USBTERM_BUILTIN=n CONFIG_EXAMPLES_USBTERM_BUFLEN=256 CONFIG_EXAMPLES_USBTERM_TRACEINIT=n CONFIG_EXAMPLES_USBTERM_TRACECLASS=n diff --git a/nuttx/configs/hymini-stm32v/usbstorage/defconfig b/nuttx/configs/hymini-stm32v/usbstorage/defconfig index 1982faaf07..da13197a53 100755 --- a/nuttx/configs/hymini-stm32v/usbstorage/defconfig +++ b/nuttx/configs/hymini-stm32v/usbstorage/defconfig @@ -464,7 +464,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=n CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/kwikstik-k40/ostest/defconfig b/nuttx/configs/kwikstik-k40/ostest/defconfig index 16b3bd321b..bcf204bb48 100755 --- a/nuttx/configs/kwikstik-k40/ostest/defconfig +++ b/nuttx/configs/kwikstik-k40/ostest/defconfig @@ -463,7 +463,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/kwikstik-k40/src/up_usbmsc.c b/nuttx/configs/kwikstik-k40/src/up_usbmsc.c index ea97cb99f2..bbdbbba943 100644 --- a/nuttx/configs/kwikstik-k40/src/up_usbmsc.c +++ b/nuttx/configs/kwikstik-k40/src/up_usbmsc.c @@ -110,9 +110,9 @@ int usbmsc_archinitialize(void) * this case, there is nothing further to be done here. */ -#ifndef CONFIG_EXAMPLES_USBMSC_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS # warning "Missing logic" -#endif /* CONFIG_EXAMPLES_USBMSC_BUILTIN */ +#endif /* CONFIG_NSH_BUILTIN_APPS */ return OK; } diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig index eff3f6b210..2c554bfd29 100755 --- a/nuttx/configs/lm3s6965-ek/ostest/defconfig +++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig @@ -413,7 +413,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/lm4f120-launchpad/ostest/defconfig b/nuttx/configs/lm4f120-launchpad/ostest/defconfig index 3ee3a56bd3..9eee8efeb0 100755 --- a/nuttx/configs/lm4f120-launchpad/ostest/defconfig +++ b/nuttx/configs/lm4f120-launchpad/ostest/defconfig @@ -432,7 +432,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/lpc4330-xplorer/nsh/defconfig b/nuttx/configs/lpc4330-xplorer/nsh/defconfig index 4aba64d421..75d55359b6 100644 --- a/nuttx/configs/lpc4330-xplorer/nsh/defconfig +++ b/nuttx/configs/lpc4330-xplorer/nsh/defconfig @@ -537,7 +537,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR diff --git a/nuttx/configs/lpc4330-xplorer/ostest/defconfig b/nuttx/configs/lpc4330-xplorer/ostest/defconfig index d4b1bda471..1f1eb5bc9b 100644 --- a/nuttx/configs/lpc4330-xplorer/ostest/defconfig +++ b/nuttx/configs/lpc4330-xplorer/ostest/defconfig @@ -520,7 +520,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR diff --git a/nuttx/configs/mikroe-stm32f4/fulldemo/defconfig b/nuttx/configs/mikroe-stm32f4/fulldemo/defconfig index 67bc28f197..d870b629ac 100644 --- a/nuttx/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/nuttx/configs/mikroe-stm32f4/fulldemo/defconfig @@ -747,7 +747,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_DEFAULT_COLORS=y @@ -787,7 +786,6 @@ CONFIG_EXAMPLES_NXIMAGE=y # CONFIG_EXAMPLES_THTTPD is not set # CONFIG_EXAMPLES_TIFF is not set CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" # CONFIG_EXAMPLES_UDP is not set diff --git a/nuttx/configs/mikroe-stm32f4/kostest/defconfig b/nuttx/configs/mikroe-stm32f4/kostest/defconfig index 651243f995..5c09035e56 100644 --- a/nuttx/configs/mikroe-stm32f4/kostest/defconfig +++ b/nuttx/configs/mikroe-stm32f4/kostest/defconfig @@ -671,7 +671,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -CONFIG_EXAMPLES_OSTEST_BUILTIN=y CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8 diff --git a/nuttx/configs/mikroe-stm32f4/nx/defconfig b/nuttx/configs/mikroe-stm32f4/nx/defconfig index cda3929818..0e3d213605 100644 --- a/nuttx/configs/mikroe-stm32f4/nx/defconfig +++ b/nuttx/configs/mikroe-stm32f4/nx/defconfig @@ -586,7 +586,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set CONFIG_EXAMPLES_NX=y -# CONFIG_EXAMPLES_NX_BUILTIN is not set CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_DEFAULT_COLORS=y diff --git a/nuttx/configs/mikroe-stm32f4/nxtext/defconfig b/nuttx/configs/mikroe-stm32f4/nxtext/defconfig index 6f7f569b33..a7d3880932 100644 --- a/nuttx/configs/mikroe-stm32f4/nxtext/defconfig +++ b/nuttx/configs/mikroe-stm32f4/nxtext/defconfig @@ -596,7 +596,6 @@ CONFIG_EXAMPLES_NXTEXT=y # # Basic Configuration of the example # -# CONFIG_EXAMPLES_NXTEXT_BUILTIN is not set CONFIG_EXAMPLES_NXTEXT_VPLANE=0 CONFIG_EXAMPLES_NXTEXT_DEVNO=0 CONFIG_EXAMPLES_NXTEXT_BPP=16 diff --git a/nuttx/configs/mikroe-stm32f4/src/mikroe-stm32f4-internal.h b/nuttx/configs/mikroe-stm32f4/src/mikroe-stm32f4-internal.h index 0f6894316e..c27306048a 100644 --- a/nuttx/configs/mikroe-stm32f4/src/mikroe-stm32f4-internal.h +++ b/nuttx/configs/mikroe-stm32f4/src/mikroe-stm32f4-internal.h @@ -190,7 +190,6 @@ GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN7) #define GPIO_VS1053_DREQ (GPIO_INPUT|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6) - /**************************************************************************************************** * Public Types ****************************************************************************************************/ diff --git a/nuttx/configs/nutiny-nuc120/ostest/defconfig b/nuttx/configs/nutiny-nuc120/ostest/defconfig index 2dd7568d48..014bd1d150 100644 --- a/nuttx/configs/nutiny-nuc120/ostest/defconfig +++ b/nuttx/configs/nutiny-nuc120/ostest/defconfig @@ -468,7 +468,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=1536 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/open1788/README.txt b/nuttx/configs/open1788/README.txt index c15985d169..f4a269f58c 100644 --- a/nuttx/configs/open1788/README.txt +++ b/nuttx/configs/open1788/README.txt @@ -540,11 +540,22 @@ CONFIGURATION CONFIG_GPIO_IRQ=y : GPIO interrupt support CONFIG_LPC17_SSP1=y : Enable support for SSP1 + RTOS Features: + CONFIG_DISABLE_SIGNALS=n : Signals are required + + Library Support: + CONFIG_SCHED_WORKQUEUE=y : Work queue support required + Applicaton Configuration: CONFIG_EXAMPLES_TOUCHSCREEN=y : Enable the touchscreen built-int test - CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y - Defaults should be okay for related touchscreen settings. + Defaults should be okay for related touchscreen settings. Touchscreen + debug output can be enabled with: + + Build Setup: + CONFIG_DEBUG=y : Enable debug features + CONFIG_DEBUG_VERBOSE=y : Enable verbose debug output + CONFIG_DEBUG_INPUT=y : Enable debug output from input devices c) You will also have to disable SD card support to use this test. The SD card detect (CD) signal is on P0[13]. This signal is shared. It diff --git a/nuttx/configs/open1788/ostest/defconfig b/nuttx/configs/open1788/ostest/defconfig index f78adeaaaf..010f5a80f1 100644 --- a/nuttx/configs/open1788/ostest/defconfig +++ b/nuttx/configs/open1788/ostest/defconfig @@ -469,7 +469,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/p112/ostest/defconfig b/nuttx/configs/p112/ostest/defconfig index 3699475c59..000b1b57dc 100644 --- a/nuttx/configs/p112/ostest/defconfig +++ b/nuttx/configs/p112/ostest/defconfig @@ -405,7 +405,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=1024 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=4 diff --git a/nuttx/configs/pcblogic-pic32mx/ostest/defconfig b/nuttx/configs/pcblogic-pic32mx/ostest/defconfig index 5db1312059..569b34adb5 100644 --- a/nuttx/configs/pcblogic-pic32mx/ostest/defconfig +++ b/nuttx/configs/pcblogic-pic32mx/ostest/defconfig @@ -537,7 +537,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/pic32-starterkit/nsh/defconfig b/nuttx/configs/pic32-starterkit/nsh/defconfig index 2c88881daa..89e5d24987 100644 --- a/nuttx/configs/pic32-starterkit/nsh/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh/defconfig @@ -599,7 +599,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=4 #CONFIG_I2CTOOL_MINADDR @@ -628,7 +627,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" @@ -641,7 +639,6 @@ CONFIG_EXAMPLES_USBMSC_TRACEINTERRUPTS=n # # Settings for examples/usbterm # -CONFIG_EXAMPLES_USBTERM_BUILTIN=y CONFIG_EXAMPLES_USBTERM_DEVINIT=y #CONFIG_EXAMPLES_USBTERM_BUFLEN CONFIG_EXAMPLES_USBTERM_TRACEINIT=n diff --git a/nuttx/configs/pic32-starterkit/nsh2/defconfig b/nuttx/configs/pic32-starterkit/nsh2/defconfig index 23deb44711..2b596ea2f1 100644 --- a/nuttx/configs/pic32-starterkit/nsh2/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh2/defconfig @@ -598,7 +598,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=4 #CONFIG_I2CTOOL_MINADDR @@ -627,7 +626,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" @@ -640,7 +638,6 @@ CONFIG_EXAMPLES_USBMSC_TRACEINTERRUPTS=n # # Settings for examples/usbterm # -CONFIG_EXAMPLES_USBTERM_BUILTIN=y CONFIG_EXAMPLES_USBTERM_DEVINIT=y #CONFIG_EXAMPLES_USBTERM_BUFLEN CONFIG_EXAMPLES_USBTERM_TRACEINIT=n diff --git a/nuttx/configs/pic32-starterkit/ostest/defconfig b/nuttx/configs/pic32-starterkit/ostest/defconfig index b1b99e4c62..048a148af9 100644 --- a/nuttx/configs/pic32-starterkit/ostest/defconfig +++ b/nuttx/configs/pic32-starterkit/ostest/defconfig @@ -595,7 +595,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=4 #CONFIG_I2CTOOL_MINADDR @@ -624,7 +623,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=n CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" @@ -637,7 +635,6 @@ CONFIG_EXAMPLES_USBMSC_TRACEINTERRUPTS=n # # Settings for examples/usbterm # -CONFIG_EXAMPLES_USBTERM_BUILTIN=y CONFIG_EXAMPLES_USBTERM_DEVINIT=y #CONFIG_EXAMPLES_USBTERM_BUFLEN CONFIG_EXAMPLES_USBTERM_TRACEINIT=n diff --git a/nuttx/configs/pic32-starterkit/src/up_usbmsc.c b/nuttx/configs/pic32-starterkit/src/up_usbmsc.c index 51e450c564..00b374dfd5 100644 --- a/nuttx/configs/pic32-starterkit/src/up_usbmsc.c +++ b/nuttx/configs/pic32-starterkit/src/up_usbmsc.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/pic32-starterkit/src/up_usbmsc.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -87,9 +87,9 @@ int usbmsc_archinitialize(void) * this case, there is nothing further to be done here. */ -#ifndef CONFIG_EXAMPLES_USBMSC_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS # warning "Missing Logic" -#endif /* CONFIG_EXAMPLES_USBMSC_BUILTIN */ +#endif /* CONFIG_NSH_BUILTIN_APPS */ return 0; } diff --git a/nuttx/configs/pic32-starterkit/src/up_usbterm.c b/nuttx/configs/pic32-starterkit/src/up_usbterm.c index 012e8a5c0a..e362f09efc 100644 --- a/nuttx/configs/pic32-starterkit/src/up_usbterm.c +++ b/nuttx/configs/pic32-starterkit/src/up_usbterm.c @@ -2,7 +2,7 @@ * configs/pic32-starterkit/src/up_usbterm.c * arch/arm/src/board/up_usbterm.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -80,7 +80,7 @@ int usbterm_devinit(void) * pic32mx_usbattach() will be called in nsh_archinitialize(). */ -#ifndef CONFIG_EXAMPLES_USBTERM_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS pic32mx_usbattach(); #endif return OK; diff --git a/nuttx/configs/pic32mx7mmb/nsh/defconfig b/nuttx/configs/pic32mx7mmb/nsh/defconfig index 23adc8f5bb..781b819711 100644 --- a/nuttx/configs/pic32mx7mmb/nsh/defconfig +++ b/nuttx/configs/pic32mx7mmb/nsh/defconfig @@ -646,7 +646,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=4 #CONFIG_I2CTOOL_MINADDR @@ -661,7 +660,6 @@ CONFIG_I2CTOOL_DEFFREQ=100000 # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -681,7 +679,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 CONFIG_EXAMPLES_NXHELLO_DEVNO=0 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 @@ -693,7 +690,6 @@ CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 @@ -722,7 +718,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/touchscreen # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 @@ -744,7 +739,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" @@ -757,7 +751,6 @@ CONFIG_EXAMPLES_USBMSC_TRACEINTERRUPTS=n # # Settings for examples/usbterm # -CONFIG_EXAMPLES_USBTERM_BUILTIN=y CONFIG_EXAMPLES_USBTERM_DEVINIT=y #CONFIG_EXAMPLES_USBTERM_BUFLEN CONFIG_EXAMPLES_USBTERM_TRACEINIT=n diff --git a/nuttx/configs/pic32mx7mmb/ostest/defconfig b/nuttx/configs/pic32mx7mmb/ostest/defconfig index 1148aac377..70f6db37e6 100644 --- a/nuttx/configs/pic32mx7mmb/ostest/defconfig +++ b/nuttx/configs/pic32mx7mmb/ostest/defconfig @@ -595,7 +595,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=4 #CONFIG_I2CTOOL_MINADDR @@ -624,7 +623,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=n CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" @@ -637,7 +635,6 @@ CONFIG_EXAMPLES_USBMSC_TRACEINTERRUPTS=n # # Settings for examples/usbterm # -CONFIG_EXAMPLES_USBTERM_BUILTIN=y CONFIG_EXAMPLES_USBTERM_DEVINIT=y #CONFIG_EXAMPLES_USBTERM_BUFLEN CONFIG_EXAMPLES_USBTERM_TRACEINIT=n diff --git a/nuttx/configs/pic32mx7mmb/src/up_usbmsc.c b/nuttx/configs/pic32mx7mmb/src/up_usbmsc.c index d1f473d4f5..5ec64336c7 100644 --- a/nuttx/configs/pic32mx7mmb/src/up_usbmsc.c +++ b/nuttx/configs/pic32mx7mmb/src/up_usbmsc.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/pic32mx7mmb/src/up_usbmsc.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -87,9 +87,9 @@ int usbmsc_archinitialize(void) * this case, there is nothing further to be done here. */ -#ifndef CONFIG_EXAMPLES_USBMSC_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS # warning "Missing Logic" -#endif /* CONFIG_EXAMPLES_USBMSC_BUILTIN */ +#endif /* CONFIG_NSH_BUILTIN_APPS */ return 0; } diff --git a/nuttx/configs/pic32mx7mmb/src/up_usbterm.c b/nuttx/configs/pic32mx7mmb/src/up_usbterm.c index e9da92be8d..7640befc7c 100644 --- a/nuttx/configs/pic32mx7mmb/src/up_usbterm.c +++ b/nuttx/configs/pic32mx7mmb/src/up_usbterm.c @@ -2,7 +2,7 @@ * configs/pic32mx7mmb/src/up_usbterm.c * arch/arm/src/board/up_usbterm.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -81,7 +81,7 @@ int usbterm_devinit(void) * pic32mx_usbattach() will be called in nsh_archinitialize(). */ -#ifndef CONFIG_EXAMPLES_USBTERM_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS pic32mx_usbattach(); #endif return OK; diff --git a/nuttx/configs/sam3u-ek/README.txt b/nuttx/configs/sam3u-ek/README.txt index fbda5d92c7..6cb173e92c 100644 --- a/nuttx/configs/sam3u-ek/README.txt +++ b/nuttx/configs/sam3u-ek/README.txt @@ -1,8 +1,8 @@ README ^^^^^^ -This README discusses issues unique to NuttX configurations for the -Atmel SAM3U-EK development board. +This README discusses issues unique to NuttX configurations for the Atmel +SAM3U-EK development board featuring the ATAM3U Contents ^^^^^^^^ @@ -91,7 +91,7 @@ IDEs NuttX is built using command-line make. It can be used with an IDE, but some effort will be required to create the project (There is a simple RIDE project in the RIDE subdirectory). - + Makefile Build -------------- Under Eclipse, it is pretty easy to set up an "empty makefile project" and @@ -188,7 +188,7 @@ NXFLAT Toolchain tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can be downloaded from the NuttX SourceForge download site (https://sourceforge.net/projects/nuttx/files/). - + This GNU toolchain builds and executes in the Linux or Cygwin environment. 1. You must have already configured Nuttx in /nuttx. @@ -313,15 +313,28 @@ SAM3U-EK-specific Configuration Options Individual subsystems can be enabled: - CONFIG_SAM34_DMA - CONFIG_SAM34_HSMCI - CONFIG_SAM34_NAND - CONFIG_SAM34_SPI - CONFIG_SAM34_UART - CONFIG_SAM34_USART0 - CONFIG_SAM34_USART1 - CONFIG_SAM34_USART2 - CONFIG_SAM34_USART3 + CONFIG_SAM34_RTC - Real Time Clock + CONFIG_SAM34_RTT - Real Time Timer + CONFIG_SAM34_WDT - Watchdog Timer + CONFIG_SAM34_UART0 - UART 0 + CONFIG_SAM34_SMC - Static Memory Controller + CONFIG_SAM34_USART0 - USART 0 + CONFIG_SAM34_USART1 - USART 1 + CONFIG_SAM34_USART2 - USART 2 + CONFIG_SAM34_USART3 - USART 3 + CONFIG_SAM34_HSMCI - High Speed Multimedia Card Interface + CONFIG_SAM34_TWI0 - Two-Wire Interface 0 + CONFIG_SAM34_TWI1 - Two-Wire Interface 1 + CONFIG_SAM34_SPI - Serial Peripheral Interface + CONFIG_SAM34_SSC - Synchronous Serial Controller + CONFIG_SAM34_TC0 - Timer Counter 0 + CONFIG_SAM34_TC1 - Timer Counter 1 + CONFIG_SAM34_TC2 - Timer Counter 2 + CONFIG_SAM34_PWM - Pulse Width Modulation Controller + CONFIG_SAM34_ADC12B - 12-bit ADC Controller + CONFIG_SAM34_ADC - 10-bit ADC Controller + CONFIG_SAM34_DMA - DMA Controller + CONFIG_SAM34_UDPHS - USB Device High Speed Some subsystems can be configured to operate in different ways. The drivers need to know how to configure the subsystem. @@ -333,6 +346,7 @@ SAM3U-EK-specific Configuration Options CONFIG_USART1_ISUART CONFIG_USART2_ISUART CONFIG_USART3_ISUART + CONFIG_SAM34_NAND - NAND memory AT91SAM3U specific device driver settings @@ -357,25 +371,42 @@ SAM3U-EK-specific Configuration Options Configurations ^^^^^^^^^^^^^^ -Each SAM3U-EK configuration is maintained in a sub-directory and -can be selected as follow: + Each SAM3U-EK configuration is maintained in a sub-directory and + can be selected as follow: cd tools ./configure.sh sam3u-ek/ cd - . ./setenv.sh -Before sourcing the setenv.sh file above, you should examine it and perform -edits as necessary so that BUILDROOT_BIN is the correct path to the directory -than holds your toolchain binaries. + Before sourcing the setenv.sh file above, you should examine it and perform + edits as necessary so that BUILDROOT_BIN is the correct path to the directory + than holds your toolchain binaries. -And then build NuttX by simply typing the following. At the conclusion of -the make, the nuttx binary will reside in an ELF file called, simply, nuttx. + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, nuttx. make -The that is provided above as an argument to the tools/configure.sh -must be is one of the following: + The that is provided above as an argument to the tools/configure.sh + must be is one of the following. + + NOTES: + + 1. These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Unless stated otherwise, all configurations generate console + output of UART0 (J3). + +Configuration sub-directories +----------------------------- knsh: This is identical to the nsh configuration below except that NuttX @@ -392,23 +423,14 @@ must be is one of the following: binaries (pass2) NOTES: - - 1. This configuration uses the mconf-based configuration tool. To - change this configuration using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - and misc/tools/README.txt. - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 2. Uses the older, OABI, buildroot toolchain. But that is easily - reconfigured: + 1. This configuration uses the older, OABI, buildroot toolchain. But + that is easily reconfigured: CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain - 3. At the end of the build, there will be several files in the top-level + 2. At the end of the build, there will be several files in the top-level NuttX build directory: PASS1: @@ -424,7 +446,7 @@ must be is one of the following: The J-Link programmer will except files in .hex, .mot, .srec, and .bin formats. - 4. Combining .hex files. If you plan to use the .hex files with your + 3. Combining .hex files. If you plan to use the .hex files with your debugger or FLASH utility, then you may need to combine the two hex files into a single .hex file. Here is how you can do that. @@ -472,18 +494,71 @@ must be is one of the following: Configures the NuttShell (nsh) located at examples/nsh. The Configuration enables both the serial and telnetd NSH interfaces. + NOTES: + + 1. This configuration uses the older, OABI, buildroot toolchain. But + that is easily reconfigured: + + System Type: + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain + CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain + + 2. NSH built-in applications are supported. However, there are + no built-in applications built with the default configuration. + + Binary Formats: + CONFIG_BUILTIN=y : Enable support for built-in programs + + Applicaton Configuration: + CONFIG_NSH_BUILTIN_APPS=y : Enable starting apps from NSH command line + + 3. This configuration has been used for verifying the touchscreen on + on the SAM3U-EK LCD. With these modifications, you can include the + touchscreen test program at apps/examples/touchscreen as an NSH built-in + application. You can enable the touchscreen and test by modifying the + default configuration in the following ways: + + Drivers: + CONFIG_INPUT=y : Enable support for input devices + CONFIG_INPUT_ADS7843E=y : Enable support for the XPT2048 + CONFIG_ADS7843E_SPIDEV=0 : Use SPI for communication + CONFIG_ADS7843E_SPIMODE=0 : Use SPI mode 0 + CONFIG_ADS7843E_THRESHX=39 : These will probably need to be tuned + CONFIG_ADS7843E_THRESHY=51 + CONFIG_SPI=y : Enable SPI support + CONFIG_SPI_EXCHANGE=n : exchange() method is not supported + + System Type: + CONFIG_GPIO_IRQ=y : GPIO interrupt support + CONFIG_GPIOA_IRQ=y : Enable GPIO interrupts from port A + CONFIG_SAM34_SPI=y : Enable support for SPI + + RTOS Features: + CONFIG_DISABLE_SIGNALS=n : Signals are required + + Library Support: + CONFIG_SCHED_WORKQUEUE=y : Work queue support required + + Applicaton Configuration: + CONFIG_EXAMPLES_TOUCHSCREEN=y : Enable the touchscreen built-int test + + Defaults should be okay for related touchscreen settings. Touchscreen + debug output on UART0 can be enabled with: + + Build Setup: + CONFIG_DEBUG=y : Enable debug features + CONFIG_DEBUG_VERBOSE=y : Enable verbose debug output + CONFIG_DEBUG_INPUT=y : Enable debug output from input devices + + NOTE: + As of this writing, the touchscreen is not functional (no + interrupts). More work is needed. + nx: - Configures to use examples/nx using the HX834x LCD hardwar on + Configures to use examples/nx using the HX834x LCD hardware on the SAM3U-EK development board. ostest: This configuration directory, performs a simple OS test using examples/ostest. By default, this project assumes that you are using the DFU bootloader. - - touchscreen: - This configuration implements an NSH configuratin with several - built-in applications. The configuration is called touchscreen - because we intend to use this configuration to develop the - SAM3U-EK touchscreen. However, there is no touchscreen driver - in place as of this writing. diff --git a/nuttx/configs/sam3u-ek/include/board.h b/nuttx/configs/sam3u-ek/include/board.h index b5e1124793..98b3e74b6a 100644 --- a/nuttx/configs/sam3u-ek/include/board.h +++ b/nuttx/configs/sam3u-ek/include/board.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_BOARD_BOARD_H -#define __ARCH_BOARD_BOARD_H +#ifndef __ARCH_SAM3U_EK_INCLUDE_BOARD_H +#define __ARCH_SAM3U_EK_INCLUDE_BOARD_H /************************************************************************************ * Included Files @@ -60,14 +60,14 @@ /* Main oscillator register settings */ -#define BOARD_CKGR_MOR_MOSCXTST (63 << CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ +#define BOARD_CKGR_MOR_MOSCXTST (63 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ /* PLLA configuration */ -#define BOARD_CKGR_PLLAR_MULA (7 << CKGR_PLLAR_MULA_SHIFT) -#define BOARD_CKGR_PLLAR_STMODE CKGR_PLLAR_STMODE_FAST -#define BOARD_CKGR_PLLAR_PLLACOUNT (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) -#define BOARD_CKGR_PLLAR_DIVA CKGR_PLLAR_DIVA_BYPASS +#define BOARD_CKGR_PLLAR_MUL (7 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST +#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS /* PMC master clock register settings */ @@ -76,14 +76,14 @@ /* USB UTMI PLL start-up time */ -#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << CKGR_UCKR_UPLLCOUNT_SHIFT) +#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT) /* Resulting frequencies */ -#define SAM_MAINOSC_FREQUENCY (12000000) -#define SAM_MCK_FREQUENCY (48000000) -#define SAM_PLLA_FREQUENCY (96000000) -#define SAM_CPU_FREQUENCY (48000000) +#define BOARD_MAINOSC_FREQUENCY (12000000) +#define BOARD_MCK_FREQUENCY (48000000) +#define BOARD_PLLA_FREQUENCY (96000000) +#define BOARD_CPU_FREQUENCY (48000000) /* HSMCI clocking * @@ -96,16 +96,20 @@ /* MCK = 48MHz, CLKDIV = 59, MCI_SPEED = 48MHz / 2 * (59+1) = 400 KHz */ -#define HSMCI_INIT_CLKDIV (59 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_INIT_CLKDIV (59 << HSMCI_MR_CLKDIV_SHIFT) /* MCK = 48MHz, CLKDIV = 1, MCI_SPEED = 48MHz / 2 * (1+1) = 12 MHz */ -#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT) /* MCK = 48MHz, CLKDIV = 0, MCI_SPEED = 48MHz / 2 * (0+1) = 24 MHz */ -#define HSMCI_SDXFR_CLKDIV (0 << HSMCI_MR_CLKDIV_SHIFT) -#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV +#define HSMCI_SDXFR_CLKDIV (0 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV + +/* FLASH wait states */ + +#define BOARD_FWS 2 /* LED definitions ******************************************************************/ @@ -201,4 +205,4 @@ xcpt_t up_irqbutton(int id, xcpt_t irqhandler); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_BOARD_BOARD_H */ +#endif /* __ARCH_SAM3U_EK_INCLUDE_BOARD_H */ diff --git a/nuttx/configs/sam3u-ek/knsh/defconfig b/nuttx/configs/sam3u-ek/knsh/defconfig index 82bb5d0219..8411ea3c79 100644 --- a/nuttx/configs/sam3u-ek/knsh/defconfig +++ b/nuttx/configs/sam3u-ek/knsh/defconfig @@ -85,6 +85,7 @@ CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="sam34" # CONFIG_ARMV7M_USEBASEPRI is not set +# CONFIG_ARCH_HAVE_FPU is not set CONFIG_ARCH_HAVE_MPU=y CONFIG_ARMV7M_MPU=y CONFIG_ARMV7M_MPU_NREGIONS=8 @@ -97,37 +98,76 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set CONFIG_ARMV7M_OABI_TOOLCHAIN=y +# CONFIG_GPIO_IRQ is not set # CONFIG_SDIO_DMA is not set # CONFIG_SDIO_WIDTH_D1_ONLY is not set # -# AT91SAM3/SAM4 Configuration Options +# AT91SAM3/4 Configuration Options # CONFIG_ARCH_CHIP_AT91SAM3U4E=y +# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4A is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32B is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16B is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S16C is not set +# CONFIG_ARCH_CHIP_ATSAM4S16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S8C is not set +# CONFIG_ARCH_CHIP_ATSAM4S8B is not set CONFIG_ARCH_CHIP_SAM3U=y - -# -# AT91SAM3 Peripheral Support -# -# CONFIG_SAM34_DMA is not set -# CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y +# CONFIG_ARCH_CHIP_SAM4L is not set +# CONFIG_ARCH_CHIP_SAM4S is not set + +# +# AT91SAM3/4 Peripheral Support +# +# CONFIG_SAM34_SPI is not set +# CONFIG_SAM34_SSC is not set +# CONFIG_SAM34_TC0 is not set +# CONFIG_SAM34_TC1 is not set +# CONFIG_SAM34_TC2 is not set +# CONFIG_SAM34_PWM is not set +# CONFIG_SAM34_TWIM0 is not set +# CONFIG_SAM34_TWIS0 is not set +# CONFIG_SAM34_TWIM1 is not set +# CONFIG_SAM34_TWIS1 is not set +CONFIG_SAM34_UART0=y # CONFIG_SAM34_USART0 is not set # CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set # CONFIG_SAM34_USART3 is not set +# CONFIG_SAM34_ADC12B is not set +# CONFIG_SAM34_ADC is not set +# CONFIG_SAM34_SMC is not set +# CONFIG_SAM34_NAND is not set +# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_UDPHS is not set +# CONFIG_SAM34_RTC is not set +# CONFIG_SAM34_RTT is not set +# CONFIG_SAM34_WDT is not set +# CONFIG_SAM34_HSMCI is not set # -# AT91SAM3 UART Configuration +# AT91SAM3/4 USART Configuration # # -# AT91SAM3 GPIO Interrupt Configuration +# AT91SAM3/4 GPIO Interrupt Configuration # -# CONFIG_GPIOA_IRQ is not set -# CONFIG_GPIOB_IRQ is not set -# CONFIG_GPIOC_IRQ is not set # # External Memory Configuration @@ -145,7 +185,8 @@ CONFIG_ARCH_IRQPRIO=y CONFIG_ARCH_HAVE_VFORK=y CONFIG_ARCH_STACKDUMP=y # CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +# CONFIG_ARCH_RAMFUNCS is not set CONFIG_ARCH_HAVE_RAMVECTORS=y # CONFIG_ARCH_RAMVECTORS is not set @@ -297,21 +338,25 @@ CONFIG_SDIO_BLOCKSETUP=y CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_UART0=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_UART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# UART0 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set @@ -588,6 +633,7 @@ CONFIG_NSH_DISABLE_PS=y CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 +CONFIG_NSH_MAXARGUMENTS=6 CONFIG_NSH_NESTDEPTH=3 # CONFIG_NSH_DISABLESCRIPT is not set # CONFIG_NSH_DISABLEBG is not set diff --git a/nuttx/configs/sam3u-ek/nsh/defconfig b/nuttx/configs/sam3u-ek/nsh/defconfig index ef2475c1bb..2f0e524ab7 100644 --- a/nuttx/configs/sam3u-ek/nsh/defconfig +++ b/nuttx/configs/sam3u-ek/nsh/defconfig @@ -80,6 +80,7 @@ CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="sam34" # CONFIG_ARMV7M_USEBASEPRI is not set +# CONFIG_ARCH_HAVE_FPU is not set CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set @@ -91,35 +92,74 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set CONFIG_ARMV7M_OABI_TOOLCHAIN=y +# CONFIG_GPIO_IRQ is not set # -# AT91SAM3/SAM4 Configuration Options +# AT91SAM3/4 Configuration Options # CONFIG_ARCH_CHIP_AT91SAM3U4E=y +# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4A is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32B is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16B is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S16C is not set +# CONFIG_ARCH_CHIP_ATSAM4S16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S8C is not set +# CONFIG_ARCH_CHIP_ATSAM4S8B is not set CONFIG_ARCH_CHIP_SAM3U=y - -# -# AT91SAM3 Peripheral Support -# -# CONFIG_SAM34_DMA is not set -# CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y +# CONFIG_ARCH_CHIP_SAM4L is not set +# CONFIG_ARCH_CHIP_SAM4S is not set + +# +# AT91SAM3/4 Peripheral Support +# +# CONFIG_SAM34_SPI is not set +# CONFIG_SAM34_SSC is not set +# CONFIG_SAM34_TC0 is not set +# CONFIG_SAM34_TC1 is not set +# CONFIG_SAM34_TC2 is not set +# CONFIG_SAM34_PWM is not set +# CONFIG_SAM34_TWIM0 is not set +# CONFIG_SAM34_TWIS0 is not set +# CONFIG_SAM34_TWIM1 is not set +# CONFIG_SAM34_TWIS1 is not set +CONFIG_SAM34_UART0=y # CONFIG_SAM34_USART0 is not set # CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set # CONFIG_SAM34_USART3 is not set +# CONFIG_SAM34_ADC12B is not set +# CONFIG_SAM34_ADC is not set +# CONFIG_SAM34_SMC is not set +# CONFIG_SAM34_NAND is not set +# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_UDPHS is not set +# CONFIG_SAM34_RTC is not set +# CONFIG_SAM34_RTT is not set +# CONFIG_SAM34_WDT is not set +# CONFIG_SAM34_HSMCI is not set # -# AT91SAM3 UART Configuration +# AT91SAM3/4 USART Configuration # # -# AT91SAM3 GPIO Interrupt Configuration +# AT91SAM3/4 GPIO Interrupt Configuration # -# CONFIG_GPIOA_IRQ is not set -# CONFIG_GPIOB_IRQ is not set -# CONFIG_GPIOC_IRQ is not set # # External Memory Configuration @@ -137,7 +177,8 @@ CONFIG_ARCH_IRQPRIO=y CONFIG_ARCH_HAVE_VFORK=y CONFIG_ARCH_STACKDUMP=y # CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +# CONFIG_ARCH_RAMFUNCS is not set CONFIG_ARCH_HAVE_RAMVECTORS=y # CONFIG_ARCH_RAMVECTORS is not set @@ -273,21 +314,25 @@ CONFIG_DEV_NULL=y CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_UART0=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_UART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# UART0 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set @@ -323,6 +368,7 @@ CONFIG_FS_FAT=y # CONFIG_FS_NXFFS is not set # CONFIG_FS_ROMFS is not set # CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set # # System Logging @@ -355,7 +401,7 @@ CONFIG_MM_REGIONS=3 # CONFIG_BINFMT_EXEPATH is not set # CONFIG_NXFLAT is not set # CONFIG_ELF is not set -# CONFIG_BUILTIN is not set +CONFIG_BUILTIN=y # CONFIG_PIC is not set # CONFIG_SYMTAB_ORDEREDBYNAME is not set @@ -408,6 +454,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Built-In Applications # +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples @@ -443,7 +490,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PASHELLO is not set # CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set # CONFIG_EXAMPLES_RGMP is not set @@ -451,6 +497,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set # CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMART is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set @@ -505,6 +552,7 @@ CONFIG_EXAMPLES_NSH=y # NSH Library # CONFIG_NSH_LIBRARY=y +CONFIG_NSH_BUILTIN_APPS=y # # Disable Individual commands @@ -556,6 +604,7 @@ CONFIG_NSH_LIBRARY=y CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 +CONFIG_NSH_MAXARGUMENTS=6 CONFIG_NSH_NESTDEPTH=3 # CONFIG_NSH_DISABLESCRIPT is not set # CONFIG_NSH_DISABLEBG is not set @@ -565,7 +614,7 @@ CONFIG_NSH_CONSOLE=y # USB Trace Support # # CONFIG_NSH_CONDEV is not set -# CONFIG_NSH_ARCHINIT is not set +CONFIG_NSH_ARCHINIT=y # # NxWidgets/NxWM diff --git a/nuttx/configs/sam3u-ek/nx/defconfig b/nuttx/configs/sam3u-ek/nx/defconfig index 7329bd2a40..feb302b271 100644 --- a/nuttx/configs/sam3u-ek/nx/defconfig +++ b/nuttx/configs/sam3u-ek/nx/defconfig @@ -80,6 +80,7 @@ CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="sam34" # CONFIG_ARMV7M_USEBASEPRI is not set +# CONFIG_ARCH_HAVE_FPU is not set CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set @@ -91,35 +92,74 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set CONFIG_ARMV7M_OABI_TOOLCHAIN=y +# CONFIG_GPIO_IRQ is not set # -# AT91SAM3/SAM4 Configuration Options +# AT91SAM3/4 Configuration Options # CONFIG_ARCH_CHIP_AT91SAM3U4E=y +# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4A is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32B is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16B is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S16C is not set +# CONFIG_ARCH_CHIP_ATSAM4S16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S8C is not set +# CONFIG_ARCH_CHIP_ATSAM4S8B is not set CONFIG_ARCH_CHIP_SAM3U=y - -# -# AT91SAM3 Peripheral Support -# -# CONFIG_SAM34_DMA is not set -# CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y +# CONFIG_ARCH_CHIP_SAM4L is not set +# CONFIG_ARCH_CHIP_SAM4S is not set + +# +# AT91SAM3/4 Peripheral Support +# +# CONFIG_SAM34_SPI is not set +# CONFIG_SAM34_SSC is not set +# CONFIG_SAM34_TC0 is not set +# CONFIG_SAM34_TC1 is not set +# CONFIG_SAM34_TC2 is not set +# CONFIG_SAM34_PWM is not set +# CONFIG_SAM34_TWIM0 is not set +# CONFIG_SAM34_TWIS0 is not set +# CONFIG_SAM34_TWIM1 is not set +# CONFIG_SAM34_TWIS1 is not set +CONFIG_SAM34_UART0=y # CONFIG_SAM34_USART0 is not set # CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set # CONFIG_SAM34_USART3 is not set +# CONFIG_SAM34_ADC12B is not set +# CONFIG_SAM34_ADC is not set +# CONFIG_SAM34_SMC is not set +# CONFIG_SAM34_NAND is not set +# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_UDPHS is not set +# CONFIG_SAM34_RTC is not set +# CONFIG_SAM34_RTT is not set +# CONFIG_SAM34_WDT is not set +# CONFIG_SAM34_HSMCI is not set # -# AT91SAM3 UART Configuration +# AT91SAM3/4 USART Configuration # # -# AT91SAM3 GPIO Interrupt Configuration +# AT91SAM3/4 GPIO Interrupt Configuration # -# CONFIG_GPIOA_IRQ is not set -# CONFIG_GPIOB_IRQ is not set -# CONFIG_GPIOC_IRQ is not set # # External Memory Configuration @@ -137,7 +177,8 @@ CONFIG_ARCH_IRQPRIO=y CONFIG_ARCH_HAVE_VFORK=y CONFIG_ARCH_STACKDUMP=y # CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +# CONFIG_ARCH_RAMFUNCS is not set CONFIG_ARCH_HAVE_RAMVECTORS=y # CONFIG_ARCH_RAMVECTORS is not set @@ -149,7 +190,7 @@ CONFIG_BOARD_LOOPSPERMSEC=4768 CONFIG_DRAM_START=0x20000000 CONFIG_DRAM_SIZE=32768 CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_INTERRUPTSTACK=1024 # # Boot options @@ -281,8 +322,8 @@ CONFIG_LCD_MAXPOWER=31 # CONFIG_LCD_ST7567 is not set # CONFIG_LCD_UG2864AMBAG01 is not set # CONFIG_LCD_SSD1289 is not set -CONFIG_LCD_LANDSCAPE=y -# CONFIG_LCD_PORTRAIT is not set +# CONFIG_LCD_LANDSCAPE is not set +CONFIG_LCD_PORTRAIT=y # CONFIG_LCD_RPORTRAIT is not set # CONFIG_LCD_RLANDSCAPE is not set @@ -299,21 +340,25 @@ CONFIG_LCD_LANDSCAPE=y CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_UART0=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_UART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# UART0 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set @@ -378,9 +423,9 @@ CONFIG_NX_KBD=y # Framed Window Borders # CONFIG_NXTK_BORDERWIDTH=4 -CONFIG_NXTK_BORDERCOLOR1=0 -CONFIG_NXTK_BORDERCOLOR2=0 -CONFIG_NXTK_BORDERCOLOR3=0 +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf # CONFIG_NXTK_AUTORAISE is not set # diff --git a/nuttx/configs/sam3u-ek/ostest/defconfig b/nuttx/configs/sam3u-ek/ostest/defconfig index 9152a05289..1cf406a934 100644 --- a/nuttx/configs/sam3u-ek/ostest/defconfig +++ b/nuttx/configs/sam3u-ek/ostest/defconfig @@ -80,6 +80,7 @@ CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="sam34" # CONFIG_ARMV7M_USEBASEPRI is not set +# CONFIG_ARCH_HAVE_FPU is not set CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set @@ -91,35 +92,74 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set CONFIG_ARMV7M_OABI_TOOLCHAIN=y +# CONFIG_GPIO_IRQ is not set # -# AT91SAM3/SAM4 Configuration Options +# AT91SAM3/4 Configuration Options # CONFIG_ARCH_CHIP_AT91SAM3U4E=y +# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4A is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32B is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16B is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S16C is not set +# CONFIG_ARCH_CHIP_ATSAM4S16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S8C is not set +# CONFIG_ARCH_CHIP_ATSAM4S8B is not set CONFIG_ARCH_CHIP_SAM3U=y - -# -# AT91SAM3 Peripheral Support -# -# CONFIG_SAM34_DMA is not set -# CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y +# CONFIG_ARCH_CHIP_SAM4L is not set +# CONFIG_ARCH_CHIP_SAM4S is not set + +# +# AT91SAM3/4 Peripheral Support +# +# CONFIG_SAM34_SPI is not set +# CONFIG_SAM34_SSC is not set +# CONFIG_SAM34_TC0 is not set +# CONFIG_SAM34_TC1 is not set +# CONFIG_SAM34_TC2 is not set +# CONFIG_SAM34_PWM is not set +# CONFIG_SAM34_TWIM0 is not set +# CONFIG_SAM34_TWIS0 is not set +# CONFIG_SAM34_TWIM1 is not set +# CONFIG_SAM34_TWIS1 is not set +CONFIG_SAM34_UART0=y # CONFIG_SAM34_USART0 is not set # CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set # CONFIG_SAM34_USART3 is not set +# CONFIG_SAM34_ADC12B is not set +# CONFIG_SAM34_ADC is not set +# CONFIG_SAM34_SMC is not set +# CONFIG_SAM34_NAND is not set +# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_UDPHS is not set +# CONFIG_SAM34_RTC is not set +# CONFIG_SAM34_RTT is not set +# CONFIG_SAM34_WDT is not set +# CONFIG_SAM34_HSMCI is not set # -# AT91SAM3 UART Configuration +# AT91SAM3/4 USART Configuration # # -# AT91SAM3 GPIO Interrupt Configuration +# AT91SAM3/4 GPIO Interrupt Configuration # -# CONFIG_GPIOA_IRQ is not set -# CONFIG_GPIOB_IRQ is not set -# CONFIG_GPIOC_IRQ is not set # # External Memory Configuration @@ -137,7 +177,8 @@ CONFIG_ARCH_IRQPRIO=y CONFIG_ARCH_HAVE_VFORK=y CONFIG_ARCH_STACKDUMP=y # CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +# CONFIG_ARCH_RAMFUNCS is not set CONFIG_ARCH_HAVE_RAMVECTORS=y # CONFIG_ARCH_RAMVECTORS is not set @@ -272,20 +313,24 @@ CONFIG_DEV_NULL=y CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_UART0=y CONFIG_MCU_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_UART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# UART0 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set @@ -429,7 +474,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/sam3u-ek/src/Makefile b/nuttx/configs/sam3u-ek/src/Makefile index 8dbf0eae59..788a506204 100644 --- a/nuttx/configs/sam3u-ek/src/Makefile +++ b/nuttx/configs/sam3u-ek/src/Makefile @@ -42,7 +42,7 @@ AOBJS = $(ASRCS:.S=$(OBJEXT)) CSRCS = up_boot.c up_leds.c up_buttons.c up_spi.c up_usbdev.c -ifeq ($(CONFIG_SAM34_HSMCI),y) +ifeq ($(CONFIG_LCD),y) CSRCS += up_lcd.c endif diff --git a/nuttx/configs/sam3u-ek/src/sam3u-ek.h b/nuttx/configs/sam3u-ek/src/sam3u-ek.h index 21e0e2649a..df53985cf5 100644 --- a/nuttx/configs/sam3u-ek/src/sam3u-ek.h +++ b/nuttx/configs/sam3u-ek/src/sam3u-ek.h @@ -138,7 +138,12 @@ #define GPIO_LCD_BKL (GPIO_OUTPUT|GPIO_CFG_DEFAULT|GPIO_OUTPUT_CLEAR|GPIO_PORT_PIOC|GPIO_PIN19) -/* Touchscreen controller (TSC) */ +/* Touchscreen controller (TSC) + * + * BUSY is high impedance when CS is high (not selected). When CS is + * is low, BUSY is active high. Since the pin is pulled up, it will appear + * busy if CS is not selected. + */ #define GPIO_TCS_IRQ (GPIO_INPUT|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN24) #define GPIO_TCS_BUSY (GPIO_INPUT|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN2) diff --git a/nuttx/configs/sam3u-ek/src/up_lcd.c b/nuttx/configs/sam3u-ek/src/up_lcd.c index ebeb35d911..5951f7a185 100644 --- a/nuttx/configs/sam3u-ek/src/up_lcd.c +++ b/nuttx/configs/sam3u-ek/src/up_lcd.c @@ -88,7 +88,7 @@ * other custom usage). * * The SAM3U4E communicates with the LCD through PIOB where a 16-bit parallel - * “8080-like” protocol data bus has to be implemented by software. + * 8080-like protocol data bus has to be implemented by software. * * LCD backlight is made of 4 white chip LEDs in parallel, driven by an AAT3194 * charge pump, MN4. The AAT3194 is controlled by the SAM3U4E through a single line @@ -125,7 +125,7 @@ #include "up_arch.h" #include "sam_gpio.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam_smc.h" #include "sam3u-ek.h" @@ -910,7 +910,7 @@ int up_lcdinitialize(void) putreg32(regval, SAM_SMCCS_SETUP(2)); regval = (5 << SMCCS_PULSE_NWEPULSE_SHIFT) | (18 << SMCCS_PULSE_NCSWRPULSE_SHIFT) | - (5 << SMCCS_PULSE_RDPULSE_SHIFT) | (18 << SMCCS_PULSE_NCSRDPULSE_SHIFT); + (5 << SMCCS_PULSE_NRDPULSE_SHIFT) | (18 << SMCCS_PULSE_NCSRDPULSE_SHIFT); putreg32(regval, SAM_SMCCS_PULSE(2)); regval = (22 << SMCCS_CYCLE_NWECYCLE_SHIFT) | (22 << SMCCS_CYCLE_NRDCYCLE_SHIFT); diff --git a/nuttx/configs/sam3u-ek/src/up_nsh.c b/nuttx/configs/sam3u-ek/src/up_nsh.c index dfa2961170..ded7d5527a 100644 --- a/nuttx/configs/sam3u-ek/src/up_nsh.c +++ b/nuttx/configs/sam3u-ek/src/up_nsh.c @@ -50,8 +50,6 @@ #include "sam_hsmci.h" #include "sam3u-ek.h" -#ifdef CONFIG_SAM34_HSMCI - /**************************************************************************** * Pre-Processor Definitions ****************************************************************************/ @@ -63,19 +61,10 @@ #define NSH_HAVE_USBDEV 1 #define NSH_HAVE_MMCSD 1 -#if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 -# error "Only one MMC/SD slot" -# undef CONFIG_NSH_MMCSDSLOTNO -#endif - -#ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -#endif - -/* Can't support USB features if USB is not enabled */ +/* Can't support MMC/SD if the card interface is not enable */ -#ifndef CONFIG_USBDEV -# undef NSH_HAVE_USBDEV +#ifndef CONFIG_SAM34_HSMCI +# undef NSH_HAVE_MMCSD #endif /* Can't support MMC/SD features if mountpoints are disabled or if SDIO support @@ -86,8 +75,25 @@ # undef NSH_HAVE_MMCSD #endif -#ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 +#ifdef NSH_HAVE_MMCSD +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot" +# undef CONFIG_NSH_MMCSDSLOTNO +# endif + +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif + +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#endif + +/* Can't support USB features if USB is not enabled */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVE_USBDEV #endif /* Debug ********************************************************************/ @@ -155,4 +161,3 @@ int nsh_archinitialize(void) #endif return OK; } -#endif diff --git a/nuttx/configs/sam3u-ek/src/up_touchscreen.c b/nuttx/configs/sam3u-ek/src/up_touchscreen.c index 251d9b624b..f8b465748e 100644 --- a/nuttx/configs/sam3u-ek/src/up_touchscreen.c +++ b/nuttx/configs/sam3u-ek/src/up_touchscreen.c @@ -183,7 +183,9 @@ static bool tsc_busy(FAR struct ads7843e_config_s *state) static bool last = (bool)-1; #endif - /* REVISIT: This might need to be inverted */ + /* BUSY is high impedance when CS is high (not selected). When CS is + * is low, BUSY is active high. + */ bool busy = sam_gpioread(GPIO_TCS_BUSY); #if defined(CONFIG_DEBUG_INPUT) && defined(CONFIG_DEBUG_VERBOSE) diff --git a/nuttx/configs/sam4l-xplained/README.txt b/nuttx/configs/sam4l-xplained/README.txt index ea97942f7a..6057223ec1 100644 --- a/nuttx/configs/sam4l-xplained/README.txt +++ b/nuttx/configs/sam4l-xplained/README.txt @@ -15,7 +15,7 @@ Contents - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain - LEDs - - Virtual COM Port + - Serial Consoles - SAM4L Xplained Pro-specific Configuration Options - Configurations @@ -243,8 +243,27 @@ LEDs apparently, running normmally. If LED0 is flashing at approximately 2Hz, then a fatal error has been detected and the system has halted. -Virtual COM Port -^^^^^^^^^^^^^^^^ +Serial Consoles +^^^^^^^^^^^^^^^ + + USART0 + ------ + + USART is available on connectors EXT1 and EXT4 + + EXT1 TXT4 GPIO Function + ---- ---- ------ ----------- + 13 13 PB00 USART0_RXD + 14 14 PB01 USART0_TXD + 19 19 GND + 20 20 VCC + + If you have a TTL to RS-232 convertor then this is the most convenient + serial console to use. It is the default in all of these configurations. + An option is to use the virtual COM port. + + Virtual COM Port + ---------------- The SAM4L Xplained Pro contains an Embedded Debugger (EDBG) that can be used to program and debug the ATSAM4LC4C using Serial Wire Debug (SWD). @@ -268,7 +287,7 @@ SAM4L Xplained Pro-specific Configuration Options CONFIG_ARCH_architecture - For use in C code: - CONFIG_ARCH_CORTEXM3=y + CONFIG_ARCH_CORTEXM4=y CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory @@ -278,8 +297,8 @@ SAM4L Xplained Pro-specific Configuration Options chip: CONFIG_ARCH_CHIP_SAM34 - CONFIG_ARCH_CHIP_SAM3U - CONFIG_ARCH_CHIP_AT91SAM3U4 + CONFIG_ARCH_CHIP_SAM4L + CONFIG_ARCH_CHIP_ATSAM4LC4C CONFIG_ARCH_BOARD - Identifies the configs subdirectory and hence, the board that supports the particular chip or SoC. @@ -298,7 +317,7 @@ SAM4L Xplained Pro-specific Configuration Options CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case): - CONFIG_DRAM_SIZE=0x0000c000 (48Kb) + CONFIG_DRAM_SIZE=0x00008000 (32Kb) CONFIG_DRAM_START - The start address of installed DRAM @@ -329,15 +348,61 @@ SAM4L Xplained Pro-specific Configuration Options Individual subsystems can be enabled: - CONFIG_SAM34_DMA - CONFIG_SAM34_HSMCI - CONFIG_SAM34_NAND + CPU + --- + CONFIG_SAM34_OCD + + HSB + --- + CONFIG_SAM34_APBA + CONFIG_SAM34_AESA + + PBA + --- + CONFIG_SAM34_IISC CONFIG_SAM34_SPI - CONFIG_SAM34_UART + CONFIG_SAM34_TC0 + CONFIG_SAM34_TC1 + CONFIG_SAM34_TWIM0 + CONFIG_SAM34_TWIS0 + CONFIG_SAM34_TWIM1 + CONFIG_SAM34_TWIS1 CONFIG_SAM34_USART0 CONFIG_SAM34_USART1 CONFIG_SAM34_USART2 CONFIG_SAM34_USART3 + CONFIG_SAM34_ADC12B + CONFIG_SAM34_DACC + CONFIG_SAM34_ACC + CONFIG_SAM34_GLOC + CONFIG_SAM34_ABDACB + CONFIG_SAM34_TRNG + CONFIG_SAM34_PARC + CONFIG_SAM34_CATB + CONFIG_SAM34_TWIM2 + CONFIG_SAM34_TWIM3 + CONFIG_SAM34_LCDCA + + PBB + --- + CONFIG_SAM34_HRAMC1 + CONFIG_SAM34_HMATRIX + CONFIG_SAM34_PDCA + CONFIG_SAM34_CRCCU + CONFIG_SAM34_USBC + CONFIG_SAM34_PEVC + + PBC + --- + CONFIG_SAM34_CHIPID + CONFIG_SAM34_FREQM + + PBD + --- + CONFIG_SAM34_AST + CONFIG_SAM34_WDT + CONFIG_SAM34_EIC + CONFIG_SAM34_PICOUART Some subsystems can be configured to operate in different ways. The drivers need to know how to configure the subsystem. @@ -350,7 +415,7 @@ SAM4L Xplained Pro-specific Configuration Options CONFIG_USART2_ISUART CONFIG_USART3_ISUART - AT91SAM3U specific device driver settings + ST91SAM4L specific device driver settings CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=0,1,2,3) or UART m (m=4,5) for the console and ttys0 (default is the USART1). @@ -363,36 +428,96 @@ SAM4L Xplained Pro-specific Configuration Options CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity CONFIG_U[S]ARTn_2STOP - Two stop bits - LCD Options. Other than the standard LCD configuration options - (see configs/README.txt), the SAM4L Xplained Pro driver also supports: - - CONFIG_LCD_PORTRAIT - Present the display in the standard 240x320 - "Portrait" orientation. Default: The display is rotated to - support a 320x240 "Landscape" orientation. - Configurations ^^^^^^^^^^^^^^ -Each SAM4L Xplained Pro configuration is maintained in a sub-directory and -can be selected as follow: + Each SAM4L Xplained Pro configuration is maintained in a sub-directory and + can be selected as follow: cd tools ./configure.shsam4l-xplained/ cd - . ./setenv.sh -Before sourcing the setenv.sh file above, you should examine it and perform -edits as necessary so that BUILDROOT_BIN is the correct path to the directory -than holds your toolchain binaries. + Before sourcing the setenv.sh file above, you should examine it and perform + edits as necessary so that BUILDROOT_BIN is the correct path to the directory + than holds your toolchain binaries. -And then build NuttX by simply typing the following. At the conclusion of -the make, the nuttx binary will reside in an ELF file called, simply, nuttx. + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, nuttx. make -The that is provided above as an argument to the tools/configure.sh -must be is one of the following: + The that is provided above as an argument to the tools/configure.sh + must be is one of the following. + + NOTE: These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + +Configuration sub-directories +----------------------------- ostest: - This configuration directory, performs a simple OS test using + This configuration directory performs a simple OS test using examples/ostest. + + NOTES: + + 1. This configuration provides test output on USART0 which is available + on EXT1 or EXT4 (see the section "Serial Consoles" above). The + virtual COM port could be used, instead, by reconfiguring to use + USART1 instead of USART0: + + System Type -> AT91SAM3/4 Peripheral Support + CONFIG_SAM_USART0=y + CONFIG_SAM_USART1=n + + Device Drivers -> Serial Driver Support -> Serial Console + CONFIG_USART0_SERIAL_CONSOLE=y + + Device Drivers -> Serial Driver Support -> USART0 Configuration + CONFIG_USART0_2STOP=0 + CONFIG_USART0_BAUD=115200 + CONFIG_USART0_BITS=8 + CONFIG_USART0_PARITY=0 + CONFIG_USART0_RXBUFSIZE=256 + CONFIG_USART0_TXBUFSIZE=256 + + 2. This configuration is set up to use the NuttX OABI toolchain (see + above). Of course this can be reconfigured if you prefer a different + toolchain. + + nsh: + This configuration directory will built the NuttShell. + + NOTES: + + 1. This configuration provides test output on USART0 which is available + on EXT1 or EXT4 (see the section "Serial Consoles" above). The + virtual COM port could be used, instead, by reconfiguring to use + USART1 instead of USART0: + + System Type -> AT91SAM3/4 Peripheral Support + CONFIG_SAM_USART0=y + CONFIG_SAM_USART1=n + + Device Drivers -> Serial Driver Support -> Serial Console + CONFIG_USART0_SERIAL_CONSOLE=y + + Device Drivers -> Serial Driver Support -> USART0 Configuration + CONFIG_USART0_2STOP=0 + CONFIG_USART0_BAUD=115200 + CONFIG_USART0_BITS=8 + CONFIG_USART0_PARITY=0 + CONFIG_USART0_RXBUFSIZE=256 + CONFIG_USART0_TXBUFSIZE=256 + + 2. This configuration is set up to use the NuttX OABI toolchain (see + above). Of course this can be reconfigured if you prefer a different + toolchain. diff --git a/nuttx/configs/sam4l-xplained/include/board.h b/nuttx/configs/sam4l-xplained/include/board.h index 4aaefd3fbc..de175a484f 100644 --- a/nuttx/configs/sam4l-xplained/include/board.h +++ b/nuttx/configs/sam4l-xplained/include/board.h @@ -54,66 +54,144 @@ ************************************************************************************/ /* Clocking *************************************************************************/ -/* After power-on reset, the sam3u device is running on a 4MHz internal RC. These - * definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=48MHz. - */ - -/* Main oscillator register settings */ - -#define BOARD_CKGR_MOR_MOSCXTST (63 << CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ -/* PLLA configuration */ +/* Select the DFLL as the source of the system clock. + * + * Options (define one): + * BOARD_SYSCLK_SOURCE_RCSYS - System RC oscillator + * BOARD_SYSCLK_SOURCE_OSC0 - Oscillator 0 + * BOARD_SYSCLK_SOURCE_PLL0 - Phase Locked Loop 0 + * BOARD_SYSCLK_SOURCE_DFLL0 - Digital Frequency Locked Loop + * BOARD_SYSCLK_SOURCE_RC80M - 80 MHz RC oscillator + * BOARD_SYSCLK_SOURCE_FCFAST12M - 12 MHz RC oscillator + * BOARD_SYSCLK_SOURCE_FCFAST8M - 8 MHz RC oscillator + * BOARD_SYSCLK_SOURCE_FCFAST4M - 4 MHz RC oscillator + * BOARD_SYSCLK_SOURCE_RC1M - 1 MHz RC oscillator + */ -#define BOARD_CKGR_PLLAR_MULA (7 << CKGR_PLLAR_MULA_SHIFT) -#define BOARD_CKGR_PLLAR_STMODE CKGR_PLLAR_STMODE_FAST -#define BOARD_CKGR_PLLAR_PLLACOUNT (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) -#define BOARD_CKGR_PLLAR_DIVA CKGR_PLLAR_DIVA_BYPASS +#define BOARD_SYSCLK_SOURCE_DFLL0 1 -/* PMC master clock register settings */ +/* Nominal frequencies in on-chip RC oscillators. These are *not* configurable + * but appear here for use in frequency calculations. NOTE: These may frequencies + * may vary with temperature changes. + */ -#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA -#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2 +#define BOARD_RCSYS_FREQUENCY 115000 /* Nominal frequency of RCSYS (Hz) */ +#define BOARD_RC32K_FREQUENCY 32768 /* Nominal frequency of RC32K (Hz) */ +#define BOARD_RC80M_FREQUENCY 80000000 /* Nominal frequency of RC80M (Hz) */ +#define BOARD_RCFAST4M_FREQUENCY 4000000 /* Nominal frequency of RCFAST4M (Hz) */ +#define BOARD_RCFAST8M_FREQUENCY 8000000 /* Nominal frequency of RCFAST8M (Hz) */ +#define BOARD_RCFAST12M_FREQUENCY 12000000 /* Nominal frequency of RCFAST12M (Hz) */ +#define BOARD_RC1M_FREQUENCY 1000000 /* Nominal frequency of RC1M (Hz) */ + +/* The SAM4L Xplained Pro has two on-board crystals: + * XC100 12MHz OSC0 + * XC101 32.768KHz OSC32 + */ -/* USB UTMI PLL start-up time */ +/* OSC0 Configuration */ -#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << CKGR_UCKR_UPLLCOUNT_SHIFT) +#define BOARD_OSC0_FREQUENCY 12000000 /* 12MHz XTAL */ -/* System clock dividers: Fbus = Fsys / (2 ^ BUS_div) */ +/* OSC32 Configuration */ -#define BOARD_SYSCLK_CPU_DIV 0 -#define BOARD_SYSCLK_PBA_DIV 0 -#define BOARD_SYSCLK_PBB_DIV 0 -#define BOARD_SYSCLK_PBC_DIV 0 -#define BOARD_SYSCLK_PBD_DIV 0 +#define BOARD_OSC32_FREQUENCY 32768 /* 32.768KHz XTAL */ +#define BOARD_OSC32_STARTUP_US 6100 +#define BOARD_OSC32_SELCURR BSCIF_OSCCTRL32_SELCURR_300 +#define BOARD_OSC32_ISXTAL 1 /* OSC32 is a crystal */ -/* Resulting frequencies */ +/* Digital Frequency Locked Loop configuration + * Fdfll = (Fclk * DFLLmul) / DFLLdiv + * = 32768 * (48000000/32768) / 1 = 48MHz + * + * The actual frequency is 47.97MHz due to truncation of the multiplier. + * The 48MHz target value is treated as "not-to-exceed" value). Use OSC0 + * if you need more accuracy (12MHz with a multiplier of 4). + * + * DFLL0 source options (select one): + * BOARD_DFLL0_SOURCE_RCSYS - System RC oscillator + * BOARD_DFLL0_SOURCE_OSC32K - 32.768KHz oscillator + * BOARD_DFLL0_SOURCE_OSC0 - Oscillator 0 + * BOARD_DFLL0_SOURCE_RC80M - 80 MHz RC oscillator + * BOARD_DFLL0_SOURCE_RC32K - 32 kHz RC oscillator + * + * NOTE: Nothing must be defined if the DFPLL is not used + */ -#define SAM_MAINOSC_FREQUENCY (12000000) -#define SAM_MCK_FREQUENCY (48000000) -#define SAM_PLLA_FREQUENCY (96000000) -#define SAM_CPU_FREQUENCY (48000000) +#define BOARD_DFLL0_SOURCE_OSC32K 1 +#define BOARD_DFLL0_TARGET 48000000 +#define BOARD_DFLL0_MUL (BOARD_DFLL0_TARGET / BOARD_OSC32_FREQUENCY) +#define BOARD_DFLL0_DIV 1 +#define BOARD_DFLL0_FREQUENCY (BOARD_OSC32_FREQUENCY * BOARD_DFLL0_MUL / BOARD_DFLL0_DIV) -/* HSMCI clocking +/* Phase Locked Loop configuration + * Fdfll = (Fclk * PLLmul) / PLLdiv * - * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) - * divided by (2*(CLKDIV+1)). + * PLL0 source options (select one): + * BOARD_PLL0_SOURCE_OSC0 - Oscillator 0 + * BOARD_PLL0_SOURCE_GCLK9 - General clock 9 * - * MCI_SPEED = MCK / (2*(CLKDIV+1)) - * CLKDIV = MCI / MCI_SPEED / 2 - 1 + * BOARD_GLCK9_SOURCE_RCSYS - System RC oscillator + * BOARD_GLCK9_SOURCE_OSC32K - Output from OSC32K + * BOARD_GLCK9_SOURCE_DFLL0 - Output from DFLL0 + * BOARD_GLCK9_SOURCE_OSC0 - Output from Oscillator0 + * BOARD_GLCK9_SOURCE_RC80M - Output from 80MHz RCOSC + * BOARD_GLCK9_SOURCE_RCFAST - Output from 4,8,12MHz RCFAST + * BOARD_GLCK9_SOURCE_RC1M - Output from 1MHz RC1M + * BOARD_GLCK9_SOURCE_CPUCLK - The CPU clock + * BOARD_GLCK9_SOURCE_HSBCLK - High Speed Bus clock + * BOARD_GLCK9_SOURCE_PBACLK - Peripheral Bus A clock + * BOARD_GLCK9_SOURCE_PBBCLK - Peripheral Bus B clock + * BOARD_GLCK9_SOURCE_PBCCLK - Peripheral Bus C clock + * BOARD_GLCK9_SOURCE_PBDCLK - Peripheral Bus D clock + * BOARD_GLCK9_SOURCE_RC32K - Output from 32kHz RCOSC + * + * NOTE: Nothing must be defined if the PLL0 is not used */ -/* MCK = 48MHz, CLKDIV = 59, MCI_SPEED = 48MHz / 2 * (59+1) = 400 KHz */ +/* System clock dividers: Fbus = Fmck >> BUSshift */ -#define HSMCI_INIT_CLKDIV (59 << HSMCI_MR_CLKDIV_SHIFT) +#define BOARD_CPU_SHIFT 0 /* Fcpu = Fmck = 48MHz */ +#define BOARD_PBA_SHIFT 0 /* Fpba = Fmck = 48MHz */ +#define BOARD_PBB_SHIFT 0 /* Fpbb = Fmck = 48MHz */ +#define BOARD_PBC_SHIFT 0 /* Fpbc = Fmck = 48MHz */ +#define BOARD_PBD_SHIFT 0 /* Fpbd = Fmck = 48MHz */ -/* MCK = 48MHz, CLKDIV = 1, MCI_SPEED = 48MHz / 2 * (1+1) = 12 MHz */ +/* Resulting frequencies */ -#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT) +#define BOARD_MCK_FREQUENCY (BOARD_DFLL0_FREQUENCY) +#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_CPU_SHIFT) +#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBA_SHIFT) +#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBB_SHIFT) +#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBC_SHIFT) +#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBD_SHIFT) -/* MCK = 48MHz, CLKDIV = 0, MCI_SPEED = 48MHz / 2 * (0+1) = 24 MHz */ +/* USBC. + * + * "The USBC has two bus clocks connected: One High Speed Bus clock + * (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks + * are generated by the Power Manager. Both clocks are enabled at reset + * and can be disabled by the Power Manager. It is recommended to disable + * the USBC before disabling the clocks, to avoid freezing the USBC in + * an undefined state. + * + * "To follow the usb data rate at 12Mbit/s in full-speed mode, the + * CLK_USBC_AHB clock should be at minimum 12MHz. + * + * "The 48MHz USB clock is generated by a dedicated generic clock from + * the SCIF module. Before using the USB, the user must ensure that the + * USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module." + * + * USB Generic Clock 7 (GCLK_USBC) source selection (one only) + * + * BOARD_USBC_SRC_OSC0 + * BOARD_USBC_SRC_PLL0 + * BOARD_USBC_SRC_DFLL + * BOARD_USBC_SRC_GCLKIN0 + */ -#define HSMCI_SDXFR_CLKDIV (0 << HSMCI_MR_CLKDIV_SHIFT) -#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV +#define BOARD_USBC_SRC_DFLL 1 /* Source DFLL0 at 48MHz */ +#define BOARD_USBC_GCLK_DIV 1 /* Fusb = Fdfll / 1 = 48MHz */ /* LED definitions ******************************************************************/ /* There are three LEDs on board the SAM4L Xplained Pro board: The EDBG @@ -135,7 +213,7 @@ #define BOARD_LED0_BIT (1 << BOARD_LED0) /* When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will - * control LED0 as defined below. Thus is LED0 is statically on, NuttX has + * control LED0 as defined below. Thus if LED0 is statically on, NuttX has * successfully booted and is, apparently, running normmally. If LED0 is * flashing at approximately 2Hz, then a fatal error has been detected and the * system has halted. @@ -175,10 +253,21 @@ #define BUTTON_SW0_BIT (1 << BUTTON_SW0) /* Alternate Function Disambiguation ************************************************/ -/* The SAM4L Xplained Pro contains an Embedded Debugger (EDBG) that can be - * used to program and debug the ATSAM4LC4C using Serial Wire Debug (SWD). - * The Embedded debugger also include a Virtual Com port interface over - * USART1. Virtual COM port connections: +/* USART0 is also available on connectors EXT1 and EXT4: + * + * EXT1 TXT4 GPIO Function + * ---- ---- ------ ----------- + * 13 13 PB00 USART0_RXD + * 14 14 PB01 USART0_TXD + */ + +#define GPIO_USART0_RXD GPIO_USART0_RXD_4 +#define GPIO_USART0_TXD GPIO_USART0_TXD_4 + +/* The SAM4L Xplained Pro contains an Embedded Debugger (EDBG) that can be used to + * program and debug the ATSAM4LC4C using Serial Wire Debug (SWD). The Embedded + * debugger also include a Virtual Com port interface over USART1. Virtual COM + * port connections: * * PC26 USART1 RXD * PC27 USART1 TXD diff --git a/nuttx/configs/sam3u-ek/touchscreen/Make.defs b/nuttx/configs/sam4l-xplained/nsh/Make.defs similarity index 97% rename from nuttx/configs/sam3u-ek/touchscreen/Make.defs rename to nuttx/configs/sam4l-xplained/nsh/Make.defs index 436d316c8d..25cdee290d 100644 --- a/nuttx/configs/sam3u-ek/touchscreen/Make.defs +++ b/nuttx/configs/sam4l-xplained/nsh/Make.defs @@ -1,7 +1,7 @@ ############################################################################ -# configs/sam3u-ek/touchscreen/Make.defs +# configs/sam4l-xplained/nsh/Make.defs # -# Copyright (C) 2011 Gregory Nutt. All rights reserved. +# Copyright (C) 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without diff --git a/nuttx/configs/sam3u-ek/touchscreen/defconfig b/nuttx/configs/sam4l-xplained/nsh/defconfig similarity index 71% rename from nuttx/configs/sam3u-ek/touchscreen/defconfig rename to nuttx/configs/sam4l-xplained/nsh/defconfig index f2d933864f..a2c2551f77 100644 --- a/nuttx/configs/sam3u-ek/touchscreen/defconfig +++ b/nuttx/configs/sam4l-xplained/nsh/defconfig @@ -76,10 +76,11 @@ CONFIG_ARCH="arm" CONFIG_ARCH_CHIP_SAM34=y # CONFIG_ARCH_CHIP_STM32 is not set # CONFIG_ARCH_CHIP_STR71X is not set -CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_CORTEXM4=y CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="sam34" # CONFIG_ARMV7M_USEBASEPRI is not set +# CONFIG_ARCH_HAVE_FPU is not set CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set @@ -93,32 +94,88 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # -# AT91SAM3/SAM4 Configuration Options -# -CONFIG_ARCH_CHIP_AT91SAM3U4E=y -CONFIG_ARCH_CHIP_SAM3U=y - -# -# AT91SAM3 Peripheral Support -# -# CONFIG_SAM34_DMA is not set -# CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y -# CONFIG_SAM34_USART0 is not set +# AT91SAM3/4 Configuration Options +# +# CONFIG_ARCH_CHIP_AT91SAM3U4E is not set +# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2A is not set +CONFIG_ARCH_CHIP_ATSAM4LC4C=y +# CONFIG_ARCH_CHIP_ATSAM4LC4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4A is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD32C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD32B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD16C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD16B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SA16C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SA16B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S16C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S16B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S8C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S8B is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +CONFIG_ARCH_CHIP_SAM4L=y +# CONFIG_ARCH_CHIP_SAM4S is not set + +# +# AT91SAM3/4 Peripheral Support +# +CONFIG_SAM_PICOCACHE=y +# CONFIG_SAM34_OCD is not set +# CONFIG_SAM34_APBA is not set +# CONFIG_SAM34_AESA is not set +# CONFIG_SAM34_IISC is not set +# CONFIG_SAM34_SPI is not set +# CONFIG_SAM34_TC0 is not set +# CONFIG_SAM34_TC1 is not set +# CONFIG_SAM34_TWIM0 is not set +# CONFIG_SAM34_TWIS0 is not set +# CONFIG_SAM34_TWIM1 is not set +# CONFIG_SAM34_TWIS1 is not set +# CONFIG_SAM34_TWIM2 is not set +# CONFIG_SAM34_TWIM3 is not set +# CONFIG_SAM34_PICOUART is not set +CONFIG_SAM34_USART0=y # CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set # CONFIG_SAM34_USART3 is not set -CONFIG_SAM34_SPI=y - -# -# AT91SAM3 UART Configuration -# - -# -# AT91SAM3 GPIO Interrupt Configuration -# -CONFIG_GPIOA_IRQ=y +# CONFIG_SAM34_ADCIFE is not set +# CONFIG_SAM34_DACC is not set +# CONFIG_SAM34_ACIFC is not set +# CONFIG_SAM34_GLOC is not set +# CONFIG_SAM34_ABDACB is not set +# CONFIG_SAM34_TRNG is not set +# CONFIG_SAM34_PARC is not set +# CONFIG_SAM34_CATB is not set +# CONFIG_SAM34_LCDCA is not set +# CONFIG_SAM34_HRAMC1 is not set +# CONFIG_SAM34_HMATRIX is not set +# CONFIG_SAM34_PDCA is not set +# CONFIG_SAM34_CRCCU is not set +# CONFIG_SAM34_USBC is not set +# CONFIG_SAM34_PEVC is not set +# CONFIG_SAM34_CHIPID is not set +# CONFIG_SAM34_FREQM is not set +# CONFIG_SAM34_AST is not set +# CONFIG_SAM34_WDT is not set +# CONFIG_SAM34_EIC is not set +# CONFIG_SAM32_RESET_PERIPHCLKS is not set + +# +# AT91SAM3/4 USART Configuration +# +CONFIG_USART0_ISUART=y + +# +# AT91SAM3/4 GPIO Interrupt Configuration +# +# CONFIG_GPIOA_IRQ is not set # CONFIG_GPIOB_IRQ is not set # CONFIG_GPIOC_IRQ is not set @@ -138,14 +195,15 @@ CONFIG_ARCH_IRQPRIO=y CONFIG_ARCH_HAVE_VFORK=y CONFIG_ARCH_STACKDUMP=y # CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y CONFIG_ARCH_HAVE_RAMVECTORS=y # CONFIG_ARCH_RAMVECTORS is not set # # Board Settings # -CONFIG_BOARD_LOOPSPERMSEC=4768 +CONFIG_BOARD_LOOPSPERMSEC=3410 # CONFIG_ARCH_CALIBRATION is not set CONFIG_DRAM_START=0x20000000 CONFIG_DRAM_SIZE=32768 @@ -164,9 +222,9 @@ CONFIG_BOOT_RUNFROMFLASH=y # # Board Selection # -CONFIG_ARCH_BOARD_SAM3UEK=y +CONFIG_ARCH_BOARD_SAM4L_XPLAINED=y # CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="sam3u-ek" +CONFIG_ARCH_BOARD="sam4l-xplained" # # Common Board Options @@ -193,16 +251,16 @@ CONFIG_RR_INTERVAL=200 CONFIG_TASK_NAME_SIZE=0 # CONFIG_SCHED_HAVE_PARENT is not set # CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=9 -CONFIG_START_DAY=30 +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=6 +CONFIG_START_DAY=9 CONFIG_DEV_CONSOLE=y # CONFIG_MUTEX_TYPES is not set # CONFIG_PRIORITY_INHERITANCE is not set # CONFIG_FDCLONE_DISABLE is not set # CONFIG_FDCLONE_STDIO is not set CONFIG_SDCLONE_DISABLE=y -CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_WAITPID is not set # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set @@ -213,7 +271,7 @@ CONFIG_DISABLE_OS_API=y # CONFIG_DISABLE_PTHREAD is not set # CONFIG_DISABLE_SIGNALS is not set # CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set +CONFIG_DISABLE_ENVIRON=y # # Signal Numbers @@ -222,7 +280,6 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 -CONFIG_SIG_SIGWORK=17 # # Sizes of configurable things (0 disables) @@ -243,9 +300,9 @@ CONFIG_PREALLOC_TIMERS=4 # Stack and heap information # CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=1536 CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 +CONFIG_PTHREAD_STACK_DEFAULT=1536 # # Device Drivers @@ -258,55 +315,14 @@ CONFIG_DEV_NULL=y # CONFIG_CAN is not set # CONFIG_PWM is not set # CONFIG_I2C is not set -CONFIG_SPI=y -# CONFIG_SPI_OWNBUS is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set # CONFIG_AUDIO_DEVICES is not set # CONFIG_BCH is not set -CONFIG_INPUT=y -# CONFIG_INPUT_TSC2007 is not set -CONFIG_INPUT_ADS7843E=y -# CONFIG_ADS7843E_MULTIPLE is not set -CONFIG_ADS7843E_SPIDEV=0 -CONFIG_ADS7843E_DEVMINOR=0 -CONFIG_ADS7843E_SPIMODE=0 -CONFIG_ADS7843E_FREQUENCY=100000 -# CONFIG_ADS7843E_SWAPXY is not set -CONFIG_ADS7843E_THRESHX=12 -CONFIG_ADS7843E_THRESHY=12 -# CONFIG_INPUT_STMPE811 is not set -CONFIG_LCD=y - -# -# Common LCD Settings -# -# CONFIG_LCD_NOGETRUN is not set -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_MAXPOWER=31 - -# -# Graphic LCD Devices -# -# CONFIG_LCD_P14201 is not set -# CONFIG_LCD_NOKIA6100 is not set -# CONFIG_LCD_MIO283QT2 is not set -# CONFIG_LCD_UG9664HSWAG01 is not set -# CONFIG_LCD_ST7567 is not set -# CONFIG_LCD_UG2864AMBAG01 is not set -# CONFIG_LCD_SSD1289 is not set -# CONFIG_LCD_LANDSCAPE is not set -CONFIG_LCD_PORTRAIT=y -# CONFIG_LCD_RPORTRAIT is not set -# CONFIG_LCD_RLANDSCAPE is not set - -# -# Alphanumeric/Segment LCD Devices -# -# CONFIG_LCD_LCD1602 is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set # CONFIG_MMCSD is not set # CONFIG_MTD is not set # CONFIG_PIPES is not set @@ -316,21 +332,25 @@ CONFIG_LCD_PORTRAIT=y CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_USART0=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_USART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# USART0 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_USART0_RXBUFSIZE=256 +CONFIG_USART0_TXBUFSIZE=256 +CONFIG_USART0_BAUD=115200 +CONFIG_USART0_BITS=8 +CONFIG_USART0_PARITY=0 +CONFIG_USART0_2STOP=0 +# CONFIG_USART0_IFLOWCONTROL is not set +# CONFIG_USART0_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set @@ -358,12 +378,7 @@ CONFIG_UART_2STOP=0 # # CONFIG_DISABLE_MOUNTPOINT is not set # CONFIG_FS_RAMMAP is not set -CONFIG_FS_FAT=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=32 -# CONFIG_FS_FATTIME is not set -# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_FAT is not set # CONFIG_FS_NXFFS is not set # CONFIG_FS_ROMFS is not set # CONFIG_FS_SMARTFS is not set @@ -378,66 +393,7 @@ CONFIG_FAT_MAXFNAME=32 # # Graphics Support # -CONFIG_NX=y -CONFIG_NX_LCDDRIVER=y -CONFIG_NX_NPLANES=1 -# CONFIG_NX_WRITEONLY is not set - -# -# Supported Pixel Depths -# -CONFIG_NX_DISABLE_1BPP=y -CONFIG_NX_DISABLE_2BPP=y -CONFIG_NX_DISABLE_4BPP=y -CONFIG_NX_DISABLE_8BPP=y -# CONFIG_NX_DISABLE_16BPP is not set -CONFIG_NX_DISABLE_24BPP=y -CONFIG_NX_DISABLE_32BPP=y -# CONFIG_NX_PACKEDMSFIRST is not set - -# -# Input Devices -# -CONFIG_NX_MOUSE=y -CONFIG_NX_KBD=y - -# -# Framed Window Borders -# -CONFIG_NXTK_BORDERWIDTH=4 -CONFIG_NXTK_BORDERCOLOR1=0 -CONFIG_NXTK_BORDERCOLOR2=0 -CONFIG_NXTK_BORDERCOLOR3=0 -# CONFIG_NXTK_AUTORAISE is not set - -# -# Font Selections -# -CONFIG_NXFONTS_CHARBITS=7 -# CONFIG_NXFONT_MONO5X8 is not set -# CONFIG_NXFONT_SANS17X22 is not set -# CONFIG_NXFONT_SANS20X26 is not set -CONFIG_NXFONT_SANS23X27=y -# CONFIG_NXFONT_SANS22X29 is not set -# CONFIG_NXFONT_SANS28X37 is not set -# CONFIG_NXFONT_SANS39X48 is not set -# CONFIG_NXFONT_SANS17X23B is not set -# CONFIG_NXFONT_SANS20X27B is not set -# CONFIG_NXFONT_SANS22X29B is not set -# CONFIG_NXFONT_SANS28X37B is not set -# CONFIG_NXFONT_SANS40X49B is not set -# CONFIG_NXFONT_SERIF22X29 is not set -# CONFIG_NXFONT_SERIF29X37 is not set -# CONFIG_NXFONT_SERIF38X48 is not set -# CONFIG_NXFONT_SERIF22X28B is not set -# CONFIG_NXFONT_SERIF27X38B is not set -# CONFIG_NXFONT_SERIF38X49B is not set -# CONFIG_NXCONSOLE is not set - -# -# NX Multi-user only options -# -# CONFIG_NX_MULTIUSER is not set +# CONFIG_NX is not set # # Memory Management @@ -456,7 +412,6 @@ CONFIG_MM_REGIONS=3 # Binary Formats # # CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set # CONFIG_NXFLAT is not set # CONFIG_ELF is not set CONFIG_BUILTIN=y @@ -473,7 +428,6 @@ CONFIG_BUILTIN=y CONFIG_STDIO_BUFFER_SIZE=64 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBM is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set # CONFIG_LIBC_FLOATINGPOINT is not set @@ -484,7 +438,7 @@ CONFIG_LIB_RAND_ORDER=1 CONFIG_EOL_IS_EITHER_CRLF=y # CONFIG_LIBC_EXECFUNCS is not set CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 # CONFIG_LIBC_STRERROR is not set # CONFIG_LIBC_PERROR_STDOUT is not set CONFIG_ARCH_LOWPUTC=y @@ -495,12 +449,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Library Support # -CONFIG_SCHED_WORKQUEUE=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WORKPRIORITY=192 -CONFIG_SCHED_WORKPERIOD=50000 -CONFIG_SCHED_WORKSTACKSIZE=1024 -# CONFIG_SCHED_LPWORK is not set +# CONFIG_SCHED_WORKQUEUE is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set @@ -508,7 +457,14 @@ CONFIG_SCHED_WORKSTACKSIZE=1024 # Basic CXX Support # # CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_CXX_NEWLONG=y + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set # # Application Configuration @@ -525,6 +481,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CAN is not set # CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -542,41 +499,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BUILTIN=y -CONFIG_EXAMPLES_NX_VPLANE=0 -CONFIG_EXAMPLES_NX_DEVNO=0 -# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set -CONFIG_EXAMPLES_NX_BGCOLOR=0x7b5d -CONFIG_EXAMPLES_NX_COLOR1=0xe73f -CONFIG_EXAMPLES_NX_COLOR2=0xdefb -CONFIG_EXAMPLES_NX_TBCOLOR=0xad55 -CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 -CONFIG_EXAMPLES_NX_DEFAULT_FONT=y -CONFIG_EXAMPLES_NX_BPP=16 -# CONFIG_EXAMPLES_NX_RAWWINDOWS is not set -# CONFIG_EXAMPLES_NX_EXTERNINIT is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXCONSOLE is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXFLAT is not set -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_VPLANE=0 -CONFIG_EXAMPLES_NXHELLO_DEVNO=0 -CONFIG_EXAMPLES_NXHELLO_BPP=16 - -# -# Example Color Configuration -# -# CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set -CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NXHELLO_FONTCOLOR=0xffdf - -# -# Example Font Configuration -# -# CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT is not set -CONFIG_EXAMPLES_NXHELLO_FONTID=6 -# CONFIG_EXAMPLES_NXHELLO_EXTERNINIT is not set +# CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -596,10 +523,7 @@ CONFIG_EXAMPLES_NXHELLO_FONTID=6 # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_THTTPD is not set # CONFIG_EXAMPLES_TIFF is not set -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 -CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" -CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 +# CONFIG_EXAMPLES_TOUCHSCREEN is not set # CONFIG_EXAMPLES_UDP is not set # CONFIG_EXAMPLES_UIP is not set # CONFIG_EXAMPLES_USBSERIAL is not set @@ -700,6 +624,7 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 +CONFIG_NSH_MAXARGUMENTS=6 CONFIG_NSH_NESTDEPTH=3 # CONFIG_NSH_DISABLESCRIPT is not set # CONFIG_NSH_DISABLEBG is not set diff --git a/nuttx/configs/sam3u-ek/touchscreen/setenv.sh b/nuttx/configs/sam4l-xplained/nsh/setenv.sh similarity index 65% rename from nuttx/configs/sam3u-ek/touchscreen/setenv.sh rename to nuttx/configs/sam4l-xplained/nsh/setenv.sh index 868c4de389..f83126fdf3 100755 --- a/nuttx/configs/sam3u-ek/touchscreen/setenv.sh +++ b/nuttx/configs/sam4l-xplained/nsh/setenv.sh @@ -1,7 +1,7 @@ #!/bin/bash -# configs/sam3u-ek/toolchain/setenv.sh +# configs/sam4l-xplained/nsh/setenv.sh # -# Copyright (C) 2010 Gregory Nutt. All rights reserved. +# Copyright (C) 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -32,16 +32,32 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then + +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi - WD=`pwd` -export BUILDROOT_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" -export PATH="${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi -echo "PATH : ${PATH}" +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/sam4l-xplained/ostest/defconfig b/nuttx/configs/sam4l-xplained/ostest/defconfig index 3cab5109b3..3d674f4558 100644 --- a/nuttx/configs/sam4l-xplained/ostest/defconfig +++ b/nuttx/configs/sam4l-xplained/ostest/defconfig @@ -94,7 +94,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # -# AT91SAM3/SAM4 Configuration Options +# AT91SAM3/4 Configuration Options # # CONFIG_ARCH_CHIP_AT91SAM3U4E is not set # CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set @@ -124,25 +124,56 @@ CONFIG_ARCH_CHIP_SAM4L=y # CONFIG_ARCH_CHIP_SAM4S is not set # -# AT91SAM3 Peripheral Support +# AT91SAM3/4 Peripheral Support # -# CONFIG_SAM34_DMA is not set -# CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_HSMCI is not set -# CONFIG_SAM34_UART is not set -# CONFIG_SAM34_USART0 is not set -CONFIG_SAM34_USART1=y +CONFIG_SAM_PICOCACHE=y +# CONFIG_SAM34_OCD is not set +# CONFIG_SAM34_APBA is not set +# CONFIG_SAM34_AESA is not set +# CONFIG_SAM34_IISC is not set +# CONFIG_SAM34_SPI is not set +# CONFIG_SAM34_TC0 is not set +# CONFIG_SAM34_TC1 is not set +# CONFIG_SAM34_TWIM0 is not set +# CONFIG_SAM34_TWIS0 is not set +# CONFIG_SAM34_TWIM1 is not set +# CONFIG_SAM34_TWIS1 is not set +# CONFIG_SAM34_TWIM2 is not set +# CONFIG_SAM34_TWIM3 is not set +# CONFIG_SAM34_PICOUART is not set +CONFIG_SAM34_USART0=y +# CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set # CONFIG_SAM34_USART3 is not set -# CONFIG_SAM34_SPI is not set - -# -# AT91SAM3 UART Configuration -# -CONFIG_USART1_ISUART=y - -# -# AT91SAM3 GPIO Interrupt Configuration +# CONFIG_SAM34_ADCIFE is not set +# CONFIG_SAM34_DACC is not set +# CONFIG_SAM34_ACIFC is not set +# CONFIG_SAM34_GLOC is not set +# CONFIG_SAM34_ABDACB is not set +# CONFIG_SAM34_TRNG is not set +# CONFIG_SAM34_PARC is not set +# CONFIG_SAM34_CATB is not set +# CONFIG_SAM34_LCDCA is not set +# CONFIG_SAM34_HRAMC1 is not set +# CONFIG_SAM34_HMATRIX is not set +# CONFIG_SAM34_PDCA is not set +# CONFIG_SAM34_CRCCU is not set +# CONFIG_SAM34_USBC is not set +# CONFIG_SAM34_PEVC is not set +# CONFIG_SAM34_CHIPID is not set +# CONFIG_SAM34_FREQM is not set +# CONFIG_SAM34_AST is not set +# CONFIG_SAM34_WDT is not set +# CONFIG_SAM34_EIC is not set +# CONFIG_SAM32_RESET_PERIPHCLKS is not set + +# +# AT91SAM3/4 USART Configuration +# +CONFIG_USART0_ISUART=y + +# +# AT91SAM3/4 GPIO Interrupt Configuration # # CONFIG_GPIOA_IRQ is not set # CONFIG_GPIOB_IRQ is not set @@ -164,14 +195,15 @@ CONFIG_ARCH_IRQPRIO=y CONFIG_ARCH_HAVE_VFORK=y CONFIG_ARCH_STACKDUMP=y # CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y CONFIG_ARCH_HAVE_RAMVECTORS=y # CONFIG_ARCH_RAMVECTORS is not set # # Board Settings # -CONFIG_BOARD_LOOPSPERMSEC=4768 +CONFIG_BOARD_LOOPSPERMSEC=3410 # CONFIG_ARCH_CALIBRATION is not set CONFIG_DRAM_START=0x20000000 CONFIG_DRAM_SIZE=32768 @@ -299,20 +331,24 @@ CONFIG_DEV_NULL=y CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_USART1=y +CONFIG_ARCH_HAVE_USART0=y CONFIG_MCU_SERIAL=y -CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# USART1 Configuration +# USART0 Configuration # -CONFIG_USART1_RXBUFSIZE=256 -CONFIG_USART1_TXBUFSIZE=256 -CONFIG_USART1_BAUD=115200 -CONFIG_USART1_BITS=8 -CONFIG_USART1_PARITY=0 -CONFIG_USART1_2STOP=0 +CONFIG_USART0_RXBUFSIZE=256 +CONFIG_USART0_TXBUFSIZE=256 +CONFIG_USART0_BAUD=115200 +CONFIG_USART0_BITS=8 +CONFIG_USART0_PARITY=0 +CONFIG_USART0_2STOP=0 +# CONFIG_USART0_IFLOWCONTROL is not set +# CONFIG_USART0_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set @@ -456,7 +492,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/sam4l-xplained/scripts/ld.script b/nuttx/configs/sam4l-xplained/scripts/ld.script index 751ab0299f..7a225b9991 100755 --- a/nuttx/configs/sam4l-xplained/scripts/ld.script +++ b/nuttx/configs/sam4l-xplained/scripts/ld.script @@ -33,8 +33,8 @@ * ****************************************************************************/ -/* The ATSAM4LC4C has 256Kb of FLASH beginning at address 0x0000:0000 and - * 32Kb of SRAM beginning at address 0x2000:0000 +/* The ATSAM4LC4C has 256KB of FLASH beginning at address 0x0000:0000 and + * 32KB of SRAM beginning at address 0x2000:0000 */ MEMORY @@ -63,7 +63,21 @@ SECTIONS _etext = ABSOLUTE(.); } > flash - _eronly = ABSOLUTE(.); + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } >flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } >flash + __exidx_end = ABSOLUTE(.); .data : { _sdata = ABSOLUTE(.); @@ -73,15 +87,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sram AT > flash - .ARM.extab : { - *(.ARM.extab*) - } >sram + _eronly = LOADADDR(.data); - .ARM.exidx : { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } >sram + .ramfunc ALIGN(4): { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > flash + + _framfuncs = LOADADDR(.ramfunc); .bss : { _sbss = ABSOLUTE(.); diff --git a/nuttx/configs/sam4l-xplained/src/Makefile b/nuttx/configs/sam4l-xplained/src/Makefile index 15b5ff67ef..01813faf4c 100644 --- a/nuttx/configs/sam4l-xplained/src/Makefile +++ b/nuttx/configs/sam4l-xplained/src/Makefile @@ -42,6 +42,10 @@ AOBJS = $(ASRCS:.S=$(OBJEXT)) CSRCS = sam_boot.c sam_spi.c +ifeq ($(CONFIG_HAVE_CXX),y) +CSRCS += sam_cxxinitialize.c +endif + ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += sam_autoleds.c else diff --git a/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h b/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h index e9efe88fea..ba6978a822 100644 --- a/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h +++ b/nuttx/configs/sam4l-xplained/src/sam4l-xplained.h @@ -1,7 +1,7 @@ /************************************************************************************ - * configs/sam3uek_eval/src/sam4l-xplained.h + * configs/sam4l-xplained/src/sam4l-xplained.h * - * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -80,8 +80,8 @@ * 2Hz, then a fatal error has been detected and the system has halted. */ -#define GPIO_LED0 (GPIO_OUTPUT | GPIO_PULL_NONE | GPIO_PORTC | \ - GPIO_OUTPUT_SET | GPIO_PIN7) +#define GPIO_LED0 (GPIO_OUTPUT | GPIO_PULL_NONE | GPIO_OUTPUT_SET | \ + GPIO_PORTC | GPIO_PIN7) /* QTouch button: The SAM4L Xplained Pro kit has one QTouch button. The connection * to the SAM4L is: @@ -99,8 +99,8 @@ * PC24 SW0 */ -#define GPIO_SW0 (GPIO_INPUT | GPIO_PULL_UP | GPIO_GLITCH_FILTER | GPIO_PORTC | \ - GPIO_PIN24) +#define GPIO_SW0 (GPIO_INPUT | GPIO_PULL_UP | GPIO_GLITCH_FILTER | \ + GPIO_PORTC | GPIO_PIN24) #define IRQ_SW0 SAM_IRQ_PC24 /************************************************************************************ diff --git a/nuttx/configs/sam4l-xplained/src/sam_autoleds.c b/nuttx/configs/sam4l-xplained/src/sam_autoleds.c index 09b673a966..06d647b63f 100644 --- a/nuttx/configs/sam4l-xplained/src/sam_autoleds.c +++ b/nuttx/configs/sam4l-xplained/src/sam_autoleds.c @@ -123,19 +123,19 @@ void up_ledon(int led) switch (led) { - case LED_STARTED : /* NuttX has been started LED0=OFF */ - case LED_HEAPALLOCATE: /* Heap has been allocated LED0=OFF */ - case LED_IRQSENABLED: /* Interrupts enabled LED0=OFF */ + case 0: /* LED_STARTED: NuttX has been started LED0=OFF */ + /* LED_HEAPALLOCATE: Heap has been allocated LED0=OFF */ + /* LED_IRQSENABLED: Interrupts enabled LED0=OFF */ break; /* Leave ledstate == true to turn OFF */ default: - case LED_INIRQ: /* In an interrupt LED0=N/C */ - case LED_SIGNAL: /* In a signal handler LED0=N/C */ - case LED_ASSERTION: /* An assertion failed LED0=N/C */ - return; + case 2: /* LED_INIRQ: In an interrupt LED0=N/C */ + /* LED_SIGNAL: In a signal handler LED0=N/C */ + /* LED_ASSERTION: An assertion failed LED0=N/C */ + return; /* Return to leave LED0 unchanged */ - case LED_PANIC: /* The system has crashed LED0=FLASH */ - case LED_STACKCREATED: /* Idle stack created LED0=ON */ + case 3: /* LED_PANIC: The system has crashed LED0=FLASH */ + case 1: /* LED_STACKCREATED: Idle stack created LED0=ON */ ledstate = false; /* Set ledstate == false to turn ON */ break; } @@ -154,21 +154,21 @@ void up_ledoff(int led) /* These should not happen and are ignored */ default: - case LED_STARTED : /* NuttX has been started LED0=OFF */ - case LED_HEAPALLOCATE: /* Heap has been allocated LED0=OFF */ - case LED_IRQSENABLED: /* Interrupts enabled LED0=OFF */ - case LED_STACKCREATED: /* Idle stack created LED0=ON */ + case 0: /* LED_STARTED: NuttX has been started LED0=OFF */ + /* LED_HEAPALLOCATE: Heap has been allocated LED0=OFF */ + /* LED_IRQSENABLED: Interrupts enabled LED0=OFF */ + case 1: /* LED_STACKCREATED: Idle stack created LED0=ON */ /* These result in no-change */ - case LED_INIRQ: /* In an interrupt LED0=N/C */ - case LED_SIGNAL: /* In a signal handler LED0=N/C */ - case LED_ASSERTION: /* An assertion failed LED0=N/C */ - return; + case 2: /* LED_INIRQ: In an interrupt LED0=N/C */ + /* LED_SIGNAL: In a signal handler LED0=N/C */ + /* LED_ASSERTION: An assertion failed LED0=N/C */ + return; /* Return to leave LED0 unchanged */ /* Turn LED0 off set driving the output high */ - case LED_PANIC: /* The system has crashed LED0=FLASH */ + case 3: /* LED_PANIC: The system has crashed LED0=FLASH */ sam_gpiowrite(GPIO_LED0, true); break; } diff --git a/nuttx/configs/sam4l-xplained/src/sam_cxxinitialize.c b/nuttx/configs/sam4l-xplained/src/sam_cxxinitialize.c new file mode 100644 index 0000000000..1958e09185 --- /dev/null +++ b/nuttx/configs/sam4l-xplained/src/sam_cxxinitialize.c @@ -0,0 +1,154 @@ +/************************************************************************************ + * configs/sam4l-xplained/src/sam_cxxinitialize.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include +#include "chip.h" + +#if defined(CONFIG_HAVE_CXX) && defined(CONFIG_HAVE_CXXINITIALIZE) + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Debug ****************************************************************************/ +/* Non-standard debug that may be enabled just for testing the static constructors */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_CXX +#endif + +#ifdef CONFIG_DEBUG_CXX +# define cxxdbg dbg +# define cxxlldbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define cxxvdbg vdbg +# define cxxllvdbg llvdbg +# else +# define cxxvdbg(x...) +# define cxxllvdbg(x...) +# endif +#else +# define cxxdbg(x...) +# define cxxlldbg(x...) +# define cxxvdbg(x...) +# define cxxllvdbg(x...) +#endif + +/************************************************************************************ + * Private Types + ************************************************************************************/ +/* This type defines one entry in initialization array */ + +typedef void (*initializer_t)(void); + +/************************************************************************************ + * External references + ************************************************************************************/ +/* _sinit and _einit are symbols exported by the linker script that mark the + * beginning and the end of the C++ initialization section. + */ + +extern initializer_t _sinit; +extern initializer_t _einit; + +/* _stext and _etext are symbols exported by the linker script that mark the + * beginning and the end of text. + */ + +extern uint32_t _stext; +extern uint32_t _etext; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: up_cxxinitialize + * + * Description: + * If C++ and C++ static constructors are supported, then this function + * must be provided by board-specific logic in order to perform + * initialization of the static C++ class instances. + * + * This function should then be called in the application-specific + * user_start logic in order to perform the C++ initialization. NOTE + * that no component of the core NuttX RTOS logic is involved; This + * function defintion only provides the 'contract' between application + * specific C++ code and platform-specific toolchain support + * + ***************************************************************************/ + +void up_cxxinitialize(void) +{ + initializer_t *initp; + + cxxdbg("_sinit: %p _einit: %p _stext: %p _etext: %p\n", + &_sinit, &_einit, &_stext, &_etext); + + /* Visit each entry in the initialzation table */ + + for (initp = &_sinit; initp != &_einit; initp++) + { + initializer_t initializer = *initp; + cxxdbg("initp: %p initializer: %p\n", initp, initializer); + + /* Make sure that the address is non-NULL and lies in the text region + * defined by the linker script. Some toolchains may put NULL values + * or counts in the initialization table + */ + + if ((void*)initializer > (void*)&_stext && (void*)initializer < (void*)&_etext) + { + cxxdbg("Calling %p\n", initializer); + initializer(); + } + } +} + +#endif /* CONFIG_HAVE_CXX && CONFIG_HAVE_CXXINITIALIZE */ + diff --git a/nuttx/configs/sam4s-xplained/Kconfig b/nuttx/configs/sam4s-xplained/Kconfig new file mode 100644 index 0000000000..76aa30c149 --- /dev/null +++ b/nuttx/configs/sam4s-xplained/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_SAM4S_XPLAINED +endif diff --git a/nuttx/configs/sam4s-xplained/README.txt b/nuttx/configs/sam4s-xplained/README.txt new file mode 100644 index 0000000000..536189ac06 --- /dev/null +++ b/nuttx/configs/sam4s-xplained/README.txt @@ -0,0 +1,599 @@ +README +^^^^^^ + + This README discusses issues unique to NuttX configurations for the + Atmel SAM4S Xplained development board. This board features the + ATSAM4S16C MCU with 1MB FLASH and 128KB. + + The SAM4S Xplained features: + + - 120 MHz Cortex-M4 with MPU + - 12MHz crystal (no 32.768KHz crystal) + - Segger J-Link JTAG emulator on-board for program and debug + - MICRO USB A/B connector for USB connectivity + - IS66WV51216DBLL ISSI SRAM 8Mb 512K x 16 55ns PSRAM 2.5v-3.6v + - Four Atmel QTouch buttons + - External voltage input + - Four LEDs, two controllable from software + - Xplained expansion headers + - Footprint for external serial Flash (not fitted) + +Contents +^^^^^^^^ + + - PIO Muxing + - Development Environment + - GNU Toolchain Options + - IDEs + - NuttX EABI "buildroot" Toolchain + - NuttX OABI "buildroot" Toolchain + - NXFLAT Toolchain + - Buttons and LEDs + - Serial Consoles + - SAM4S Xplained-specific Configuration Options + - Configurations + +PIO Muxing +^^^^^^^^^^ + + PA0 SMC_A17 PB0 J2.3 default PC0 SMC_D0 + PA1 SMC_A18 PB1 J2.4 PC1 SMC_D1 + PA2 J3.7 default PB2 J1.3 & J4.3 PC2 SMC_D2 + PA3 J1.1 & J4.1 PB3 J1.4 & J4.4 PC3 SMC_D3 + PA4 J1.2 & J4.2 PB4 JTAG PC4 SMC_D4 + PA5 User_button BP2 PB5 JTAG PC5 SMC_D5 + PA6 J3.7 optional PB6 JTAG PC6 SMC_D6 + PA7 CLK_32K PB7 JTAG PC7 SMC_D7 + PA8 CLK_32K PB8 CLK_12M PC8 SMC_NWE + PA9 RX_UART0 PB9 CLK_12M PC9 Power on detect + PA10 TX_UART0 PB10 USB_DDM PC10 User LED D9 + PA11 J3.2 default PB11 USB_DDP PC11 SMC_NRD + PA12 MISO PB12 ERASE PC12 J2.2 + PA13 MOSI PB13 J2.3 optional PC13 J2.7 + PA14 SPCK PB14 N/A PC14 SMC_NCS0 + PA15 J3.5 PC15 SMC_NSC1 + PA16 J3.6 PC16 N/A + PA17 J2.5 PC17 User LED D10 + PA18 J3.4 & SMC_A14 PC18 SMC_A0 + PA19 J3.4 optional & SMC_A15 PC19 SMC_A1 + PA20 J3.1 & SMC_A16 PC20 SMC_A2 + PA21 J2.6 PC21 SMC_A3 + PA22 J2.1 PC22 SMC_A4 + PA23 J3.3 PC23 SMC_A5 + PA24 TSLIDR_SL_SN PC24 SMC_A6 + PA25 TSLIDR_SL_SNSK PC25 SMC_A7 + PA26 TSLIDR_SM_SNS PC26 SMC_A8 + PA27 TSLIDR_SM_SNSK PC27 SMC_A9 + PA28 TSLIDR_SR_SNS PC28 SMC_A10 + PA29 TSLIDR_SR_SNSK PC29 SMC_A11 + PA30 J4.5 PC30 SMC_A12 + PA31 J1.5 PC31 SMC_A13 + +Development Environment +^^^^^^^^^^^^^^^^^^^^^^^ + + Either Linux or Cygwin on Windows can be used for the development environment. + The source has been built only using the GNU toolchain (see below). Other + toolchains will likely cause problems. Testing was performed using the Cygwin + environment. + +GNU Toolchain Options +^^^^^^^^^^^^^^^^^^^^^ + + The NuttX make system has been modified to support the following different + toolchain options. + + 1. The CodeSourcery GNU toolchain, + 2. The devkitARM GNU toolchain, ok + 4. The NuttX buildroot Toolchain (see below). + + All testing has been conducted using the NuttX buildroot toolchain. However, + the make system is setup to default to use the devkitARM toolchain. To use + the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to + add one of the following configuration options to your .config (or defconfig) + file: + + CONFIG_SAM34_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_SAM34_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_SAM34_DEVKITARM=y : devkitARM under Windows + CONFIG_SAM34_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + + If you are not using CONFIG_SAM34_BUILDROOT, then you may also have to modify + the PATH in the setenv.h file if your make cannot find the tools. + + NOTE: the CodeSourcery (for Windows), devkitARM, and Raisonance toolchains are + Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot + toolchains are Cygwin and/or Linux native toolchains. There are several limitations + to using a Windows based toolchain in a Cygwin environment. The three biggest are: + + 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are + performed automatically in the Cygwin makefiles using the 'cygpath' utility + but you might easily find some new path problems. If so, check out 'cygpath -w' + + 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links + are used in Nuttx (e.g., include/arch). The make system works around these + problems for the Windows tools by copying directories instead of linking them. + But this can also cause some confusion for you: For example, you may edit + a file in a "linked" directory and find that your changes had no effect. + That is because you are building the copy of the file in the "fake" symbolic + directory. If you use a Windows toolchain, you should get in the habit of + making like this: + + make clean_context all + + An alias in your .bashrc file might make that less painful. + + 3. Dependencies are not made when using Windows versions of the GCC. This is + because the dependencies are generated using Windows pathes which do not + work with the Cygwin make. + + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + + NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization + level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with + -Os. + + NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that + the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM + path or will get the wrong version of make. + +IDEs +^^^^ + + NuttX is built using command-line make. It can be used with an IDE, but some + effort will be required to create the project (There is a simple RIDE project + in the RIDE subdirectory). + + Makefile Build + -------------- + Under Eclipse, it is pretty easy to set up an "empty makefile project" and + simply use the NuttX makefile to build the system. That is almost for free + under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty + makefile project in order to work with Windows (Google for "Eclipse Cygwin" - + there is a lot of help on the internet). + + Native Build + ------------ + Here are a few tips before you start that effort: + + 1) Select the toolchain that you will be using in your .config file + 2) Start the NuttX build at least one time from the Cygwin command line + before trying to create your project. This is necessary to create + certain auto-generated files and directories that will be needed. + 3) Set up include pathes: You will need include/, arch/arm/src/sam34, + arch/arm/src/common, arch/arm/src/armv7-m, and sched/. + 4) All assembly files need to have the definition option -D __ASSEMBLY__ + on the command line. + + Startup files will probably cause you some headaches. The NuttX startup file + is arch/arm/src/sam34/sam_vectors.S. You may need to build NuttX + one time from the Cygwin command line in order to obtain the pre-built + startup object needed by RIDE. + +NuttX EABI "buildroot" Toolchain +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + A GNU GCC-based toolchain is assumed. The files */setenv.sh should + be modified to point to the correct path to the Cortex-M3 GCC toolchain (if + different from the default in your PATH variable). + + If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX + SourceForge download site (https://sourceforge.net/projects/nuttx/files/buildroot/). + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in /nuttx. + + cd tools + ./configure.shsam4s-xplained/ + + 2. Download the latest buildroot package into + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename /buildroot-x.y.z to /buildroot. + + 4. cd /buildroot + + 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly built binaries. + + See the file configs/README.txt in the buildroot source tree. That has more + details PLUS some special instructions that you will need to follow if you are + building a Cortex-M3 toolchain for Cygwin under Windows. + + NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the + the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for + more information about this problem. If you plan to use NXFLAT, please do not + use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. + See instructions below. + +NuttX OABI "buildroot" Toolchain +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + The older, OABI buildroot toolchain is also available. To use the OABI + toolchain: + + 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 + configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI + configuration such as cortexm3-defconfig-4.3.3 + + 2. Modify the Make.defs file to use the OABI conventions: + + +CROSSDEV = arm-nuttx-elf- + +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft + +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections + -CROSSDEV = arm-nuttx-eabi- + -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft + -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections + +NXFLAT Toolchain +^^^^^^^^^^^^^^^^ + + If you are *not* using the NuttX buildroot toolchain and you want to use + the NXFLAT tools, then you will still have to build a portion of the buildroot + tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can + be downloaded from the NuttX SourceForge download site + (https://sourceforge.net/projects/nuttx/files/). + + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in /nuttx. + + cd tools + ./configure.sh lpcxpresso-lpc1768/ + + 2. Download the latest buildroot package into + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename /buildroot-x.y.z to /buildroot. + + 4. cd /buildroot + + 5. cp configs/cortexm3-defconfig-nxflat .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly builtNXFLAT binaries. + +Buttons and LEDs +^^^^^^^^^^^^^^^^ + + Buttons + ------- + + The SAM4S Xplained has two mechanical buttons. One button is the RESET button + connected to the SAM4S reset line and the other is a generic user configurable + button labeled BP2 and connected to GPIO PA5. When a button is pressed it + will drive the I/O line to GND. + + LEDs + ---- + + There are four LEDs on board the SAM4X Xplained board, two of these can be + controlled by software in the SAM4S: + + LED GPIO + ---------------- ----- + D9 Yellow LED PC10 + D10 Yellow LED PC17 + + Both can be illuminated by driving the GPIO output to ground (low). + + These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + defined. In that case, the usage by the board port is defined in + include/board.h and src/up_leds.c. The LEDs are used to encode OS-related + events as follows: + + SYMBOL Meaning LED state + D9 D10 + ------------------- ----------------------- -------- -------- + LED_STARTED NuttX has been started OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF + LED_IRQSENABLED Interrupts enabled OFF OFF + LED_STACKCREATED Idle stack created ON OFF + LED_INIRQ In an interrupt No change + LED_SIGNAL In a signal handler No change + LED_ASSERTION An assertion failed No change + LED_PANIC The system has crashed OFF Blinking + LED_IDLE MCU is is sleep mode Not used + + Thus if D9 is statically on, NuttX has successfully booted and is, + apparently, running normmally. If D10 is flashing at approximately + 2Hz, then a fatal error has been detected and the system has halted. + +Serial Consoles +^^^^^^^^^^^^^^^ + + USART0 + ------ + + If you have a TTL to RS-232 convertor then this is the most convenient + serial console to use. UART1 is the default in all of these + configurations. + + UART1 RXD PB2 J1 pin 3 J4 pin 3 + UART1 TXD PB3 J1 pin 4 J4 pin 4 + GND J1 pin 9 J4 pin 9 + Vdd J1 pin 10 J4 pin 10 + + USART1 is another option: + + USART1 RXD PA21 J2 pin 6 + USART1 TXD PA22 J2 pin 1 + GND J2 pin 9 + Vdd J2 pin 10 + + Yet another option is to use UART0 and the virtual COM port. This + option may be more convenient for long term development, but was + painful to use during board bring-up. + + Virtual COM Port + ---------------- + + The SAM4S Xplained contains an Embedded Debugger (EDBG) that can be + used to program and debug the ATSAM4S16C using Serial Wire Debug (SWD). + The Embedded debugger also include a Virtual Com port interface over + USART1. Virtual COM port connections: + + AT91SAM4S16 ATSAM3U4CAU + -------------- -------------- + PA9 RX_UART0 PA9_4S PA12 + PA10 TX_UART0 RX_3U PA11 + +SAM4S Xplained-specific Configuration Options +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + CONFIG_ARCH - Identifies the arch/ subdirectory. This should + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM4=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP="sam34" + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_SAM34 + CONFIG_ARCH_CHIP_SAM4S + CONFIG_ARCH_CHIP_ATSAM4S16C + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD=sam4s-xplained (for the SAM4S Xplained development board) + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_SAM4S_XPLAINED=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case): + + CONFIG_DRAM_SIZE=0x00008000 (32Kb) + + CONFIG_DRAM_START - The start address of installed DRAM + + CONFIG_DRAM_START=0x20000000 + + CONFIG_ARCH_IRQPRIO - The SAM3UF103Z supports interrupt prioritization + + CONFIG_ARCH_IRQPRIO=y + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibratre + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + + CONFIG_SAM34_RTC - Real Time Clock + CONFIG_SAM34_RTT - Real Time Timer + CONFIG_SAM34_WDT - Watchdog Timer + CONFIG_SAM34_UART0 - UART 0 + CONFIG_SAM34_UART1 - UART 1 + CONFIG_SAM34_SMC - Static Memory Controller + CONFIG_SAM34_USART0 - USART 0 + CONFIG_SAM34_USART1 - USART 1 + CONFIG_SAM34_HSMCI - High Speed Multimedia Card Interface + CONFIG_SAM34_TWI0 - Two-Wire Interface 0 + CONFIG_SAM34_TWI1 - Two-Wire Interface 1 + CONFIG_SAM34_SPI - Serial Peripheral Interface + CONFIG_SAM34_SSC - Synchronous Serial Controller + CONFIG_SAM34_TC0 - Timer Counter 0 + CONFIG_SAM34_TC1 - Timer Counter 1 + CONFIG_SAM34_TC2 - Timer Counter 2 + CONFIG_SAM34_TC3 - Timer Counter 3 + CONFIG_SAM34_TC4 - Timer Counter 4 + CONFIG_SAM34_TC5 - Timer Counter 5 + CONFIG_SAM34_ADC12B - 12-bit Analog To Digital Converter + CONFIG_SAM34_DACC - Digital To Analog Converter + CONFIG_SAM34_PWM - Pulse Width Modulation + CONFIG_SAM34_CRCCU - CRC Calculation Unit + CONFIG_SAM34_ACC - Analog Comparator + CONFIG_SAM34_UDP - USB Device Port + + Some subsystems can be configured to operate in different ways. The drivers + need to know how to configure the subsystem. + + CONFIG_GPIOA_IRQ + CONFIG_GPIOB_IRQ + CONFIG_GPIOC_IRQ + CONFIG_USART0_ISUART + CONFIG_USART1_ISUART + CONFIG_USART2_ISUART + CONFIG_USART3_ISUART + + ST91SAM4S specific device driver settings + + CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=0,1,2,3) or UART + m (m=4,5) for the console and ttys0 (default is the USART1). + CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be + CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8. + CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + CONFIG_U[S]ARTn_2STOP - Two stop bits + +Configurations +^^^^^^^^^^^^^^ + + Each SAM4S Xplained configuration is maintained in a sub-directory and + can be selected as follow: + + cd tools + ./configure.shsam4s-xplained/ + cd - + . ./setenv.sh + + Before sourcing the setenv.sh file above, you should examine it and perform + edits as necessary so that BUILDROOT_BIN is the correct path to the directory + than holds your toolchain binaries. + + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, nuttx. + + make + + The that is provided above as an argument to the tools/configure.sh + must be is one of the following. + + NOTE: These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + +Configuration sub-directories +----------------------------- + + ostest: + This configuration directory performs a simple OS test using + examples/ostest. + + NOTES: + + 1. This configuration provides test output on USART0 which is available + on EXT1 or EXT4 (see the section "Serial Consoles" above). The + virtual COM port could be used, instead, by reconfiguring to use + USART1 instead of USART0: + + System Type -> AT91SAM3/4 Peripheral Support + CONFIG_SAM_USART0=y + CONFIG_SAM_USART1=n + + Device Drivers -> Serial Driver Support -> Serial Console + CONFIG_USART0_SERIAL_CONSOLE=y + + Device Drivers -> Serial Driver Support -> USART0 Configuration + CONFIG_USART0_2STOP=0 + CONFIG_USART0_BAUD=115200 + CONFIG_USART0_BITS=8 + CONFIG_USART0_PARITY=0 + CONFIG_USART0_RXBUFSIZE=256 + CONFIG_USART0_TXBUFSIZE=256 + + 2. This configuration is set up to use the NuttX OABI toolchain (see + above). Of course this can be reconfigured if you prefer a different + toolchain. + + nsh: + This configuration directory will built the NuttShell. + + NOTES: + + 1. This configuration provides test output on UART1 which is available + on J3 or J4 (see the section "Serial Consoles" above). The + virtual COM port could be used, instead, by reconfiguring to use + UART0 instead of UART1: + + System Type -> AT91SAM3/4 Peripheral Support + CONFIG_SAM_UART0=y + CONFIG_SAM_UART1=n + + Device Drivers -> Serial Driver Support -> Serial Console + CONFIG_UART0_SERIAL_CONSOLE=y + + Device Drivers -> Serial Driver Support -> USART0 Configuration + CONFIG_UART0_2STOP=0 + CONFIG_UART0_BAUD=115200 + CONFIG_UART0_BITS=8 + CONFIG_UART0_PARITY=0 + CONFIG_UART0_RXBUFSIZE=256 + CONFIG_UART0_TXBUFSIZE=256 + + 2. This configuration is set up to use the NuttX OABI toolchain (see + above). Of course this can be reconfigured if you prefer a different + toolchain. + + nsh: + This configuration directory will built the NuttShell. + + NOTES: + + 1. This configuration provides test output on UART1 which is available + on J3 or J4 (see the section "Serial Consoles" above). The + virtual COM port could be used, instead, by reconfiguring to use + UART0 instead of UART1: + + System Type -> AT91SAM3/4 Peripheral Support + CONFIG_SAM_UART0=y + CONFIG_SAM_UART1=n + + Device Drivers -> Serial Driver Support -> Serial Console + CONFIG_UART0_SERIAL_CONSOLE=y + + Device Drivers -> Serial Driver Support -> USART0 Configuration + CONFIG_UART0_2STOP=0 + CONFIG_UART0_BAUD=115200 + CONFIG_UART0_BITS=8 + CONFIG_UART0_PARITY=0 + CONFIG_UART0_RXBUFSIZE=256 + CONFIG_UART0_TXBUFSIZE=256 + + 2. This configuration is set up to use the NuttX OABI toolchain (see + above). Of course this can be reconfigured if you prefer a different + toolchain. diff --git a/nuttx/configs/sam4s-xplained/include/board.h b/nuttx/configs/sam4s-xplained/include/board.h new file mode 100644 index 0000000000..7f29380a02 --- /dev/null +++ b/nuttx/configs/sam4s-xplained/include/board.h @@ -0,0 +1,323 @@ +/************************************************************************************ + * configs/sam4s-xplained/include/board.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAM4L_XPLAINED_INCLUDE_BOARD_H +#define __CONFIGS_SAM4L_XPLAINED_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# ifdef CONFIG_GPIO_IRQ +# include +# endif +#endif + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# ifdef CONFIG_GPIO_IRQ +# include +# endif +#endif + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* After power-on reset, the sam3u device is running on a 4MHz internal RC. These + * definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=120MHz. + */ + +/* Main oscillator register settings */ + +#define BOARD_CKGR_MOR_MOSCXTST (63 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ + +/* PLLA configuration: + * + * Source: 12MHz crystall at 12MHz + * PLLdiv: 10 + * PLLmul: 1 (bypassed) + * Fpll: (12MHz * 10) / 1 = 120MHz + */ + +#define BOARD_MAINOSC_FREQUENCY (12000000) +#define BOARD_CKGR_PLLAR_MUL (9 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS +#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define BOARD_PLLA_FREQUENCY (10*BOARD_MAINOSC_FREQUENCY) + +/* PMC master clock register settings */ + +#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA +#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1 +#define BOARD_MCK_FREQUENCY (BOARD_PLLA_FREQUENCY/1) +#define BOARD_CPU_FREQUENCY (BOARD_PLLA_FREQUENCY/1) + +/* USB UTMI PLL start-up time */ + +#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT) + +/* HSMCI clocking + * + * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + * divided by (2*(CLKDIV+1)). + * + * MCI_SPEED = MCK / (2*(CLKDIV+1)) + * CLKDIV = MCI / MCI_SPEED / 2 - 1 + */ + +/* MCK = 48MHz, CLKDIV = 59, MCI_SPEED = 48MHz / 2 * (59+1) = 400 KHz */ + +#define HSMCI_INIT_CLKDIV (59 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 48MHz, CLKDIV = 1, MCI_SPEED = 48MHz / 2 * (1+1) = 12 MHz */ + +#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 48MHz, CLKDIV = 0, MCI_SPEED = 48MHz / 2 * (0+1) = 24 MHz */ + +#define HSMCI_SDXFR_CLKDIV (0 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV + +/* FLASH wait states: + * + * DC Characteristics + * + * Parameter Min Typ Max + * ---------------------- ----- ----- ---- + * Vddcore DC Supply Core 1.08V 1.2V 1.32V + * Vvddio DC Supply I/Os 1.62V 3.3V 3.6V + * + * Wait Maximum + * Vddcore Vvddio States Frequency (MHz) + * ------- ---------- ------ --------------- + * 1.08V 1.62-3.6V 0 16 + * " " " "-" " 1 33 + * " " " "-" " 2 50 + * " " " "-" " 3 67 + * " " " "-" " 4 84 + * " " " "-" " 5 100 + * 1.08V 2.7-3.6V 0 20 + * " " " "-" " 1 40 + * " " " "-" " 2 60 + * " " " "-" " 3 80 + * " " " "-" " 4 100 + * 1.2V 1.62-3.6V 0 17 + * " " " "-" " 1 34 + * " " " "-" " 2 52 + * " " " "-" " 3 69 + * " " " "-" " 4 87 + * " " " "-" " 5 104 + * " " " "-" " 6 121 + * 1.2V 2.7-3.6V 0 21 + * " " " "-" " 1 42 + * " " " "-" " 2 63 + * " " " "-" " 3 84 + * " " " "-" " 4 105 + * " " " "-" " 5 123 << SELECTION + */ + +#define BOARD_FWS 5 + +/* LED definitions ******************************************************************/ +/* There are four LEDs on board the SAM4S Xplained board, two of these can be + * controlled by software in the SAM4S: + * + * LED GPIO + * ---------------- ----- + * D9 Yellow LED PC10 + * D10 Yellow LED PC17 + * + * Both can be illuminated by driving the GPIO output to ground (low). + */ + +/* LED index values for use with sam_setled() */ + +#define BOARD_D9 0 +#define BOARD_D10 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with sam_setleds() */ + +#define BOARD_D9_BIT (1 << BOARD_D9) +#define BOARD_D10_BIT (1 << BOARD_D10) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/up_leds.c. The LEDs are used to encode OS-related + * events as follows: + * + * SYMBOL Val Meaning LED state + * D9 D10 + * ----------------------- --- ----------------------- -------- -------- */ +#define LED_STARTED 0 /* NuttX has been started OFF OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */ +#define LED_STACKCREATED 0 /* Idle stack created ON OFF */ +#define LED_INIRQ 0 /* In an interrupt No change */ +#define LED_SIGNAL 0 /* In a signal handler No change */ +#define LED_ASSERTION 0 /* An assertion failed No change */ +#define LED_PANIC 0 /* The system has crashed OFF Blinking */ +#define LED_IDLE 0 /* MCU is is sleep mode Not used */ + +/* Thus if D9 is statically on, NuttX has successfully booted and is, + * apparently, running normmally. If D10 is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* Button definitions ***************************************************************/ +/* Mechanical buttons: + * + * The SAM4S Xplained has two mechanical buttons. One button is the RESET button + * connected to the SAM4S reset line and the other is a generic user configurable + * button labeled BP2. When a button is pressed it will drive the I/O line to GND. + * + * PA5 BP2 + */ + +#define BUTTON_BP2 0 +#define NUM_BUTTONS 1 + +#define BUTTON_BP2_BIT (1 << BUTTON_BP2) + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAM3U architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void sam_boardinitialize(void); + +/************************************************************************************ + * Name: sam_ledinit, sam_setled, and sam_setleds + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If + * CONFIG_ARCH_LEDS is not defined, then the following interfaces are available to + * control the LEDs from user applications. + * + ************************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +void sam_ledinit(void); +void sam_setled(int led, bool ledon); +void sam_setleds(uint8_t ledset); +#endif + +/************************************************************************************ + * Name: up_buttoninit + * + * Description: + * up_buttoninit() must be called to initialize button resources. After that, + * up_buttons() may be called to collect the current state of all buttons or + * up_irqbutton() may be called to register button interrupt handlers. + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_BUTTONS +void up_buttoninit(void); + +/************************************************************************************ + * Name: up_buttons + * + * Description: + * After up_buttoninit() has been called, up_buttons() may be called to collect + * the state of all buttons. up_buttons() returns an 8-bit bit set with each bit + * associated with a button. See the BUTTON* definitions above for the meaning of + * each bit in the returned value. + * + ************************************************************************************/ + +uint8_t up_buttons(void); + +/************************************************************************************ + * Name: up_irqbutton + * + * Description: + * This function may be called to register an interrupt handler that will be + * called when a button is depressed or released. The ID value is one of the + * BUTTON* definitions provided above. The previous interrupt handler address is + * returned (so that it may restored, if so desired). + * + ************************************************************************************/ + +#ifdef CONFIG_GPIOA_IRQ +xcpt_t up_irqbutton(int id, xcpt_t irqhandler); +#endif +#endif /* CONFIG_ARCH_BUTTONS */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_SAM4L_XPLAINED_INCLUDE_BOARD_H */ diff --git a/nuttx/configs/sam4s-xplained/nsh/Make.defs b/nuttx/configs/sam4s-xplained/nsh/Make.defs new file mode 100644 index 0000000000..5d7798abce --- /dev/null +++ b/nuttx/configs/sam4s-xplained/nsh/Make.defs @@ -0,0 +1,109 @@ +############################################################################ +# configs/sam4s-xplained/nsh/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" + MAXOPTIMIZATION = -O2 +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + diff --git a/nuttx/configs/sam4s-xplained/nsh/defconfig b/nuttx/configs/sam4s-xplained/nsh/defconfig new file mode 100644 index 0000000000..2a5f3f15a2 --- /dev/null +++ b/nuttx/configs/sam4s-xplained/nsh/defconfig @@ -0,0 +1,676 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +CONFIG_ARCH_CHIP_SAM34=y +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_CORTEXM4=y +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="sam34" +# CONFIG_ARMV7M_USEBASEPRI is not set +# CONFIG_ARCH_HAVE_FPU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set + +# +# ARMV7M Configuration Options +# +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +CONFIG_ARMV7M_OABI_TOOLCHAIN=y + +# +# AT91SAM3/4 Configuration Options +# +# CONFIG_ARCH_CHIP_AT91SAM3U4E is not set +# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4A is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32B is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16B is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16B is not set +CONFIG_ARCH_CHIP_ATSAM4S16C=y +# CONFIG_ARCH_CHIP_ATSAM4S16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S8C is not set +# CONFIG_ARCH_CHIP_ATSAM4S8B is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_SAM4L is not set +CONFIG_ARCH_CHIP_SAM4S=y + +# +# AT91SAM3/4 Peripheral Support +# +# CONFIG_SAM34_SPI is not set +# CONFIG_SAM34_SSC is not set +# CONFIG_SAM34_TC0 is not set +# CONFIG_SAM34_TC1 is not set +# CONFIG_SAM34_TC2 is not set +# CONFIG_SAM34_TC3 is not set +# CONFIG_SAM34_TC4 is not set +# CONFIG_SAM34_TC5 is not set +# CONFIG_SAM34_PWM is not set +# CONFIG_SAM34_TWIM0 is not set +# CONFIG_SAM34_TWIS0 is not set +# CONFIG_SAM34_TWIM1 is not set +# CONFIG_SAM34_TWIS1 is not set +# CONFIG_SAM34_UART0 is not set +CONFIG_SAM34_UART1=y +# CONFIG_SAM34_USART0 is not set +# CONFIG_SAM34_USART1 is not set +# CONFIG_SAM34_ADC12B is not set +# CONFIG_SAM34_DACC is not set +# CONFIG_SAM34_ACC is not set +# CONFIG_SAM34_SMC is not set +# CONFIG_SAM34_PDCA is not set +# CONFIG_SAM34_CRCCU is not set +# CONFIG_SAM34_UDP is not set +# CONFIG_SAM34_RTC is not set +# CONFIG_SAM34_RTT is not set +# CONFIG_SAM34_WDT is not set +# CONFIG_SAM34_HSMCI is not set + +# +# AT91SAM3/4 USART Configuration +# + +# +# AT91SAM3/4 GPIO Interrupt Configuration +# +# CONFIG_GPIOA_IRQ is not set +# CONFIG_GPIOB_IRQ is not set +# CONFIG_GPIOC_IRQ is not set + +# +# External Memory Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=9186 +# CONFIG_ARCH_CALIBRATION is not set +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=131072 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_SAM4S_XPLAINED=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="sam4s-xplained" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# + +# +# RTOS Features +# +# CONFIG_BOARD_INITIALIZE is not set +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=6 +CONFIG_START_DAY=12 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +CONFIG_DISABLE_ENVIRON=y + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART1=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +CONFIG_DISABLE_MOUNTPOINT=y +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_BINFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG_ENABLE is not set +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_MULTIHEAP is not set +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=3 +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Library Support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_CXX_NEWLONG=y + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_CONSOLE=y + +# +# USB Trace Support +# +# CONFIG_NSH_CONDEV is not set +# CONFIG_NSH_ARCHINIT is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# FLASH Erase-all Command +# + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set + +# +# USB Monitor +# diff --git a/nuttx/configs/sam4s-xplained/nsh/setenv.sh b/nuttx/configs/sam4s-xplained/nsh/setenv.sh new file mode 100755 index 0000000000..cf9df57ed4 --- /dev/null +++ b/nuttx/configs/sam4s-xplained/nsh/setenv.sh @@ -0,0 +1,63 @@ +#!/bin/bash +# configs/sam4s-xplained/nsh/setenv.sh +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/sam4s-xplained/ostest/Make.defs b/nuttx/configs/sam4s-xplained/ostest/Make.defs new file mode 100644 index 0000000000..742260e29a --- /dev/null +++ b/nuttx/configs/sam4s-xplained/ostest/Make.defs @@ -0,0 +1,109 @@ +############################################################################ +# configs/sam4s-xplained/ostest/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" + MAXOPTIMIZATION = -O2 +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + diff --git a/nuttx/configs/sam4s-xplained/ostest/defconfig b/nuttx/configs/sam4s-xplained/ostest/defconfig new file mode 100644 index 0000000000..c6f77f38fd --- /dev/null +++ b/nuttx/configs/sam4s-xplained/ostest/defconfig @@ -0,0 +1,604 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +CONFIG_ARCH_CHIP_SAM34=y +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_CORTEXM4=y +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="sam34" +# CONFIG_ARMV7M_USEBASEPRI is not set +# CONFIG_ARCH_HAVE_FPU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set + +# +# ARMV7M Configuration Options +# +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +CONFIG_ARMV7M_OABI_TOOLCHAIN=y + +# +# AT91SAM3/4 Configuration Options +# +# CONFIG_ARCH_CHIP_AT91SAM3U4E is not set +# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4A is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32B is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16B is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16B is not set +CONFIG_ARCH_CHIP_ATSAM4S16C=y +# CONFIG_ARCH_CHIP_ATSAM4S16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S8C is not set +# CONFIG_ARCH_CHIP_ATSAM4S8B is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_SAM4L is not set +CONFIG_ARCH_CHIP_SAM4S=y + +# +# AT91SAM3/4 Peripheral Support +# +# CONFIG_SAM34_SSC is not set +# CONFIG_SAM34_TC0 is not set +# CONFIG_SAM34_TC1 is not set +# CONFIG_SAM34_TC2 is not set +# CONFIG_SAM34_TC3 is not set +# CONFIG_SAM34_TC4 is not set +# CONFIG_SAM34_TC5 is not set +# CONFIG_SAM34_PWM is not set +# CONFIG_SAM34_TWIM0 is not set +# CONFIG_SAM34_TWIS0 is not set +# CONFIG_SAM34_TWIM1 is not set +# CONFIG_SAM34_TWIS1 is not set +# CONFIG_SAM34_UART0 is not set +CONFIG_SAM34_UART1=y +# CONFIG_SAM34_USART0 is not set +# CONFIG_SAM34_USART1 is not set +# CONFIG_SAM34_ADC12B is not set +# CONFIG_SAM34_DACC is not set +# CONFIG_SAM34_ACC is not set +# CONFIG_SAM34_SMC is not set +# CONFIG_SAM34_PDCA is not set +# CONFIG_SAM34_CRCCU is not set +# CONFIG_SAM34_UDP is not set +# CONFIG_SAM34_RTC is not set +# CONFIG_SAM34_RTT is not set +# CONFIG_SAM34_WDT is not set +# CONFIG_SAM34_HSMCI is not set + +# +# AT91SAM3/4 USART Configuration +# + +# +# AT91SAM3/4 GPIO Interrupt Configuration +# +# CONFIG_GPIOA_IRQ is not set +# CONFIG_GPIOB_IRQ is not set +# CONFIG_GPIOC_IRQ is not set + +# +# External Memory Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=9186 +# CONFIG_ARCH_CALIBRATION is not set +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=131072 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_SAM4S_XPLAINED=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="sam4s-xplained" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set + +# +# Board-Specific Options +# + +# +# RTOS Features +# +# CONFIG_BOARD_INITIALIZE is not set +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=6 +CONFIG_START_DAY=3 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="ostest_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +CONFIG_DISABLE_ENVIRON=y + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_SERIAL=y +CONFIG_DEV_LOWCONSOLE=y +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART1=y +CONFIG_MCU_SERIAL=y +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +CONFIG_DISABLE_MOUNTPOINT=y +# CONFIG_FS_RAMMAP is not set + +# +# System Logging +# +# CONFIG_SYSLOG_ENABLE is not set +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_MULTIHEAP is not set +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=3 +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Library Support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +CONFIG_EXAMPLES_OSTEST=y +CONFIG_EXAMPLES_OSTEST_LOOPS=1 +CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 +CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 +CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# FLASH Erase-all Command +# + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set + +# +# USB Monitor +# diff --git a/nuttx/configs/sam4s-xplained/ostest/setenv.sh b/nuttx/configs/sam4s-xplained/ostest/setenv.sh new file mode 100755 index 0000000000..f6ddcb085b --- /dev/null +++ b/nuttx/configs/sam4s-xplained/ostest/setenv.sh @@ -0,0 +1,63 @@ +#!/bin/bash +# configs/sam4s-xplained/ostest/setenv.sh +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/sam4s-xplained/scripts/ld.script b/nuttx/configs/sam4s-xplained/scripts/ld.script new file mode 100755 index 0000000000..8e4c874df8 --- /dev/null +++ b/nuttx/configs/sam4s-xplained/scripts/ld.script @@ -0,0 +1,121 @@ +/**************************************************************************** + * configs/sam4s-xplained/scripts/ld.script + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The ATSAM4S16C has 1MB of FLASH beginning at address 0x0040:0000 and + * 128KB of SRAM beginning at address 0x2000:0000 + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00400000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } >flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } >flash + __exidx_end = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(4): { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/sam4s-xplained/src/Makefile b/nuttx/configs/sam4s-xplained/src/Makefile new file mode 100644 index 0000000000..80d8f4719a --- /dev/null +++ b/nuttx/configs/sam4s-xplained/src/Makefile @@ -0,0 +1,100 @@ +############################################################################ +# configs/sam4s-xplained/src/Makefile +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +CFLAGS += -I$(TOPDIR)/sched + +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = sam_boot.c + +ifeq ($(CONFIG_HAVE_CXX),y) +CSRCS += sam_cxxinitialize.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += sam_autoleds.c +else +CSRCS += sam_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += sam_buttons.c +endif + +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(WINTOOL),y) + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}" +else + CFLAGS += -I$(ARCH_SRCDIR)/chip + CFLAGS += -I$(ARCH_SRCDIR)/common + CFLAGS += -I$(ARCH_SRCDIR)/armv7-m +endif + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h b/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h new file mode 100644 index 0000000000..f9ea61858d --- /dev/null +++ b/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h @@ -0,0 +1,132 @@ +/************************************************************************************ + * configs/sam3uek_eval/src/sam4s-xplained.h + * + * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAM4S_XPLAINED_SRC_SAM4S_XPLAINED_H +#define __CONFIGS_SAM4S_XPLAINED_SRC_SAM4S_XPLAINED_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include + +#include +#include + +#include "chip/sam_pinmap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* There are four LEDs on board the SAM4S Xplained board, two of these can be + * controlled by software in the SAM4S: + * + * LED GPIO + * ---------------- ----- + * D9 Yellow LED PC10 + * D10 Yellow LED PC17 + * + * Both can be illuminated by driving the GPIO output to ground (low). + * + * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/up_leds.c. The LEDs are used to encode OS-related + * events as follows: + * + * SYMBOL Meaning LED state + * D9 D10 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE MCU is is sleep mode Not used + * + * Thus if D9 is statically on, NuttX has successfully booted and is, + * apparently, running normmally. If D10 is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + + +#define GPIO_D9 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \ + GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_D10 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \ + GPIO_PORT_PIOC | GPIO_PIN17) + +/* Mechanical buttons: + * + * The SAM4S Xplained has two mechanical buttons. One button is the RESET button + * connected to the SAM4S reset line and the other is a generic user configurable + * button labeled BP2. When a button is pressed it will drive the I/O line to GND. + * + * PA5 BP2 + */ + +#define GPIO_BP2 (GPIO_INPUT | GPIO_CFG_PULLUP | GPIO_CFG_DEGLITCH | \ + GPIO_PORT_PIOA | GPIO_PIN5) +#define IRQ_BP2 SAM_IRQ_PA5 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: up_ledinit + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void up_ledinit(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_SAM4S_XPLAINED_SRC_SAM4S_XPLAINED_H */ + diff --git a/nuttx/configs/sam4s-xplained/src/sam_autoleds.c b/nuttx/configs/sam4s-xplained/src/sam_autoleds.c new file mode 100644 index 0000000000..9b912e4ff2 --- /dev/null +++ b/nuttx/configs/sam4s-xplained/src/sam_autoleds.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * configs/sam4s-xplained/src/sam_autoleds.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "sam_gpio.h" +#include "sam4s-xplained.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Definitions + ****************************************************************************/ +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the two LEDs on + * board the SAM4S Xplained. The following definitions describe how NuttX + * controls the LEDs: + * + * SYMBOL Meaning LED state + * D9 D10 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE MCU is is sleep mode Not used + */ + +/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG + * with CONFIG_DEBUG_VERBOSE too) + */ + +#ifdef CONFIG_DEBUG_LEDS +# define leddbg lldbg +# define ledvdbg llvdbg +#else +# define leddbg(x...) +# define ledvdbg(x...) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_ledinit + ****************************************************************************/ + +void up_ledinit(void) +{ + /* Configure LED1-2 GPIOs for output */ + + sam_configgpio(GPIO_D9); + sam_configgpio(GPIO_D10); +} + +/**************************************************************************** + * Name: up_ledon + ****************************************************************************/ + +void up_ledon(int led) +{ + bool led1on = false; + bool led2on = false; + + switch (led) + { + case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ + break; + + case 1: /* LED_STACKCREATED */ + led1on = true; + break; + + default: + case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ + return; + + case 3: /* LED_PANIC */ + led2on = true; + break; + } + + sam_gpiowrite(GPIO_D9, led1on); + sam_gpiowrite(GPIO_D10, led2on); +} + +/**************************************************************************** + * Name: up_ledoff + ****************************************************************************/ + +void up_ledoff(int led) +{ + if (led != 2) + { + sam_gpiowrite(GPIO_D9, false); + sam_gpiowrite(GPIO_D10, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pio.h b/nuttx/configs/sam4s-xplained/src/sam_boot.c similarity index 75% rename from nuttx/arch/arm/src/sam34/chip/sam_pio.h rename to nuttx/configs/sam4s-xplained/src/sam_boot.c index e2596475d5..54d29053ee 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_pio.h +++ b/nuttx/configs/sam4s-xplained/src/sam_boot.c @@ -1,5 +1,5 @@ -/**************************************************************************************** - * arch/arm/src/sam34/chip/sam_pio.h +/************************************************************************************ + * configs/sam4s-xplained/src/sam_boot.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -31,41 +31,45 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************/ + ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H - -/**************************************************************************************** +/************************************************************************************ * Included Files - ****************************************************************************************/ + ************************************************************************************/ #include -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_SAM3U) -# include "chip/sam3u_vectors.h" -#elif defined(CONFIG_ARCH_CHIP_SAM4S) -# include "chip/sam4s_vectors.h" -#else -# error Unrecognized SAM architecture -#endif +#include -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ +#include "sam4s-xplained.h" -/**************************************************************************************** - * Public Types - ****************************************************************************************/ +/************************************************************************************ + * Definitions + ************************************************************************************/ -/**************************************************************************************** - * Public Data - ****************************************************************************************/ +/************************************************************************************ + * Private Functions + ************************************************************************************/ -/**************************************************************************************** +/************************************************************************************ * Public Functions - ****************************************************************************************/ + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAM3U architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H */ +void sam_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinit(); +#endif +} diff --git a/nuttx/configs/sam4s-xplained/src/sam_buttons.c b/nuttx/configs/sam4s-xplained/src/sam_buttons.c new file mode 100644 index 0000000000..fe5c0b7768 --- /dev/null +++ b/nuttx/configs/sam4s-xplained/src/sam_buttons.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * configs/sam4s-xplained/src/sam_buttons.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include +#include + +#include "sam_gpio.h" +#include "sam4s-xplained.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static xcpt_t g_irqbp2; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_buttoninit + * + * Description: + * up_buttoninit() must be called to initialize button resources. After + * that, up_buttons() may be called to collect the current state of all + * buttons or up_irqbutton() may be called to register button interrupt + * handlers. + * + ****************************************************************************/ + +void up_buttoninit(void) +{ + (void)sam_configgpio(GPIO_BP2); +} + +/************************************************************************************ + * Name: up_buttons + * + * Description: + * After up_buttoninit() has been called, up_buttons() may be called to collect + * the state of all buttons. up_buttons() returns an 8-bit bit set with each bit + * associated with a button. See the BUTTON* definitions above for the meaning of + * each bit in the returned value. + * + ************************************************************************************/ + +uint8_t up_buttons(void) +{ + return sam_gpioread(GPIO_BP2) ? 0 : BUTTON_BP2_BIT; +} + +/**************************************************************************** + * Name: up_irqbutton + * + * Description: + * This function may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is one + * of the BUTTON* definitions provided above. The previous interrupt + * handler address isreturned (so that it may restored, if so desired). + * + * Configuration Notes: + * Configuration CONFIG_AVR32_GPIOIRQ must be selected to enable the + * overall GPIO IRQ feature and CONFIG_AVR32_GPIOIRQSETA and/or + * CONFIG_AVR32_GPIOIRQSETB must be enabled to select GPIOs to support + * interrupts on. For button support, bits 2 and 3 must be set in + * CONFIG_AVR32_GPIOIRQSETB (PB2 and PB3). + * + ****************************************************************************/ + +#if defined(CONFIG_GPIOA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) +xcpt_t up_irqbutton(int id, xcpt_t irqhandler) +{ + xcpt_t oldhandler = NULL; + + if (id == BUTTON_BP2) + { + irqstate_t flags; + + /* Disable interrupts until we are done. This guarantees that the + * following operations are atomic. + */ + + flags = irqsave(); + + /* Get the old button interrupt handler and save the new one */ + + oldhandler = *g_irqbp2; + *g_irqbp2 = irqhandler; + + /* Configure the interrupt */ + + sam_gpioirq(IRQ_BP2); + (void)irq_attach(IRQ_BP2, irqhandler); + sam_gpioirqenable(IRQ_BP2); + } + + /* Return the old button handler (so that it can be restored) */ + + return oldhandler; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/nuttx/configs/sam4s-xplained/src/sam_cxxinitialize.c b/nuttx/configs/sam4s-xplained/src/sam_cxxinitialize.c new file mode 100644 index 0000000000..0fd845488d --- /dev/null +++ b/nuttx/configs/sam4s-xplained/src/sam_cxxinitialize.c @@ -0,0 +1,154 @@ +/************************************************************************************ + * configs/sam4s-xplained/src/sam_cxxinitialize.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include +#include "chip.h" + +#if defined(CONFIG_HAVE_CXX) && defined(CONFIG_HAVE_CXXINITIALIZE) + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Debug ****************************************************************************/ +/* Non-standard debug that may be enabled just for testing the static constructors */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_CXX +#endif + +#ifdef CONFIG_DEBUG_CXX +# define cxxdbg dbg +# define cxxlldbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define cxxvdbg vdbg +# define cxxllvdbg llvdbg +# else +# define cxxvdbg(x...) +# define cxxllvdbg(x...) +# endif +#else +# define cxxdbg(x...) +# define cxxlldbg(x...) +# define cxxvdbg(x...) +# define cxxllvdbg(x...) +#endif + +/************************************************************************************ + * Private Types + ************************************************************************************/ +/* This type defines one entry in initialization array */ + +typedef void (*initializer_t)(void); + +/************************************************************************************ + * External references + ************************************************************************************/ +/* _sinit and _einit are symbols exported by the linker script that mark the + * beginning and the end of the C++ initialization section. + */ + +extern initializer_t _sinit; +extern initializer_t _einit; + +/* _stext and _etext are symbols exported by the linker script that mark the + * beginning and the end of text. + */ + +extern uint32_t _stext; +extern uint32_t _etext; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: up_cxxinitialize + * + * Description: + * If C++ and C++ static constructors are supported, then this function + * must be provided by board-specific logic in order to perform + * initialization of the static C++ class instances. + * + * This function should then be called in the application-specific + * user_start logic in order to perform the C++ initialization. NOTE + * that no component of the core NuttX RTOS logic is involved; This + * function defintion only provides the 'contract' between application + * specific C++ code and platform-specific toolchain support + * + ***************************************************************************/ + +void up_cxxinitialize(void) +{ + initializer_t *initp; + + cxxdbg("_sinit: %p _einit: %p _stext: %p _etext: %p\n", + &_sinit, &_einit, &_stext, &_etext); + + /* Visit each entry in the initialzation table */ + + for (initp = &_sinit; initp != &_einit; initp++) + { + initializer_t initializer = *initp; + cxxdbg("initp: %p initializer: %p\n", initp, initializer); + + /* Make sure that the address is non-NULL and lies in the text region + * defined by the linker script. Some toolchains may put NULL values + * or counts in the initialization table + */ + + if ((void*)initializer > (void*)&_stext && (void*)initializer < (void*)&_etext) + { + cxxdbg("Calling %p\n", initializer); + initializer(); + } + } +} + +#endif /* CONFIG_HAVE_CXX && CONFIG_HAVE_CXXINITIALIZE */ + diff --git a/nuttx/configs/sam4s-xplained/src/sam_userleds.c b/nuttx/configs/sam4s-xplained/src/sam_userleds.c new file mode 100644 index 0000000000..21b0e2486c --- /dev/null +++ b/nuttx/configs/sam4s-xplained/src/sam_userleds.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * configs/sam4s-xplained/src/sam_userleds.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "sam_gpio.h" +#include "sam4s-xplained.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG + * with CONFIG_DEBUG_VERBOSE too) + */ + +#ifdef CONFIG_DEBUG_LEDS +# define leddbg lldbg +# define ledvdbg llvdbg +#else +# define leddbg(x...) +# define ledvdbg(x...) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_ledinit + ****************************************************************************/ + +void sam_ledinit(void) +{ + /* Configure LED1-2 GPIOs for output */ + + sam_configgpio(GPIO_D9); + sam_configgpio(GPIO_D10); +} + +/**************************************************************************** + * Name: sam_setled + ****************************************************************************/ + +void sam_setled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED1) + { + ledcfg = GPIO_D9; + } + else if (led == BOARD_LED2) + { + ledcfg = GPIO_D10; + } + else + { + return; + } + + sam_gpiowrite(ledcfg, ledon); +} + +/**************************************************************************** + * Name: sam_setleds + ****************************************************************************/ + +void sam_setleds(uint8_t ledset) +{ + bool ledon; + + ledon = ((ledset & BOARD_LED1_BIT) != 0); + sam_gpiowrite(GPIO_D9, ledon); + + ledon = ((ledset & BOARD_LED2_BIT) != 0); + sam_gpiowrite(GPIO_D10, ledon); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/nuttx/configs/shenzhou/src/up_usbmsc.c b/nuttx/configs/shenzhou/src/up_usbmsc.c index d957b76da7..e2ca462d19 100644 --- a/nuttx/configs/shenzhou/src/up_usbmsc.c +++ b/nuttx/configs/shenzhou/src/up_usbmsc.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/shenzhou/src/up_usbmsc.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Configure and register the STM32 SPI-based MMC/SD block driver. @@ -95,7 +95,7 @@ int usbmsc_archinitialize(void) * this case, there is nothing further to be done here. */ -#ifndef CONFIG_EXAMPLES_USBMSC_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS return stm32_sdinitialize(CONFIG_EXAMPLES_USBMSC_DEVMINOR1); #else return OK; diff --git a/nuttx/configs/sim/nsh2/defconfig b/nuttx/configs/sim/nsh2/defconfig index 50c7adc5af..1a2cde4031 100644 --- a/nuttx/configs/sim/nsh2/defconfig +++ b/nuttx/configs/sim/nsh2/defconfig @@ -304,7 +304,6 @@ CONFIG_NSH_FATMOUNTPT="/tmp" # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 #CONFIG_EXAMPLES_NX_BGCOLOR #CONFIG_EXAMPLES_NX_COLOR1 @@ -321,7 +320,6 @@ CONFIG_EXAMPLES_NX_NOTIFYSIGNO=4 # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 #CONFIG_EXAMPLES_NXHELLO_BGCOLOR CONFIG_EXAMPLES_NXHELLO_FONTID=6 @@ -345,7 +343,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/touchscreen # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 diff --git a/nuttx/configs/sim/ostest/defconfig b/nuttx/configs/sim/ostest/defconfig index bcfadabd72..ce052c2e77 100644 --- a/nuttx/configs/sim/ostest/defconfig +++ b/nuttx/configs/sim/ostest/defconfig @@ -364,7 +364,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=100 CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8 diff --git a/nuttx/configs/sim/touchscreen/defconfig b/nuttx/configs/sim/touchscreen/defconfig index bfa9bcbad0..35059c06ea 100644 --- a/nuttx/configs/sim/touchscreen/defconfig +++ b/nuttx/configs/sim/touchscreen/defconfig @@ -296,7 +296,6 @@ CONFIG_EXAMPLES_MOUNT_DEVNAME="/dev/ram0" # # Settings for examples/touchscreen # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=n CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 diff --git a/nuttx/configs/stm3210e-eval/README.txt b/nuttx/configs/stm3210e-eval/README.txt index 789a599d16..b6c2cfc583 100644 --- a/nuttx/configs/stm3210e-eval/README.txt +++ b/nuttx/configs/stm3210e-eval/README.txt @@ -754,7 +754,7 @@ Where is one of the following: long file names in the FAT file system. Please refer to the details in the top-level COPYING file. Please do not use FAT long file name unless you are familiar with these patent issues. - (5) When built as an NSH add-on command (CONFIG_EXAMPLES_USBMSC_BUILTIN=y), + (5) When built as an NSH add-on command (CONFIG_NSH_BUILTIN_APPS=y), Caution should be used to assure that the SD drive is not in use when the USB storage device is configured. Specifically, the SD driver should be unmounted like: diff --git a/nuttx/configs/stm3210e-eval/composite/defconfig b/nuttx/configs/stm3210e-eval/composite/defconfig index 6ead077f4b..4d48576b79 100755 --- a/nuttx/configs/stm3210e-eval/composite/defconfig +++ b/nuttx/configs/stm3210e-eval/composite/defconfig @@ -522,7 +522,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=n CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm3210e-eval/nsh2/defconfig b/nuttx/configs/stm3210e-eval/nsh2/defconfig index d5e19733f9..7bda1d45bb 100644 --- a/nuttx/configs/stm3210e-eval/nsh2/defconfig +++ b/nuttx/configs/stm3210e-eval/nsh2/defconfig @@ -610,7 +610,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=2 #CONFIG_I2CTOOL_MINADDR @@ -638,7 +637,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -658,7 +656,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 CONFIG_EXAMPLES_NXHELLO_DEVNO=0 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 @@ -670,7 +667,6 @@ CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 @@ -699,7 +695,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm3210e-eval/nx/defconfig b/nuttx/configs/stm3210e-eval/nx/defconfig index f4a3cb4e3b..90dd053d0a 100644 --- a/nuttx/configs/stm3210e-eval/nx/defconfig +++ b/nuttx/configs/stm3210e-eval/nx/defconfig @@ -545,7 +545,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=n CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -565,7 +564,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=n CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 diff --git a/nuttx/configs/stm3210e-eval/nxconsole/defconfig b/nuttx/configs/stm3210e-eval/nxconsole/defconfig index ccfea526ef..b5edf7c57e 100644 --- a/nuttx/configs/stm3210e-eval/nxconsole/defconfig +++ b/nuttx/configs/stm3210e-eval/nxconsole/defconfig @@ -548,7 +548,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=n CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -568,7 +567,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxtext # -CONFIG_EXAMPLES_NXTEXT_BUILTIN=n CONFIG_EXAMPLES_NXTEXT_VPLANE=0 CONFIG_EXAMPLES_NXTEXT_DEVNO=0 CONFIG_EXAMPLES_NXTEXT_BGCOLOR=0x0011 @@ -590,7 +588,6 @@ CONFIG_EXAMPLES_NXTEXT_NOTIFYSIGNO=4 # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=n CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 diff --git a/nuttx/configs/stm3210e-eval/nxlines/defconfig b/nuttx/configs/stm3210e-eval/nxlines/defconfig index 580b28019a..a9dc3d7aa3 100644 --- a/nuttx/configs/stm3210e-eval/nxlines/defconfig +++ b/nuttx/configs/stm3210e-eval/nxlines/defconfig @@ -544,7 +544,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=n CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -564,7 +563,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxtext # -CONFIG_EXAMPLES_NXTEXT_BUILTIN=n CONFIG_EXAMPLES_NXTEXT_VPLANE=0 CONFIG_EXAMPLES_NXTEXT_DEVNO=0 CONFIG_EXAMPLES_NXTEXT_BGCOLOR=0x0011 @@ -586,7 +584,6 @@ CONFIG_EXAMPLES_NXTEXT_NOTIFYSIGNO=4 # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=n CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 diff --git a/nuttx/configs/stm3210e-eval/nxtext/defconfig b/nuttx/configs/stm3210e-eval/nxtext/defconfig index 46a25103e9..453b0282b0 100644 --- a/nuttx/configs/stm3210e-eval/nxtext/defconfig +++ b/nuttx/configs/stm3210e-eval/nxtext/defconfig @@ -544,7 +544,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=n CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -564,7 +563,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxtext # -CONFIG_EXAMPLES_NXTEXT_BUILTIN=n CONFIG_EXAMPLES_NXTEXT_VPLANE=0 CONFIG_EXAMPLES_NXTEXT_DEVNO=0 CONFIG_EXAMPLES_NXTEXT_BGCOLOR=0x0011 @@ -586,7 +584,6 @@ CONFIG_EXAMPLES_NXTEXT_NOTIFYSIGNO=4 # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=n CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 diff --git a/nuttx/configs/stm3210e-eval/pm/defconfig b/nuttx/configs/stm3210e-eval/pm/defconfig index be0b25194c..512cf826c5 100644 --- a/nuttx/configs/stm3210e-eval/pm/defconfig +++ b/nuttx/configs/stm3210e-eval/pm/defconfig @@ -655,7 +655,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=2 #CONFIG_I2CTOOL_MINADDR @@ -683,7 +682,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -703,7 +701,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 CONFIG_EXAMPLES_NXHELLO_DEVNO=0 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 @@ -715,7 +712,6 @@ CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 @@ -744,7 +740,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=n CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm3210e-eval/src/up_usbmsc.c b/nuttx/configs/stm3210e-eval/src/up_usbmsc.c index 185f50bb04..5bca7bf1b9 100644 --- a/nuttx/configs/stm3210e-eval/src/up_usbmsc.c +++ b/nuttx/configs/stm3210e-eval/src/up_usbmsc.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/stm3210e-eval/src/up_usbmsc.c * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Configure and register the STM32 MMC/SD SDIO block driver. @@ -114,7 +114,7 @@ int usbmsc_archinitialize(void) * this case, there is nothing further to be done here. */ -#ifndef CONFIG_EXAMPLES_USBMSC_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS FAR struct sdio_dev_s *sdio; int ret; @@ -156,7 +156,7 @@ int usbmsc_archinitialize(void) sdio_mediachange(sdio, true); -#endif /* CONFIG_EXAMPLES_USBMSC_BUILTIN */ +#endif /* CONFIG_NSH_BUILTIN_APPS */ return OK; } diff --git a/nuttx/configs/stm3210e-eval/usbstorage/defconfig b/nuttx/configs/stm3210e-eval/usbstorage/defconfig index 0d3034495b..4051790b32 100755 --- a/nuttx/configs/stm3210e-eval/usbstorage/defconfig +++ b/nuttx/configs/stm3210e-eval/usbstorage/defconfig @@ -479,7 +479,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=n CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm3220g-eval/dhcpd/defconfig b/nuttx/configs/stm3220g-eval/dhcpd/defconfig index fecf193d6b..0e1473d8ef 100644 --- a/nuttx/configs/stm3220g-eval/dhcpd/defconfig +++ b/nuttx/configs/stm3220g-eval/dhcpd/defconfig @@ -600,7 +600,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR diff --git a/nuttx/configs/stm3220g-eval/nettest/defconfig b/nuttx/configs/stm3220g-eval/nettest/defconfig index 7df818c889..d5f85cc607 100644 --- a/nuttx/configs/stm3220g-eval/nettest/defconfig +++ b/nuttx/configs/stm3220g-eval/nettest/defconfig @@ -593,7 +593,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR diff --git a/nuttx/configs/stm3220g-eval/nsh/defconfig b/nuttx/configs/stm3220g-eval/nsh/defconfig index fab3bfd16f..a9aab627c4 100644 --- a/nuttx/configs/stm3220g-eval/nsh/defconfig +++ b/nuttx/configs/stm3220g-eval/nsh/defconfig @@ -709,7 +709,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR @@ -742,7 +741,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -762,7 +760,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 CONFIG_EXAMPLES_NXHELLO_DEVNO=0 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 @@ -774,7 +771,6 @@ CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 @@ -803,7 +799,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/touchscreen # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 @@ -811,7 +806,6 @@ CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm3220g-eval/nsh2/defconfig b/nuttx/configs/stm3220g-eval/nsh2/defconfig index d14e7664ea..670c0840cf 100644 --- a/nuttx/configs/stm3220g-eval/nsh2/defconfig +++ b/nuttx/configs/stm3220g-eval/nsh2/defconfig @@ -696,7 +696,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR @@ -729,7 +728,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -749,7 +747,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 CONFIG_EXAMPLES_NXHELLO_DEVNO=0 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 @@ -761,7 +758,6 @@ CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 @@ -790,7 +786,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/touchscreen # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 @@ -798,7 +793,6 @@ CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm3220g-eval/ostest/defconfig b/nuttx/configs/stm3220g-eval/ostest/defconfig index dc23e0ab55..7bdf36849b 100644 --- a/nuttx/configs/stm3220g-eval/ostest/defconfig +++ b/nuttx/configs/stm3220g-eval/ostest/defconfig @@ -599,7 +599,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -619,7 +618,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 CONFIG_EXAMPLES_NXHELLO_DEVNO=0 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 @@ -631,7 +629,6 @@ CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 @@ -660,7 +657,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/touchscreen # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 @@ -679,7 +675,6 @@ CONFIG_EXAMPLES_BUTTONS_NAME2="Up/Down" # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR @@ -704,7 +699,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm3220g-eval/telnetd/defconfig b/nuttx/configs/stm3220g-eval/telnetd/defconfig index 5a0d96c6b4..18da96da3b 100644 --- a/nuttx/configs/stm3220g-eval/telnetd/defconfig +++ b/nuttx/configs/stm3220g-eval/telnetd/defconfig @@ -605,7 +605,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR diff --git a/nuttx/configs/stm3240g-eval/dhcpd/defconfig b/nuttx/configs/stm3240g-eval/dhcpd/defconfig index a49e94ea30..3075e373b9 100644 --- a/nuttx/configs/stm3240g-eval/dhcpd/defconfig +++ b/nuttx/configs/stm3240g-eval/dhcpd/defconfig @@ -613,7 +613,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR diff --git a/nuttx/configs/stm3240g-eval/nettest/defconfig b/nuttx/configs/stm3240g-eval/nettest/defconfig index 0fdb75229e..9891d3770a 100644 --- a/nuttx/configs/stm3240g-eval/nettest/defconfig +++ b/nuttx/configs/stm3240g-eval/nettest/defconfig @@ -606,7 +606,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR diff --git a/nuttx/configs/stm3240g-eval/nsh/defconfig b/nuttx/configs/stm3240g-eval/nsh/defconfig index 47f1a4b4cb..a53a736c52 100644 --- a/nuttx/configs/stm3240g-eval/nsh/defconfig +++ b/nuttx/configs/stm3240g-eval/nsh/defconfig @@ -709,7 +709,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR @@ -742,7 +741,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -762,7 +760,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 CONFIG_EXAMPLES_NXHELLO_DEVNO=0 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 @@ -774,7 +771,6 @@ CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 @@ -803,7 +799,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/touchscreen # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 @@ -811,7 +806,6 @@ CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm3240g-eval/nsh2/defconfig b/nuttx/configs/stm3240g-eval/nsh2/defconfig index d62098eba6..2b32ee16b4 100644 --- a/nuttx/configs/stm3240g-eval/nsh2/defconfig +++ b/nuttx/configs/stm3240g-eval/nsh2/defconfig @@ -656,7 +656,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR diff --git a/nuttx/configs/stm3240g-eval/nxconsole/defconfig b/nuttx/configs/stm3240g-eval/nxconsole/defconfig index bc9161d30b..f3e0854266 100644 --- a/nuttx/configs/stm3240g-eval/nxconsole/defconfig +++ b/nuttx/configs/stm3240g-eval/nxconsole/defconfig @@ -680,7 +680,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR @@ -713,7 +712,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -733,7 +731,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 CONFIG_EXAMPLES_NXHELLO_DEVNO=0 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 @@ -745,7 +742,6 @@ CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 @@ -774,7 +770,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm3240g-eval/nxwm/defconfig b/nuttx/configs/stm3240g-eval/nxwm/defconfig index a7ac5e38c3..80e9f867b3 100644 --- a/nuttx/configs/stm3240g-eval/nxwm/defconfig +++ b/nuttx/configs/stm3240g-eval/nxwm/defconfig @@ -741,7 +741,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR @@ -774,7 +773,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -794,7 +792,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 CONFIG_EXAMPLES_NXHELLO_DEVNO=0 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 @@ -806,7 +803,6 @@ CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 @@ -835,7 +831,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/touchscreen # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=n CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 @@ -843,7 +838,6 @@ CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm3240g-eval/ostest/defconfig b/nuttx/configs/stm3240g-eval/ostest/defconfig index 4052adafc1..89b1b755c9 100644 --- a/nuttx/configs/stm3240g-eval/ostest/defconfig +++ b/nuttx/configs/stm3240g-eval/ostest/defconfig @@ -533,7 +533,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/stm3240g-eval/telnetd/defconfig b/nuttx/configs/stm3240g-eval/telnetd/defconfig index efc548d0b3..6a91ff13e5 100644 --- a/nuttx/configs/stm3240g-eval/telnetd/defconfig +++ b/nuttx/configs/stm3240g-eval/telnetd/defconfig @@ -618,7 +618,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR diff --git a/nuttx/configs/stm3240g-eval/webserver/defconfig b/nuttx/configs/stm3240g-eval/webserver/defconfig index 85274ad4fc..c87234fd73 100644 --- a/nuttx/configs/stm3240g-eval/webserver/defconfig +++ b/nuttx/configs/stm3240g-eval/webserver/defconfig @@ -709,7 +709,6 @@ CONFIG_NSH_MMCSDMINOR=0 # # I2C tool settings # -CONFIG_I2CTOOL_BUILTIN=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=3 #CONFIG_I2CTOOL_MINADDR @@ -742,7 +741,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # # Settings for examples/nx # -CONFIG_EXAMPLES_NX_BUILTIN=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 @@ -762,7 +760,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=n # # Settings for examples/nxhello # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 CONFIG_EXAMPLES_NXHELLO_DEVNO=0 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 @@ -774,7 +771,6 @@ CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n # # Settings for examples/nximage # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 CONFIG_EXAMPLES_NXIMAGE_BPP=16 @@ -803,7 +799,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n # # Settings for examples/touchscreen # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 @@ -811,7 +806,6 @@ CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 # # Settings for examples/usbstorage # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y CONFIG_EXAMPLES_USBMSC_NLUNS=1 CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" diff --git a/nuttx/configs/stm32f100rc_generic/ostest/defconfig b/nuttx/configs/stm32f100rc_generic/ostest/defconfig index 907a9b800c..16f56e3335 100644 --- a/nuttx/configs/stm32f100rc_generic/ostest/defconfig +++ b/nuttx/configs/stm32f100rc_generic/ostest/defconfig @@ -444,7 +444,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/stm32f3discovery/ostest/defconfig b/nuttx/configs/stm32f3discovery/ostest/defconfig index 3db0015460..997f9681c0 100644 --- a/nuttx/configs/stm32f3discovery/ostest/defconfig +++ b/nuttx/configs/stm32f3discovery/ostest/defconfig @@ -504,7 +504,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/stm32f4discovery/kostest/defconfig b/nuttx/configs/stm32f4discovery/kostest/defconfig index 316ba3f806..96a2490a41 100644 --- a/nuttx/configs/stm32f4discovery/kostest/defconfig +++ b/nuttx/configs/stm32f4discovery/kostest/defconfig @@ -543,7 +543,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/stm32f4discovery/ostest/defconfig b/nuttx/configs/stm32f4discovery/ostest/defconfig index ae2af1656b..46e8161e48 100644 --- a/nuttx/configs/stm32f4discovery/ostest/defconfig +++ b/nuttx/configs/stm32f4discovery/ostest/defconfig @@ -533,7 +533,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/stm32f4discovery/winbuild/defconfig b/nuttx/configs/stm32f4discovery/winbuild/defconfig index 30f6a225cc..07940af88e 100644 --- a/nuttx/configs/stm32f4discovery/winbuild/defconfig +++ b/nuttx/configs/stm32f4discovery/winbuild/defconfig @@ -464,7 +464,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/stm32ldiscovery/src/stm32_autoleds.c b/nuttx/configs/stm32ldiscovery/src/stm32_autoleds.c index b03a612660..6fcdbcc21b 100644 --- a/nuttx/configs/stm32ldiscovery/src/stm32_autoleds.c +++ b/nuttx/configs/stm32ldiscovery/src/stm32_autoleds.c @@ -1,6 +1,5 @@ /**************************************************************************** - * configs/stm32ldiscovery/src/up_autoleds.c - * arch/arm/src/board/up_autoleds.c + * configs/stm32ldiscovery/src/stm32_autoleds.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -55,7 +54,7 @@ /**************************************************************************** * Definitions ****************************************************************************/ -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on * board the STM32L-Discovery. The following definitions describe how NuttX * controls the LEDs: * diff --git a/nuttx/configs/stm32ldiscovery/src/stm32_userleds.c b/nuttx/configs/stm32ldiscovery/src/stm32_userleds.c index e556f4f236..1e3094c6d8 100644 --- a/nuttx/configs/stm32ldiscovery/src/stm32_userleds.c +++ b/nuttx/configs/stm32ldiscovery/src/stm32_userleds.c @@ -1,6 +1,5 @@ /**************************************************************************** - * configs/stm32ldiscovery/src/up_leds.c - * arch/arm/src/board/up_leds.c + * configs/stm32ldiscovery/src/stm32_userleds.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/nuttx/configs/sure-pic32mx/ostest/defconfig b/nuttx/configs/sure-pic32mx/ostest/defconfig index e01c9f3807..b053374fce 100644 --- a/nuttx/configs/sure-pic32mx/ostest/defconfig +++ b/nuttx/configs/sure-pic32mx/ostest/defconfig @@ -539,7 +539,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/sure-pic32mx/src/pic32mx_usbterm.c b/nuttx/configs/sure-pic32mx/src/pic32mx_usbterm.c index 6905951b82..16fa4f1eea 100644 --- a/nuttx/configs/sure-pic32mx/src/pic32mx_usbterm.c +++ b/nuttx/configs/sure-pic32mx/src/pic32mx_usbterm.c @@ -82,7 +82,7 @@ int usbterm_devinit(void) * pic32mx_usbattach() will be called in nsh_archinitialize(). */ -#ifndef CONFIG_EXAMPLES_USBTERM_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS pic32mx_usbattach(); #endif return OK; diff --git a/nuttx/configs/twr-k60n512/ostest/defconfig b/nuttx/configs/twr-k60n512/ostest/defconfig index db6b2cc6f3..f7dbf53153 100644 --- a/nuttx/configs/twr-k60n512/ostest/defconfig +++ b/nuttx/configs/twr-k60n512/ostest/defconfig @@ -464,7 +464,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/twr-k60n512/src/up_usbmsc.c b/nuttx/configs/twr-k60n512/src/up_usbmsc.c index c893551cad..41a21beaac 100644 --- a/nuttx/configs/twr-k60n512/src/up_usbmsc.c +++ b/nuttx/configs/twr-k60n512/src/up_usbmsc.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/twr-k60n512/src/up_usbmsc.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Configure and register the Kinetis MMC/SD block driver. @@ -110,9 +110,9 @@ int usbmsc_archinitialize(void) * this case, there is nothing further to be done here. */ -#ifndef CONFIG_EXAMPLES_USBMSC_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS # warning "Missing logic" -#endif /* CONFIG_EXAMPLES_USBMSC_BUILTIN */ +#endif /* CONFIG_NSH_BUILTIN_APPS */ return OK; } diff --git a/nuttx/configs/ubw32/ostest/defconfig b/nuttx/configs/ubw32/ostest/defconfig index e183b75265..42ec764d6b 100644 --- a/nuttx/configs/ubw32/ostest/defconfig +++ b/nuttx/configs/ubw32/ostest/defconfig @@ -522,7 +522,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 diff --git a/nuttx/configs/ubw32/src/up_usbterm.c b/nuttx/configs/ubw32/src/up_usbterm.c index 401d17026a..9fe84b548b 100644 --- a/nuttx/configs/ubw32/src/up_usbterm.c +++ b/nuttx/configs/ubw32/src/up_usbterm.c @@ -2,7 +2,7 @@ * configs/ubw32/src/up_usbterm.c * arch/arm/src/board/up_usbterm.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -80,7 +80,7 @@ int usbterm_devinit(void) * pic32mx_usbattach() will be called in nsh_archinitialize(). */ -#ifndef CONFIG_EXAMPLES_USBTERM_BUILTIN +#ifndef CONFIG_NSH_BUILTIN_APPS pic32mx_usbattach(); #endif return OK; diff --git a/nuttx/configs/xtrs/ostest/defconfig b/nuttx/configs/xtrs/ostest/defconfig index 74a0199dfe..162036143c 100644 --- a/nuttx/configs/xtrs/ostest/defconfig +++ b/nuttx/configs/xtrs/ostest/defconfig @@ -337,7 +337,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=1024 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=4 diff --git a/nuttx/configs/z16f2800100zcog/ostest/defconfig b/nuttx/configs/z16f2800100zcog/ostest/defconfig index d94a521245..3e420b75fe 100644 --- a/nuttx/configs/z16f2800100zcog/ostest/defconfig +++ b/nuttx/configs/z16f2800100zcog/ostest/defconfig @@ -376,7 +376,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8 diff --git a/nuttx/configs/z80sim/ostest/defconfig b/nuttx/configs/z80sim/ostest/defconfig index bd4144821a..3c317cfa0d 100644 --- a/nuttx/configs/z80sim/ostest/defconfig +++ b/nuttx/configs/z80sim/ostest/defconfig @@ -337,7 +337,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=1024 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=4 diff --git a/nuttx/configs/z8encore000zco/ostest/defconfig b/nuttx/configs/z8encore000zco/ostest/defconfig index 605bec669b..89b278e0cf 100644 --- a/nuttx/configs/z8encore000zco/ostest/defconfig +++ b/nuttx/configs/z8encore000zco/ostest/defconfig @@ -363,7 +363,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=256 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8 diff --git a/nuttx/configs/z8f64200100kit/ostest/defconfig b/nuttx/configs/z8f64200100kit/ostest/defconfig index aabfc6ee4e..35be6d3161 100644 --- a/nuttx/configs/z8f64200100kit/ostest/defconfig +++ b/nuttx/configs/z8f64200100kit/ostest/defconfig @@ -363,7 +363,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTEXT is not set CONFIG_EXAMPLES_OSTEST=y -# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=256 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8 diff --git a/nuttx/drivers/input/ads7843e.c b/nuttx/drivers/input/ads7843e.c index 620b8faee5..98893a2f65 100644 --- a/nuttx/drivers/input/ads7843e.c +++ b/nuttx/drivers/input/ads7843e.c @@ -270,6 +270,11 @@ static inline void ads7843e_configspi(FAR struct spi_dev_s *spi) static inline void ads7843e_waitbusy(FAR struct ads7843e_dev_s *priv) { + /* BUSY is high impedance when the ads7843e not selected. When the + * ads7843e selected, BUSY is active high. Hence, it is necessary to have + * the ads7843e selected when this function is called. + */ + while (priv->config->busy(priv->config)); } diff --git a/nuttx/drivers/serial/Kconfig b/nuttx/drivers/serial/Kconfig index c013d281fb..8b5868d44f 100644 --- a/nuttx/drivers/serial/Kconfig +++ b/nuttx/drivers/serial/Kconfig @@ -66,6 +66,20 @@ config 16550_UART0_TXBUFSIZE ---help--- 16550 UART0 Tx buffer size. Default: 256 +config 16550_UART0_IFLOWCONTROL + bool "16550 UART0 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable 16550 UART0 RTS flow control + +config 16550_UART0_OFLOWCONTROL + bool "16550 UART0 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable 16550 UART0 CTS flow control + endif config 16550_UART1 @@ -116,6 +130,20 @@ config 16550_UART1_TXBUFSIZE ---help--- 16550 UART1 Tx buffer size. Default: 256 +config 16550_UART1_IFLOWCONTROL + bool "16550 UART1 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable 16550 UART1 RTS flow control + +config 16550_UART1_OFLOWCONTROL + bool "16550 UART1 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable 16550 UART1 CTS flow control + endif config 16550_UART2 @@ -166,6 +194,20 @@ config 16550_UART2_TXBUFSIZE ---help--- 16550 UART2 Tx buffer size. Default: 256 +config 16550_UART2_IFLOWCONTROL + bool "16550 UART2 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable 16550 UART2 RTS flow control + +config 16550_UART2_OFLOWCONTROL + bool "16550 UART2 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable 16550 UART2 CTS flow control + endif config 16550_UART3 @@ -216,6 +258,20 @@ config 16550_UART3_TXBUFSIZE ---help--- 16550 UART3 Tx buffer size. Default: 256 +config 16550_UART3_IFLOWCONTROL + bool "16550 UART3 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable 16550 UART3 RTS flow control + +config 16550_UART3_OFLOWCONTROL + bool "16550 UART3 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable 16550 UART3 CTS flow control + endif choice @@ -452,40 +508,54 @@ menu "UART Configuration" config UART_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config UART_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config UART_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the UART. + ---help--- + The configured BAUD of the UART. config UART_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config UART_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config UART_2STOP int "use 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config UART_IFLOWCONTROL + bool "UART RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART RTS flow control + +config UART_OFLOWCONTROL + bool "UART CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART CTS flow control endmenu @@ -495,40 +565,54 @@ menu "UART0 Configuration" config UART0_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config UART0_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config UART0_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the UART. + ---help--- + The configured BAUD of the UART. config UART0_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config UART0_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config UART0_2STOP int "use 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config UART0_IFLOWCONTROL + bool "UART0 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART0 RTS flow control + +config UART0_OFLOWCONTROL + bool "UART0 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART0 CTS flow control endmenu @@ -538,40 +622,54 @@ menu "USART0 Configuration" config USART0_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config USART0_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config USART0_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the USART. + ---help--- + The configured BAUD of the USART. config USART0_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config USART0_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config USART0_2STOP int "use 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config USART0_IFLOWCONTROL + bool "USART0 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable USART0 RTS flow control + +config USART0_OFLOWCONTROL + bool "USART0 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable USART0 CTS flow control endmenu @@ -581,40 +679,54 @@ menu "UART1 Configuration" config UART1_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config UART1_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config UART1_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the UART. + ---help--- + The configured BAUD of the UART. config UART1_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config UART1_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config UART1_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config UART1_IFLOWCONTROL + bool "UART1 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART1 RTS flow control + +config UART1_OFLOWCONTROL + bool "UART1 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART1 CTS flow control endmenu @@ -624,40 +736,54 @@ menu "USART1 Configuration" config USART1_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config USART1_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config USART1_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the USART. + ---help--- + The configured BAUD of the USART. config USART1_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config USART1_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config USART1_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config USART1_IFLOWCONTROL + bool "USART1 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable USART1 RTS flow control + +config USART1_OFLOWCONTROL + bool "USART1 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable USART1 CTS flow control endmenu @@ -667,40 +793,54 @@ menu "UART2 Configuration" config UART2_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config UART2_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config UART2_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the UART. + ---help--- + The configured BAUD of the UART. config UART2_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config UART2_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config UART2_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config UART2_IFLOWCONTROL + bool "UART2 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART2 RTS flow control + +config UART2_OFLOWCONTROL + bool "UART2 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART2 CTS flow control endmenu @@ -710,40 +850,54 @@ menu "USART2 Configuration" config USART2_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config USART2_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config USART2_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the USART. + ---help--- + The configured BAUD of the USART. config USART2_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config USART2_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config USART2_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config USART2_IFLOWCONTROL + bool "USART2 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable USART2 RTS flow control + +config USART2_OFLOWCONTROL + bool "USART2 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable USART2 CTS flow control endmenu @@ -753,40 +907,54 @@ menu "UART3 Configuration" config UART3_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config UART3_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config UART3_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the UART. + ---help--- + The configured BAUD of the UART. config UART3_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config UART3_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config UART3_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config UART3_IFLOWCONTROL + bool "UART3 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART3 RTS flow control + +config UART3_OFLOWCONTROL + bool "UART3 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART3 CTS flow control endmenu @@ -796,40 +964,54 @@ menu "USART3 Configuration" config USART3_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config USART3_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config USART3_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the USART. + ---help--- + The configured BAUD of the USART. config USART3_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config USART3_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config USART3_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config USART3_IFLOWCONTROL + bool "USART3 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable USART3 RTS flow control + +config USART3_OFLOWCONTROL + bool "USART3 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable USART3 CTS flow control endmenu @@ -839,40 +1021,54 @@ menu "UART4 Configuration" config UART4_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config UART4_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config UART4_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the UART. + ---help--- + The configured BAUD of the UART. config UART4_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config UART4_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config UART4_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config UART4_IFLOWCONTROL + bool "UART4 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART4 RTS flow control + +config UART4_OFLOWCONTROL + bool "UART4 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART4 CTS flow control endmenu @@ -882,40 +1078,54 @@ menu "USART4 Configuration" config USART4_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config USART4_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config USART4_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the USART. + ---help--- + The configured BAUD of the USART. config USART4_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config USART4_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config USART4_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config USART4_IFLOWCONTROL + bool "USART4 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable USART4 RTS flow control + +config USART4_OFLOWCONTROL + bool "USART4 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable USART4 CTS flow control endmenu @@ -925,40 +1135,54 @@ menu "UART5 Configuration" config UART5_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config UART5_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config UART5_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the UART. + ---help--- + The configured BAUD of the UART. config UART5_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config UART5_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config UART5_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config UART5_IFLOWCONTROL + bool "UART5 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART5 RTS flow control + +config UART5_OFLOWCONTROL + bool "UART5 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART5 CTS flow control endmenu @@ -968,40 +1192,54 @@ menu "USART5 Configuration" config USART5_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config USART5_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config USART5_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the USART. + ---help--- + The configured BAUD of the USART. config USART5_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config USART5_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config USART5_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config USART5_IFLOWCONTROL + bool "USART5 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable USART5 RTS flow control + +config USART5_OFLOWCONTROL + bool "USART5 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable USART5 CTS flow control endmenu @@ -1011,40 +1249,54 @@ menu "USART6 Configuration" config USART6_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config USART6_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config USART6_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the USART. + ---help--- + The configured BAUD of the USART. config USART6_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config USART6_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config USART6_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config USART6_IFLOWCONTROL + bool "UART6 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable USART6 RTS flow control + +config USART6_OFLOWCONTROL + bool "USART6 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable USART6 CTS flow control endmenu @@ -1054,40 +1306,54 @@ menu "UART6 Configuration" config UART6_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config UART6_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config UART6_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the UART. + ---help--- + The configured BAUD of the UART. config UART6_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config UART6_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config UART6_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config UART6_IFLOWCONTROL + bool "UART6 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART6 RTS flow control + +config UART6_OFLOWCONTROL + bool "UART6 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART6 CTS flow control endmenu @@ -1097,40 +1363,54 @@ menu "USART7 Configuration" config USART7_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config USART7_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config USART7_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the USART. + ---help--- + The configured BAUD of the USART. config USART7_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config USART7_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config USART7_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config USART7_IFLOWCONTROL + bool "USART7 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable USART7 RTS flow control + +config USART7_OFLOWCONTROL + bool "USART7 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable USART7 CTS flow control endmenu @@ -1140,40 +1420,54 @@ menu "UART7 Configuration" config UART7_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config UART7_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config UART7_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the UART. + ---help--- + The configured BAUD of the UART. config UART7_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config UART7_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config UART7_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config UART7_IFLOWCONTROL + bool "UART7 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART7 RTS flow control + +config UART7_OFLOWCONTROL + bool "UART7 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART7 CTS flow control endmenu @@ -1183,40 +1477,54 @@ menu "USART8 Configuration" config USART8_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config USART8_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config USART8_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the USART. + ---help--- + The configured BAUD of the USART. config USART8_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config USART8_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config USART8_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config USART8_IFLOWCONTROL + bool "USART8 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable USART8 RTS flow control + +config USART8_OFLOWCONTROL + bool "USART8 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable USART8 CTS flow control endmenu @@ -1226,39 +1534,62 @@ menu "UART8 Configuration" config UART8_RXBUFSIZE int "Receive buffer size" default 256 - help - Characters are buffered as they are received. This specifies - the size of the receive buffer. + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. config UART8_TXBUFSIZE int "Transmit buffer size" default 256 - help - Characters are buffered before being sent. This specifies - the size of the transmit buffer. + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. config UART8_BAUD int "BAUD rate" default 115200 - help - The configured BAUD of the UART. + ---help--- + The configured BAUD of the UART. config UART8_BITS int "Character size" default 8 - help - The number of bits. Must be either 7 or 8. + ---help--- + The number of bits. Must be either 7 or 8. config UART8_PARITY int "Parity setting" default 0 - help - 0=no parity, 1=odd parity, 2=even parity + ---help--- + 0=no parity, 1=odd parity, 2=even parity config UART8_2STOP int "Uses 2 stop bits" default 0 - help - 1=Two stop bits + ---help--- + 1=Two stop bits + +config UART8_IFLOWCONTROL + bool "UART8 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable UART8 RTS flow control + +config UART8_OFLOWCONTROL + bool "UART8 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable UART8 CTS flow control endmenu + +config SERIAL_IFLOWCONTROL + bool + default n + +config SERIAL_OFLOWCONTROL + bool + default n + diff --git a/nuttx/include/nuttx/serial/serial.h b/nuttx/include/nuttx/serial/serial.h index 4ee2005ef2..7f5ea91704 100644 --- a/nuttx/include/nuttx/serial/serial.h +++ b/nuttx/include/nuttx/serial/serial.h @@ -290,7 +290,7 @@ void uart_recvchars(FAR uart_dev_t *dev); * Name: uart_datareceived * * Description: - * This function is called from uart_recvchars when new serial data is place in + * This function is called from uart_recvchars when new serial data is place in * the driver's circular buffer. This function will wake-up any stalled read() * operations that are waiting for incoming data. * diff --git a/nuttx/mm/Kconfig b/nuttx/mm/Kconfig index 960c979e81..20d83b5dbb 100644 --- a/nuttx/mm/Kconfig +++ b/nuttx/mm/Kconfig @@ -56,7 +56,14 @@ config MM_SMALL MM_SMALL can be defined so that those MCUs will also benefit from the smaller, 16-bit-based allocation overhead. - NOTE: If MM_MULTIHEAP is selected, then this applies to all heaps. + WARNING: This selection will also change the alignment of allocated + memory. For example, on ARM memory will have 8-byte alignment by + default. If MM_SMALL is selected, then allocated memory will have + only 4-byte alignment. This may be important on some platforms where + 64-bit data is in allocated structures and 8-byte alignment is required. + + NOTE: If MM_MULTIHEAP is selected, then this selection applies to all + heaps. config MM_REGIONS int "Number of memory regions" From 39285f158348448d725de11ef8d29da4bb5fb3a9 Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Mon, 17 Jun 2013 09:16:16 +0200 Subject: [PATCH 40/41] Enabled HW flow control --- nuttx/configs/px4fmu-v1/nsh/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/nuttx/configs/px4fmu-v1/nsh/defconfig b/nuttx/configs/px4fmu-v1/nsh/defconfig index 3470034f4a..727c19b599 100644 --- a/nuttx/configs/px4fmu-v1/nsh/defconfig +++ b/nuttx/configs/px4fmu-v1/nsh/defconfig @@ -94,6 +94,8 @@ CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI=y CONFIG_SERIAL_TERMIOS=y +CONFIG_SERIAL_IFLOWCONTROL=y +CONFIG_SERIAL_OFLOWCONTROL=y # # STM32 Configuration Options From 5a74e9a664c1dc1b48f36428b535ca2b84e776bb Mon Sep 17 00:00:00 2001 From: Lorenz Meier Date: Mon, 17 Jun 2013 09:17:42 +0200 Subject: [PATCH 41/41] added MacOs files to gitignore, since our devs are already struggling enough --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 83f6546a69..a9a4a345e0 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ .depend Make.dep +.DS_Store *.o *.a *.d