Skip to content

Commit f2d241e

Browse files
igorban-inteligcbot
igorban-intel
authored and
igcbot
committed
Fix rdregion creation in GenXAddressCommoning
This fixes the generation of the correct intrinsic mnemonic (llvm.genx.rdregioni.v1i8.v16i8.i16) and prevents type mismatches in downstream passes.
1 parent 3a4d443 commit f2d241e

File tree

2 files changed

+81
-1
lines changed

2 files changed

+81
-1
lines changed

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXAddressCommoning.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1007,7 +1007,7 @@ bool GenXAddressCommoning::vectorizeAddrsFromOneVector(
10071007
auto ui = OldConv->use_begin();
10081008
auto user = cast<Instruction>(ui->getUser());
10091009
auto NewExtract = R2.createRdRegion(NewConv, OldConv->getName(), user,
1010-
user->getDebugLoc(), /*ScalarAllowed=*/true);
1010+
user->getDebugLoc(), /*ScalarAllowed=*/!OldConv->getType()->isVectorTy());
10111011
Numbering->setNumber(NewExtract, Numbering->getNumber(user));
10121012
// At this late stage, I believe nothing relies on the baling type for
10131013
// this instruction being set to RDREGION, but we set it anyway for

‎IGC/VectorCompiler/test/GenXAddressCommoning/rdregion_reduce.ll

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2025 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
;
9+
; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXModule -GenXLiveRangesWrapper \
10+
; RUN: -GenXAddressCommoningWrapper -march=genx64 -mtriple=spir64-unknown-unknown \
11+
; RUN: -mcpu=Gen9 -S < %s | FileCheck %s
12+
13+
target datalayout = "e-p:64:64-p3:32:32-p6:32:32-i64:64-n8:16:32:64"
14+
target triple = "spir64-unknown-unknown"
15+
16+
define spir_kernel void @"foo<char, 2, 8>"() #0 {
17+
entry:
18+
call spir_func void @_Z4funcIcLi2ELi8EEvyiiu2CMmrT0_xT1__T_()
19+
ret void
20+
}
21+
22+
; CHECK: define internal spir_func void @_Z4funcIcLi2ELi8EEvyiiu2CMmrT0_xT1__T_
23+
; CHECK: entry:
24+
; CHECK: %iselect.split14.multiindirect_idx_subregion.categoryconv3 =
25+
; CHECK-SAME: call <1 x i16> @llvm.genx.rdregioni.v1i16.v2i16.i16(<2 x i16> {{.*}}, i32 1, i32 1, i32 1, i16 2, i32 undef)
26+
27+
define internal spir_func void @_Z4funcIcLi2ELi8EEvyiiu2CMmrT0_xT1__T_() {
28+
entry:
29+
%rdregioni = call <16 x i16> @llvm.genx.rdregioni.v16i16.v1i16.i16(<1 x i16> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0)
30+
%constant.split.int81 = call <16 x i8> @llvm.genx.wrregioni.v16i8.v8i8.i16.i1(<16 x i8> zeroinitializer, <8 x i8> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0, i1 false)
31+
%iselect.split7.multiindirect_idx_subregion = call <1 x i16> @llvm.genx.rdregioni.v1i16.v16i16.i16(<16 x i16> %rdregioni, i32 1, i32 0, i32 0, i16 0, i32 0)
32+
%iselect.split7.multiindirect_idx_subregion.categoryconv = call <1 x i16> @llvm.genx.convert.addr.v1i16(<1 x i16> %iselect.split7.multiindirect_idx_subregion, i16 0)
33+
%iselect.split7 = call <1 x i8> @llvm.genx.rdregioni.v1i8.v16i8.v1i16(<16 x i8> %constant.split.int81, i32 0, i32 1, i32 0, <1 x i16> %iselect.split7.multiindirect_idx_subregion.categoryconv, i32 0)
34+
%iselect.split7.join7 = call <16 x i8> @llvm.genx.wrregioni.v16i8.v1i8.i16.i1(<16 x i8> zeroinitializer, <1 x i8> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0, i1 false)
35+
%iselect.split8.multiindirect_idx_subregion.categoryconv = call <1 x i16> @llvm.genx.convert.addr.v1i16(<1 x i16> zeroinitializer, i16 0)
36+
%iselect.split8 = call <1 x i8> @llvm.genx.rdregioni.v1i8.v16i8.v1i16(<16 x i8> zeroinitializer, i32 0, i32 0, i32 0, <1 x i16> zeroinitializer, i32 0)
37+
%iselect.split8.join8 = call <16 x i8> @llvm.genx.wrregioni.v16i8.v1i8.i16.i1(<16 x i8> zeroinitializer, <1 x i8> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0, i1 false)
38+
%iselect.split9.multiindirect_idx_subregion = call <1 x i16> @llvm.genx.rdregioni.v1i16.v16i16.i16(<16 x i16> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0)
39+
%iselect.split9.multiindirect_idx_subregion.categoryconv = call <1 x i16> @llvm.genx.convert.addr.v1i16(<1 x i16> zeroinitializer, i16 0)
40+
%iselect.split9 = call <1 x i8> @llvm.genx.rdregioni.v1i8.v16i8.v1i16(<16 x i8> zeroinitializer, i32 0, i32 0, i32 0, <1 x i16> zeroinitializer, i32 0)
41+
%iselect.split9.join9 = call <16 x i8> @llvm.genx.wrregioni.v16i8.v1i8.i16.i1(<16 x i8> zeroinitializer, <1 x i8> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0, i1 false)
42+
%iselect.split10.multiindirect_idx_subregion = call <1 x i16> @llvm.genx.rdregioni.v1i16.v16i16.i16(<16 x i16> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0)
43+
%iselect.split10.multiindirect_idx_subregion.categoryconv = call <1 x i16> @llvm.genx.convert.addr.v1i16(<1 x i16> zeroinitializer, i16 0)
44+
%iselect.split10 = call <1 x i8> @llvm.genx.rdregioni.v1i8.v16i8.v1i16(<16 x i8> zeroinitializer, i32 0, i32 0, i32 0, <1 x i16> zeroinitializer, i32 0)
45+
%iselect.split10.join10 = call <16 x i8> @llvm.genx.wrregioni.v16i8.v1i8.i16.i1(<16 x i8> zeroinitializer, <1 x i8> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0, i1 false)
46+
%iselect.split11.join11 = call <16 x i8> @llvm.genx.wrregioni.v16i8.v1i8.i16.i1(<16 x i8> zeroinitializer, <1 x i8> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0, i1 false)
47+
%iselect.split12.multiindirect_idx_subregion = call <1 x i16> @llvm.genx.rdregioni.v1i16.v16i16.i16(<16 x i16> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0)
48+
%iselect.split12.multiindirect_idx_subregion.categoryconv = call <1 x i16> @llvm.genx.convert.addr.v1i16(<1 x i16> zeroinitializer, i16 0)
49+
%iselect.split12 = call <1 x i8> @llvm.genx.rdregioni.v1i8.v16i8.v1i16(<16 x i8> zeroinitializer, i32 0, i32 0, i32 0, <1 x i16> zeroinitializer, i32 0)
50+
%iselect.split12.join12 = call <16 x i8> @llvm.genx.wrregioni.v16i8.v1i8.i16.i1(<16 x i8> zeroinitializer, <1 x i8> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0, i1 false)
51+
%iselect.split13.join13 = call <16 x i8> @llvm.genx.wrregioni.v16i8.v1i8.i16.i1(<16 x i8> zeroinitializer, <1 x i8> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0, i1 false)
52+
%iselect.split14.multiindirect_idx_subregion = call <1 x i16> @llvm.genx.rdregioni.v1i16.v16i16.i16(<16 x i16> %rdregioni, i32 0, i32 0, i32 0, i16 0, i32 0)
53+
%iselect.split14.multiindirect_idx_subregion.categoryconv = call <1 x i16> @llvm.genx.convert.addr.v1i16(<1 x i16> %iselect.split14.multiindirect_idx_subregion, i16 0)
54+
%iselect.split14 = call <1 x i8> @llvm.genx.rdregioni.v1i8.v16i8.v1i16(<16 x i8> %constant.split.int81, i32 0, i32 1, i32 0, <1 x i16> %iselect.split14.multiindirect_idx_subregion.categoryconv, i32 0)
55+
%iselect.split14.join14 = call <16 x i8> @llvm.genx.wrregioni.v16i8.v1i8.i16.i1(<16 x i8> zeroinitializer, <1 x i8> zeroinitializer, i32 0, i32 0, i32 0, i16 0, i32 0, i1 false)
56+
%iselect.split15.multiindirect_idx_subregion = call <1 x i16> @llvm.genx.rdregioni.v1i16.v16i16.i16(<16 x i16> %rdregioni, i32 0, i32 0, i32 0, i16 0, i32 1)
57+
%iselect.split15.multiindirect_idx_subregion.categoryconv = call <1 x i16> @llvm.genx.convert.addr.v1i16(<1 x i16> %iselect.split15.multiindirect_idx_subregion, i16 0)
58+
%iselect.split15 = call <1 x i8> @llvm.genx.rdregioni.v1i8.v16i8.v1i16(<16 x i8> %constant.split.int81, i32 0, i32 1, i32 0, <1 x i16> %iselect.split15.multiindirect_idx_subregion.categoryconv, i32 0)
59+
ret void
60+
}
61+
62+
declare <16 x i16> @llvm.genx.rdregioni.v16i16.v1i16.i16(<1 x i16>, i32, i32, i32, i16, i32)
63+
64+
declare <1 x i16> @llvm.genx.rdregioni.v1i16.v16i16.i16(<16 x i16>, i32, i32, i32, i16, i32)
65+
66+
declare <1 x i8> @llvm.genx.rdregioni.v1i8.v16i8.v1i16(<16 x i8>, i32, i32, i32, <1 x i16>, i32)
67+
68+
declare <16 x i8> @llvm.genx.wrregioni.v16i8.v1i8.i16.i1(<16 x i8>, <1 x i8>, i32, i32, i32, i16, i32, i1)
69+
70+
declare <16 x i8> @llvm.genx.wrregioni.v16i8.v8i8.i16.i1(<16 x i8>, <8 x i8>, i32, i32, i32, i16, i32, i1)
71+
72+
declare <1 x i16> @llvm.genx.convert.addr.v1i16(<1 x i16>, i16)
73+
74+
; uselistorder directives
75+
uselistorder ptr @llvm.genx.rdregioni.v1i16.v16i16.i16, { 5, 4, 3, 2, 1, 0 }
76+
uselistorder ptr @llvm.genx.rdregioni.v1i8.v16i8.v1i16, { 6, 5, 4, 3, 2, 1, 0 }
77+
uselistorder ptr @llvm.genx.wrregioni.v16i8.v1i8.i16.i1, { 7, 6, 5, 4, 3, 2, 1, 0 }
78+
uselistorder ptr @llvm.genx.convert.addr.v1i16, { 6, 5, 4, 3, 2, 1, 0 }
79+
80+
attributes #0 = { "CMGenxMain" }

0 commit comments

Comments
 (0)