Fix untyped load 2D intrinsic whole GRF allocation in VC

.

(cherry picked from commit 8acdb71)

Author: vsemenov368

IGC/VectorCompiler/lib/GenXCodeGen/GenXLoadStoreLegalization.cpp

@@ -488,7 +488,7 @@ Value *GenXLoadStoreLegalization::extendUntypedBlockLoad2d(CallInst &CI) const {
 
   if (WidthBytes % ST->getGRFByteSize()) {
     SmallVector<Type *, 2> OverloadedTypes;
-    auto NewNumElements = ST->getGRFByteSize() / ElemSizeBytes;
+    auto NewNumElements = alignTo(NumElements, ST->getGRFByteSize() / ElemSizeBytes);
     auto *VTy = IGCLLVM::FixedVectorType::get(ETy, NewNumElements);
     OverloadedTypes.push_back(VTy);
     const auto CacheControlIndex =

IGC/VectorCompiler/test/GenXLoadStoreLegalization/LSC/load_2d_ugm.ll

@@ -8,21 +8,22 @@
 
 ; RUN: %opt %use_old_pass_manager% -GenXLoadStoreLegalization -march=genx64 -mcpu=Xe2 -mtriple=spir64-unknown-unknown -S %s | FileCheck %s
 
-declare <6 x i32> @llvm.vc.internal.lsc.load.block.2d.ugm.v6i32.v2i8(i1, i8, <2 x i8>, i8, i16, i16, i64, i32, i32, i32, i32, i32, i32, i32, <6 x i32>)
 declare <32 x i16> @llvm.vc.internal.lsc.load.block.2d.ugm.v32i16.v2i8(i1, i8, <2 x i8>, i8, i16, i16, i64, i32, i32, i32, i32, i32, i32, i32, <32 x i16>)
 declare <16 x i8> @llvm.vc.internal.lsc.load.2d.ugm.desc.v16i8.v2i8(i1, <2 x i8>, i8, i16, i16, <16 x i32>, i32, i32, <16 x i8>)
 declare <16 x i32> @llvm.vc.internal.lsc.load.2d.ugm.desc.v16i32.v2i8(i1, <2 x i8>, i8, i16, i16, <16 x i32>, i32, i32, <16 x i32>)
 declare <65 x i8> @llvm.vc.internal.lsc.load.2d.ugm.desc.transpose.v65i8.v2i8(i1, <2 x i8>, i8, i16, i16, <16 x i32>, i32, i32, <65 x i8>)
+declare <80 x i16> @llvm.vc.internal.lsc.load.block.2d.ugm.vnni.v80i16.v2i8(i1, i8, <2 x i8>, i8, i16, i16, i64, i32, i32, i32, i32, i32, i32, i32, <80 x i16>)
 
 ; CHECK-LABEL: @test_load(
-define <6 x i32> @test_load(i64 %base, i32 %width, i32 %height, i32 %pitch, i32 %x, i32 %y, <6 x i32> %passthru) {
-; CHECK: [[WRREG:%[^ ]+]] = call <16 x i32> @llvm.genx.wrregioni.v16i32.v6i32.i16.i1(<16 x i32> undef, <6 x i32> %passthru, i32 1, i32 1, i32 0, i16 0, i32 undef, i1 true)
-; CHECK: [[LOAD:%[^ ]+]] = call <16 x i32> @llvm.vc.internal.lsc.load.block.2d.ugm.v16i32.v2i8(i1 true, i8 3, <2 x i8> <i8 1, i8 2>, i8 1, i16 2, i16 3, i64 %base, i32 %width, i32 %height, i32 %pitch, i32 %x, i32 %y, i32 0, i32 0, <16 x i32> [[WRREG]])
-; CHECK: [[RDREG:%[^ ]+]] = call <6 x i32> @llvm.genx.rdregioni.v6i32.v16i32.i16(<16 x i32> [[LOAD]], i32 1, i32 1, i32 0, i16 0, i32 undef)
-; CHECK: ret <6 x i32> [[RDREG]]
+define <80 x i16> @test_load(i64 %base, i32 %width, i32 %height, i32 %pitch, i32 %x, i32 %y, <80 x i16> %passthru) {
 
-  %load = call <6 x i32> @llvm.vc.internal.lsc.load.block.2d.ugm.v6i32.v2i8(i1 true, i8 3, <2 x i8> <i8 1, i8 2>, i8 1, i16 2, i16 3, i64 %base, i32 %width, i32 %height, i32 %pitch, i32 %x, i32 %y, i32 0, i32 0, <6 x i32> %passthru)
-  ret <6 x i32> %load
+; CHECK: [[WRREG:%[^ ]+]] = call <96 x i16> @llvm.genx.wrregioni.v96i16.v80i16.i16.i1(<96 x i16> undef, <80 x i16> %passthru, i32 1, i32 1, i32 0, i16 0, i32 undef, i1 true)
+; CHECK: [[LOAD:%[^ ]+]] = call <96 x i16> @llvm.vc.internal.lsc.load.block.2d.ugm.vnni.v96i16.v2i8(i1 true, i8 2, <2 x i8> zeroinitializer, i8 1, i16 6, i16 10, i64 %base, i32 %width, i32 %height, i32 %pitch, i32 %x, i32 %y, i32 0, i32 0, <96 x i16> [[WRREG]])
+; CHECK: [[RDREG:%[^ ]+]] = call <80 x i16> @llvm.genx.rdregioni.v80i16.v96i16.i16(<96 x i16> [[LOAD]], i32 1, i32 1, i32 0, i16 0, i32 undef)
+; CHECK: ret <80 x i16> [[RDREG]]
+
+  %load = call <80 x i16> @llvm.vc.internal.lsc.load.block.2d.ugm.vnni.v80i16.v2i8(i1 true, i8 2, <2 x i8> zeroinitializer, i8 1, i16 6, i16 10, i64 %base, i32 %width, i32 %height, i32 %pitch, i32 %x, i32 %y, i32 0, i32 0, <80 x i16> %passthru)
+  ret <80 x i16> %load
 }
 
 ; CHECK-LABEL: @test_load_whole_grf(
@@ -56,8 +57,8 @@ define <16 x i32> @test_load_desc_whole_grf(<16 x i32> %addr) {
 
 ; CHECK-LABEL: test_load_desc_transpose_undef(
 define <65 x i8> @test_load_desc_transpose_undef(<16 x i32> %addr) {
-; CHECK: [[LOAD:%[^ ]+]] = call <64 x i8> @llvm.vc.internal.lsc.load.2d.ugm.desc.transpose.v64i8.v2i8(i1 true, <2 x i8> <i8 2, i8 2>, i8 1, i16 13, i16 5, <16 x i32> %addr, i32 0, i32 0, <64 x i8> undef)
-; CHECK: [[RDREG:%[^ ]+]] = call <65 x i8> @llvm.genx.rdregioni.v65i8.v64i8.i16(<64 x i8> [[LOAD]], i32 1, i32 1, i32 0, i16 0, i32 undef)
+; CHECK: [[LOAD:%[^ ]+]] = call <128 x i8> @llvm.vc.internal.lsc.load.2d.ugm.desc.transpose.v128i8.v2i8(i1 true, <2 x i8> <i8 2, i8 2>, i8 1, i16 13, i16 5, <16 x i32> %addr, i32 0, i32 0, <128 x i8> undef)
+; CHECK: [[RDREG:%[^ ]+]] = call <65 x i8> @llvm.genx.rdregioni.v65i8.v128i8.i16(<128 x i8> %1, i32 1, i32 1, i32 0, i16 0, i32 undef)
 ; CHECK: ret <65 x i8> [[RDREG]]
 
   %load = call <65 x i8> @llvm.vc.internal.lsc.load.2d.ugm.desc.transpose.v65i8.v2i8(i1 true, <2 x i8> <i8 2, i8 2>, i8 1, i16 13, i16 5, <16 x i32> %addr, i32 0, i32 0, <65 x i8> undef)