DPAS intrinsics

Enables certain DPAS intrinsics

Author: trbauer

IGC/BiFModule/Languages/OpenCL/IBiF_dpas.cl

@@ -36,4 +36,14 @@ SPDX-License-Identifier: MIT
 //*****************************************************************************/
 #include "IBiF_matrix.cl"
 
+//*****************************************************************************/
+// DPAS Functions - Extension
+//*****************************************************************************/
+#include "IBiF_dpas.cl"
+
+//*****************************************************************************/
+// DP4A Dot product extensions
+//*****************************************************************************/
+#include "IBiF_Dot_Product.cl"
+
 

IGC/BiFModule/Languages/OpenCL/PreRelease/IBIF_PreRelease_Impl.cl

@@ -2182,6 +2182,35 @@ static e_alignment GetPreferredAlignmentOnUse(llvm::Value* V, WIAnalysis* WIA,
                     return (pCtx->platform.getGRFSize() == 64) ? EALIGN_32WORD : EALIGN_HWORD;
                 }
             }
+            GenISAIntrinsic::ID gid = GII->getIntrinsicID();
+            if (GII && (gid == GenISAIntrinsic::GenISA_dpas ||
+                gid == GenISAIntrinsic::GenISA_sub_group_dpas))
+            {
+                // Only oprd1 could be uniform and its alignment could
+                // be less than GRF. All the others are GRF-aligned.
+                if (aV == GII->getArgOperand(1)) {
+                    ConstantInt* pa = dyn_cast<ConstantInt>(GII->getOperand(3)); // oprd1's precision
+                    ConstantInt* sdepth = dyn_cast<ConstantInt>(GII->getOperand(5));
+
+                    int PA = (int)pa->getSExtValue();
+                    int SD = (int)sdepth->getSExtValue();
+                    uint32_t bits = getPrecisionInBits((PrecisionType)PA);
+                    uint32_t OPS_PER_CHAN = (GII->getType()->isFloatTy() ? 2 : 4);
+                    bits = bits * OPS_PER_CHAN;
+                    bits = bits * SD;
+                    uint32_t NDWs = bits / 32;
+                    switch (NDWs) {
+                    default:
+                        break;
+                    case 2:
+                        return EALIGN_QWORD;
+                    case 4:
+                        return EALIGN_OWORD;
+                    case 8:
+                        return EALIGN_HWORD;
+                    }
+                }
+            }
         }
         return EALIGN_AUTO;
     };

IGC/Compiler/CISACodeGen/CShader.cpp

@@ -426,10 +426,10 @@ bool DeSSA::runOnFunction(Function& MF)
     //  so it is likely for the algorithm to coalesce the phi's dst and the
     //  other src that is used in the loop, and therefore remove mov instrutions
     //  in the loop.
-  //
-  //  Note that isolating a value introduce additional copy, thus a threshold
-  //  is used here as a heuristic to try to make sure that a benefit is more
-  //  than the cost.
+    //
+    //  Note that isolating a value introduce additional copy, thus a threshold
+    //  is used here as a heuristic to try to make sure that a benefit is more
+    //  than the cost.
     enum { PHI_SRC_USE_THRESHOLD = 3 };  // arbitrary number
     DenseMap<Value*, int> PHILoopPreHeaderSrcs;
 

IGC/Compiler/CISACodeGen/DeSSA.cpp

@@ -241,6 +241,49 @@ void VariableReuseAnalysis::mergeVariables(Function* F)
         if (GenIntrinsicInst * CI = dyn_cast<GenIntrinsicInst>(I))
         {
             switch (CI->getIntrinsicID()) {
+            case GenISAIntrinsic::GenISA_sub_group_dpas:
+            case GenISAIntrinsic::GenISA_dpas:
+            {
+                if (!m_DeSSA) {
+                    // Skip if no DeSSA
+                    break;
+                }
+
+                Value* out = CI;
+                Value* input = CI->getOperand(0);
+
+                if (!(isa<Instruction>(input) || isa<Argument>(input)))
+                {
+                    // input may be a constant for example
+                    break;
+                }
+                Type* OTy = out->getType();
+                Type* ITy = input->getType();
+                if (getTypeSizeInBits(OTy) != getTypeSizeInBits(ITy))
+                {
+                    // If out and input are different size, skip
+                    break;
+                }
+
+                // For now, coalescing out and input if at least one of them
+                // is local, and input is the last use.
+                if ((m_WIA && m_WIA->whichDepend(out) == m_WIA->whichDepend(input)) &&
+                    !hasBeenPayloadCoalesced(input) &&
+                    !hasBeenPayloadCoalesced(out) &&
+                    !m_DeSSA->interfere(out, input))
+                {
+                    // For dpas, alignment for out/input are the same
+                    e_alignment align = EALIGN_AUTO;
+                    if (m_WIA) {
+                        align = GetPreferredAlignment(out, m_WIA, m_pCtx);
+                    }
+                    // Make sure that nodes have been created before doing union
+                    m_DeSSA->addReg(out, align);
+                    m_DeSSA->addReg(input, align);
+                    m_DeSSA->unionRegs(out, input);
+                }
+                break;
+            }
             default:
                 break;
             }  // End of switch

IGC/Compiler/CISACodeGen/VariableReuseAnalysis.cpp

@@ -112,6 +112,7 @@ void initializeSubGroupFuncsResolutionPass(llvm::PassRegistry&);
 void initializeTransformUnmaskedFunctionsPassPass(llvm::PassRegistry&);
 void initializeIndirectCallOptimizationPass(llvm::PassRegistry&);
 void initializePromoteInt8TypePass(llvm::PassRegistry&);
+void initializeDpasFuncsResolutionPass(llvm::PassRegistry&);
 void initializePrepareLoadsStoresPassPass(llvm::PassRegistry&);
 void initializeVectorBitCastOptPass(llvm::PassRegistry&);
 void initializeVectorPreProcessPass(llvm::PassRegistry&);

IGC/Compiler/InitializePasses.h

@@ -629,6 +629,8 @@ void ScalarizeFunction::scalarizeInstruction(PHINode* PI)
                     {
                     default:
                         break;
+                    case GenISAIntrinsic::GenISA_sub_group_dpas:
+                    case GenISAIntrinsic::GenISA_dpas:
                     case GenISAIntrinsic::GenISA_simdBlockWrite:
                         recoverNonScalarizableInst(PI);
                         return;