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YuriPlyakhinigcbot
YuriPlyakhin
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igcbot
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Support predicated loads/stores in MemOpt and LdStCombine
This patch adds support for predicated loads and stores in the Memory Optimization (MemOpt) and Load/Store Combination (LdStCombine) passes.
1 parent d6d0b61 commit 86a80e1

33 files changed

+4003
-360
lines changed

‎IGC/Compiler/CISACodeGen/MemOpt.cpp

Lines changed: 371 additions & 360 deletions
Large diffs are not rendered by default.

‎IGC/Compiler/tests/LdStCombine/DI_call_between_stores-predicated.ll

Lines changed: 122 additions & 0 deletions
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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; This test is a modification of store_use_vector.ll and it's purpose is to make sure, that debug calls
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; are neutral to LdStCombine pass optimizations. They should not be treated as fence-like calls.
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;
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; REQUIRES: llvm-14-plus, regkeys
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;
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; RUN: igc_opt --opaque-pointers %s -S -inputocl -igc-ldstcombine -regkey=EnableLdStCombine=1 \
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; RUN: -platformbmg \
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; RUN: | FileCheck %s
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;
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; CHECK-LABEL: define spir_kernel void @f0
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; CHECK: call void @llvm.genx.GenISA.PredicatedStore.p1.v8i32(ptr addrspace(1) %{{.*}}, <8 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 117835012, i32 8, i32 202050057, i32 269422093, i32 336794129>, i64 32, i1 true)
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; CHECK: ret void
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32"
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target triple = "spir64-unknown-unknown"
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%struct.Result = type { [3 x float], [4 x i8], i32, [12 x i8] }
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; Function Attrs: convergent nounwind
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define spir_kernel void @f0(ptr addrspace(1) %result, <8 x i32> %r0, <8 x i32> %payloadHeader, i16 %localIdX, i16 %localIdY, i16 %localIdZ, ptr %privateBase) {
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entry:
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%idxprom = zext i16 %localIdX to i64
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx1 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 0, i64 0
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call void @llvm.genx.GenISA.PredicatedStore.p1.f32(ptr addrspace(1) %arrayidx1, float 0.000000e+00, i64 32, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx5 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 0, i64 1
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call void @llvm.genx.GenISA.PredicatedStore.p1.f32(ptr addrspace(1) %arrayidx5, float 1.000000e+00, i64 4, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx9 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 0, i64 2
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call void @llvm.genx.GenISA.PredicatedStore.p1.f32(ptr addrspace(1) %arrayidx9, float 2.000000e+00, i64 8, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx12 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 1, i64 0
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx12, i8 4, i64 4, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx16 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 1, i64 1
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx16, i8 5, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx20 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 1, i64 2
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx20, i8 6, i64 2, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx24 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 1, i64 3
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx24, i8 7, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%test0 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 2
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call void @llvm.genx.GenISA.PredicatedStore.p1.i32(ptr addrspace(1) %test0, i32 8, i64 16, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 0
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32, i8 9, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.1 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 1
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.1, i8 10, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.2 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 2
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.2, i8 11, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.3 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 3
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.3, i8 12, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.4 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 4
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.4, i8 13, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.5 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 5
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.5, i8 14, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.6 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 6
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.6, i8 15, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.7 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 7
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.7, i8 16, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.8 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 8
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.8, i8 17, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.9 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 9
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.9, i8 18, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.10 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 10
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.10, i8 19, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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%arrayidx32.11 = getelementptr inbounds %struct.Result, ptr addrspace(1) %result, i64 %idxprom, i32 3, i64 11
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call void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1) %arrayidx32.11, i8 20, i64 1, i1 true)
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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ret void
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}
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; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
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declare void @llvm.dbg.value(metadata, metadata, metadata) #0
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declare void @llvm.genx.GenISA.PredicatedStore.p1.f32(ptr addrspace(1), float, i64, i1)
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declare void @llvm.genx.GenISA.PredicatedStore.p1.i8(ptr addrspace(1), i8, i64, i1)
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declare void @llvm.genx.GenISA.PredicatedStore.p1.i32(ptr addrspace(1), i32, i64, i1)
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!igc.functions = !{!12}
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!llvm.dbg.cu = !{!0}
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!llvm.debugify = !{!3, !4}
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!llvm.module.flags = !{!5}
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!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
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!1 = !DIFile(filename: "DI_call_betwen_stores.ll", directory: "/")
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!2 = !{}
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!3 = !{i32 13}
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!4 = !{i32 11}
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!5 = !{i32 2, !"Debug Info Version", i32 3}
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!6 = distinct !DISubprogram(name: "test_dbginfo", linkageName: "test_dbginfo", scope: null, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0, retainedNodes: !8)
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!7 = !DISubroutineType(types: !2)
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!8 = !{!9}
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!9 = !DILocalVariable(name: "testvar", scope: !6, file: !1, line: 1, type: !10)
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!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
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!11 = !DILocation(line: 1, column: 1, scope: !6)
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!12 = !{ptr @f0, !13}
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!13 = !{!14}
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!14 = !{!"function_type", i32 0}

‎IGC/Compiler/tests/LdStCombine/predicated-load_favor_vector.ll

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; This is to test the optimization. Normally, those tests should use struct as the type for
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; loaded value. However, as vector has been extensively optmized. Load combining specially
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; generates vector instead of struct for those tests, thus result in less instructions.
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; REQUIRES: llvm-14-plus, regkeys
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; RUN: igc_opt --opaque-pointers -S -inputocl -igc-ldstcombine -regkey=EnableLdStCombine=5 -platformbmg %s \
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; RUN: | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32"
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target triple = "spir64-unknown-unknown"
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; CHECK-LABEL: define spir_kernel void @test_vector_creation
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; Function Attrs: convergent nounwind
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define spir_kernel void @test_vector_creation(i8 addrspace(1)* %src, <4 x i8> addrspace(1)* %result) #0 {
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entry:
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; case 0: 4 load i8 --> load i32 --> bitcast <4 x i8> --> store
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; handle insertelement
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; CHECK-LABEL: c0.base
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; CHECK: [[T0_0:%.*]] = call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1.i32(ptr addrspace(1) %{{.*}}, i32 84148994)
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; CHECK: {{.*}} = bitcast i32 [[T0_0]] to <4 x i8>
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%c0.base = getelementptr inbounds i8, i8 addrspace(1)* %src, i64 0
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%c0.0 = call i8 @llvm.genx.GenISA.PredicatedLoad.i8.p1i8.i8(i8 addrspace(1)* %c0.base, i64 1, i1 true, i8 2)
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%c0.arrayidx1 = getelementptr inbounds i8, i8 addrspace(1)* %c0.base, i64 1
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%c0.1 = call i8 @llvm.genx.GenISA.PredicatedLoad.i8.p1i8.i8(i8 addrspace(1)* %c0.arrayidx1, i64 1, i1 true, i8 3)
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%c0.arrayidx3 = getelementptr inbounds i8, i8 addrspace(1)* %c0.base, i64 2
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%c0.2 = call i8 @llvm.genx.GenISA.PredicatedLoad.i8.p1i8.i8(i8 addrspace(1)* %c0.arrayidx3, i64 1, i1 true, i8 4)
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%c0.arrayidx5 = getelementptr inbounds i8, i8 addrspace(1)* %c0.base, i64 3
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%c0.3 = call i8 @llvm.genx.GenISA.PredicatedLoad.i8.p1i8.i8(i8 addrspace(1)* %c0.arrayidx5, i64 1, i1 true, i8 5)
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%c0.v.0 = insertelement <4 x i8> undef, i8 %c0.0, i32 0
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%c0.v.1 = insertelement <4 x i8> %c0.v.0, i8 %c0.1, i32 1
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%c0.v.2 = insertelement <4 x i8> %c0.v.1, i8 %c0.2, i32 2
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%c0.v.3 = insertelement <4 x i8> %c0.v.2, i8 %c0.3, i32 3
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%c0.dst = getelementptr inbounds <4 x i8>, <4 x i8> addrspace(1)* %result, i64 0
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store <4 x i8> %c0.v.3, <4 x i8> addrspace(1)* %c0.dst, align 4
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; case 1: [i8, i8, <2 x i8>] --> load i32
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; handle insertelement and shufflevector
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; CHECK-LABEL: c1.base
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; CHECK: [[T1_0:%.*]] = call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1.i32(ptr addrspace(1) %{{.*}}, i32 84148994)
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; CHECK: {{.*}} = bitcast i32 [[T1_0]] to <4 x i8>
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%c1.base = getelementptr inbounds i8, i8 addrspace(1)* %src, i64 16
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%c1.0 = call i8 @llvm.genx.GenISA.PredicatedLoad.i8.p1i8.i8(i8 addrspace(1)* %c1.base, i64 1, i1 true, i8 2)
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%c1.arrayidx1 = getelementptr inbounds i8, i8 addrspace(1)* %c1.base, i64 1
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%c1.1 = call i8 @llvm.genx.GenISA.PredicatedLoad.i8.p1i8.i8(i8 addrspace(1)* %c1.arrayidx1, i64 1, i1 true, i8 3)
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%c1.arrayidx3 = getelementptr inbounds i8, i8 addrspace(1)* %c1.base, i64 2
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%c1.arrayidx3.0 = bitcast i8 addrspace(1)* %c1.arrayidx3 to <2 x i8> addrspace(1)*
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%c1.2 = call <2 x i8> @llvm.genx.GenISA.PredicatedLoad.v2i8.p1v2i8.v2i8(<2 x i8> addrspace(1)* %c1.arrayidx3.0, i64 1, i1 true, <2 x i8> <i8 4, i8 5>)
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%c1.2.0 = shufflevector <2 x i8> %c1.2, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%c1.v.0 = insertelement <4 x i8> undef, i8 %c1.0, i32 0
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%c1.v.1 = insertelement <4 x i8> %c1.v.0, i8 %c1.1, i32 1
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%c1.v.2 = shufflevector <4 x i8> %c1.v.1, <4 x i8> %c1.2.0, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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%c1.dst = getelementptr inbounds <4 x i8>, <4 x i8> addrspace(1)* %result, i64 2
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store <4 x i8> %c1.v.2, <4 x i8> addrspace(1)* %c1.dst, align 4
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; case 2: [i8, <2 x i8>, i8] --> load i32
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; handle extractelement and insertelement
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; CHECK-LABEL: c2.base
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; CHECK: [[T2_0:%.*]] = call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1.i32(ptr addrspace(1) %{{.*}}, i32 84148994)
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; CHECK: {{.*}} = bitcast i32 [[T2_0]] to <4 x i8>
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%c2.base = getelementptr inbounds i8, i8 addrspace(1)* %src, i64 32
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%c2.0 = call i8 @llvm.genx.GenISA.PredicatedLoad.i8.p1i8.i8(i8 addrspace(1)* %c2.base, i64 1, i1 true, i8 2)
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%c2.arrayidx1 = getelementptr inbounds i8, i8 addrspace(1)* %c2.base, i64 1
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%c2.arrayidx1.0 = bitcast i8 addrspace(1)* %c2.arrayidx1 to <2 x i8> addrspace(1)*
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%c2.1 = call <2 x i8> @llvm.genx.GenISA.PredicatedLoad.v2i8.p1v2i8.v2i8(<2 x i8> addrspace(1)* %c2.arrayidx1.0, i64 1, i1 true, <2 x i8> <i8 3, i8 4>)
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%c2.1.0 = extractelement <2 x i8> %c2.1, i32 0
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%c2.1.1 = extractelement <2 x i8> %c2.1, i32 1
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%c2.arrayidx3 = getelementptr inbounds i8, i8 addrspace(1)* %c2.base, i64 3
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%c2.2 = call i8 @llvm.genx.GenISA.PredicatedLoad.i8.p1i8.i8(i8 addrspace(1)* %c2.arrayidx3, i64 1, i1 true, i8 5)
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%c2.v.0 = insertelement <4 x i8> undef, i8 %c2.0, i32 0
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%c2.v.1 = insertelement <4 x i8> %c2.v.0, i8 %c2.1.0, i32 1
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%c2.v.2 = insertelement <4 x i8> %c2.v.1, i8 %c2.1.1, i32 2
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%c2.v.3 = insertelement <4 x i8> %c2.v.2, i8 %c2.2, i32 3
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%c2.dst = getelementptr inbounds <4 x i8>, <4 x i8> addrspace(1)* %result, i64 4
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store <4 x i8> %c2.v.3, <4 x i8> addrspace(1)* %c2.dst, align 4
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; case 3 : [ <2 x i8> <2 x i8> ] --> i32
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; handle shufflevector
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; CHECK-LABEL: c3.base
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; CHECK: [[T3_0:%.*]] = call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1.i32(ptr addrspace(1) %{{.*}}, i32 84148994)
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; CHECK: {{.*}} = bitcast i32 [[T3_0]] to <4 x i8>
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; CHECK: ret void
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%c3.base = getelementptr inbounds i8, i8 addrspace(1)* %src, i64 48
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%c3.base.0 = bitcast i8 addrspace(1)* %c3.base to <2 x i8> addrspace(1)*
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%c3.arrayidx1 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(1)* %c3.base.0, i64 0
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%c3.0 = call <2 x i8> @llvm.genx.GenISA.PredicatedLoad.v2i8.p1v2i8.v2i8(<2 x i8> addrspace(1)* %c3.arrayidx1, i64 1, i1 true, <2 x i8> <i8 2, i8 3>)
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%c3.arrayidx3 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(1)* %c3.base.0, i64 1
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%c3.1 = call <2 x i8> @llvm.genx.GenISA.PredicatedLoad.v2i8.p1v2i8.v2i8(<2 x i8> addrspace(1)* %c3.arrayidx3, i64 1, i1 true, <2 x i8> <i8 4, i8 5>)
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%c3.v = shufflevector <2 x i8> %c3.0, <2 x i8> %c3.1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%c3.dst = getelementptr inbounds <4 x i8>, <4 x i8> addrspace(1)* %result, i64 10
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store <4 x i8> %c3.v, <4 x i8> addrspace(1)* %c3.dst, align 4
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ret void
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}
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; Function Attrs: nounwind readonly
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declare i8 @llvm.genx.GenISA.PredicatedLoad.i8.p1i8.i8(i8 addrspace(1)*, i64, i1, i8) #1
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; Function Attrs: nounwind readonly
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declare <2 x i8> @llvm.genx.GenISA.PredicatedLoad.v2i8.p1v2i8.v2i8(<2 x i8> addrspace(1)*, i64, i1, <2 x i8>) #1
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attributes #0 = { convergent nounwind "less-precise-fpmad"="true" "null-pointer-is-valid"="true" }
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attributes #1 = { nounwind readonly }

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