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KanclerzPiotrpszymich
KanclerzPiotr
authored and
pszymich
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Legalize LLVM min/max intrinsics
Legalize other integral sizes for LLVM smin/smax intrinsics (cherry picked from commit a0d0be2)
1 parent f3bcfa2 commit 8044f62

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11 files changed

+236
-127
lines changed

11 files changed

+236
-127
lines changed

‎IGC/Compiler/Legalizer/InstLegalChecker.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*========================== begin_copyright_notice ============================
22
3-
Copyright (C) 2017-2021 Intel Corporation
3+
Copyright (C) 2017-2025 Intel Corporation
44
55
SPDX-License-Identifier: MIT
66
@@ -11,6 +11,7 @@ SPDX-License-Identifier: MIT
1111
#include "common/LLVMWarningsPush.hpp"
1212
#include "llvm/Config/llvm-config.h"
1313
#include "llvm/Support/Debug.h"
14+
#include <llvm/IR/Intrinsics.h>
1415
#include "llvmWrapper/IR/Instructions.h"
1516
#include "common/LLVMWarningsPop.hpp"
1617
#include "Probe/Assertion.h"
@@ -164,6 +165,10 @@ LegalizeAction InstLegalChecker::visitIntrinsicInst(IntrinsicInst& I) {
164165
// case Intrinsic::round:
165166
return TL->getTypeLegalizeAction(I.getType());
166167
// Intrinsics on integer are legal iff their result types are legal.
168+
case Intrinsic::umax:
169+
case Intrinsic::umin:
170+
case Intrinsic::smax:
171+
case Intrinsic::smin:
167172
case Intrinsic::bswap:
168173
case Intrinsic::ctpop:
169174
case Intrinsic::ctlz:

‎IGC/Compiler/Legalizer/InstLegalChecker.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*========================== begin_copyright_notice ============================
22
3-
Copyright (C) 2017-2021 Intel Corporation
3+
Copyright (C) 2017-2025 Intel Corporation
44
55
SPDX-License-Identifier: MIT
66

‎IGC/Compiler/Legalizer/InstPromoter.cpp

Lines changed: 38 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*========================== begin_copyright_notice ============================
22
3-
Copyright (C) 2017-2021 Intel Corporation
3+
Copyright (C) 2017-2025 Intel Corporation
44
55
SPDX-License-Identifier: MIT
66
@@ -14,6 +14,7 @@ SPDX-License-Identifier: MIT
1414
#include "llvmWrapper/IR/DerivedTypes.h"
1515
#include "llvm/IR/Dominators.h"
1616
#include "llvm/Transforms/Utils/Local.h"
17+
#include <llvm/IR/Intrinsics.h>
1718
#include "common/LLVMWarningsPop.hpp"
1819
#include "Probe/Assertion.h"
1920

@@ -664,31 +665,53 @@ bool InstPromoter::visitGenIntrinsicInst(GenIntrinsicInst& I) {
664665
return false;
665666
}
666667

667-
bool InstPromoter::visitLLVMIntrinsicInst(IntrinsicInst& I) {
668-
switch (I.getIntrinsicID()) {
669-
case Intrinsic::bitreverse: {
670-
auto [ValSeq, ValAct] = TL->getLegalizedValues(I.getOperand(0));
671-
672-
Value* Val = I.getOperand(0);
668+
std::pair<Value*, Type*>
669+
InstPromoter::preparePromotedIntrinsicInst(IntrinsicInst& I)
670+
{
671+
SmallVector<Value*, 2> PromotedArgs;
672+
// -1 because we want to avoid the last operand which is intrinsic declaration
673+
for (unsigned i = 0; i < I.getNumOperands() - 1; i++) {
674+
auto [ValSeq, ValAct] = TL->getLegalizedValues(I.getOperand(i));
675+
Value* Val = I.getOperand(i);
673676
if (ValAct != Legal)
674677
Val = ValSeq->front();
678+
PromotedArgs.push_back(Val);
679+
}
675680

676-
auto [TySeq, Act] = TL->getLegalizedTypes(I.getType());
677-
IGC_ASSERT(Act == Promote);
678-
IGC_ASSERT(TySeq->size() == 1);
679-
Type* PromotedTy = TySeq->front();
680-
unsigned PromotedBitWidth = cast<IntegerType>(PromotedTy->getScalarType())->getBitWidth();
681+
auto [TySeq, Act] = TL->getLegalizedTypes(I.getType());
682+
IGC_ASSERT(Act == Promote);
683+
IGC_ASSERT(TySeq->size() == 1);
684+
Type* PromotedTy = TySeq->front();
685+
686+
687+
unsigned PromotedBitWidth = cast<IntegerType>(PromotedTy->getScalarType())->getBitWidth();
688+
for(Value* Val : PromotedArgs) {
681689
unsigned ValBitWidth = cast<IntegerType>(Val->getType()->getScalarType())->getBitWidth();
682690
IGC_ASSERT(PromotedBitWidth == ValBitWidth);
691+
}
692+
693+
Function* Func = Intrinsic::getDeclaration(I.getModule(), I.getIntrinsicID(), PromotedTy);
694+
return {IRB->CreateCall(Func, PromotedArgs), PromotedTy};
695+
}
696+
683697

684-
Function* Func = Intrinsic::getDeclaration(I.getModule(), I.getIntrinsicID(), PromotedTy);
685-
Value* Call = IRB->CreateCall(Func, Val);
698+
bool InstPromoter::visitLLVMIntrinsicInst(IntrinsicInst& I) {
699+
switch (I.getIntrinsicID()) {
700+
case Intrinsic::bitreverse: {
701+
auto [Call, PromotedTy] = preparePromotedIntrinsicInst(I);
702+
unsigned PromotedBitWidth = cast<IntegerType>(PromotedTy->getScalarType())->getBitWidth();
686703
unsigned shift = PromotedBitWidth
687704
- cast<IntegerType>(I.getType()->getScalarType())->getBitWidth();
688705
IGC_ASSERT(shift > 0);
689706
Promoted = IRB->CreateLShr(Call, shift);
707+
break;
690708
}
691-
break;
709+
case Intrinsic::smin:
710+
case Intrinsic::smax:
711+
case Intrinsic::umin:
712+
case Intrinsic::umax:
713+
Promoted = preparePromotedIntrinsicInst(I).first;
714+
break;
692715
default:
693716
IGC_ASSERT_EXIT_MESSAGE(0, "UNKNOWN INSTRINSIC INSTRUCTION IS BEING PROMOTED!");
694717
}

‎IGC/Compiler/Legalizer/InstPromoter.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*========================== begin_copyright_notice ============================
22
3-
Copyright (C) 2017-2021 Intel Corporation
3+
Copyright (C) 2017-2025 Intel Corporation
44
55
SPDX-License-Identifier: MIT
66
@@ -36,6 +36,7 @@ namespace IGC {
3636
const char* getSuffix() const { return TL->getSuffix(Promote); }
3737
Value* getSinglePromotedValueIfExist(Value* OriginalValue);
3838
Type* getSinglePromotedTypeIfExist(Type* OriginalType);
39+
std::pair<Value*, Type*> preparePromotedIntrinsicInst(IntrinsicInst& I);
3940

4041
private:
4142
// By default, capture all missing instructions!

‎IGC/Compiler/tests/DebugInfo/Legalization/fcmp-nan-typed-pointers.ll

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
;=========================== begin_copyright_notice ============================
22
;
3-
; Copyright (C) 2022-2024 Intel Corporation
3+
; Copyright (C) 2022-2025 Intel Corporation
44
;
55
; SPDX-License-Identifier: MIT
66
;
@@ -24,9 +24,9 @@ define spir_kernel void @test_fcmp(float %src1, float %src2) !dbg !7 {
2424

2525
; Testcase 1
2626
; cmp ord to and(oeq,oeq)
27-
; CHECK: [[FCMP_OEQ2:%[0-9]*]] = fcmp oeq float %src2, %src2
28-
; CHECK-NEXT: [[FCMP_OEQ1:%[0-9]*]] = fcmp oeq float %src1, %src1
29-
; CHECK-NEXT: [[FCMP_ORD_V:%[0-9]*]] = and i1 [[FCMP_OEQ1]], [[FCMP_OEQ2]], !dbg [[FCMP_ORD_LOC:![0-9]*]]
27+
; CHECK-DAG: [[FCMP_OEQ2:%[0-9]*]] = fcmp oeq float %src2, %src2
28+
; CHECK-DAG: [[FCMP_OEQ1:%[0-9]*]] = fcmp oeq float %src1, %src1
29+
; CHECK: [[FCMP_ORD_V:%[0-9]*]] = and i1 [[FCMP_OEQ1]], [[FCMP_OEQ2]], !dbg [[FCMP_ORD_LOC:![0-9]*]]
3030
; CHECK-NEXT: [[DBG_VALUE_CALL:dbg.value\(metadata]] i1 [[FCMP_ORD_V]], metadata [[FCMP_ORD_MD:![0-9]*]], metadata !DIExpression()), !dbg [[FCMP_ORD_LOC]]
3131
; CHECK-NEXT: [[ZEXT_ORD_V:%[0-9]*]] = zext i1 [[FCMP_ORD_V]] to i32, !dbg [[ZEXT_ORD_LOC:![0-9]*]]
3232
; CHECK-NEXT: [[DBG_VALUE_CALL]] i32 [[ZEXT_ORD_V]], metadata [[ZEXT_ORD_MD:![0-9]*]], metadata !DIExpression()), !dbg [[ZEXT_ORD_LOC]]
@@ -38,9 +38,9 @@ define spir_kernel void @test_fcmp(float %src1, float %src2) !dbg !7 {
3838

3939
; Testcase 2
4040
; cmp uno to or(une,une)
41-
; CHECK-NEXT: [[FCMP_UNE1:%[0-9]*]] = fcmp une float %src1, %src1
42-
; CHECK-NEXT: [[FCMP_UNE2:%[0-9]*]] = fcmp une float %src2, %src2
43-
; CHECK-NEXT: [[FCMP_UNO_V:%[0-9]*]] = or i1 [[FCMP_UNE1]], [[FCMP_UNE2]], !dbg [[FCMP_UNO_LOC:![0-9]*]]
41+
; CHECK-DAG: [[FCMP_UNE1:%[0-9]*]] = fcmp une float %src1, %src1
42+
; CHECK-DAG: [[FCMP_UNE2:%[0-9]*]] = fcmp une float %src2, %src2
43+
; CHECK: [[FCMP_UNO_V:%[0-9]*]] = or i1 [[FCMP_UNE1]], [[FCMP_UNE2]], !dbg [[FCMP_UNO_LOC:![0-9]*]]
4444
; CHECK-NEXT: [[DBG_VALUE_CALL:dbg.value\(metadata]] i1 [[FCMP_UNO_V]], metadata [[FCMP_UNO_MD:![0-9]*]], metadata !DIExpression()), !dbg [[FCMP_UNO_LOC]]
4545
; CHECK-NEXT: [[ZEXT_UNO_V:%[0-9]*]] = zext i1 [[FCMP_UNO_V]] to i32, !dbg [[ZEXT_UNO_LOC:![0-9]*]]
4646
; CHECK-NEXT: [[DBG_VALUE_CALL]] i32 [[ZEXT_UNO_V]], metadata [[ZEXT_UNO_MD:![0-9]*]], metadata !DIExpression()), !dbg [[ZEXT_UNO_LOC]]
@@ -53,9 +53,9 @@ define spir_kernel void @test_fcmp(float %src1, float %src2) !dbg !7 {
5353
; Testcase 3
5454
; cmp one to and(une, and(oeq,oeq))
5555

56-
; CHECK-NEXT: [[FCMP_OEQ2:%[0-9]*]] = fcmp oeq float %src2, %src2
57-
; CHECK-NEXT: [[FCMP_OEQ1:%[0-9]*]] = fcmp oeq float %src1, %src1
58-
; CHECK-NEXT: [[FCMP_ORD_V:%[0-9]*]] = and i1 [[FCMP_OEQ1]], [[FCMP_OEQ2]]
56+
; CHECK-DAG: [[FCMP_OEQ2:%[0-9]*]] = fcmp oeq float %src2, %src2
57+
; CHECK-DAG: [[FCMP_OEQ1:%[0-9]*]] = fcmp oeq float %src1, %src1
58+
; CHECK: [[FCMP_ORD_V:%[0-9]*]] = and i1 [[FCMP_OEQ1]], [[FCMP_OEQ2]]
5959
; CHECK-NEXT: [[FCMP_UNE_V:%[0-9]*]] = fcmp une float %src1, %src2
6060
; CHECK-NEXT: [[FCMP_ONE_V:%[0-9]*]] = and i1 [[FCMP_ORD_V]], [[FCMP_UNE_V]], !dbg [[FCMP_ONE_LOC:![0-9]*]]
6161
; CHECK-NEXT: [[DBG_VALUE_CALL:dbg.value\(metadata]] i1 [[FCMP_ONE_V]], metadata [[FCMP_ONE_MD:![0-9]*]], metadata !DIExpression()), !dbg [[FCMP_ONE_LOC]]
@@ -69,9 +69,9 @@ define spir_kernel void @test_fcmp(float %src1, float %src2) !dbg !7 {
6969

7070
; Testcase 4
7171
; cmp ueq to or(oeq, or(une,une))
72-
; CHECK-NEXT: [[FCMP_UNE1:%[0-9]*]] = fcmp une float %src1, %src1
73-
; CHECK-NEXT: [[FCMP_UNE2:%[0-9]*]] = fcmp une float %src2, %src2
74-
; CHECK-NEXT: [[FCMP_UNO_V:%[0-9]*]] = or i1 [[FCMP_UNE1]], [[FCMP_UNE2]]
72+
; CHECK-DAG: [[FCMP_UNE1:%[0-9]*]] = fcmp une float %src1, %src1
73+
; CHECK-DAG: [[FCMP_UNE2:%[0-9]*]] = fcmp une float %src2, %src2
74+
; CHECK: [[FCMP_UNO_V:%[0-9]*]] = or i1 [[FCMP_UNE1]], [[FCMP_UNE2]]
7575
; CHECK-NEXT: [[FCMP_OEQ_V:%[0-9]*]] = fcmp oeq float %src1, %src2
7676
; CHECK-NEXT: [[FCMP_UEQ_V:%[0-9]*]] = or i1 [[FCMP_UNO_V]], [[FCMP_OEQ_V]], !dbg [[FCMP_UEQ_LOC:![0-9]*]]
7777
; CHECK-NEXT: [[DBG_VALUE_CALL:dbg.value\(metadata]] i1 [[FCMP_UEQ_V]], metadata [[FCMP_UEQ_MD:![0-9]*]], metadata !DIExpression()), !dbg [[FCMP_UEQ_LOC]]

‎IGC/Compiler/tests/DebugInfo/Legalization/fcmp-nan.ll

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
;=========================== begin_copyright_notice ============================
22
;
3-
; Copyright (C) 2022-2024 Intel Corporation
3+
; Copyright (C) 2022-2025 Intel Corporation
44
;
55
; SPDX-License-Identifier: MIT
66
;
@@ -26,9 +26,9 @@ define spir_kernel void @test_fcmp(float %src1, float %src2) !dbg !7 {
2626

2727
; Testcase 1
2828
; cmp ord to and(oeq,oeq)
29-
; CHECK: [[FCMP_OEQ2:%[0-9]*]] = fcmp oeq float %src2, %src2
30-
; CHECK-NEXT: [[FCMP_OEQ1:%[0-9]*]] = fcmp oeq float %src1, %src1
31-
; CHECK-NEXT: [[FCMP_ORD_V:%[0-9]*]] = and i1 [[FCMP_OEQ1]], [[FCMP_OEQ2]], !dbg [[FCMP_ORD_LOC:![0-9]*]]
29+
; CHECK-DAG: [[FCMP_OEQ2:%[0-9]*]] = fcmp oeq float %src2, %src2
30+
; CHECK-DAG: [[FCMP_OEQ1:%[0-9]*]] = fcmp oeq float %src1, %src1
31+
; CHECK: [[FCMP_ORD_V:%[0-9]*]] = and i1 [[FCMP_OEQ1]], [[FCMP_OEQ2]], !dbg [[FCMP_ORD_LOC:![0-9]*]]
3232
; CHECK-NEXT: [[DBG_VALUE_CALL:dbg.value\(metadata]] i1 [[FCMP_ORD_V]], metadata [[FCMP_ORD_MD:![0-9]*]], metadata !DIExpression()), !dbg [[FCMP_ORD_LOC]]
3333
; CHECK-NEXT: [[ZEXT_ORD_V:%[0-9]*]] = zext i1 [[FCMP_ORD_V]] to i32, !dbg [[ZEXT_ORD_LOC:![0-9]*]]
3434
; CHECK-NEXT: [[DBG_VALUE_CALL]] i32 [[ZEXT_ORD_V]], metadata [[ZEXT_ORD_MD:![0-9]*]], metadata !DIExpression()), !dbg [[ZEXT_ORD_LOC]]
@@ -40,9 +40,9 @@ define spir_kernel void @test_fcmp(float %src1, float %src2) !dbg !7 {
4040

4141
; Testcase 2
4242
; cmp uno to or(une,une)
43-
; CHECK-NEXT: [[FCMP_UNE1:%[0-9]*]] = fcmp une float %src1, %src1
44-
; CHECK-NEXT: [[FCMP_UNE2:%[0-9]*]] = fcmp une float %src2, %src2
45-
; CHECK-NEXT: [[FCMP_UNO_V:%[0-9]*]] = or i1 [[FCMP_UNE1]], [[FCMP_UNE2]], !dbg [[FCMP_UNO_LOC:![0-9]*]]
43+
; CHECK-DAG: [[FCMP_UNE1:%[0-9]*]] = fcmp une float %src1, %src1
44+
; CHECK-DAG: [[FCMP_UNE2:%[0-9]*]] = fcmp une float %src2, %src2
45+
; CHECK: [[FCMP_UNO_V:%[0-9]*]] = or i1 [[FCMP_UNE1]], [[FCMP_UNE2]], !dbg [[FCMP_UNO_LOC:![0-9]*]]
4646
; CHECK-NEXT: [[DBG_VALUE_CALL:dbg.value\(metadata]] i1 [[FCMP_UNO_V]], metadata [[FCMP_UNO_MD:![0-9]*]], metadata !DIExpression()), !dbg [[FCMP_UNO_LOC]]
4747
; CHECK-NEXT: [[ZEXT_UNO_V:%[0-9]*]] = zext i1 [[FCMP_UNO_V]] to i32, !dbg [[ZEXT_UNO_LOC:![0-9]*]]
4848
; CHECK-NEXT: [[DBG_VALUE_CALL]] i32 [[ZEXT_UNO_V]], metadata [[ZEXT_UNO_MD:![0-9]*]], metadata !DIExpression()), !dbg [[ZEXT_UNO_LOC]]
@@ -55,9 +55,9 @@ define spir_kernel void @test_fcmp(float %src1, float %src2) !dbg !7 {
5555
; Testcase 3
5656
; cmp one to and(une, and(oeq,oeq))
5757

58-
; CHECK-NEXT: [[FCMP_OEQ2:%[0-9]*]] = fcmp oeq float %src2, %src2
59-
; CHECK-NEXT: [[FCMP_OEQ1:%[0-9]*]] = fcmp oeq float %src1, %src1
60-
; CHECK-NEXT: [[FCMP_ORD_V:%[0-9]*]] = and i1 [[FCMP_OEQ1]], [[FCMP_OEQ2]]
58+
; CHECK-DAG: [[FCMP_OEQ2:%[0-9]*]] = fcmp oeq float %src2, %src2
59+
; CHECK-DAG: [[FCMP_OEQ1:%[0-9]*]] = fcmp oeq float %src1, %src1
60+
; CHECK: [[FCMP_ORD_V:%[0-9]*]] = and i1 [[FCMP_OEQ1]], [[FCMP_OEQ2]]
6161
; CHECK-NEXT: [[FCMP_UNE_V:%[0-9]*]] = fcmp une float %src1, %src2
6262
; CHECK-NEXT: [[FCMP_ONE_V:%[0-9]*]] = and i1 [[FCMP_ORD_V]], [[FCMP_UNE_V]], !dbg [[FCMP_ONE_LOC:![0-9]*]]
6363
; CHECK-NEXT: [[DBG_VALUE_CALL:dbg.value\(metadata]] i1 [[FCMP_ONE_V]], metadata [[FCMP_ONE_MD:![0-9]*]], metadata !DIExpression()), !dbg [[FCMP_ONE_LOC]]
@@ -71,9 +71,9 @@ define spir_kernel void @test_fcmp(float %src1, float %src2) !dbg !7 {
7171

7272
; Testcase 4
7373
; cmp ueq to or(oeq, or(une,une))
74-
; CHECK-NEXT: [[FCMP_UNE1:%[0-9]*]] = fcmp une float %src1, %src1
75-
; CHECK-NEXT: [[FCMP_UNE2:%[0-9]*]] = fcmp une float %src2, %src2
76-
; CHECK-NEXT: [[FCMP_UNO_V:%[0-9]*]] = or i1 [[FCMP_UNE1]], [[FCMP_UNE2]]
74+
; CHECK-DAG: [[FCMP_UNE1:%[0-9]*]] = fcmp une float %src1, %src1
75+
; CHECK-DAG: [[FCMP_UNE2:%[0-9]*]] = fcmp une float %src2, %src2
76+
; CHECK: [[FCMP_UNO_V:%[0-9]*]] = or i1 [[FCMP_UNE1]], [[FCMP_UNE2]]
7777
; CHECK-NEXT: [[FCMP_OEQ_V:%[0-9]*]] = fcmp oeq float %src1, %src2
7878
; CHECK-NEXT: [[FCMP_UEQ_V:%[0-9]*]] = or i1 [[FCMP_UNO_V]], [[FCMP_OEQ_V]], !dbg [[FCMP_UEQ_LOC:![0-9]*]]
7979
; CHECK-NEXT: [[DBG_VALUE_CALL:dbg.value\(metadata]] i1 [[FCMP_UEQ_V]], metadata [[FCMP_UEQ_MD:![0-9]*]], metadata !DIExpression()), !dbg [[FCMP_UEQ_LOC]]

‎IGC/Compiler/tests/Legalization/fcmp-preserve-nan.ll

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
;=========================== begin_copyright_notice ============================
22
;
3-
; Copyright (C) 2024 Intel Corporation
3+
; Copyright (C) 2024-2025 Intel Corporation
44
;
55
; SPDX-License-Identifier: MIT
66
;
@@ -18,12 +18,12 @@
1818
define i1 @test_fcmp_ueq(float %a, float %b) {
1919
; CHECK-LABEL: define i1 @test_fcmp_ueq(
2020
; CHECK-SAME: float [[A:%.*]], float [[B:%.*]]) {
21-
; CHECK: [[TMP1:%.*]] = fcmp une float [[A]], [[A]]
22-
; CHECK: [[TMP2:%.*]] = fcmp une float [[B]], [[B]]
23-
; CHECK: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
24-
; CHECK: [[TMP4:%.*]] = fcmp oeq float [[A]], [[B]]
25-
; CHECK: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]]
26-
; CHECK: ret i1 [[TMP5]]
21+
; CHECK-DAG: [[TMP1:%.*]] = fcmp une float [[A]], [[A]]
22+
; CHECK-DAG: [[TMP2:%.*]] = fcmp une float [[B]], [[B]]
23+
; CHECK: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
24+
; CHECK: [[TMP4:%.*]] = fcmp oeq float [[A]], [[B]]
25+
; CHECK: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]]
26+
; CHECK: ret i1 [[TMP5]]
2727
;
2828
%1 = fcmp ueq float %a, %b
2929
ret i1 %1
@@ -94,12 +94,12 @@ define i1 @test_fcmp_uno(float %a, float %b) {
9494
define i1 @test_fcmp_one(float %a, float %b) {
9595
; CHECK-LABEL: define i1 @test_fcmp_one(
9696
; CHECK-SAME: float [[A:%.*]], float [[B:%.*]]) {
97-
; CHECK: [[TMP1:%.*]] = fcmp oeq float [[B]], [[B]]
98-
; CHECK: [[TMP2:%.*]] = fcmp oeq float [[A]], [[A]]
99-
; CHECK: [[TMP3:%.*]] = and i1 [[TMP2]], [[TMP1]]
100-
; CHECK: [[TMP4:%.*]] = fcmp une float [[A]], [[B]]
101-
; CHECK: [[TMP5:%.*]] = and i1 [[TMP3]], [[TMP4]]
102-
; CHECK: ret i1 [[TMP5]]
97+
; CHECK-DAG: [[TMP1:%.*]] = fcmp oeq float [[B]], [[B]]
98+
; CHECK-DAG: [[TMP2:%.*]] = fcmp oeq float [[A]], [[A]]
99+
; CHECK: [[TMP3:%.*]] = and i1 [[TMP2]], [[TMP1]]
100+
; CHECK: [[TMP4:%.*]] = fcmp une float [[A]], [[B]]
101+
; CHECK: [[TMP5:%.*]] = and i1 [[TMP3]], [[TMP4]]
102+
; CHECK: ret i1 [[TMP5]]
103103
;
104104
%1 = fcmp one float %a, %b
105105
ret i1 %1
@@ -109,10 +109,10 @@ define i1 @test_fcmp_one(float %a, float %b) {
109109
define i1 @test_fcmp_ord(float %a, float %b) {
110110
; CHECK-LABEL: define i1 @test_fcmp_ord(
111111
; CHECK-SAME: float [[A:%.*]], float [[B:%.*]]) {
112-
; CHECK: [[TMP1:%.*]] = fcmp oeq float [[B]], [[B]]
113-
; CHECK: [[TMP2:%.*]] = fcmp oeq float [[A]], [[A]]
114-
; CHECK: [[TMP3:%.*]] = and i1 [[TMP2]], [[TMP1]]
115-
; CHECK: ret i1 [[TMP3]]
112+
; CHECK-DAG: [[TMP1:%.*]] = fcmp oeq float [[B]], [[B]]
113+
; CHECK-DAG: [[TMP2:%.*]] = fcmp oeq float [[A]], [[A]]
114+
; CHECK: [[TMP3:%.*]] = and i1 [[TMP2]], [[TMP1]]
115+
; CHECK: ret i1 [[TMP3]]
116116
;
117117
%1 = fcmp ord float %a, %b
118118
ret i1 %1

‎IGC/Compiler/tests/MinimumValidAddressChecking/generic-address-space.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
;=========================== begin_copyright_notice ============================
22
;
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; Copyright (C) 2024 Intel Corporation
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; Copyright (C) 2024-2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
@@ -31,9 +31,9 @@ define spir_kernel void @kernel(ptr addrspace(1) %input) nounwind {
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; CHECK-NEXT: [[IS_GENERIC_GLOBAL:%[0-9]+]] = or i1 [[IS_ADDRESS_SPACE_TAG_0]], [[IS_ADDRESS_SPACE_TAG_7]]
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; CHECK-NEXT: [[CLEARING_TAG_TMP:%[0-9]+]] = shl i64 [[ADDRESS]], 4
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; CHECK-NEXT: [[ADDRESS_WITHOUT_ADDRESS_SPACE_TAG:%[0-9]+]] = ashr i64 [[CLEARING_TAG_TMP]], 4
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; CHECK-NEXT: [[IS_ADDRESS_IN_VALID_REGION:%[0-9]+]] = icmp uge i64 [[ADDRESS_WITHOUT_ADDRESS_SPACE_TAG]], {{[0-9]+}}
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; CHECK-NEXT: [[IS_NOT_GENERIC_GLOBAL:%[0-9]+]] = xor i1 [[IS_GENERIC_GLOBAL]], true
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; CHECK-NEXT: [[IS_VALID_ADDRESS:%[0-9]+]] = or i1 [[IS_NOT_GENERIC_GLOBAL]], [[IS_ADDRESS_IN_VALID_REGION]]
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; CHECK-DAG: [[IS_ADDRESS_IN_VALID_REGION:%[0-9]+]] = icmp uge i64 [[ADDRESS_WITHOUT_ADDRESS_SPACE_TAG]], {{[0-9]+}}
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; CHECK-DAG: [[IS_NOT_GENERIC_GLOBAL:%[0-9]+]] = xor i1 [[IS_GENERIC_GLOBAL]], true
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; CHECK: [[IS_VALID_ADDRESS:%[0-9]+]] = or i1 [[IS_NOT_GENERIC_GLOBAL]], [[IS_ADDRESS_IN_VALID_REGION]]
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; CHECK-NEXT: br i1 [[IS_VALID_ADDRESS]], label %minimumvalidaddresschecking.valid, label %minimumvalidaddresschecking.invalid
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; CHECK: minimumvalidaddresschecking.valid:

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