Handle inline asm in vector alias

 1. Improve vector alias optim to handle inline asm
 2. Allow constant insert elements

Author: jgu222

IGC/Compiler/CISACodeGen/DeSSA.cpp

@@ -1542,7 +1542,7 @@ bool DeSSA::isAliasee(Value *V) const {
 //      c = 2
 //      ...
 //   L:   = a
-//        = b
+//        = c
 //
 //  In this case, if a is aliased to b, a would get 2 at L, but the correct
 //  value should be 1. In order to find out if a can be aliased to b, it

IGC/Compiler/CISACodeGen/VariableReuseAnalysis.cpp

@@ -581,7 +581,7 @@ void VariableReuseAnalysis::visitExtractElementInst(ExtractElementInst &I) {
   // Valid vec alias and add it into alias map
   addVecAlias(EEI_nv, vec_nv, vecVal, iIdx);
 
-  // Mark this inst as noop inst
+  // Mark this inst as no-op inst
   m_HasBecomeNoopInsts[EEI] = 1;
 }
 
@@ -657,9 +657,13 @@ void VariableReuseAnalysis::printAlias(raw_ostream &OS, const Function *F) const
     for (auto VI : BV->Aliasers) {
       SSubVecDesc *aSV = VI;
       Value *aliaser = aSV->Aliaser;
+      bool HasBeenNoop = false;
+      if (Instruction *AliaserInst = dyn_cast<Instruction>(aliaser))
+        HasBeenNoop = (m_HasBecomeNoopInsts.count(AliaserInst) > 0);
       bool isSinglVal = m_DeSSA ? m_DeSSA->isSingleValued(aliaser) : true;
+      const char *Noop = HasBeenNoop ? " [no-op]" : " ";
       const char *inCC = !isSinglVal ? ".inDessaCC" : "";
-      OS << "    " << *aliaser << "  [" << aSV->StartElementOffset << "]" << inCC << "\n";
+      OS << "    " << *aliaser << "  [" << aSV->StartElementOffset << "]" << inCC << Noop << "\n";
     }
     OS << "\n";
   }
@@ -887,16 +891,16 @@ bool VariableReuseAnalysis::getAllInsEltsIfAvailable(InsertElementInst *FirstIEI
     IGC_ASSERT_MESSAGE(IEI_ix < nelts, "ICE: IEI's index out of bound!");
     SVecInsEltInfo &InsEltInfo = AllIEIs[IEI_ix];
     if (InsEltInfo.IEI) {
-      // One element is inserted more than once, skip.
+      // This element is inserted more than once, skip.
       return false;
     }
     InsEltInfo.IEI = I;
     InsEltInfo.Elt = E;
     InsEltInfo.FromVec = V;
     InsEltInfo.FromVec_eltIx = V_ix;
-    if (E) {
-      InsEltInfo.EEI = dyn_cast<ExtractElementInst>(E);
-    }
+
+    // So far, E is never nullptr (could be in the future)
+    InsEltInfo.EEI = dyn_cast_or_null<ExtractElementInst>(E);
 
     if (!I->hasOneUse()) {
       break;
@@ -923,19 +927,26 @@ bool VariableReuseAnalysis::getAllInsEltsIfAvailable(InsertElementInst *FirstIEI
     if (tV == nullptr)
       return false;
 
-    // Expect node values for all IEIs are identical. In general, if they
-    // are in the same DeSSA CC, that would be fine.
+    // Expect all IEIs are in the same DeSSA CC (DeSSA special-handles IEIs)
     Value *tV_nv = m_DeSSA->getNodeValue(tV);
     if (V_root != getRootValue(tV_nv))
       return false;
 
     Value *E = AllIEIs[i].Elt;
+    if (!E || isa<Constant>(E)) {
+      // constant is okay for either non-uniform or uniform.
+      // (Note: if any E is constant, this chain of IEI cannot be
+      //  a sub-vector of another larger vector).
+      continue;
+    }
     Value *FromVec = AllIEIs[i].FromVec;
-    Value *FromVec_nv = m_DeSSA->getNodeValue(FromVec);
-    // check if FromVec has been coalesced with IEI already by DeSSA.
-    // (Wouldn't happen under current DeSSA, but might happen in future)
-    if (V_root == getRootValue(FromVec_nv))
-      return false;
+    if (FromVec) {
+      Value *FromVec_nv = m_DeSSA->getNodeValue(FromVec);
+      // check if FromVec has been coalesced with IEI already by DeSSA.
+      // (Wouldn't happen under current DeSSA, but might happen in future)
+      if (V_root == getRootValue(FromVec_nv))
+        return false;
+    }
 
     // Make sure FromVec or E have the same uniformness as V.
     if ((E && V_dep != m_WIA->whichDepend(E)) || (FromVec && V_dep != m_WIA->whichDepend(FromVec)))
@@ -946,7 +957,7 @@ bool VariableReuseAnalysis::getAllInsEltsIfAvailable(InsertElementInst *FirstIEI
 
 Value *VariableReuseAnalysis::traceAliasValue(Value *V) {
   if (CastInst *CastI = dyn_cast_or_null<CastInst>(V)) {
-    // Only handle Noop cast inst. For example,
+    // Only handle no-op cast inst. For example,
     //    dst = bitcast <3 x i32> src to <3 x float>,
     // it is okay, but the following isn't.
     //    dst = bitcast <3 x i64> src to <6 x i32>
@@ -969,17 +980,13 @@ Value *VariableReuseAnalysis::traceAliasValue(Value *V) {
 }
 
 //
-// Returns true if the following is true
+// Returns true if there is the following pattern; otherwise return false.
 //     IEI = insertElement  <vectorType> Vec,  S,  <constant IEI_ix>
-// Return false, otherwise.
-//
-// When the above condition is true, V and V_ix are used for the
-// following cases:
-//     1. S is from another vector V.
-//        S = extractElement <vectorType> V, <constant V_ix>
-//        S is the element denoted by (V, V_ix)
-//     2. otherwise, V=nullptr, V_ix=0.
-//        S is a candidate inserted and could be alias to the vector.
+//   1. S is from another vector V.
+//      S = extractElement <vectorType> V, <constant V_ix>
+//      In this case, S is the element denoted by (V, V_ix)
+//   2. otherwise, V=nullptr, V_ix=0.
+//      S is some value other than a vector element.
 //
 //  Input: IEI
 //  Output: IEI_ix, S, V, V_ix
@@ -999,9 +1006,9 @@ bool VariableReuseAnalysis::getElementValue(InsertElementInst *IEI, int &IEI_ix,
   IEI_ix = (int)CI->getZExtValue();
 
   Value *elem0 = IEI->getOperand(1);
-  if (hasBeenPayloadCoalesced(elem0) || isa<Constant>(elem0) || isOrCoalescedWithArg(elem0)) {
-    // If elem0 has been payload-coalesced, is constant,
-    // or it has been aliased to an argument, skip it.
+  if (hasBeenPayloadCoalesced(elem0) || isOrCoalescedWithArg(elem0)) {
+    // If elem0 has been payload-coalesced or it has been aliased to
+    // an argument, skip it.
     return false;
   }
 
@@ -1046,11 +1053,10 @@ void VariableReuseAnalysis::InsertElementAliasing(Function *F) {
 
   // IGC Key VectorAlias controls vectorAlias optimiation.
   //
-  // Do it if VectorAlias != 0.
-  // VectorAlias=0x1: subvec aliasing for isolated values
-  // (getRootValue()=null)
-  //            =0x2: subvec aliasing for both isolated and non-isolated
-  //            value)
+  // VectorAlias (also from m_pCtx->getVectorCoalescingControl())
+  //   0x0: disable vector aliasing
+  //   0x1: subvec aliasing for isolated values (getRootValue()=null)
+  //   0x2: subvec aliasing for both isolated and non-isolated value)
   const auto control = (m_pCtx->getVectorCoalescingControl() & 0x3);
   // To avoid increasing GRF pressure, skip if F is too large or not an entry
   const int32_t NumBBThreshold = IGC_GET_FLAG_VALUE(VectorAliasBBThreshold);
@@ -1078,9 +1084,9 @@ void VariableReuseAnalysis::InsertElementAliasing(Function *F) {
       //      In this case, 's' becomes a part of 'b'. In LLVM IR,
       //      there are a chain of extElt and insElt instructions for
       //      doing so.
-      //   2. insertTo: sub-vector is used to create a base vector.
+      //   2. insertTo: small vector is used to create a larger base vector.
       //      For example:
-      //         given sub-vector int4 s0, s1;  int8 vector b is created like:
+      //         given small vector int4 s0, s1;  int8 vector b is created like:
       //           b = (int8) (s0, s1)
       //      In this case,  both s0 and s1 become part of b.
 
@@ -1095,12 +1101,12 @@ void VariableReuseAnalysis::InsertElementAliasing(Function *F) {
         continue;
       }
 
-      // Check if this is an extractFrom pattern, if so, add alias.
+      // Case 1: check if this is an extractFrom pattern, if so, add alias.
       if (processExtractFrom(AllIEIs)) {
         continue;
       }
 
-      // Check if this is an insertTo pattern, if so add alias.
+      // Case 2: check if this is an insertTo pattern, if so add alias.
       if (processInsertTo(BB, AllIEIs)) {
         continue;
       }
@@ -1123,6 +1129,8 @@ bool VariableReuseAnalysis::processExtractFrom(VecInsEltInfoTy &AllIEIs) {
   }
 
   for (int i = 1; i < nelts; ++i) {
+    // If any of AllIEIs[i] has a constant element (IEI's opeand 1), this check
+    // will be true, thus AllIEIs cannot be a sub-vector
     if (AllIEIs[i].FromVec != BaseVec || AllIEIs[i].FromVec_eltIx != (BaseStartIx + i))
       return false;
   }
@@ -1187,9 +1195,9 @@ bool VariableReuseAnalysis::processExtractFrom(VecInsEltInfoTy &AllIEIs) {
   // add alias
   addVecAlias(Sub_nv, Base_nv, BaseVec, BaseStartIx, BaseAlign);
 
-  // Make sure noop insts are in the map so they won't be emitted later.
+  // Make sure no-op insts are in the map so they won't be emitted later.
   for (int i = 0, sz = nelts; i < sz; ++i) {
-    // IEI chain is coalesced by DeSSA, so it's safe to mark it as noop
+    // IEI chain is coalesced by DeSSA, so it's safe to mark it as no-op
     InsertElementInst *IEI = AllIEIs[i].IEI;
     if (!m_DeSSA->isNoopAliaser(IEI)) {
       m_HasBecomeNoopInsts[IEI] = 1;
@@ -1198,7 +1206,7 @@ bool VariableReuseAnalysis::processExtractFrom(VecInsEltInfoTy &AllIEIs) {
     ExtractElementInst *EEI = AllIEIs[i].EEI;
     IGC_ASSERT(EEI);
     if (!m_DeSSA->isNoopAliaser(EEI)) {
-      // Set EEI as an aliser, thus it become noop.
+      // Set EEI as an aliser, thus it become no-op.
       Value *EEI_nv = m_DeSSA->getNodeValue(EEI);
       addVecAlias(EEI_nv, Base_nv, BaseVec, AllIEIs[i].FromVec_eltIx, EALIGN_AUTO);
       m_HasBecomeNoopInsts[EEI] = 1;
@@ -1253,9 +1261,22 @@ bool VariableReuseAnalysis::processInsertTo(BasicBlock *BB, VecInsEltInfoTy &All
       isSubCandidate = false;
     }
 
-    if (Elt && Sub == nullptr && skipScalarAliaser(BB, Elt)) {
-      // Skip scalar coalescing
-      isSubCandidate = false;
+    // Check scalar
+    if (isSubCandidate && Elt && Sub == nullptr) {
+      if (isa<Constant>(Elt)) {
+        // Skip as alias is b/w two variables
+        isSubCandidate = false;
+      } else if (Instruction *TmpInst = dyn_cast<Instruction>(Elt)) {
+        // This is to skip inst such as @llvm.genx.GenISA.simdSize(),
+        // which is specially handled during EmitCodeGen
+        if (m_PatternMatch->SIMDConstExpr(TmpInst))
+          isSubCandidate = false;
+      }
+
+      if (isSubCandidate && skipScalarAliaser(BB, Elt)) {
+        // Skip scalar coalescing
+        isSubCandidate = false;
+      }
     }
 
     // If Sub == nullptr or NextSub != Sub, this is the last element
@@ -1329,9 +1350,9 @@ bool VariableReuseAnalysis::processInsertTo(BasicBlock *BB, VecInsEltInfoTy &All
 
     int V_sz = getNumElts(V);
     if (V_sz > 1) {
-      // set up Noop inst map to skip emitting them later.
+      // set up No-op inst map to skip emitting them later.
       for (int j = V_ix, sz = V_ix + V_sz; j < sz; ++j) {
-        // Safe to mark IEI as noop as IEI chain's coalesced by DeSSA
+        // Safe to mark IEI as no-op as its aliaser will set it
         InsertElementInst *IEI = AllIEIs[j].IEI;
         if (!m_DeSSA->isNoopAliaser(IEI)) {
           m_HasBecomeNoopInsts[IEI] = 1;
@@ -1341,15 +1362,15 @@ bool VariableReuseAnalysis::processInsertTo(BasicBlock *BB, VecInsEltInfoTy &All
         IGC_ASSERT(EEI);
         // Sub-vector
         if (!m_DeSSA->isNoopAliaser(EEI)) {
-          // EEI should be in alias map so it can be marked as noop
+          // Safe to set EEI to no-op
           Value *EEI_nv = m_DeSSA->getNodeValue(EEI);
           addVecAlias(EEI_nv, Base_nv, FirstIEI, j);
           m_HasBecomeNoopInsts[EEI] = 1;
         }
       }
     } else {
       // scalar
-      // Safe to mark IEI as noop as IEI chain's coalesced by DeSSA
+      // Safe to mark IEI as no-op
       InsertElementInst *IEI = AllIEIs[V_ix].IEI;
       if (m_DeSSA->isNoopAliaser(IEI))
         continue;
@@ -1433,8 +1454,11 @@ VariableReuseAnalysis::AState VariableReuseAnalysis::getCandidateStateUse(Value
       }
     } else if (StoreInst *SI = dyn_cast<StoreInst>(Val)) {
       retSt = AState::TARGET;
-    } else if (isa<CallInst>(Val)) {
-      return AState::SKIP;
+    } else if (CallInst *CallI = dyn_cast<CallInst>(Val)) {
+      if (CallI->isInlineAsm())
+        retSt = AState::TARGET;
+      else
+        return AState::SKIP;
     }
   }
   return retSt;
@@ -1460,15 +1484,17 @@ VariableReuseAnalysis::AState VariableReuseAnalysis::getCandidateStateDef(Value
     }
   } else if (LoadInst *SI = dyn_cast<LoadInst>(Val)) {
     return AState::TARGET;
-  } else if (isa<CallInst>(Val)) {
+  } else if (CallInst *CallI = dyn_cast<CallInst>(Val)) {
+    if (CallI->isInlineAsm())
+      return AState::TARGET;
     return AState::SKIP;
   }
   return AState::OK;
 }
 
 // Vector alias disables extractMask optimization. This function
 // checks if extractMask optim can be applied. And the caller
-// will decide whether to favor extractMask optimization.
+// will decide whether to favor extractMask optimization or not.
 bool VariableReuseAnalysis::isExtractMaskCandidate(Value *V) const {
   auto BIT = [](int n) { return (uint32_t)(1 << n); };
 

IGC/Compiler/CISACodeGen/VariableReuseAnalysis.hpp

@@ -131,8 +131,8 @@ struct SVecInsEltInfo {
   llvm::InsertElementInst *IEI;
   llvm::Value *Elt;
 
-  // If Elt is null, EEI must not be null. EEI is used as scalar operand
-  // in IEI and is the same as (FromVec, FromVec_eltIx).
+  // EEI, if not nullptr, is used as scalar operand of IEI and is the same as
+  // (FromVec, FromVec_eltIx).
   llvm::ExtractElementInst *EEI;
   llvm::Value *FromVec;
   int FromVec_eltIx;

IGC/Compiler/tests/EmitVISAPass/inline_asm_vectoralias.ll

@@ -0,0 +1,89 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2023 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; To vector alias on inline asm
+
+; REQUIRES: llvm-14-plus, regkeys
+
+; RUN: igc_opt --opaque-pointers --CheckInstrTypes --igc-update-instrtypes-on-run -inputocl --neo \
+; RUN:         -platformpvc -igc-emit-visa -regkey DumpVISAASMToConsole,VectorAlias=1 -simd-mode 16 %s  \
+; RUN: | FileCheck %s
+
+; CHECK-LABEL: .function
+; CHECK: lsc_load_block2d.ugm (M1, 1)  [[INPUT:.*]]:d8.16x8nt  flat[{{.+}}]
+; CHECK: mov (M1_NM, 16) [[OUTPUT:.*]](0,0)<2> [[INPUT]](0,0)<4;1,0>
+; CHECK: mov (M1_NM, 16) [[OUTPUT]](0,1)<2> [[INPUT]](0,1)<4;1,0>
+; CHECK: mov (M1_NM, 16) [[OUTPUT]](1,0)<2> [[INPUT]](0,2)<4;1,0>
+; CHECK: mov (M1_NM, 16) [[OUTPUT]](1,1)<2> [[INPUT]](0,3)<4;1,0>
+; CHECK: mov (M1, 16) [[OUTPUT]](2,0)<1> 0x0:w
+; CHECK: mov (M1, 16) [[OUTPUT]](2,16)<1> 0x0:w
+; CHECK: mov (M1, 16) [[OUTPUT]](3,0)<1> 0x0:w
+; CHECK: mov (M1, 16) [[OUTPUT]](3,16)<1> 0x0:w
+; CHECK: lsc_store_block2d.ugm (M1, 1)  flat[{{.+}}]  [[OUTPUT]]:d16.16x8nn
+; CHECK: ret (M1, 1)
+
+; Function Attrs: convergent nounwind null_pointer_is_valid
+define spir_kernel void @test(i8 addrspace(1)* align 1 %a, i16 addrspace(1)* align 2 %b, <8 x i32> %r0, <8 x i32> %payloadHeader, i8 addrspace(2)* %constBase, i32 %bufferOffset, i32 %bufferOffset1) {
+entry:
+  %0 = call <8 x i8> asm "lsc_load_block2d.ugm (M1, 1) $0:d8.16x8nt flat[$1,15,15,15,0,0]", "=rw,rw.u"(i8 addrspace(1)* %a)
+  %1 = extractelement <8 x i8> %0, i32 0
+  %2 = insertelement <4 x i8> undef, i8 %1, i32 0
+  %3 = extractelement <8 x i8> %0, i32 1
+  %4 = insertelement <4 x i8> %2, i8 %3, i32 1
+  %5 = extractelement <8 x i8> %0, i32 2
+  %6 = insertelement <4 x i8> %4, i8 %5, i32 2
+  %7 = extractelement <8 x i8> %0, i32 3
+  %8 = insertelement <4 x i8> %6, i8 %7, i32 3
+  %9 = call <4 x i16> asm "mov (M1_NM, 16) $0(0,0)<2> $1(0,0)<4;1,0>\0Amov (M1_NM, 16) $0(0,1)<2> $1(0,1)<4;1,0>\0Amov (M1_NM, 16) $0(1,0)<2> $1(0,2)<4;1,0>\0Amov (M1_NM, 16) $0(1,1)<2> $1(0,3)<4;1,0>\0A", "=rw,rw"(<4 x i8> %8)
+  %10 = extractelement <4 x i16> %9, i32 0
+  %11 = extractelement <4 x i16> %9, i32 1
+  %12 = extractelement <4 x i16> %9, i32 2
+  %13 = extractelement <4 x i16> %9, i32 3
+  %14 = insertelement <8 x i16> undef, i16 %10, i32 0
+  %15 = insertelement <8 x i16> %14, i16 %11, i32 1
+  %16 = insertelement <8 x i16> %15, i16 %12, i32 2
+  %17 = insertelement <8 x i16> %16, i16 %13, i32 3
+  %18 = insertelement <8 x i16> %17, i16 0, i32 4
+  %19 = insertelement <8 x i16> %18, i16 0, i32 5
+  %20 = insertelement <8 x i16> %19, i16 0, i32 6
+  %21 = insertelement <8 x i16> %20, i16 0, i32 7
+  call void asm sideeffect "lsc_store_block2d.ugm (M1, 1) flat[$1,15,15,15,0,0] $0:d16.16x8nn", "rw,rw.u"(<8 x i16> %21, i16 addrspace(1)* %b)
+  ret void
+}
+
+
+!igc.functions = !{!0}
+!IGCMetadata = !{!13}
+
+!0 = !{void (i8 addrspace(1)*, i16 addrspace(1)*, <8 x i32>, <8 x i32>, i8 addrspace(2)*, i32, i32)* @test, !1}
+!1 = !{!2, !3}
+!2 = !{!"function_type", i32 0}
+!3 = !{!"sub_group_size", i32 16}
+!13 = !{!"ModuleMD", !14}
+!14 = !{!"FuncMD", !15, !16}
+!15 = !{!"FuncMDMap[0]", void (i8 addrspace(1)*, i16 addrspace(1)*, <8 x i32>, <8 x i32>, i8 addrspace(2)*, i32, i32)* @test}
+!16 = !{!"FuncMDValue[0]", !100, !226}
+!100 = !{!"resAllocMD", !183, !184, !185, !186}
+!183 = !{!"uavsNumType", i32 0}
+!184 = !{!"srvsNumType", i32 0}
+!185 = !{!"samplersNumType", i32 0}
+!186 = !{!"argAllocMDList", !187, !191, !192, !193, !194, !195, !196}
+!187 = !{!"argAllocMDListVec[0]", !188, !189, !190}
+!188 = !{!"type", i32 0}
+!189 = !{!"extensionType", i32 -1}
+!190 = !{!"indexType", i32 -1}
+!191 = !{!"argAllocMDListVec[1]", !188, !189, !190}
+!192 = !{!"argAllocMDListVec[2]", !188, !189, !190}
+!193 = !{!"argAllocMDListVec[3]", !188, !189, !190}
+!194 = !{!"argAllocMDListVec[4]", !188, !189, !190}
+!195 = !{!"argAllocMDListVec[5]", !188, !189, !190}
+!196 = !{!"argAllocMDListVec[6]", !188, !189, !190}
+!226 = !{!"m_OpenCLArgTypeQualifiers", !227, !228}
+!227 = !{!"m_OpenCLArgTypeQualifiersVec[0]", !""}
+!228 = !{!"m_OpenCLArgTypeQualifiersVec[1]", !""}
+