diff --git a/.ci-functions/boards_platforms.sh b/.ci-functions/boards_platforms.sh index efdc40b..ecb796f 100644 --- a/.ci-functions/boards_platforms.sh +++ b/.ci-functions/boards_platforms.sh @@ -5,13 +5,14 @@ declare -a R01=("adl_p" "mec1501_adl_p" "") declare -a R04=("mtl_p" "mec1501_mtl_p" "") declare -a R05=("mtl_s" "mec172x_mtl_s" "") +declare -a R06=("ptl_uh" "mec172x_ptl_uh" "") # Platform (folder name) Board config Additional cfg declare -a S03=("mtlp_mec172x_card" "mec172xmodular_assy6930" "") declare -a SUPPORTED_PLATFORMS=( \ # Regular RVP - "R01" "R04" "R05" \ + "R01" "R04" "R05" "R06" \ # MECC enablement "S03" # Special binaries diff --git a/boards/CMakeLists.txt b/boards/CMakeLists.txt index ec0cacc..1e72257 100644 --- a/boards/CMakeLists.txt +++ b/boards/CMakeLists.txt @@ -48,6 +48,13 @@ target_sources_ifdef(CONFIG_BOARD_MEC172X_MTL_S app ${CMAKE_CURRENT_LIST_DIR}/microchip/mtl_s_mec172x.h ) +target_sources_ifdef(CONFIG_BOARD_MEC172X_PTL_UH app + PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/microchip/ptl_uh_mec172x.c + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/microchip/ptl_uh_mec172x.h + ) + target_include_directories(app PRIVATE ${CMAKE_CURRENT_LIST_DIR} @@ -56,4 +63,4 @@ target_include_directories(app ${CMAKE_CURRENT_LIST_DIR}/microchip/mec172x_mecc ) -endif() +endif() \ No newline at end of file diff --git a/boards/board_config.h b/boards/board_config.h index 651e4a4..de8541a 100644 --- a/boards/board_config.h +++ b/boards/board_config.h @@ -30,6 +30,8 @@ extern uint8_t boot_mode_maf; #include "mtl_template_mec172xlj.h" #elif defined(CONFIG_BOARD_MEC172X_MTL_S) #include "mtl_s_mec172x.h" +#elif defined(CONFIG_BOARD_MEC172X_PTL_UH) +#include "ptl_uh_mec172x.h" #else #error "Platform not supported" #endif /* CONFIG_BOARD_MEC1501MODULAR_ASSY6885 */ diff --git a/boards/mec172x_ptl_uh.conf b/boards/mec172x_ptl_uh.conf new file mode 100644 index 0000000..9aa2198 --- /dev/null +++ b/boards/mec172x_ptl_uh.conf @@ -0,0 +1,36 @@ +# Zephyr-based EC FW + +# EC FW features configuration +# ---------------------------- + +# Enable PS2 device management but only keyboard due SoC port limitation +CONFIG_PS2_KEYBOARD=y +CONFIG_PS2_MOUSE=n + +# EC FW keyscan configuration +CONFIG_KSCAN_EC=y +CONFIG_SOC_DEBUG_CONSENT_GPIO=y + +#Use UART0 for the eSPI communication +#------------------------------------- +CONFIG_ESPI_PERIPHERAL_UART_SOC_MAPPING=0 + +# Support deprecated SMChost commands for backward compatibility +CONFIG_DEPRECATED_SMCHOST_CMD=y + +# Enable gigadevice sequence +CONFIG_SAF_ENABLE_XIP=y + +# Zephyr kernel/driver configuration required by EC FW +# ---------------------------------------------------- +CONFIG_PS2=y +CONFIG_ESPI_PERIPHERAL_8042_KBC=y + +# IO expander support interrupt +CONFIG_GPIO_PCA95XX_INTERRUPT=y + +# Workaround to avoid overlap in SPI layout +CONFIG_FLASH_SIZE=224 + +# Enable SAF +CONFIG_ESPI_SAF=y \ No newline at end of file diff --git a/boards/microchip/ptl_uh_mec172x.c b/boards/microchip/ptl_uh_mec172x.c new file mode 100644 index 0000000..e976048 --- /dev/null +++ b/boards/microchip/ptl_uh_mec172x.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "i2c_hub.h" +#include +#include "gpio_ec.h" +#include "espi_hub.h" +#include "board.h" +#include "board_config.h" +#include "ptl_uh_mec172x.h" +#include "vci.h" + +LOG_MODULE_DECLARE(board, CONFIG_BOARD_LOG_LEVEL); + +uint8_t platformskutype; +uint8_t pd_i2c_addr_set; + +/** @brief EC FW app owned gpios list. + * + * This list is not exhaustive, it do not include driver-owned pins, + * the initialization is done as part of corresponding Zephyr pinmux driver. + * BSP drivers are responsible to control gpios in soc power transitions and + * system transitions. + * + * Note: Pins not assigned to any app function are identified with their + * original pin number instead of signal + * + */ + +/* APP-owned gpios */ +struct gpio_ec_config mecc172x_cfg[] = { + { HOME_BUTTON, GPIO_INPUT }, + { EC_GPIO_002, GPIO_DISCONNECTED }, + { PM_SLP_SUS, GPIO_DISCONNECTED }, + { PM_PWRBTN, GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN }, + { RSMRST_PWRGD_G3SAF_P, GPIO_INPUT }, + { RSMRST_PWRGD_MAF_P, GPIO_INPUT }, + { CPU_C10_GATE, GPIO_INPUT }, + { DNX_FORCE_RELOAD_EC, GPIO_DISCONNECTED }, + { EC_GPIO_015, GPIO_DISCONNECTED }, + + /* Not used */ + { SLP_S0_PLT_EC_N, GPIO_DISCONNECTED }, + + { ALL_SYS_PWRGD, GPIO_INPUT }, + { FAN_PWR_DISABLE_N, GPIO_OUTPUT_HIGH }, + { PCA9555_1_R_INT_N, GPIO_INPUT }, + { EC_GPIO_063, GPIO_DISCONNECTED }, + { EC_GPIO_067, GPIO_DISCONNECTED }, + + { PCH_PWROK, GPIO_OUTPUT_LOW | GPIO_OPEN_DRAIN }, + { PWRBTN_EC_IN_N, GPIO_INPUT | GPIO_INT_EDGE_BOTH }, + { EC_GPIO_115, GPIO_DISCONNECTED }, + { KBC_CAPS_LOCK, GPIO_OUTPUT_LOW }, + { TYPEC_EC_SMBUS_ALERT_0_R, GPIO_INPUT | GPIO_INT_EDGE_FALLING }, + { EC_PG3_EXIT, GPIO_OUTPUT_LOW }, + + { KBD_BKLT_CTRL, GPIO_OUTPUT_LOW }, + { PM_BAT_STATUS_LED1, GPIO_OUTPUT_LOW }, + { PM_BAT_STATUS_LED2, GPIO_OUTPUT_LOW }, + { KBC_NUM_LOCK, GPIO_OUTPUT_LOW }, + { BC_ACOK, GPIO_INPUT }, + { BATT_ID_N, GPIO_INPUT }, + { PM_BATLOW, GPIO_OUTPUT_LOW | GPIO_OPEN_DRAIN }, + + { PROCHOT, GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN }, + { RETIMER_FORCE_PWR_BTP_EC_R, GPIO_DISCONNECTED}, + { EC_SLATEMODE_HALLOUT_SNSR_R, GPIO_INPUT | GPIO_INT_EDGE_BOTH }, + { PM_DS3, GPIO_OUTPUT_LOW }, + { EC_GPIO_240, GPIO_DISCONNECTED }, + { EC_PWRBTN_LED, GPIO_OUTPUT_LOW }, + { VOL_UP, GPIO_INPUT | GPIO_INT_EDGE_BOTH }, + { STD_ADP_PRSNT, GPIO_INPUT }, + { TOP_SWAP_OVERRIDE_GPIO, GPIO_OUTPUT }, + { EC_GPIO_245, GPIO_DISCONNECTED }, + { VOL_DOWN, GPIO_INPUT | GPIO_INT_EDGE_BOTH }, + { STD_ADPT_CNTRL_GPIO, GPIO_OUTPUT_LOW }, + { CATERR_LED_DRV, GPIO_DISCONNECTED}, + + /* Not used */ + { SLP_S0_PLT_EC_N, GPIO_DISCONNECTED }, + +}; + +/* Any IO expanders pins should be defined here */ +struct gpio_ec_config expander_cfg[] = { +#ifdef CONFIG_GPIO_PCA95XX + { SPD_PRSNT, GPIO_INPUT }, + { VIRTUAL_BAT, GPIO_INPUT }, + { VIRTUAL_DOCK, GPIO_INPUT }, + { TIMEOUT_DISABLE, GPIO_INPUT }, + { SOC_VR_CNTRL, GPIO_INPUT }, + { EC_M_2_SSD_PLN, GPIO_OUTPUT_HIGH }, + { THERM_STRAP, GPIO_INPUT }, + { KBC_SCROLL_LOCK, GPIO_OUTPUT_LOW }, + { CS_INDICATE_LED, GPIO_OUTPUT_LOW }, + { C10_GATE_LED, GPIO_OUTPUT_LOW }, +#endif +}; + +struct gpio_ec_config mecc172x_cfg_sus[] = { +}; + +struct gpio_ec_config mecc172x_cfg_res[] = { +}; + +#ifdef CONFIG_THERMAL_MANAGEMENT +/** + * @brief Fan device table. + * + * This table lists the supported fan devices for board. By default, each + * board is assigned one fan for CPU. + */ +static struct fan_dev fan_tbl[] = { +/* PWM_CH_## TACH_CH_## */ + { PWM_CH_08, TACH_CH_00 }, /* CPU Fan */ +}; + +void board_fan_dev_tbl_init(uint8_t *pmax_fan, struct fan_dev **pfan_tbl) +{ + *pfan_tbl = fan_tbl; + *pmax_fan = ARRAY_SIZE(fan_tbl); +} + +void board_therm_sensor_list_init(uint8_t therm_sensors[]) +{ + switch (platformskutype) { + case PLATFORM_PTL_UH_SKUs: + therm_sensors[ACPI_THRM_SEN_2] = ADC_CH_07; + therm_sensors[ACPI_THRM_SEN_3] = ADC_CH_04; + therm_sensors[ACPI_THRM_SEN_4] = ADC_CH_05; + therm_sensors[ACPI_THRM_SEN_5] = ADC_CH_06; + break; + default: + break; + } +} +#endif + +void board_config_io_buffer(void) +{ + int ret; + + /* PS2 requires additional configuration not possible in pinmux */ + ret = gpio_interrupt_configure_pin(PS2_KB_DATA, GPIO_INT_EDGE_FALLING); + if (ret) { + LOG_ERR("Failed to enable PS2 KB interrupt"); + } +} + +void update_platform_sku_type(void) +{ + switch (get_board_id()) { + /* PTL UH Board ID List */ + case BRD_ID_PTL_UH_LP5x_T3_ERB: + case BRD_ID_PTL_UH_LP5x_T3_RVP1: + case BRD_ID_PTL_UH_LP5x_T4_RVP3: + platformskutype = PLATFORM_PTL_UH_SKUs; + pd_i2c_addr_set = PTL_UH_I2C_SET1; + break; + case BRD_ID_PTL_UH_LP5x_CAMM_DTBT_RVP2: + case BRD_ID_PTL_UH_DDR5_T3_RVP4: + platformskutype = PLATFORM_PTL_UH_SKUs; + pd_i2c_addr_set = PTL_UH_I2C_SET2; + break; + default: + platformskutype = PLATFORM_PTL_UH_SKUs; + pd_i2c_addr_set = PTL_UH_I2C_SET1; + break; + } +} + +int board_init(void) +{ + int ret; + + LOG_WRN("%s", __func__); + bgpo_disable(); + + ret = gpio_init(); + if (ret) { + LOG_ERR("Failed to initialize gpio devs: %d", ret); + return ret; + } + + LOG_WRN("%s about to initialize i2c0", __func__); + ret = i2c_hub_config(I2C_0); + if (ret) { + return ret; + } + + LOG_WRN("%s about to initialize i2c1", __func__); + ret = i2c_hub_config(I2C_1); + if (ret) { + return ret; + } + + LOG_WRN("%s about to read board id", __func__); + ret = read_board_id(); + if (ret) { + LOG_ERR("Failed to fetch brd id: %d", ret); + return ret; + } + + LOG_WRN("%s about to update sku", __func__); + update_platform_sku_type(); + + LOG_WRN("%s about to configure expander", __func__); + ret = gpio_configure_array(expander_cfg, ARRAY_SIZE(expander_cfg)); + if (ret) { + LOG_ERR("%s: %d", __func__, ret); + return ret; + } + + /* In PTL UH G3_SAF HW strap is not in the expander_cfg + * MEC172x has by default GPIO input disabled. + * Need to configure strap prior to decide boot mode + */ + gpio_configure_pin(G3_SAF_DETECT, GPIO_INPUT); + + detect_boot_mode(); + + ret = gpio_configure_array(mecc172x_cfg, ARRAY_SIZE(mecc172x_cfg)); + if (ret) { + LOG_ERR("%s: %d", __func__, ret); + return ret; + } + + + /* In MAF, boot ROM already made this pin output and high, so we must + * keep it like that during the boot phase in order to avoid espi reset + */ + if (espihub_boot_mode() == FLASH_BOOT_MODE_MAF) { + gpio_force_configure_pin(PM_RSMRST_MAF_P, GPIO_OUTPUT_HIGH); + /* LPM optimizations */ + gpio_force_configure_pin(G3_SAF_DETECT, GPIO_DISCONNECTED); + gpio_force_configure_pin(PM_RSMRST_G3SAF_P, GPIO_DISCONNECTED); + } else { + gpio_configure_pin(RSMRST_PWRGD_G3SAF_P, GPIO_INPUT); + gpio_configure_pin(PM_RSMRST_G3SAF_P, GPIO_OUTPUT_LOW); + } + + board_config_io_buffer(); + + return 0; +} + +int board_suspend(void) +{ + int ret; + + ret = gpio_configure_array(mecc172x_cfg_sus, + ARRAY_SIZE(mecc172x_cfg_sus)); + if (ret) { + LOG_ERR("%s: %d", __func__, ret); + return ret; + } + + return 0; +} + +int board_resume(void) +{ + int ret; + + ret = gpio_configure_array(mecc172x_cfg_res, + ARRAY_SIZE(mecc172x_cfg_res)); + if (ret) { + LOG_ERR("%s: %d", __func__, ret); + return ret; + } + + return 0; +} diff --git a/boards/microchip/ptl_uh_mec172x.h b/boards/microchip/ptl_uh_mec172x.h new file mode 100644 index 0000000..9793551 --- /dev/null +++ b/boards/microchip/ptl_uh_mec172x.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "mec172x_pin.h" +#include "common_mec172x.h" +#include "board.h" + +#ifndef __MEC172x_PTL_UH__ +#define __MEC172x_PTL_UH__ + +#define KSC_PLAT_NAME "PTL_UH" + +extern uint8_t platformskutype; +extern uint8_t pd_i2c_addr_set; + +#define PLATFORM_DATA(x, y) ((x) | ((y) << 8)) + +/* In PTL UH board id is 6-bits */ +#define BOARD_ID_MASK 0x003Fu +#define BOM_ID_MASK 0x01C0u +#define FAB_ID_MASK 0x0600u +#define HW_STRAP_MASK 0xF800u +#define HW_ID_MASK (FAB_ID_MASK|BOM_ID_MASK|BOARD_ID_MASK) +#define BOARD_ID_OFFSET 0u +#define BOM_ID_OFFSET 6u +#define FAB_ID_OFFSET 9u +#define HW_STRAP_OFFSET 11u + +/* Support PTL UH skus */ +enum platform_skus { + PLATFORM_PTL_UH_SKUs, +}; + +/* PTL UH PD I2C Address Group*/ +enum i2c_addr_set { + PTL_UH_I2C_SET1 = 0, + PTL_UH_I2C_SET2 = 1, +}; + +/* Support board ids */ +#define BRD_ID_PTL_UH_LP5x_T3_ERB 0x09u +#define BRD_ID_PTL_UH_LP5x_T3_RVP1 0x01u +#define BRD_ID_PTL_UH_LP5x_CAMM_DTBT_RVP2 0x02u +#define BRD_ID_PTL_UH_LP5x_T4_RVP3 0x03u +#define BRD_ID_PTL_UH_DDR5_T3_RVP4 0x04u + +/* I2C addresses */ +#define EEPROM_DRIVER_I2C_ADDR 0x50 +#define IO_EXPANDER_0_I2C_ADDR 0x22 + +/* Signal to gpio mapping for MEC1728 based PTL UH is described here */ +#define HOME_BUTTON EC_GPIO_000 + +#define PS2_KB_DATA EC_GPIO_010 +#define PM_PWRBTN EC_GPIO_011 + +#define RSMRST_PWRGD_G3SAF_P EC_GPIO_012 +#define RSMRST_PWRGD_MAF_P EC_GPIO_227 +#define RSMRST_PWRGD ((boot_mode_maf == 1) ? \ + RSMRST_PWRGD_MAF_P : \ + RSMRST_PWRGD_G3SAF_P) +#define CPU_C10_GATE EC_GPIO_013 +#define DNX_FORCE_RELOAD_EC EC_GPIO_014 + +#define G3_SAF_DETECT EC_GPIO_022 +#define RECOVERY_INDICATOR_N EC_GPIO_023 +#define MOD_TCSS_EC_SX_CNTRL EC_GPIO_024 + +#define SMC_LID EC_GPIO_033 +#define WAKE_SCI EC_GPIO_034 + +#define SLP_S0_PLT_EC_N EC_GPIO_052 +//#define MIC_PRIVACY_EC EC_GPIO_053 +#define PM_RSMRST_G3SAF_P EC_GPIO_054 +#define PM_RSMRST_MAF_P EC_GPIO_055 +#define PM_RSMRST ((boot_mode_maf == 1) ? \ + PM_RSMRST_MAF_P : \ + PM_RSMRST_G3SAF_P) +#define ALL_SYS_PWRGD EC_GPIO_057 + + +#define FAN_PWR_DISABLE_N EC_GPIO_060 +#define ESPI_RESET_MAF EC_GPIO_061 +#define PCA9555_1_R_INT_N EC_GPIO_062 + +#define PCH_PWROK EC_GPIO_100 +#define SYS_PWROK EC_DUMMY_GPIO_LOW +#define PWRBTN_EC_IN_N EC_GPIO_106 + +#define KBC_CAPS_LOCK EC_GPIO_127 +#define TYPEC_EC_SMBUS_ALERT_0_R EC_GPIO_143 +#define EC_PG3_EXIT EC_GPIO_144 + +#define KBD_BKLT_CTRL EC_GPIO_153 +#define PM_BAT_STATUS_LED1 EC_GPIO_156 +#define PM_BAT_STATUS_LED2 EC_GPIO_157 +#define KBC_NUM_LOCK EC_GPIO_154 +#define BC_ACOK EC_GPIO_155 +#define BATT_ID_N EC_GPIO_162 +#define PM_BATLOW EC_GPIO_165 + +#define PROCHOT EC_GPIO_171 +//#define M2_BT_LED2_N_EC EC_GPIO_175 +//#define EDP1_BKLT_EN EC_GPIO_200 + +#define RETIMER_FORCE_PWR_BTP_EC_R EC_GPIO_221 + +#define EC_SLATEMODE_HALLOUT_SNSR_R EC_GPIO_222 + +#define PM_DS3 EC_GPIO_226 +#define EC_PWRBTN_LED EC_GPIO_241 + +#define EC_PCH_DEBUG EC_DUMMY_GPIO_HIGH +#define VOL_UP EC_GPIO_242 +#endif +#define STD_ADP_PRSNT EC_GPIO_243 + +#define TOP_SWAP_OVERRIDE_GPIO EC_GPIO_244 + +#define VOL_DOWN EC_GPIO_246 + +#define STD_ADPT_CNTRL_GPIO EC_GPIO_254 +#define CATERR_LED_DRV EC_GPIO_255 + +#define PM_SLP_SUS EC_DUMMY_GPIO_HIGH + +#define DG2_PRESENT EC_DUMMY_GPIO_LOW +#define PEG_RTD3_COLD_MOD_SW_R EC_DUMMY_GPIO_LOW + +/* IO expander HW strap pins IO expander 1 */ +#define SPD_PRSNT EC_GPIO_PORT_PIN(EC_EXP_PORT_1, 0x03) +#define DISPLAY_ID_0 EC_GPIO_PORT_PIN(EC_EXP_PORT_1, 0x04) +#define DISPLAY_ID_1 EC_GPIO_PORT_PIN(EC_EXP_PORT_1, 0x05) +#define DISPLAY_ID_2 EC_GPIO_PORT_PIN(EC_EXP_PORT_1, 0x06) +#define DISPLAY_ID_3 EC_GPIO_PORT_PIN(EC_EXP_PORT_1, 0x07) + +/* IO expander HW strap pins IO expander 2 */ +/* Pin2 is named as VAL_PECI_ESPI in schematics but using this EC_EMUL_HW_STRAP */ +#define PNP_NPNP_SKU EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x02) +#define TIMEOUT_DISABLE EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x03) +#define SOC_VR_CNTRL EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x04) +#define EC_M_2_SSD_PLN EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x05) +#define VIRTUAL_BAT EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x06) +#define VIRTUAL_DOCK EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x07) +/* IO expander pin mapping is in hex decimal format instead of octal*/ +/* Net name TP_ESPI_TESTCRD_DET */ +#define THERM_STRAP EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x08) +//#define PD_AIC_DETECT_SLOT_ID EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x0A) +#define KBC_SCROLL_LOCK EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x0D) +#define C10_GATE_LED EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x0E) +#define CS_INDICATE_LED EC_GPIO_PORT_PIN(EC_EXP_PORT_2, 0x0F) + +/* Device instance names */ +#define I2C_BUS_0 DT_NODELABEL(i2c_smb_0) +#define I2C_BUS_1 DT_NODELABEL(i2c_smb_1) +#define I2C_BUS_2 DT_NODELABEL(i2c_smb_2) +#define PS2_KEYBOARD DT_NODELABEL(ps2_0) +#define PS2_MOUSE DT_NODELABEL(ps2_0) +#define ESPI_0 DT_NODELABEL(espi0) +#define ESPI_SAF_0 DT_NODELABEL(espi_saf0) +#define SPI_0 DT_NODELABEL(spi0) +#define ADC_CH_BASE DT_NODELABEL(adc0) +#define PECI_0_INST DT_NODELABEL(peci0) +#define KSCAN_MATRIX DT_NODELABEL(kscan0) +#define WDT_0 DT_NODELABEL(wdog) + +/* EC Emulation device instances */ +#define EC_EMUL_HUB DT_NODELABEL(ec_emul_hub0) +#define PECI_EMUL DT_NODELABEL(peci_emul0) + +/* Button/Switch Initial positions */ +#define PWR_BTN_INIT_POS 1 +#define VOL_UP_INIT_POS 1 +#define VOL_DN_INIT_POS 1 +#define LID_INIT_POS 1 +#define HOME_INIT_POS 1 +#define SLATEMODE_INIT_POS 1 +#define IOEXP_INIT_POS 1 +#define VIRTUAL_BAT_INIT_POS 1 +#define VIRTUAL_DOCK_INIT_POS 1 + +#define CHARGER_CURRENT_LIMIT1_PERCENTAGE 90 +#define CHARGER_CURRENT_LIMIT2_PERCENTAGE 100 +#define CHARGER_AC_PROCHOT_PERCENTAGE 110 +#define CHARGER_FAST_CHARGING_CURRENT 0x2FF8 + +/* As per ISL charger spec, ISL92XX_CURRENT_LIMIT register needs to be + * programmed based on the value of Rs2 (input current sense resistor). + * + * Same case with ISL92XX_ADP_CURRENT_LIMIT1, ISL92XX_ADP_CURRENT_LIMIT2, + * ISL92XX_AC_PROCHOT and ISL92XX_DC_PROCHOT registers which need to be + * programmed based on the value of Rs1. + * + * RS1/RS2 is always configured in pairs either as 20/10 mohms or as 10/5 + * mohms. This may differ from platform to platform. If it is 20/10, the + * DIVISOR value should be 2. If it is 10/5, the DIVISOR value should be 1. + * + * Note: The Divisor value is provided by the PD team. + */ +#define CHARGER_CURRENT_LIMIT_DIVISOR 2U + +/* Delay to match the output adaptor current ramp-up with the + * system current + */ +#define SINK_FET_VOL_RAMPUP_DLY_MS 50U + +/* Minimum Adapter power(Milli Watts) for proceeding with boot */ +#define ADP_CRIT_POWERUP 26000 + +/* Change the BOOT mode name to APP1 for TOMCAT PD Controller*/ +#define TIPD_BOOT_COMPLETE_MODE "APP1" + +/* Configure the PD I2C addresses based on the board id */ +#define TIPD_PORT_0_I2C_ADDR ((pd_i2c_addr_set == PTL_UH_I2C_SET1) ? \ + 0x20U : \ + 0x20U) +#define TIPD_PORT_1_I2C_ADDR ((pd_i2c_addr_set == PTL_UH_I2C_SET1) ? \ + 0x24U : \ + 0x21U) +#define TIPD_PORT_2_I2C_ADDR ((pd_i2c_addr_set == PTL_UH_I2C_SET1) ? \ + 0x21U : \ + 0x22U) +#define TIPD_PORT_3_I2C_ADDR ((pd_i2c_addr_set == PTL_UH_I2C_SET1) ? \ + 0x22U : \ + 0x26U) + + +/* PD version: MSB byte represent Major version and + * LSB byte represent Minor version + */ +#define USB_PD_VERSION 0x0200 + +/* TIPD UCSI version details + * UCSI Version format is 0xJJMN (2 Bytes) + * JJ – Manjor Version + * M – Minor Version + * N – Sub Minor Version + */ +#define TIPD_UCSI_MAJOR_VERSION 0x02 +#define TIPD_UCSI_MINOR_VERSION 0x0 +#define TIPD_UCSI_SUB_MINOR_VERSION 0x0 + +/* __MEC172x_PTL_UH__ */ \ No newline at end of file diff --git a/misc/flashhdr.c b/misc/flashhdr.c index ebe58b1..8c11599 100644 --- a/misc/flashhdr.c +++ b/misc/flashhdr.c @@ -12,7 +12,7 @@ #define KSC_MAJOR_VER 3 #define KSC_MINOR_VER 1 #define KSC_PATCH_ID 2 -#define KSC_QS_BUILD_VER 2 +#define KSC_QS_BUILD_VER 3 __in_section(ecfw_info, static, var) struct ksc_img_hdr header = { /* This is replaced by real checksum in build. */ diff --git a/out_of_tree_boards/boards/arm/mec172x-espi-based-board.dtsi b/out_of_tree_boards/boards/arm/mec172x-espi-based-board.dtsi new file mode 100644 index 0000000..6292051 --- /dev/null +++ b/out_of_tree_boards/boards/arm/mec172x-espi-based-board.dtsi @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2024, Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + espitaf = &espi_saf0; + spi0 = &spi0; + }; +}; + + +/* Initialize ECIA. Does not initialize child devices */ +&ecia { + status = "okay"; +}; + +/* Enable aggregated GIRQ24 and GIRQ25 for eSPI virtual wires interrupts */ +&girq24 { + status = "okay"; +}; + +&girq25 { + status = "okay"; +}; + +&rtimer { + status = "okay"; +}; + +&pcr { + status = "okay"; +}; + +&espi0 { + status = "okay"; + pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066 + &espi_clk_gpio065 &espi_io0_gpio070 + &espi_io1_gpio071 &espi_io2_gpio072 + &espi_io3_gpio073 >; + pinctrl-names = "default"; +}; + +&espi_alert_n_gpio063 { + drive-strength = "1x"; +}; + +&espi_reset_n_gpio061 { + drive-strength = "1x"; +}; + +&espi_cs_n_gpio066 { + drive-strength = "1x"; +}; + +&espi_clk_gpio065 { + drive-strength = "1x"; +}; + +&espi_io0_gpio070 { + drive-strength = "1x"; +}; + +&espi_io1_gpio071 { + drive-strength = "1x"; +}; + +&espi_io2_gpio072 { + drive-strength = "1x"; +}; + +&espi_io3_gpio073 { + drive-strength = "1x"; +}; + +/* enable various eSPI child devices (host facing) */ +&kbc0 { + status = "okay"; +}; + +&acpi_ec0 { + status = "okay"; +}; + +&acpi_ec1 { + status = "okay"; +}; + +&emi0 { + status = "okay"; +}; + +&p80bd0 { + status = "okay"; +}; + +&espi_saf0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + compatible = "microchip,xec-qmspi-ldma"; + clock-frequency = <12000000>; + lines = <4>; + chip-select = <0>; + + pinctrl-0 = < &shd_cs0_n_gpio055 + &shd_clk_gpio056 + &shd_io0_gpio223 + &shd_io1_gpio224 + &shd_io2_gpio227 + &shd_io3_gpio016 >; + pinctrl-names = "default"; +}; + +&timer3 { + status = "okay"; +}; + +&kscan0 { + status = "okay"; + + pinctrl-0 = < &ksi0_gpio017 + &ksi1_gpio020 + &ksi2_gpio021 + &ksi3_gpio026 + &ksi4_gpio027 + &ksi5_gpio030 + &ksi6_gpio031 + &ksi7_gpio032 + &kso00_gpio040 + &kso01_gpio045 + &kso02_gpio046 + &kso03_gpio047 + &kso04_gpio107 + &kso05_gpio112 + &kso06_gpio113 + &kso07_gpio120 + &kso08_gpio121 + &kso09_gpio122 + &kso10_gpio123 + &kso11_gpio124 + &kso12_gpio125 + &kso13_gpio126 + &kso14_gpio152 + &kso15_gpio151 >; + pinctrl-names = "default"; +}; + +&ps2_0 { + status = "okay"; + + pinctrl-0 = < &ps2_clk0b_gpio007 &ps2_dat0b_gpio010 >; + pinctrl-names = "default"; +}; + + +/* Disable unwanted eSPI VWs notifications which are enabled by default */ +&vw_sus_stat_n { + status = "disabled"; +}; + +&vw_smiout_n { + status = "disabled"; +}; + +&vw_nmiout_n { + status = "disabled"; +}; + +&vw_slp_lan_n { + status = "disabled"; +}; + +&vw_slp_wlan_n { + status = "disabled"; +}; + +&vw_host_c10 { + status = "disabled"; +}; \ No newline at end of file diff --git a/out_of_tree_boards/boards/arm/mec172x_ptl_uh/CMakeLists.txt b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/CMakeLists.txt new file mode 100644 index 0000000..7febd3e --- /dev/null +++ b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/CMakeLists.txt @@ -0,0 +1,39 @@ +# +# Copyright (c) 2024 Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +#Allow users to pre-specify the tool using '-DMEC172X_SPI_GEN=/toolname' +if (NOT DEFINED MEC172X_SPI_GEN) + set(MEC172X_SPI_GEN $ENV{MEC172X_SPI_GEN}) +endif() +find_program (MEC172X_SPI_GEN NAMES mec172x_spi_gen_lin_x86_64 mec172x_spi_gen) +if(MEC172X_SPI_GEN STREQUAL MEC172X_SPI_GEN-NOTFOUND) + message(WARNING "Microchip SPI Image Generation tool is not available. SPI Image will not be generated.") +endif() + +if (NOT DEFINED MEC172X_SPI_CFG) + set(MEC172X_SPI_CFG $ENV{MEC172X_SPI_CFG}) +endif() +find_file (MEC172X_SPI_CFG NAMES spi_cfg_4MBit.txt spi_cfg_128MBit.txt spi_cfg.txt PATHS ${BOARD_DIR}/support) +if(MEC172X_SPI_CFG STREQUAL MEC172X_SPI_CFG-NOTFOUND) + message(WARNING "Microchip SPI Image Generation tool configuration file is not available. SPI Image will not be generated.") +endif() + + if(DEFINED ENV{SPI_IMAGE_NAME}) + set(SPI_IMAGE_NAME $ENV{SPI_IMAGE_NAME}) + else() + set(SPI_IMAGE_NAME ECFW.bin) + endif() + +if (NOT MEC172X_SPI_GEN STREQUAL MEC172X_SPI_GEN-NOTFOUND AND NOT MEC172X_SPI_CFG STREQUAL MEC172X_SPI_CFG-NOTFOUND) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${MEC172X_SPI_GEN} + -i ${MEC172X_SPI_CFG} + -o ${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME} + ) + + unset(MEC172X_SPI_GEN) + unset(MEC172X_SPI_CFG) +endif() \ No newline at end of file diff --git a/out_of_tree_boards/boards/arm/mec172x_ptl_uh/Kconfig.board b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/Kconfig.board new file mode 100644 index 0000000..a4c9d83 --- /dev/null +++ b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2024, Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC172X_PTL_UH + bool "Intel MEC172X PTL UH RVP board" + depends on SOC_MEC172X_NSZ \ No newline at end of file diff --git a/out_of_tree_boards/boards/arm/mec172x_ptl_uh/Kconfig.defconfig b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/Kconfig.defconfig new file mode 100644 index 0000000..f053560 --- /dev/null +++ b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/Kconfig.defconfig @@ -0,0 +1,43 @@ +# Copyright (c) 2024 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MEC172X_PTL_UH + +config BOARD + default "mec172x_ptl_uh" + +if RTOS_TIMER + +# XEC RTOS timer HW frequency is fixed at 32768 Hz. +# The driver requires tickless mode and ticks per second to be 32768 for +# accurate operation. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +endif # RTOS_TIMER + +if !RTOS_TIMER + +# If RTOS timer is not enabled we use ARM Cortex-M +# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR +# processor clock divider register. We assume PCR processor clock divider +# is set to 1. Refer to SOC_MEC172X_PROC_CLK_DIV +# + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 96000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +endif # RTOS_TIMER + +config TACH_XEC + default y + depends on SENSOR + +endif # BOARD_MEC172X_PTL_UH \ No newline at end of file diff --git a/out_of_tree_boards/boards/arm/mec172x_ptl_uh/board.cmake b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/board.cmake new file mode 100644 index 0000000..0209520 --- /dev/null +++ b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SPI_IMAGE_NAME spi_image.bin) + +board_set_flasher_ifnset(dediprog) + +# --vcc=0 - use 3.5V to flash +board_finalize_runner_args(dediprog + "--spi-image=${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME}" + "--vcc=0" +) \ No newline at end of file diff --git a/out_of_tree_boards/boards/arm/mec172x_ptl_uh/doc/index.rst b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/doc/index.rst new file mode 100644 index 0000000..9d63659 --- /dev/null +++ b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/doc/index.rst @@ -0,0 +1,99 @@ +.. _mec172X_ptl_uh: + +MEC172X PTL UH +############## + +Overview +******** + +The MEC172X PTL UH is Intel referance platform for Pantherlake. + +Hardware +******** + +- MC1723NB0SZ ARM Cortex-M4 Processor +- 416 KB RAM and 128 KB boot ROM +- PS2 Keyboard and Mouse interface +- UART0, UART1, and UART2 +- FAN0 header +- FAN PWM interface +- JTAG/SWD, ETM and MCHP Trace ports +- PECI interface 3.0 +- I2C voltage translator +- Port-80 display +- eSPI header +- CAPS LOCK, NUM LOCK and SCROLL LOCK LEDs +- Volume up, down and power buttons +- One external PCA9555 I/O port with jumper selectable I2C address. +- One I2C interface to add-in card based Type-C header. + +For more information about the SOC please see the `MEC1723 Reference Manual`_ + +Supported Features +================== + +The mec172x_ptl_uh board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| PS/2 | on-chip | ps2 | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the +:zephyr_file:`boards/arm/mec172x_ptl_uh/mec172x_ptl_uh_defconfig` +Kconfig file. + +Connections and IOs +=================== + +Please refer PTL UH rvp schematics for EC gpio allocations and IOs. +https://intel.sharepoint.com/sites/ccgptlplatformpdtprogrammanagement/SitePages/PTL-UPH-RVP-Engineering-Documents.aspx + +System Clock +============ + +The MEC1723 MCU is configured to use the 48Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock +control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in +the references at the end of this document. + +Serial Port +=========== + +UART0 is configured for serial logs. + +Building +======== +#west build -c -p auto -b mec172x_ptl_uh + +References +********** +.. target-notes:: + +.. _MEC172x Preliminary Data Sheet: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172x-Data-Sheet.pdf +.. _MEC172x Reference Manual: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172x-Data-Sheet.pdf +.. _MEC17xx EVB Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172x-MECC_Assy_6930-A1p0-SCH.pdf +.. _MEC172x Daughter Card Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-EVB-Assy_6906-A1p0-SCH.pdf +.. _SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC172x/SPI_image_gen diff --git a/out_of_tree_boards/boards/arm/mec172x_ptl_uh/mec172x_ptl_uh.dts b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/mec172x_ptl_uh.dts new file mode 100644 index 0000000..dda5f94 --- /dev/null +++ b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/mec172x_ptl_uh.dts @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2024, Intel Corporation Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "../mec172x-espi-based-board.dtsi" + +/* Example of pin not defined in SoC DTS generic definitions */ +&pinctrl { + /omit-if-no-ref/ gpio063_gpio063: gpio063_gpio063 { + pinmux = < MCHP_XEC_PINMUX(063, MCHP_AF0) >; + }; +}; + +/ { + model = "Intel MEC172X_PTL_UH Development board"; + compatible = "microchip,mec172x_ptl_uh", "microchip,mec172xnsz"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + }; + + aliases { + pwm-0 = &pwm8; + peci-0 = &peci0; + i2c0 = &i2c_smb_0; + i2c1 = &i2c_smb_1; + i2c2 = &i2c_smb_2; + + }; + + zephyr,user { + /* Set as GPIos. These are not in GPIO mode due to HW default or ROM */ + pinctrl-0 = < &gpio000_gpio000 &gpio063_gpio063 &gpio161_gpio161 &gpio162_gpio162 >; + pinctrl-names = "default"; + }; + + power-states { + suspend_to_ram_ov: suspend_to_ram { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-ram"; + min-residency-us = <100000>; + }; + }; +}; + +&cpu0 { + cpu-power-states = <&suspend_to_ram_ov>; + clock-frequency = <96000000>; + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_tx_gpio104 &uart0_rx_gpio105>; + pinctrl-names = "default"; +}; + +/* I2C */ +&i2c_smb_0 { + status = "okay"; + port_sel = <0>; + pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >; + pinctrl-names = "default"; + + pca9555@22 { + compatible = "nxp,pca95xx"; + + /* Depends on JP53 for device address. + * Pin 1-2 = A0, pin 3-4 = A1, pin 5-6 = A2. + * Address is: 0100b. + * + * Default has pin 1-2 on JP53 connected, + * resulting in device address 0x26. + */ + reg = <0x22>; + + gpio-controller; + #gpio-cells = <2>; + }; + + pca9555@23 { + compatible = "nxp,pca95xx"; + + /* Depends on JP53 for device address. + * Pin 1-2 = A0, pin 3-4 = A1, pin 5-6 = A2. + * Address is: 0100b. + * + * Default has pin 1-2 on JP53 connected, + * resulting in device address 0x26. + */ + reg = <0x23>; + interrupt-gpios = <&gpio_040_076 18 GPIO_ACTIVE_LOW>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; +}; + +&i2c00_scl_gpio004 { + drive-open-drain; + output-enable; + output-high; +}; + +&i2c00_sda_gpio003 { + drive-open-drain; + output-enable; + output-high; +}; + +&i2c_smb_1 { + status = "okay"; + port_sel = <6>; + pinctrl-0 = <&i2c06_scl_gpio140 &i2c06_sda_gpio132 >; + pinctrl-names = "default"; +}; + +&i2c06_scl_gpio140 { + drive-open-drain; + output-enable; + output-high; +}; + +&i2c06_sda_gpio132 { + drive-open-drain; + output-enable; + output-high; +}; + +&i2c_smb_2 { + status = "okay"; + port_sel = <5>; + pinctrl-0 = <&i2c05_scl_gpio142 &i2c05_sda_gpio141>; + pinctrl-names = "default"; +}; + +&i2c05_scl_gpio142 { + drive-open-drain; + output-enable; + output-high; +}; + +&i2c05_sda_gpio141 { + drive-open-drain; + output-enable; + output-high; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc06_gpio206 &adc07_gpio207 + &adc04_gpio204 &adc05_gpio205 + &adc03_gpio203 &adc02_gpio202 + &adc01_gpio201>; + pinctrl-names = "default"; +}; + +&tach0 { + status = "okay"; + pinctrl-0 = < &tach0_gpio050 >; + pinctrl-names = "default"; +}; + +&peci0 { + status = "okay"; + + pinctrl-0 = < &peci_dat_gpio042 &vref_vtt_gpio044 >; + pinctrl-names = "default"; +}; + + +&eeprom { + status = "okay"; + + pinctrl-0 = <&eeprom_cs_gpio116 + &eeprom_clk_gpio117 + &eeprom_mosi_gpio074 + &eeprom_miso_gpio075>; + pinctrl-names = "default"; +}; + +&pwm8 { + status = "okay"; + + pinctrl-0 = < &pwm8_gpio035 >; + pinctrl-names = "default"; +}; + +&bbled0 { + compatible = "microchip,xec-bbled"; + pinctrl-0 = <&led0_gpio156>; + pinctrl-names = "default"; + status = "okay"; +}; + +&bbled1 { + compatible = "microchip,xec-bbled"; + pinctrl-0 = <&led1_gpio157>; + pinctrl-names = "default"; + status = "okay"; +}; + +&bbled2 { + compatible = "microchip,xec-bbled"; + pinctrl-0 = <&led2_gpio153>; + pinctrl-names = "default"; + status = "okay"; +}; \ No newline at end of file diff --git a/out_of_tree_boards/boards/arm/mec172x_ptl_uh/mec172x_ptl_uh.yaml b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/mec172x_ptl_uh.yaml new file mode 100644 index 0000000..5a2d37c --- /dev/null +++ b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/mec172x_ptl_uh.yaml @@ -0,0 +1,28 @@ +# +# Copyright (c) 2024, Intel Corporation. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mec172x_ptl_uh +name: MEC172X PTL_UH +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 128 +flash: 416 +supported: + - adc + - counter + - espi + - gpio + - i2c + - pinmux + - pwm + - watchdog + - ps2 + - peci + - kscan + - sensor \ No newline at end of file diff --git a/out_of_tree_boards/boards/arm/mec172x_ptl_uh/mec172x_ptl_uh_defconfig b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/mec172x_ptl_uh_defconfig new file mode 100644 index 0000000..f589d80 --- /dev/null +++ b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/mec172x_ptl_uh_defconfig @@ -0,0 +1,31 @@ +# +# Copyright (c) 2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SOC_MEC172X_NSZ=y +CONFIG_SOC_SERIES_MEC172X=y +CONFIG_BOARD_MEC172X_PTL_UH=y +CONFIG_RTOS_TIMER=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_PS2=y +CONFIG_ADC=y +CONFIG_PWM=y +CONFIG_SENSOR=y +CONFIG_PECI=y +CONFIG_I2C=y +CONFIG_KSCAN=y +CONFIG_KSCAN_XEC_DEBOUNCE_UP=1 +CONFIG_KSCAN_XEC_DEBOUNCE_DOWN=1 +CONFIG_LED=y + +CONFIG_ESPI=y +CONFIG_SPI=y +CONFIG_SPI_ASYNC=y \ No newline at end of file diff --git a/out_of_tree_boards/boards/arm/mec172x_ptl_uh/support/spi_cfg.txt b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/support/spi_cfg.txt new file mode 100644 index 0000000..21d0f64 --- /dev/null +++ b/out_of_tree_boards/boards/arm/mec172x_ptl_uh/support/spi_cfg.txt @@ -0,0 +1,94 @@ +; MEC172x SPI Image Generator configuration file for internal 512KB flash +[SPI] +SPISizeMegabits = 4 +Flashmap = false +FlshmapAddr = 0 + +[DEVICE] +TagAddr0 = 0 +TagAddr1 = 0 +; BoardID is used by a Boot-ROM feature named PlatformID. By default PlatformID +; is disabled. If PlatformID is enabled in OTP Boot-ROM will check the image +; BoardID value with an OTP PlatformID value. Load is aborted if the ID's do +; not match. +BoardID = 0 + +[IMAGE "0"] +ImageLocation = 0x100 +SpiFreqMHz = 12 +SpiReadCommand = Quad +SpiDriveStrength = 8 +SpiSlewFast = false +SpiSignalControl = 0x00 +FwBinFile = zephyr.bin +ImageRevision = 0x56 +FwOffset = 0 +FwLoadAddress = 0xC0000 +FwEntryAddress = 0 +UseECDSA = false +AuthenticateKeySelt = 5 +AutoKeyRevEn = true +KeyRevPermission = 0x11223344 +AutoRollBackProtEn = false +RollbackProtPerm031000 = 0x11223344 +RollbackProtPerm063032 = 0x55667788 +RollbackProtPerm095063 = 0 +RollbackProtPerm127096 = 0xDDEEFF99 +ECDSAPrivKeyFile = ec384.pem +ECDSAPrivKeyPassword = ec384 +FwEncrypt = false +AesGenECPubKeyFile = ec384_crt.pem +SHA256andECDSA = false +TagBuildNumber= 0x1156 +Comp0ProgDrvStrenEN = false +Comp0WritCmdTotByts = 1 +Comp0ReadCmdByte = 0x15 +Comp0WritCmdByte = 0x11 +Comp0DrvValue = 0x40 +Comp0DrvMask = 0x60 +Comp1ProgDrvStrenEN = false +Comp1WritCmdTotByts = 1 +Comp1ReadCmdByte = 0x15 +Comp1WritCmdByte = 0x11 +Comp1DrvValue = 0x20 +Comp1DrvMask = 0x60 + +[IMAGE "1"] +ImageLocation = 0x40000 +SpiFreqMHz = 12 +SpiReadCommand = Quad +SpiDriveStrength = 8 +SpiSlewFast = false +SpiSignalControl = 0x00 +FwBinFile = zephyr.bin +ImageRevision = 0x56 +FwOffset = 0 +FwLoadAddress = 0xC0000 +FwEntryAddress = 0 +UseECDSA = false +AuthenticateKeySelt = 5 +AutoKeyRevEn = true +KeyRevPermission = 0x11223344 +AutoRollBackProtEn = false +RollbackProtPerm031000 = 0x11223344 +RollbackProtPerm063032 = 0x55667788 +RollbackProtPerm095063 = 0 +RollbackProtPerm127096 = 0xDDEEFF99 +ECDSAPrivKeyFile = ec384.pem +ECDSAPrivKeyPassword = ec384 +FwEncrypt = false +AesGenECPubKeyFile = ec384_crt.pem +SHA256andECDSA = false +TagBuildNumber= 0x1156 +Comp0ProgDrvStrenEN = false +Comp0WritCmdTotByts = 1 +Comp0ReadCmdByte = 0x15 +Comp0WritCmdByte = 0x11 +Comp0DrvValue = 0x40 +Comp0DrvMask = 0x60 +Comp1ProgDrvStrenEN = false +Comp1WritCmdTotByts = 1 +Comp1ReadCmdByte = 0x15 +Comp1WritCmdByte = 0x11 +Comp1DrvValue = 0x20 +Comp1DrvMask = 0x60 \ No newline at end of file