Skip to content

Commit cb33843

Browse files
AsthachavdaAsthachavda
committed
oot: boards: Add PTL board specfic files
1 parent f0347e8 commit cb33843

15 files changed

+1247
-1
lines changed

‎boards/CMakeLists.txt

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,13 @@ target_sources_ifdef(CONFIG_BOARD_MEC172X_MTL_S app
4848
${CMAKE_CURRENT_LIST_DIR}/microchip/mtl_s_mec172x.h
4949
)
5050

51+
target_sources_ifdef(CONFIG_BOARD_MEC172X_PTL_UH app
52+
PRIVATE
53+
${CMAKE_CURRENT_LIST_DIR}/microchip/ptl_uh_mec172x.c
54+
PUBLIC
55+
${CMAKE_CURRENT_LIST_DIR}/microchip/ptl_uh_mec172x.h
56+
)
57+
5158
target_include_directories(app
5259
PRIVATE
5360
${CMAKE_CURRENT_LIST_DIR}
@@ -56,4 +63,4 @@ target_include_directories(app
5663
${CMAKE_CURRENT_LIST_DIR}/microchip/mec172x_mecc
5764
)
5865

59-
endif()
66+
endif()

‎boards/board_config.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,8 @@ extern uint8_t boot_mode_maf;
3030
#include "mtl_template_mec172xlj.h"
3131
#elif defined(CONFIG_BOARD_MEC172X_MTL_S)
3232
#include "mtl_s_mec172x.h"
33+
#elif defined(CONFIG_BOARD_MEC172X_PTL_UH)
34+
#include "ptl_uh_mec172x.h"
3335
#else
3436
#error "Platform not supported"
3537
#endif /* CONFIG_BOARD_MEC1501MODULAR_ASSY6885 */

‎boards/mec172x_ptl_uh.conf

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
# Zephyr-based EC FW
2+
3+
# EC FW features configuration
4+
# ----------------------------
5+
6+
# Enable PS2 device management but only keyboard due SoC port limitation
7+
CONFIG_PS2_KEYBOARD=y
8+
CONFIG_PS2_MOUSE=n
9+
10+
# EC FW keyscan configuration
11+
CONFIG_KSCAN_EC=y
12+
CONFIG_SOC_DEBUG_CONSENT_GPIO=y
13+
14+
#Use UART0 for the eSPI communication
15+
#-------------------------------------
16+
CONFIG_ESPI_PERIPHERAL_UART_SOC_MAPPING=0
17+
18+
# Support deprecated SMChost commands for backward compatibility
19+
CONFIG_DEPRECATED_SMCHOST_CMD=y
20+
21+
# Enable gigadevice sequence
22+
CONFIG_SAF_ENABLE_XIP=y
23+
24+
# Zephyr kernel/driver configuration required by EC FW
25+
# ----------------------------------------------------
26+
CONFIG_PS2=y
27+
CONFIG_ESPI_PERIPHERAL_8042_KBC=y
28+
29+
# IO expander support interrupt
30+
CONFIG_GPIO_PCA95XX_INTERRUPT=y
31+
32+
# Workaround to avoid overlap in SPI layout
33+
CONFIG_FLASH_SIZE=224
34+
35+
# Enable SAF
36+
CONFIG_ESPI_SAF=y

‎boards/microchip/ptl_uh_mec172x.c

Lines changed: 292 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,292 @@
1+
/*
2+
* Copyright (c) 2024 Intel Corporation
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <soc.h>
8+
#include <zephyr/drivers/gpio.h>
9+
#include "i2c_hub.h"
10+
#include <zephyr/logging/log.h>
11+
#include "gpio_ec.h"
12+
#include "espi_hub.h"
13+
#include "board.h"
14+
#include "board_config.h"
15+
#include "ptl_uh_mec172x.h"
16+
#include "vci.h"
17+
18+
LOG_MODULE_DECLARE(board, CONFIG_BOARD_LOG_LEVEL);
19+
20+
uint8_t platformskutype;
21+
uint8_t pd_i2c_addr_set;
22+
23+
/** @brief EC FW app owned gpios list.
24+
*
25+
* This list is not exhaustive, it do not include driver-owned pins,
26+
* the initialization is done as part of corresponding Zephyr pinmux driver.
27+
* BSP drivers are responsible to control gpios in soc power transitions and
28+
* system transitions.
29+
*
30+
* Note: Pins not assigned to any app function are identified with their
31+
* original pin number instead of signal
32+
*
33+
*/
34+
35+
/* APP-owned gpios */
36+
struct gpio_ec_config mecc172x_cfg[] = {
37+
{ HOME_BUTTON, GPIO_INPUT },
38+
{ EC_GPIO_002, GPIO_DISCONNECTED },
39+
{ PM_SLP_SUS, GPIO_DISCONNECTED },
40+
{ PM_PWRBTN, GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN },
41+
{ RSMRST_PWRGD_G3SAF_P, GPIO_INPUT },
42+
{ RSMRST_PWRGD_MAF_P, GPIO_INPUT },
43+
{ CPU_C10_GATE, GPIO_INPUT },
44+
{ DNX_FORCE_RELOAD_EC, GPIO_DISCONNECTED },
45+
{ EC_GPIO_015, GPIO_DISCONNECTED },
46+
47+
/* Modular TCSS
48+
{ MOD_TCSS_EC_SX_CNTRL, GPIO_OUTPUT_LOW },
49+
{ EC_GPIO_025, GPIO_DISCONNECTED },
50+
51+
{ SMC_LID, GPIO_INPUT | GPIO_INT_EDGE_BOTH },
52+
{ WAKE_SCI, GPIO_OUTPUT_HIGH },
53+
{ EC_GPIO_036, GPIO_DISCONNECTED },
54+
{ EC_GPIO_043, GPIO_DISCONNECTED },*/
55+
56+
/* Not used */
57+
{ SLP_S0_PLT_EC_N, GPIO_DISCONNECTED },
58+
59+
{ ALL_SYS_PWRGD, GPIO_INPUT },
60+
{ FAN_PWR_DISABLE_N, GPIO_OUTPUT_HIGH },
61+
{ ESPI_RESET_MAF, GPIO_INPUT },
62+
{ PCA9555_1_R_INT_N, GPIO_INPUT },
63+
{ EC_GPIO_063, GPIO_DISCONNECTED },
64+
{ EC_GPIO_067, GPIO_DISCONNECTED },
65+
66+
{ PCH_PWROK, GPIO_OUTPUT_LOW | GPIO_OPEN_DRAIN },
67+
{ PWRBTN_EC_IN_N, GPIO_INPUT | GPIO_INT_EDGE_BOTH },
68+
{ EC_GPIO_115, GPIO_DISCONNECTED },
69+
{ KBC_CAPS_LOCK, GPIO_OUTPUT_LOW },
70+
{ TYPEC_EC_SMBUS_ALERT_0_R, GPIO_INPUT | GPIO_INT_EDGE_FALLING },
71+
{ EC_PG3_EXIT, GPIO_OUTPUT_LOW },
72+
73+
{ KBD_BKLT_CTRL, GPIO_OUTPUT_LOW },
74+
{ PM_BAT_STATUS_LED1, GPIO_OUTPUT_LOW },
75+
{ PM_BAT_STATUS_LED2, GPIO_OUTPUT_LOW },
76+
{ KBC_NUM_LOCK, GPIO_OUTPUT_LOW },
77+
{ BC_ACOK, GPIO_INPUT },
78+
{ BATT_ID_N, GPIO_INPUT },
79+
{ PM_BATLOW, GPIO_OUTPUT_LOW | GPIO_OPEN_DRAIN },
80+
81+
{ PROCHOT, GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN },
82+
//{ M2_BT_LED2_N_EC, GPIO_DISCONNECTED},
83+
//{ EDP1_BKLT_EN, GPIO_DISCONNECTED },
84+
85+
{ RETIMER_FORCE_PWR_BTP_EC_R, GPIO_DISCONNECTED},
86+
{ EC_SLATEMODE_HALLOUT_SNSR_R, GPIO_INPUT | GPIO_INT_EDGE_BOTH },
87+
{ PM_DS3, GPIO_OUTPUT_LOW },
88+
{ EC_GPIO_240, GPIO_DISCONNECTED },
89+
{ EC_PWRBTN_LED, GPIO_OUTPUT_LOW },
90+
{ VOL_UP, GPIO_INPUT | GPIO_INT_EDGE_BOTH },
91+
{ STD_ADP_PRSNT, GPIO_INPUT },
92+
{ TOP_SWAP_OVERRIDE_GPIO, GPIO_OUTPUT },
93+
{ EC_GPIO_245, GPIO_DISCONNECTED },
94+
{ VOL_DOWN, GPIO_INPUT | GPIO_INT_EDGE_BOTH },
95+
{ STD_ADPT_CNTRL_GPIO, GPIO_OUTPUT_LOW },
96+
{ CATERR_LED_DRV, GPIO_DISCONNECTED},
97+
98+
/* Not used */
99+
{ SLP_S0_PLT_EC_N, GPIO_DISCONNECTED },
100+
101+
};
102+
103+
/* Any IO expanders pins should be defined here */
104+
struct gpio_ec_config expander_cfg[] = {
105+
#ifdef CONFIG_GPIO_PCA95XX
106+
{ SPD_PRSNT, GPIO_INPUT },
107+
{ VIRTUAL_BAT, GPIO_INPUT },
108+
{ VIRTUAL_DOCK, GPIO_INPUT },
109+
{ TIMEOUT_DISABLE, GPIO_INPUT },
110+
{ SOC_VR_CNTRL, GPIO_INPUT },
111+
{ EC_M_2_SSD_PLN, GPIO_OUTPUT_HIGH },
112+
{ THERM_STRAP, GPIO_INPUT },
113+
{ KBC_SCROLL_LOCK, GPIO_OUTPUT_LOW },
114+
{ CS_INDICATE_LED, GPIO_OUTPUT_LOW },
115+
{ C10_GATE_LED, GPIO_OUTPUT_LOW },
116+
#endif
117+
};
118+
119+
struct gpio_ec_config mecc172x_cfg_sus[] = {
120+
};
121+
122+
struct gpio_ec_config mecc172x_cfg_res[] = {
123+
};
124+
125+
#ifdef CONFIG_THERMAL_MANAGEMENT
126+
/**
127+
* @brief Fan device table.
128+
*
129+
* This table lists the supported fan devices for board. By default, each
130+
* board is assigned one fan for CPU.
131+
*/
132+
static struct fan_dev fan_tbl[] = {
133+
/* PWM_CH_## TACH_CH_## */
134+
{ PWM_CH_08, TACH_CH_00 }, /* CPU Fan */
135+
};
136+
137+
void board_fan_dev_tbl_init(uint8_t *pmax_fan, struct fan_dev **pfan_tbl)
138+
{
139+
*pfan_tbl = fan_tbl;
140+
*pmax_fan = ARRAY_SIZE(fan_tbl);
141+
}
142+
143+
void board_therm_sensor_list_init(uint8_t therm_sensors[])
144+
{
145+
switch (platformskutype) {
146+
case PLATFORM_PTL_UH_SKUs:
147+
therm_sensors[ACPI_THRM_SEN_2] = ADC_CH_07;
148+
therm_sensors[ACPI_THRM_SEN_3] = ADC_CH_04;
149+
therm_sensors[ACPI_THRM_SEN_4] = ADC_CH_05;
150+
therm_sensors[ACPI_THRM_SEN_5] = ADC_CH_06;
151+
break;
152+
default:
153+
break;
154+
}
155+
}
156+
#endif
157+
158+
void board_config_io_buffer(void)
159+
{
160+
int ret;
161+
162+
/* PS2 requires additional configuration not possible in pinmux */
163+
ret = gpio_interrupt_configure_pin(PS2_KB_DATA, GPIO_INT_EDGE_FALLING);
164+
if (ret) {
165+
LOG_ERR("Failed to enable PS2 KB interrupt");
166+
}
167+
}
168+
169+
void update_platform_sku_type(void)
170+
{
171+
switch (get_board_id()) {
172+
/* PTL UH Board ID List */
173+
case BRD_ID_PTL_UH_LP5x_T3_ERB:
174+
case BRD_ID_PTL_UH_LP5x_T3_RVP1:
175+
case BRD_ID_PTL_UH_LP5x_T4_RVP3:
176+
platformskutype = PLATFORM_PTL_UH_SKUs;
177+
pd_i2c_addr_set = PTL_UH_I2C_SET1;
178+
break;
179+
case BRD_ID_PTL_UH_LP5x_CAMM_DTBT_RVP2:
180+
case BRD_ID_PTL_UH_DDR5_T3_RVP4:
181+
platformskutype = PLATFORM_PTL_UH_SKUs;
182+
pd_i2c_addr_set = PTL_UH_I2C_SET2;
183+
break;
184+
default:
185+
platformskutype = PLATFORM_PTL_UH_SKUs;
186+
pd_i2c_addr_set = PTL_UH_I2C_SET1;
187+
break;
188+
}
189+
}
190+
191+
int board_init(void)
192+
{
193+
int ret;
194+
195+
LOG_WRN("%s", __func__);
196+
bgpo_disable();
197+
198+
ret = gpio_init();
199+
if (ret) {
200+
LOG_ERR("Failed to initialize gpio devs: %d", ret);
201+
return ret;
202+
}
203+
204+
LOG_WRN("%s about to initialize i2c0", __func__);
205+
ret = i2c_hub_config(I2C_0);
206+
if (ret) {
207+
return ret;
208+
}
209+
210+
LOG_WRN("%s about to initialize i2c1", __func__);
211+
ret = i2c_hub_config(I2C_1);
212+
if (ret) {
213+
return ret;
214+
}
215+
216+
LOG_WRN("%s about to read board id", __func__);
217+
ret = read_board_id();
218+
if (ret) {
219+
LOG_ERR("Failed to fetch brd id: %d", ret);
220+
return ret;
221+
}
222+
223+
LOG_WRN("%s about to update sku", __func__);
224+
update_platform_sku_type();
225+
226+
LOG_WRN("%s about to configure expander", __func__);
227+
ret = gpio_configure_array(expander_cfg, ARRAY_SIZE(expander_cfg));
228+
if (ret) {
229+
LOG_ERR("%s: %d", __func__, ret);
230+
return ret;
231+
}
232+
233+
/* In PTL UH G3_SAF HW strap is not in the expander_cfg
234+
* MEC172x has by default GPIO input disabled.
235+
* Need to configure strap prior to decide boot mode
236+
*/
237+
gpio_configure_pin(G3_SAF_DETECT, GPIO_INPUT);
238+
239+
detect_boot_mode();
240+
241+
ret = gpio_configure_array(mecc172x_cfg, ARRAY_SIZE(mecc172x_cfg));
242+
if (ret) {
243+
LOG_ERR("%s: %d", __func__, ret);
244+
return ret;
245+
}
246+
247+
248+
/* In MAF, boot ROM already made this pin output and high, so we must
249+
* keep it like that during the boot phase in order to avoid espi reset
250+
*/
251+
if (espihub_boot_mode() == FLASH_BOOT_MODE_MAF) {
252+
gpio_force_configure_pin(PM_RSMRST_MAF_P, GPIO_OUTPUT_HIGH);
253+
/* LPM optimizations */
254+
gpio_force_configure_pin(G3_SAF_DETECT, GPIO_DISCONNECTED);
255+
gpio_force_configure_pin(PM_RSMRST_G3SAF_P, GPIO_DISCONNECTED);
256+
} else {
257+
gpio_configure_pin(RSMRST_PWRGD_G3SAF_P, GPIO_INPUT);
258+
gpio_configure_pin(PM_RSMRST_G3SAF_P, GPIO_OUTPUT_LOW);
259+
}
260+
261+
board_config_io_buffer();
262+
263+
return 0;
264+
}
265+
266+
int board_suspend(void)
267+
{
268+
int ret;
269+
270+
ret = gpio_configure_array(mecc172x_cfg_sus,
271+
ARRAY_SIZE(mecc172x_cfg_sus));
272+
if (ret) {
273+
LOG_ERR("%s: %d", __func__, ret);
274+
return ret;
275+
}
276+
277+
return 0;
278+
}
279+
280+
int board_resume(void)
281+
{
282+
int ret;
283+
284+
ret = gpio_configure_array(mecc172x_cfg_res,
285+
ARRAY_SIZE(mecc172x_cfg_res));
286+
if (ret) {
287+
LOG_ERR("%s: %d", __func__, ret);
288+
return ret;
289+
}
290+
291+
return 0;
292+
}

0 commit comments

Comments
 (0)