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hilldanihilldani
authored
removing perf named events for topdown due to differing names and older kernels (#16)
1 parent 2050012 commit d3078fc

13 files changed

+110
-102
lines changed

‎Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ dist/$(PACKAGE_EXTERNAL): build_dir build/pmu-checker build/libtsc build-public/
8484
cd dist && md5sum $(PACKAGE_EXTERNAL) > $(PACKAGE_EXTERNAL).md5
8585

8686
test:
87-
cd dist && tar -xvf perfspect_$(VERSION_PUBLIC).tgz && cp -r $(BINARY_FINAL) ../test/.
87+
cd dist && tar -xvf perfspect.tgz && cp -r $(BINARY_FINAL) ../test/.
8888
cd test && pytest
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9090
format:

‎README.md

+7-7
Original file line numberDiff line numberDiff line change
@@ -8,17 +8,17 @@ The tool has two parts
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99
1. perf collection to collect underlying PMU (Performance Monitoring Unit) counters
1010
2. post processing that generates csv output of performance metrics.
11+
### Quick start (requires perf installed)
12+
```
13+
wget -qO- https://github.com/intel/PerfSpect/releases/latest/download/perfspect.tgz | tar xvz
14+
cd perfspect
15+
sudo ./perf-collect --timeout 10
16+
sudo ./perf-postprocess -r results/perfstat.csv --html perfstat.html
17+
```
1118

1219
![PerfSpect BS](images/basic_stats.JPG "perfspect-bs")
1320
![perfspect-demo1](https://user-images.githubusercontent.com/5321018/205159259-3654fa12-74d6-4cb5-8194-ea1b66aadb25.gif)
1421

15-
## Getting Started
16-
17-
### Prerequisites
18-
19-
1. Linux perf
20-
2. Linux cgroup-tools
21-
2222
## Building binaries from source code
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2424
Requires recent python and golang.

‎events/icx.txt

+5-5
Original file line numberDiff line numberDiff line change
@@ -89,11 +89,11 @@ cpu/event=0x60,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTST
8989
cpu-cycles;
9090

9191
#TMA related
92-
slots,
93-
topdown-bad-spec,
94-
topdown-be-bound,
95-
topdown-fe-bound,
96-
topdown-retiring,
92+
cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/,
93+
cpu/event=0x00,umask=0x81,period=10000003,name='PERF_METRICS.BAD_SPECULATION'/,
94+
cpu/event=0x00,umask=0x83,period=10000003,name='PERF_METRICS.BACKEND_BOUND'/,
95+
cpu/event=0x00,umask=0x82,period=10000003,name='PERF_METRICS.FRONTEND_BOUND'/,
96+
cpu/event=0x00,umask=0x80,period=10000003,name='PERF_METRICS.RETIRING'/,
9797
cpu/event=0x0d,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/,
9898
cpu/event=0x0d,umask=0x01,cmask=0x01,edge=0x01,period=500009,name='INT_MISC.RECOVERY_CYCLES_c1_e1'/;
9999

‎events/icx_aws.txt

+5-5
Original file line numberDiff line numberDiff line change
@@ -85,11 +85,11 @@ cpu/event=0x60,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTST
8585
cpu-cycles;
8686

8787
#TMA related
88-
slots,
89-
topdown-bad-spec,
90-
topdown-be-bound,
91-
topdown-fe-bound,
92-
topdown-retiring,
88+
cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/,
89+
cpu/event=0x00,umask=0x81,period=10000003,name='PERF_METRICS.BAD_SPECULATION'/,
90+
cpu/event=0x00,umask=0x83,period=10000003,name='PERF_METRICS.BACKEND_BOUND'/,
91+
cpu/event=0x00,umask=0x82,period=10000003,name='PERF_METRICS.FRONTEND_BOUND'/,
92+
cpu/event=0x00,umask=0x80,period=10000003,name='PERF_METRICS.RETIRING'/,
9393
cpu/event=0x0d,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/,
9494
cpu/event=0x0d,umask=0x01,cmask=0x01,edge=0x01,period=500009,name='INT_MISC.RECOVERY_CYCLES_c1_e1'/;
9595

‎events/icx_oci.txt

+1-1
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ cpu/event=0x60,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTST
8585
cpu-cycles;
8686

8787
#TMA related
88-
topdown.slots,
88+
cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/,
8989
cpu/event=0x0d,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/,
9090
cpu/event=0x0d,umask=0x01,cmask=0x01,edge=0x01,period=500009,name='INT_MISC.RECOVERY_CYCLES_c1_e1'/;
9191

‎events/metric_icx.json

+14-14
Original file line numberDiff line numberDiff line change
@@ -186,11 +186,11 @@
186186
},
187187
{
188188
"name": "metric_TMA_Frontend_Bound(%)",
189-
"expression": "100 * ([topdown-fe-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) - [INT_MISC.UOP_DROPPING] / ([slots]))"
189+
"expression": "100 * ([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) - [INT_MISC.UOP_DROPPING] / ([TOPDOWN.SLOTS]))"
190190
},
191191
{
192192
"name": "metric_TMA_..Fetch_Latency(%)",
193-
"expression": "100 * (5 * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [slots])"
193+
"expression": "100 * (5 * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [TOPDOWN.SLOTS])"
194194
},
195195
{
196196
"name": "metric_TMA_....ICache_Misses(%)",
@@ -218,27 +218,27 @@
218218
},
219219
{
220220
"name": "metric_TMA_..Fetch_Bandwidth(%)",
221-
"expression": "100 * max(0, (([topdown-fe-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) - [INT_MISC.UOP_DROPPING] / [slots]) - (5 * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [slots])))"
221+
"expression": "100 * max(0, (([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) - [INT_MISC.UOP_DROPPING] / [TOPDOWN.SLOTS]) - (5 * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [TOPDOWN.SLOTS])))"
222222
},
223223
{
224224
"name": "metric_TMA_Bad_Speculation(%)",
225-
"expression": "100 * (max((1 - (([topdown-fe-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) - [INT_MISC.UOP_DROPPING] / [slots]) + ([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]) + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))))), 0))"
225+
"expression": "100 * (max((1 - (([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) - [INT_MISC.UOP_DROPPING] / [TOPDOWN.SLOTS]) + ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]) + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))))), 0))"
226226
},
227227
{
228228
"name": "metric_TMA_..Branch_Mispredicts(%)",
229-
"expression": "100 * (([BR_MISP_RETIRED.ALL_BRANCHES] / ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT])) * (max((1 - (([topdown-fe-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) - [INT_MISC.UOP_DROPPING] / [slots]) + ([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]) + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))))), 0)))"
229+
"expression": "100 * (([BR_MISP_RETIRED.ALL_BRANCHES] / ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT])) * (max((1 - (([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) - [INT_MISC.UOP_DROPPING] / [TOPDOWN.SLOTS]) + ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]) + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))))), 0)))"
230230
},
231231
{
232232
"name": "metric_TMA_..Machine_Clears(%)",
233-
"expression": "100 * (max(0, ((max((1 - (([topdown-fe-bound] / (([topdown-be-bound] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring])) - [INT_MISC.UOP_DROPPING] / [slots]) + ([topdown-be-bound] / (([topdown-be-bound] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]) + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))))), 0)) - (([BR_MISP_RETIRED.ALL_BRANCHES] / ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT])) * (max((1 - (([topdown-fe-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) - [INT_MISC.UOP_DROPPING] / [slots]) + ([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]) + ([topdown-retiring] / (([topdown-be-bound] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring]))))), 0))))))"
233+
"expression": "100 * (max(0, ((max((1 - (([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.BACKEND_BOUND] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING])) - [INT_MISC.UOP_DROPPING] / [TOPDOWN.SLOTS]) + ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.BACKEND_BOUND] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]) + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))))), 0)) - (([BR_MISP_RETIRED.ALL_BRANCHES] / ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT])) * (max((1 - (([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) - [INT_MISC.UOP_DROPPING] / [TOPDOWN.SLOTS]) + ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]) + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.BACKEND_BOUND] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING]))))), 0))))))"
234234
},
235235
{
236236
"name": "metric_TMA_Backend_Bound(%)",
237-
"expression": "100 * ([topdown-be-bound] / (([topdown-be-bound] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring])) + ( 5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots])"
237+
"expression": "100 * ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.BACKEND_BOUND] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING])) + ( 5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS])"
238238
},
239239
{
240240
"name": "metric_TMA_..Memory_Bound(%)",
241-
"expression": "100 * ((([CYCLE_ACTIVITY.STALLS_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES]) / ([CYCLE_ACTIVITY.STALLS_Total] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) + [EXE_ACTIVITY.BOUND_ON_STORES])) * ([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]))"
241+
"expression": "100 * ((([CYCLE_ACTIVITY.STALLS_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES]) / ([CYCLE_ACTIVITY.STALLS_Total] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) + [EXE_ACTIVITY.BOUND_ON_STORES])) * ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]))"
242242
},
243243
{
244244
"name": "metric_TMA_....L1_Bound(%)",
@@ -290,15 +290,15 @@
290290
},
291291
{
292292
"name": "metric_TMA_..Core_Bound(%)",
293-
"expression": "100 * (max(0, (([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]) - ((([CYCLE_ACTIVITY.CYCLES_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES]) / ([CYCLE_ACTIVITY.STALLS_Total] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) + [EXE_ACTIVITY.BOUND_ON_STORES])) * ([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots])))))"
293+
"expression": "100 * (max(0, (([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]) - ((([CYCLE_ACTIVITY.CYCLES_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES]) / ([CYCLE_ACTIVITY.STALLS_Total] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) + [EXE_ACTIVITY.BOUND_ON_STORES])) * ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS])))))"
294294
},
295295
{
296296
"name": "metric_TMA_....Divider(%)",
297297
"expression": "100 * ([ARITH.DIVIDER_ACTIVE] / [cpu-cycles])"
298298
},
299299
{
300300
"name": "metric_TMA_....Ports_Utilization(%)",
301-
"expression": "100 * ((([CYCLE_ACTIVITY.STALLS_Total] - [CYCLE_ACTIVITY.CYCLES_MEM_ANY] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))) * [EXE_ACTIVITY.2_PORTS_UTIL])) / [cpu-cycles]) if ([ARITH.DIVIDER_ACTIVE] - 0) < ([CYCLE_ACTIVITY.STALLS_Total] - [CYCLE_ACTIVITY.CYCLES_MEM_ANY]) else (([EXE_ACTIVITY.1_PORTS_UTIL] + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) / [cpu-cycles]))"
301+
"expression": "100 * ((([CYCLE_ACTIVITY.STALLS_Total] - [CYCLE_ACTIVITY.CYCLES_MEM_ANY] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))) * [EXE_ACTIVITY.2_PORTS_UTIL])) / [cpu-cycles]) if ([ARITH.DIVIDER_ACTIVE] - 0) < ([CYCLE_ACTIVITY.STALLS_Total] - [CYCLE_ACTIVITY.CYCLES_MEM_ANY]) else (([EXE_ACTIVITY.1_PORTS_UTIL] + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) / [cpu-cycles]))"
302302
},
303303
{
304304
"name": "metric_TMA_......Ports_Utilized_0(%)",
@@ -318,19 +318,19 @@
318318
},
319319
{
320320
"name": "metric_TMA_Retiring(%)",
321-
"expression": "100 * ([topdown-retiring] / ([topdown-retiring] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-be-bound]))"
321+
"expression": "100 * ([PERF_METRICS.RETIRING] / ([PERF_METRICS.RETIRING] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.BACKEND_BOUND]))"
322322
},
323323
{
324324
"name": "metric_TMA_..Light_Operations(%)",
325-
"expression": "100 * (max(0, (([topdown-retiring] / (([topdown-retiring] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-be-bound]))) - ((((([topdown-retiring] / (([topdown-retiring] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-be-bound]))) * [slots]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [slots])))))"
325+
"expression": "100 * (max(0, (([PERF_METRICS.RETIRING] / (([PERF_METRICS.RETIRING] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.BACKEND_BOUND]))) - ((((([PERF_METRICS.RETIRING] / (([PERF_METRICS.RETIRING] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.BACKEND_BOUND]))) * [TOPDOWN.SLOTS]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [TOPDOWN.SLOTS])))))"
326326
},
327327
{
328328
"name": "metric_TMA_..Heavy_Operations(%)",
329-
"expression": "100 * ((((([topdown-retiring] / (([topdown-retiring] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-be-bound]))) * [slots]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [slots]))"
329+
"expression": "100 * ((((([PERF_METRICS.RETIRING] / (([PERF_METRICS.RETIRING] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.BACKEND_BOUND]))) * [TOPDOWN.SLOTS]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [TOPDOWN.SLOTS]))"
330330
},
331331
{
332332
"name": "metric_TMA_....Microcode_Sequencer(%)",
333-
"expression": "100 * (((([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-found]))) * [slots]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [slots])"
333+
"expression": "100 * (((([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [topdown-be-found]))) * [TOPDOWN.SLOTS]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [TOPDOWN.SLOTS])"
334334
},
335335
{
336336
"name": "metric_TMA_Info_CoreIPC",

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