|
| 1 | +[ |
| 2 | + { |
| 3 | + "name": "metric_CPU operating frequency (in GHz)", |
| 4 | + "expression": "([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000" |
| 5 | + }, |
| 6 | + { |
| 7 | + "name": "metric_CPU utilization %", |
| 8 | + "expression": "100 * [ref-cycles] / [TSC]" |
| 9 | + }, |
| 10 | + { |
| 11 | + "name": "metric_CPU utilization% in kernel mode", |
| 12 | + "expression": "100 * [ref-cycles:k] / [TSC]" |
| 13 | + }, |
| 14 | + { |
| 15 | + "name": "metric_CPI", |
| 16 | + "name-txn": "metric_cycles per txn", |
| 17 | + "expression": "[cpu-cycles] / [instructions]", |
| 18 | + "expression-txn": "[cpu-cycles] / [TXN]" |
| 19 | + }, |
| 20 | + { |
| 21 | + "name": "metric_kernel_CPI", |
| 22 | + "name-txn": "metric_kernel_cycles per txn", |
| 23 | + "expression": "[cpu-cycles:k] / [instructions:k]", |
| 24 | + "expression-txn": "[cpu-cycles:k] / [TXN]" |
| 25 | + }, |
| 26 | + { |
| 27 | + "name": "metric_IPC", |
| 28 | + "name-txn": "metric_txn per cycle", |
| 29 | + "expression": "[instructions] / [cpu-cycles]", |
| 30 | + "expression-txn": "[TXN] / [cpu-cycles]" |
| 31 | + }, |
| 32 | + { |
| 33 | + "name": "metric_giga_instructions_per_sec", |
| 34 | + "expression": "[instructions] / 1000000000" |
| 35 | + }, |
| 36 | + { |
| 37 | + "name": "metric_locks retired per instr", |
| 38 | + "name-txn": "metric_locks retired per txn", |
| 39 | + "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]", |
| 40 | + "expression-txn": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]" |
| 41 | + }, |
| 42 | + { |
| 43 | + "name": "metric_L1D MPI (includes data+rfo w/ prefetches)", |
| 44 | + "name-txn": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", |
| 45 | + "expression": "[L1D.REPLACEMENT] / [instructions]", |
| 46 | + "expression-txn": "[L1D.REPLACEMENT] / [TXN]" |
| 47 | + }, |
| 48 | + { |
| 49 | + "name": "metric_L1D demand data read hits per instr", |
| 50 | + "name-txn": "metric_L1D demand data read hits per txn", |
| 51 | + "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]", |
| 52 | + "expression-txn": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]" |
| 53 | + }, |
| 54 | + { |
| 55 | + "name": "metric_L1-I code read misses (w/ prefetches) per instr", |
| 56 | + "name-txn": "metric_L1I code read misses (includes prefetches) per txn", |
| 57 | + "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]", |
| 58 | + "expression-txn": "[L2_RQSTS.ALL_CODE_RD] / [TXN]" |
| 59 | + }, |
| 60 | + { |
| 61 | + "name": "metric_L2 demand data read hits per instr", |
| 62 | + "name-txn": "metric_L2 demand data read hits per txn", |
| 63 | + "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]", |
| 64 | + "expression-txn": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]" |
| 65 | + }, |
| 66 | + { |
| 67 | + "name": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", |
| 68 | + "name-txn": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", |
| 69 | + "expression": "[L2_LINES_IN.ALL] / [instructions]", |
| 70 | + "expression-txn": "[L2_LINES_IN.ALL] / [TXN]" |
| 71 | + }, |
| 72 | + { |
| 73 | + "name": "metric_L2 demand data read MPI", |
| 74 | + "name-txn": "metric_L2 demand data read misses per txn", |
| 75 | + "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]", |
| 76 | + "expression-txn": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]" |
| 77 | + }, |
| 78 | + { |
| 79 | + "name": "metric_L2 demand code MPI", |
| 80 | + "name-txn": "metric_L2 demand code misses per txn", |
| 81 | + "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]", |
| 82 | + "expression-txn": "[L2_RQSTS.CODE_RD_MISS] / [TXN]" |
| 83 | + }, |
| 84 | + { |
| 85 | + "name": "metric_LLC code read MPI (demand+prefetch)", |
| 86 | + "name-txn": "metric_LLC code read (demand+prefetch) misses per txn", |
| 87 | + "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [instructions]", |
| 88 | + "expression-txn": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [TXN]" |
| 89 | + }, |
| 90 | + { |
| 91 | + "name": "metric_LLC data read MPI (demand+prefetch)", |
| 92 | + "name-txn": "metric_LLC data read (demand+prefetch) misses per txn", |
| 93 | + "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]", |
| 94 | + "expression-txn": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]" |
| 95 | + }, |
| 96 | + { |
| 97 | + "name": "metric_Average LLC demand data read miss latency (in ns)", |
| 98 | + "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" |
| 99 | + }, |
| 100 | + { |
| 101 | + "name": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", |
| 102 | + "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" |
| 103 | + }, |
| 104 | + { |
| 105 | + "name": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", |
| 106 | + "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" |
| 107 | + }, |
| 108 | + { |
| 109 | + "name": "metric_UPI Data transmit BW (MB/sec) (only data)", |
| 110 | + "expression": "([UNC_UPI_TxL_FLITS.ALL_DATA] * (64 / 9.0) / 1000000) / 1" |
| 111 | + }, |
| 112 | + { |
| 113 | + "name": "metric_package power (watts)", |
| 114 | + "expression": "[power/energy-pkg/]" |
| 115 | + }, |
| 116 | + { |
| 117 | + "name": "metric_DRAM power (watts)", |
| 118 | + "expression": "[power/energy-ram/]" |
| 119 | + }, |
| 120 | + { |
| 121 | + "name": "metric_core c6 residency %", |
| 122 | + "expression": "100 * [cstate_core/c6-residency/] / [TSC]" |
| 123 | + }, |
| 124 | + { |
| 125 | + "name": "metric_package c6 residency %", |
| 126 | + "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" |
| 127 | + }, |
| 128 | + { |
| 129 | + "name": "metric_% Uops delivered from decoded Icache (DSB)", |
| 130 | + "expression": "100 * ([IDQ.DSB_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" |
| 131 | + }, |
| 132 | + { |
| 133 | + "name": "metric_% Uops delivered from legacy decode pipeline (MITE)", |
| 134 | + "expression": "100 * ([IDQ.MITE_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" |
| 135 | + }, |
| 136 | + { |
| 137 | + "name": "metric_memory bandwidth read (MB/sec)", |
| 138 | + "expression": "(([UNC_M_CAS_COUNT_SCH0.RD] + [UNC_M_CAS_COUNT_SCH1.RD]) * 64 / 1000000) / 1" |
| 139 | + }, |
| 140 | + { |
| 141 | + "name": "metric_memory bandwidth write (MB/sec)", |
| 142 | + "expression": "(([UNC_M_CAS_COUNT_SCH0.WR] + [UNC_M_CAS_COUNT_SCH1.WR]) * 64 / 1000000) / 1" |
| 143 | + }, |
| 144 | + { |
| 145 | + "name": "metric_memory bandwidth total (MB/sec)", |
| 146 | + "expression": "(([UNC_M_CAS_COUNT_SCH0.RD] + [UNC_M_CAS_COUNT_SCH1.RD] + [UNC_M_CAS_COUNT_SCH0.WR] + [UNC_M_CAS_COUNT_SCH1.WR]) * 64 / 1000000) / 1" |
| 147 | + }, |
| 148 | + { |
| 149 | + "name": "metric_ITLB (2nd level) MPI", |
| 150 | + "name-txn": "metric_ITLB (2nd level) misses per txn", |
| 151 | + "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]", |
| 152 | + "expression-txn": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" |
| 153 | + }, |
| 154 | + { |
| 155 | + "name": "metric_DTLB (2nd level) load MPI", |
| 156 | + "name-txn": "metric_DTLB (2nd level) load misses per txn", |
| 157 | + "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]", |
| 158 | + "expression-txn": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" |
| 159 | + }, |
| 160 | + { |
| 161 | + "name": "metric_DTLB (2nd level) store MPI", |
| 162 | + "name-txn": "metric_DTLB (2nd level) store misses per txn", |
| 163 | + "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]", |
| 164 | + "expression-txn": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" |
| 165 | + }, |
| 166 | + { |
| 167 | + "name": "metric_NUMA %_Reads addressed to local DRAM", |
| 168 | + "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" |
| 169 | + }, |
| 170 | + { |
| 171 | + "name": "metric_NUMA %_Reads addressed to remote DRAM", |
| 172 | + "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" |
| 173 | + }, |
| 174 | + { |
| 175 | + "name": "metric_uncore frequency GHz", |
| 176 | + "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" |
| 177 | + }, |
| 178 | + { |
| 179 | + "name": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", |
| 180 | + "expression": "([UNC_CHA_TOR_INSERTS.IO_PCIRDCUR] * 64 / 1000000) / 1" |
| 181 | + }, |
| 182 | + { |
| 183 | + "name": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", |
| 184 | + "expression": "(([UNC_CHA_TOR_INSERTS.IO_ITOM] + [UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR]) * 64 / 1000000) / 1" |
| 185 | + } |
| 186 | +] |
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